| blob | 15588b0611e932677e0b4967aaa80e09d089ec2b |
1 /*
2 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARC
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * vineetg: May 2011
11 * -Userspace unaligned access emulation
12 *
13 * vineetg: Feb 2011 (ptrace low level code fixes)
14 * -traced syscall return code (r0) was not saved into pt_regs for restoring
15 * into user reg-file when traded task rets to user space.
16 * -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
17 * were not invoking post-syscall trace hook (jumping directly into
18 * ret_from_system_call)
19 *
20 * vineetg: Nov 2010:
21 * -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
22 * -To maintain the slot size of 8 bytes/vector, added nop, which is
23 * not executed at runtime.
24 *
25 * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
26 * -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
27 * -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
28 * need ptregs anymore
29 *
30 * Vineetg: Oct 2009
31 * -In a rare scenario, Process gets a Priv-V exception and gets scheduled
32 * out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
33 * active (AE bit enabled). This causes a double fault for a subseq valid
34 * exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
35 * Instr Error could also cause similar scenario, so same there as well.
36 *
37 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
38 *
39 * Vineetg: Aug 28th 2008: Bug #94984
40 * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
41 * Normally CPU does this automatically, however when doing FAKE rtie,
42 * we need to explicitly do this. The problem in macros
43 * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
44 * was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
45 * setting it and not clearing it clears ZOL context
46 *
47 * Vineetg: May 16th, 2008
48 * - r25 now contains the Current Task when in kernel
49 *
50 * Vineetg: Dec 22, 2007
51 * Minor Surgery of Low Level ISR to make it SMP safe
52 * - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
53 * - _current_task is made an array of NR_CPUS
54 * - Access of _current_task wrapped inside a macro so that if hardware
55 * team agrees for a dedicated reg, no other code is touched
56 *
57 * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
58 */
60 /*------------------------------------------------------------------
61 * Function ABI
62 *------------------------------------------------------------------
63 *
64 * Arguments r0 - r7
65 * Caller Saved Registers r0 - r12
66 * Callee Saved Registers r13- r25
67 * Global Pointer (gp) r26
68 * Frame Pointer (fp) r27
69 * Stack Pointer (sp) r28
70 * Interrupt link register (ilink1) r29
71 * Interrupt link register (ilink2) r30
72 * Branch link register (blink) r31
73 *------------------------------------------------------------------
74 */
76 .cpu A7
78 ;############################ Vector Table #################################
80 .macro VECTOR lbl
81 #if 1 /* Just in case, build breaks */
82 j \lbl
83 #else
84 b \lbl
85 nop
86 #endif
87 .endm
89 .section .vector, "ax",@progbits
90 .align 4
92 /* Each entry in the vector table must occupy 2 words. Since it is a jump
93 * across sections (.vector to .text) we are gauranteed that 'j somewhere'
94 * will use the 'j limm' form of the intrsuction as long as somewhere is in
95 * a section other than .vector.
96 */
98 ; ********* Critical System Events **********************
99 VECTOR res_service ; 0x0, Restart Vector (0x0)
100 VECTOR mem_service ; 0x8, Mem exception (0x1)
101 VECTOR instr_service ; 0x10, Instrn Error (0x2)
103 ; ******************** Device ISRs **********************
104 #ifdef CONFIG_ARC_IRQ3_LV2
105 VECTOR handle_interrupt_level2
106 #else
107 VECTOR handle_interrupt_level1
108 #endif
110 VECTOR handle_interrupt_level1
112 #ifdef CONFIG_ARC_IRQ5_LV2
113 VECTOR handle_interrupt_level2
114 #else
115 VECTOR handle_interrupt_level1
116 #endif
118 #ifdef CONFIG_ARC_IRQ6_LV2
119 VECTOR handle_interrupt_level2
120 #else
121 VECTOR handle_interrupt_level1
122 #endif
124 .rept 25
125 VECTOR handle_interrupt_level1 ; Other devices
126 .endr
128 /* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
130 ; ******************** Exceptions **********************
131 VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
132 VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
133 VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
134 VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
135 ; or Misaligned Access
136 VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
137 VECTOR EV_Trap ; 0x128, Trap exception (0x25)
138 VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
140 .rept 24
141 VECTOR reserved ; Reserved Exceptions
142 .endr
144 #include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
145 #include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,SYS...} */
146 #include <asm/errno.h>
147 #include <asm/arcregs.h>
148 #include <asm/irqflags.h>
150 ;##################### Scratch Mem for IRQ stack switching #############
152 ARCFP_DATA int1_saved_reg
153 .align 32
154 .type int1_saved_reg, @object
155 .size int1_saved_reg, 4
156 int1_saved_reg:
157 .zero 4
159 /* Each Interrupt level needs it's own scratch */
160 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
162 ARCFP_DATA int2_saved_reg
163 .type int2_saved_reg, @object
164 .size int2_saved_reg, 4
165 int2_saved_reg:
166 .zero 4
168 #endif
170 ; ---------------------------------------------
171 .section .text, "ax",@progbits
173 res_service: ; processor restart
174 flag 0x1 ; not implemented
175 nop
176 nop
178 reserved: ; processor restart
179 rtie ; jump to processor initializations
181 ;##################### Interrupt Handling ##############################
183 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
184 ; ---------------------------------------------
185 ; Level 2 ISR: Can interrupt a Level 1 ISR
186 ; ---------------------------------------------
187 ARC_ENTRY handle_interrupt_level2
189 ; TODO-vineetg for SMP this wont work
190 ; free up r9 as scratchpad
191 st r9, [@int2_saved_reg]
193 ;Which mode (user/kernel) was the system in when intr occured
194 lr r9, [status32_l2]
196 SWITCH_TO_KERNEL_STK
197 SAVE_ALL_INT2
199 ;------------------------------------------------------
200 ; if L2 IRQ interrupted a L1 ISR, disable preemption
201 ;------------------------------------------------------
203 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
204 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
206 ; A1 is set in status32_l2
207 ; bump thread_info->preempt_count (Disable preemption)
208 GET_CURR_THR_INFO_FROM_SP r10
209 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
210 add r9, r9, 1
211 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
213 1:
214 ;------------------------------------------------------
215 ; setup params for Linux common ISR and invoke it
216 ;------------------------------------------------------
217 lr r0, [icause2]
218 and r0, r0, 0x1f
220 bl.d @arch_do_IRQ
221 mov r1, sp
223 mov r8,0x2
224 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
226 b ret_from_exception
228 ARC_EXIT handle_interrupt_level2
230 #endif
232 ; ---------------------------------------------
233 ; Level 1 ISR
234 ; ---------------------------------------------
235 ARC_ENTRY handle_interrupt_level1
237 /* free up r9 as scratchpad */
238 #ifdef CONFIG_SMP
239 sr r9, [ARC_REG_SCRATCH_DATA0]
240 #else
241 st r9, [@int1_saved_reg]
242 #endif
244 ;Which mode (user/kernel) was the system in when intr occured
245 lr r9, [status32_l1]
247 SWITCH_TO_KERNEL_STK
248 SAVE_ALL_INT1
250 lr r0, [icause1]
251 and r0, r0, 0x1f
253 bl.d @arch_do_IRQ
254 mov r1, sp
256 mov r8,0x1
257 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
259 b ret_from_exception
260 ARC_EXIT handle_interrupt_level1
262 ;################### Non TLB Exception Handling #############################
264 ; ---------------------------------------------
265 ; Instruction Error Exception Handler
266 ; ---------------------------------------------
268 ARC_ENTRY instr_service
270 EXCEPTION_PROLOGUE
272 lr r0, [efa]
273 mov r1, sp
275 FAKE_RET_FROM_EXCPN r9
277 bl do_insterror_or_kprobe
278 b ret_from_exception
279 ARC_EXIT instr_service
281 ; ---------------------------------------------
282 ; Memory Error Exception Handler
283 ; ---------------------------------------------
285 ARC_ENTRY mem_service
287 EXCEPTION_PROLOGUE
289 lr r0, [efa]
290 mov r1, sp
292 FAKE_RET_FROM_EXCPN r9
294 bl do_memory_error
295 b ret_from_exception
296 ARC_EXIT mem_service
298 ; ---------------------------------------------
299 ; Machine Check Exception Handler
300 ; ---------------------------------------------
302 ARC_ENTRY EV_MachineCheck
304 EXCEPTION_PROLOGUE
306 lr r2, [ecr]
307 lr r0, [efa]
308 mov r1, sp
310 lsr r3, r2, 8
311 bmsk r3, r3, 7
312 brne r3, ECR_C_MCHK_DUP_TLB, 1f
314 bl do_tlb_overlap_fault
315 b ret_from_exception
317 1:
318 ; DEAD END: can't do much, display Regs and HALT
319 SAVE_CALLEE_SAVED_USER
321 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
322 st sp, [r10, THREAD_CALLEE_REG]
324 j do_machine_check_fault
326 ARC_EXIT EV_MachineCheck
328 ; ---------------------------------------------
329 ; Protection Violation Exception Handler
330 ; ---------------------------------------------
332 ARC_ENTRY EV_TLBProtV
334 EXCEPTION_PROLOGUE
336 ;---------(3) Save some more regs-----------------
337 ; vineetg: Mar 6th: Random Seg Fault issue #1
338 ; ecr and efa were not saved in case an Intr sneaks in
339 ; after fake rtie
340 ;
341 lr r2, [ecr]
342 lr r1, [efa] ; Faulting Data address
344 ; --------(4) Return from CPU Exception Mode ---------
345 ; Fake a rtie, but rtie to next label
346 ; That way, subsequently, do_page_fault ( ) executes in pure kernel
347 ; mode with further Exceptions enabled
349 FAKE_RET_FROM_EXCPN r9
351 ;------ (5) Type of Protection Violation? ----------
352 ;
353 ; ProtV Hardware Exception is triggered for Access Faults of 2 types
354 ; -Access Violaton : 00_23_(00|01|02|03)_00
355 ; x r w r+w
356 ; -Unaligned Access : 00_23_04_00
357 ;
358 bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
360 ;========= (6a) Access Violation Processing ========
361 mov r0, sp ; pt_regs
362 bl do_page_fault
363 b ret_from_exception
365 ;========== (6b) Non aligned access ============
366 4:
367 mov r0, r1
368 mov r1, sp ; pt_regs
370 #ifdef CONFIG_ARC_MISALIGN_ACCESS
371 SAVE_CALLEE_SAVED_USER
372 mov r2, sp ; callee_regs
374 bl do_misaligned_access
376 ; TBD: optimize - do this only if a callee reg was involved
377 ; either a dst of emulated LD/ST or src with address-writeback
378 RESTORE_CALLEE_SAVED_USER
379 #else
380 bl do_misaligned_error
381 #endif
383 b ret_from_exception
385 ARC_EXIT EV_TLBProtV
387 ; ---------------------------------------------
388 ; Privilege Violation Exception Handler
389 ; ---------------------------------------------
390 ARC_ENTRY EV_PrivilegeV
392 EXCEPTION_PROLOGUE
394 lr r0, [efa]
395 mov r1, sp
397 FAKE_RET_FROM_EXCPN r9
399 bl do_privilege_fault
400 b ret_from_exception
401 ARC_EXIT EV_PrivilegeV
403 ; ---------------------------------------------
404 ; Extension Instruction Exception Handler
405 ; ---------------------------------------------
406 ARC_ENTRY EV_Extension
408 EXCEPTION_PROLOGUE
410 lr r0, [efa]
411 mov r1, sp
413 FAKE_RET_FROM_EXCPN r9
415 bl do_extension_fault
416 b ret_from_exception
417 ARC_EXIT EV_Extension
419 ;######################### System Call Tracing #########################
421 tracesys:
422 ; save EFA in case tracer wants the PC of traced task
423 ; using ERET won't work since next-PC has already committed
424 lr r12, [efa]
425 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
426 st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
428 ; PRE Sys Call Ptrace hook
429 mov r0, sp ; pt_regs needed
430 bl @syscall_trace_entry
432 ; Tracing code now returns the syscall num (orig or modif)
433 mov r8, r0
435 ; Do the Sys Call as we normally would.
436 ; Validate the Sys Call number
437 cmp r8, NR_syscalls
438 mov.hi r0, -ENOSYS
439 bhi tracesys_exit
441 ; Restore the sys-call args. Mere invocation of the hook abv could have
442 ; clobbered them (since they are in scratch regs). The tracer could also
443 ; have deliberately changed the syscall args: r0-r7
444 ld r0, [sp, PT_r0]
445 ld r1, [sp, PT_r1]
446 ld r2, [sp, PT_r2]
447 ld r3, [sp, PT_r3]
448 ld r4, [sp, PT_r4]
449 ld r5, [sp, PT_r5]
450 ld r6, [sp, PT_r6]
451 ld r7, [sp, PT_r7]
452 ld.as r9, [sys_call_table, r8]
453 jl [r9] ; Entry into Sys Call Handler
455 tracesys_exit:
456 st r0, [sp, PT_r0] ; sys call return value in pt_regs
458 ;POST Sys Call Ptrace Hook
459 bl @syscall_trace_exit
460 b ret_from_exception ; NOT ret_from_system_call at is saves r0 which
461 ; we'd done before calling post hook above
463 ;################### Break Point TRAP ##########################
465 ; ======= (5b) Trap is due to Break-Point =========
467 trap_with_param:
469 ; stop_pc info by gdb needs this info
470 lr r0, [efa]
471 mov r1, sp
473 ; Now that we have read EFA, its safe to do "fake" rtie
474 ; and get out of CPU exception mode
475 FAKE_RET_FROM_EXCPN r11
477 ; Save callee regs in case gdb wants to have a look
478 ; SP will grow up by size of CALLEE Reg-File
479 ; NOTE: clobbers r12
480 SAVE_CALLEE_SAVED_USER
482 ; save location of saved Callee Regs @ thread_struct->pc
483 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
484 st sp, [r10, THREAD_CALLEE_REG]
486 ; Call the trap handler
487 bl do_non_swi_trap
489 ; unwind stack to discard Callee saved Regs
490 DISCARD_CALLEE_SAVED_USER
492 b ret_from_exception
494 ;##################### Trap Handling ##############################
495 ;
496 ; EV_Trap caused by TRAP_S and TRAP0 instructions.
497 ;------------------------------------------------------------------
498 ; (1) System Calls
499 ; :parameters in r0-r7.
500 ; :r8 has the system call number
501 ; (2) Break Points
502 ;------------------------------------------------------------------
504 ARC_ENTRY EV_Trap
506 EXCEPTION_PROLOGUE
508 ;------- (4) What caused the Trap --------------
509 lr r12, [ecr]
510 bmsk.f 0, r12, 7
511 bnz trap_with_param
513 ; ======= (5a) Trap is due to System Call ========
515 ; Before doing anything, return from CPU Exception Mode
516 FAKE_RET_FROM_EXCPN r11
518 ; If syscall tracing ongoing, invoke pre-pos-hooks
519 GET_CURR_THR_INFO_FLAGS r10
520 btst r10, TIF_SYSCALL_TRACE
521 bnz tracesys ; this never comes back
523 ;============ This is normal System Call case ==========
524 ; Sys-call num shd not exceed the total system calls avail
525 cmp r8, NR_syscalls
526 mov.hi r0, -ENOSYS
527 bhi ret_from_system_call
529 ; Offset into the syscall_table and call handler
530 ld.as r9,[sys_call_table, r8]
531 jl [r9] ; Entry into Sys Call Handler
533 ; fall through to ret_from_system_call
534 ARC_EXIT EV_Trap
536 ARC_ENTRY ret_from_system_call
538 st r0, [sp, PT_r0] ; sys call return value in pt_regs
540 ; fall through yet again to ret_from_exception
542 ;############# Return from Intr/Excp/Trap (Linux Specifics) ##############
543 ;
544 ; If ret to user mode do we need to handle signals, schedule() et al.
546 ARC_ENTRY ret_from_exception
548 ; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32
549 ld r8, [sp, PT_status32] ; returning to User/Kernel Mode
551 bbit0 r8, STATUS_U_BIT, resume_kernel_mode
553 ; Before returning to User mode check-for-and-complete any pending work
554 ; such as rescheduling/signal-delivery etc.
555 resume_user_mode_begin:
557 ; Disable IRQs to ensures that chk for pending work itself is atomic
558 ; (and we don't end up missing a NEED_RESCHED/SIGPENDING due to an
559 ; interim IRQ).
560 IRQ_DISABLE r10
562 ; Fast Path return to user mode if no pending work
563 GET_CURR_THR_INFO_FLAGS r9
564 and.f 0, r9, _TIF_WORK_MASK
565 bz restore_regs
567 ; --- (Slow Path #1) task preemption ---
568 bbit0 r9, TIF_NEED_RESCHED, .Lchk_pend_signals
569 mov blink, resume_user_mode_begin ; tail-call to U mode ret chks
570 b @schedule ; BTST+Bnz causes relo error in link
572 .Lchk_pend_signals:
573 IRQ_ENABLE r10
575 ; --- (Slow Path #2) pending signal ---
576 mov r0, sp ; pt_regs for arg to do_signal()/do_notify_resume()
578 bbit0 r9, TIF_SIGPENDING, .Lchk_notify_resume
580 ; Normal Trap/IRQ entry only saves Scratch (caller-saved) regs
581 ; in pt_reg since the "C" ABI (kernel code) will automatically
582 ; save/restore callee-saved regs.
583 ;
584 ; However, here we need to explicitly save callee regs because
585 ; (i) If this signal causes coredump - full regfile needed
586 ; (ii) If signal is SIGTRAP/SIGSTOP, task is being traced thus
587 ; tracer might call PEEKUSR(CALLEE reg)
588 ;
589 ; NOTE: SP will grow up by size of CALLEE Reg-File
590 SAVE_CALLEE_SAVED_USER ; clobbers r12
592 ; save location of saved Callee Regs @ thread_struct->callee
593 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
594 st sp, [r10, THREAD_CALLEE_REG]
596 bl @do_signal
598 ; Ideally we want to discard the Callee reg above, however if this was
599 ; a tracing signal, tracer could have done a POKEUSR(CALLEE reg)
600 RESTORE_CALLEE_SAVED_USER
602 b resume_user_mode_begin ; loop back to start of U mode ret
604 ; --- (Slow Path #3) notify_resume ---
605 .Lchk_notify_resume:
606 btst r9, TIF_NOTIFY_RESUME
607 blnz @do_notify_resume
608 b resume_user_mode_begin ; unconditionally back to U mode ret chks
609 ; for single exit point from this block
611 resume_kernel_mode:
613 ; Disable Interrupts from this point on
614 ; CONFIG_PREEMPT: This is a must for preempt_schedule_irq()
615 ; !CONFIG_PREEMPT: To ensure restore_regs is intr safe
616 IRQ_DISABLE r9
618 #ifdef CONFIG_PREEMPT
620 ; Can't preempt if preemption disabled
621 GET_CURR_THR_INFO_FROM_SP r10
622 ld r8, [r10, THREAD_INFO_PREEMPT_COUNT]
623 brne r8, 0, restore_regs
625 ; check if this task's NEED_RESCHED flag set
626 ld r9, [r10, THREAD_INFO_FLAGS]
627 bbit0 r9, TIF_NEED_RESCHED, restore_regs
629 ; Invoke PREEMPTION
630 bl preempt_schedule_irq
632 ; preempt_schedule_irq() always returns with IRQ disabled
633 #endif
635 ; fall through
637 ;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
638 ;
639 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
640 ; IRQ shd definitely not happen between now and rtie
641 ; All 2 entry points to here already disable interrupts
643 restore_regs :
645 lr r10, [status32]
647 ; Restore REG File. In case multiple Events outstanding,
648 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
649 ; Note that we use realtime STATUS32 (not pt_regs->status32) to
650 ; decide that.
652 ; if Returning from Exception
653 bbit0 r10, STATUS_AE_BIT, not_exception
654 RESTORE_ALL_SYS
655 rtie
657 ; Not Exception so maybe Interrupts (Level 1 or 2)
659 not_exception:
661 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
663 ; Level 2 interrupt return Path - from hardware standpoint
664 bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
666 ;------------------------------------------------------------------
667 ; However the context returning might not have taken L2 intr itself
668 ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
669 ; Special considerations needed for the context which took L2 intr
671 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
672 brne r9, event_IRQ2, 149f
674 ;------------------------------------------------------------------
675 ; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
676 ; so that sched doesnt move to new task, causing L1 to be delayed
677 ; undeterministically. Now that we've achieved that, lets reset
678 ; things to what they were, before returning from L2 context
679 ;----------------------------------------------------------------
681 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
682 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
684 ; decrement thread_info->preempt_count (re-enable preemption)
685 GET_CURR_THR_INFO_FROM_SP r10
686 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
688 ; paranoid check, given A1 was active when A2 happened, preempt count
689 ; must not be 0 because we would have incremented it.
690 ; If this does happen we simply HALT as it means a BUG !!!
691 cmp r9, 0
692 bnz 2f
693 flag 1
695 2:
696 sub r9, r9, 1
697 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
699 149:
700 ;return from level 2
701 RESTORE_ALL_INT2
702 debug_marker_l2:
703 rtie
705 not_level2_interrupt:
707 #endif
709 bbit0 r10, STATUS_A1_BIT, not_level1_interrupt
711 ;return from level 1
713 RESTORE_ALL_INT1
714 debug_marker_l1:
715 rtie
717 not_level1_interrupt:
719 ;this case is for syscalls or Exceptions (with fake rtie)
721 RESTORE_ALL_SYS
722 debug_marker_syscall:
723 rtie
725 ARC_EXIT ret_from_exception
727 ARC_ENTRY ret_from_fork
728 ; when the forked child comes here from the __switch_to function
729 ; r0 has the last task pointer.
730 ; put last task in scheduler queue
731 bl @schedule_tail
733 ; If kernel thread, jump to it's entry-point
734 ld r9, [sp, PT_status32]
735 brne r9, 0, 1f
737 jl.d [r14]
738 mov r0, r13 ; arg to payload
740 1:
741 ; special case of kernel_thread entry point returning back due to
742 ; kernel_execve() - pretend return from syscall to ret to userland
743 b ret_from_exception
744 ARC_EXIT ret_from_fork
746 ;################### Special Sys Call Wrappers ##########################
748 ARC_ENTRY sys_clone_wrapper
749 SAVE_CALLEE_SAVED_USER
750 bl @sys_clone
751 DISCARD_CALLEE_SAVED_USER
753 GET_CURR_THR_INFO_FLAGS r10
754 btst r10, TIF_SYSCALL_TRACE
755 bnz tracesys_exit
757 b ret_from_system_call
758 ARC_EXIT sys_clone_wrapper
760 #ifdef CONFIG_ARC_DW2_UNWIND
761 ; Workaround for bug 94179 (STAR ):
762 ; Despite -fasynchronous-unwind-tables, linker is not making dwarf2 unwinder
763 ; section (.debug_frame) as loadable. So we force it here.
764 ; This also fixes STAR 9000487933 where the prev-workaround (objcopy --setflag)
765 ; would not work after a clean build due to kernel build system dependencies.
766 .section .debug_frame, "wa",@progbits
767 #endif