arch/mips/netlogic/xlp/wakeup.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/init.h>
  36 #include <linux/kernel.h>
  37 #include <linux/threads.h>
  38
  39 #include <asm/asm.h>
  40 #include <asm/asm-offsets.h>
  41 #include <asm/mipsregs.h>
  42 #include <asm/addrspace.h>
  43 #include <asm/string.h>
  44
  45 #include <asm/netlogic/haldefs.h>
  46 #include <asm/netlogic/common.h>
  47 #include <asm/netlogic/mips-extns.h>
  48
  49 #include <asm/netlogic/xlp-hal/iomap.h>
  50 #include <asm/netlogic/xlp-hal/pic.h>
  51 #include <asm/netlogic/xlp-hal/xlp.h>
  52 #include <asm/netlogic/xlp-hal/sys.h>
  53
  54 static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
  55 {
  56         uint32_t coremask, value;
  57         int count;
  58
  59         coremask = (1 << core);
  60
  61         /* Enable CPU clock in case of 8xx/3xx */
  62         if (!cpu_is_xlpii()) {
  63                 value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
  64                 value &= ~coremask;
  65                 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
  66         }
  67
  68         /* Remove CPU Reset */
  69         value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
  70         value &= ~coremask;
  71         nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value);
  72
  73         /* Poll for CPU to mark itself coherent */
  74         count = 100000;
  75         do {
  76                 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
  77         } while ((value & coremask) != 0 && --count > 0);
  78
  79         return count != 0;
  80 }
  81
  82 static int wait_for_cpus(int cpu, int bootcpu)
  83 {
  84         volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
  85         int i, count, notready;
  86
  87         count = 0x20000000;
  88         do {
  89                 notready = nlm_threads_per_core;
  90                 for (i = 0; i < nlm_threads_per_core; i++)
  91                         if (cpu_ready[cpu + i] || cpu == bootcpu)
  92                                 --notready;
  93         } while (notready != 0 && --count > 0);
  94
  95         return count != 0;
  96 }
  97
  98 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
  99 {
 100         struct nlm_soc_info *nodep;
 101         uint64_t syspcibase;
 102         uint32_t syscoremask;
 103         int core, n, cpu;
 104
 105         for (n = 0; n < NLM_NR_NODES; n++) {
 106                 syspcibase = nlm_get_sys_pcibase(n);
 107                 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
 108                         break;
 109
 110                 /* read cores in reset from SYS */
 111                 if (n != 0)
 112                         nlm_node_init(n);
 113                 nodep = nlm_get_node(n);
 114                 syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET);
 115                 /* The boot cpu */
 116                 if (n == 0) {
 117                         syscoremask |= 1;
 118                         nodep->coremask = 1;
 119                 }
 120
 121                 for (core = 0; core < NLM_CORES_PER_NODE; core++) {
 122                         /* we will be on node 0 core 0 */
 123                         if (n == 0 && core == 0)
 124                                 continue;
 125
 126                         /* see if the core exists */
 127                         if ((syscoremask & (1 << core)) == 0)
 128                                 continue;
 129
 130                         /* see if at least the first hw thread is enabled */
 131                         cpu = (n * NLM_CORES_PER_NODE + core)
 132                                                 * NLM_THREADS_PER_CORE;
 133                         if (!cpumask_test_cpu(cpu, wakeup_mask))
 134                                 continue;
 135
 136                         /* wake up the core */
 137                         if (!xlp_wakeup_core(nodep->sysbase, n, core))
 138                                 continue;
 139
 140                         /* core is up */
 141                         nodep->coremask |= 1u << core;
 142
 143                         /* spin until the hw threads sets their ready */
 144                         wait_for_cpus(cpu, 0);
 145                 }
 146         }
 147 }
 148
 149 void xlp_wakeup_secondary_cpus()
 150 {
 151         /*
 152          * In case of u-boot, the secondaries are in reset
 153          * first wakeup core 0 threads
 154          */
 155         xlp_boot_core0_siblings();
 156         wait_for_cpus(0, 0);
 157
 158         /* now get other cores out of reset */
 159         xlp_enable_secondary_cores(&nlm_cpumask);
 160 }