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Linux 3.12.28
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blob77046f7177d531a425392e1905d700050adf980f
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 #define KVM_NR_SHARED_MSRS 16
110
111 struct kvm_shared_msrs_global {
112 int nr;
113 u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
123 };
124
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
161 { NULL }
162 };
163
164 u64 __read_mostly host_xcr0;
165
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173 }
174
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177 unsigned slot;
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191 }
192
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195 u64 value;
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208 }
209
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220 static void kvm_shared_msr_cpu_online(void)
221 {
222 unsigned i;
223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232
233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
234 return;
235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242 }
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
245 static void drop_user_return_notifiers(void *ignore)
246 {
247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252 }
253
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 {
256 return vcpu->arch.apic_base;
257 }
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261 {
262 /* TODO: reserve bits check */
263 kvm_lapic_set_base(vcpu, data);
264 }
265 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266
267 asmlinkage void kvm_spurious_fault(void)
268 {
269 /* Fault while not rebooting. We want the trace. */
270 BUG();
271 }
272 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
273
274 #define EXCPT_BENIGN 0
275 #define EXCPT_CONTRIBUTORY 1
276 #define EXCPT_PF 2
277
278 static int exception_class(int vector)
279 {
280 switch (vector) {
281 case PF_VECTOR:
282 return EXCPT_PF;
283 case DE_VECTOR:
284 case TS_VECTOR:
285 case NP_VECTOR:
286 case SS_VECTOR:
287 case GP_VECTOR:
288 return EXCPT_CONTRIBUTORY;
289 default:
290 break;
291 }
292 return EXCPT_BENIGN;
293 }
294
295 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
296 unsigned nr, bool has_error, u32 error_code,
297 bool reinject)
298 {
299 u32 prev_nr;
300 int class1, class2;
301
302 kvm_make_request(KVM_REQ_EVENT, vcpu);
303
304 if (!vcpu->arch.exception.pending) {
305 queue:
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = has_error;
308 vcpu->arch.exception.nr = nr;
309 vcpu->arch.exception.error_code = error_code;
310 vcpu->arch.exception.reinject = reinject;
311 return;
312 }
313
314 /* to check exception */
315 prev_nr = vcpu->arch.exception.nr;
316 if (prev_nr == DF_VECTOR) {
317 /* triple fault -> shutdown */
318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
319 return;
320 }
321 class1 = exception_class(prev_nr);
322 class2 = exception_class(nr);
323 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325 /* generate double fault per SDM Table 5-5 */
326 vcpu->arch.exception.pending = true;
327 vcpu->arch.exception.has_error_code = true;
328 vcpu->arch.exception.nr = DF_VECTOR;
329 vcpu->arch.exception.error_code = 0;
330 } else
331 /* replace previous exception with a new one in a hope
332 that instruction re-execution will regenerate lost
333 exception */
334 goto queue;
335 }
336
337 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
338 {
339 kvm_multiple_exception(vcpu, nr, false, 0, false);
340 }
341 EXPORT_SYMBOL_GPL(kvm_queue_exception);
342
343 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344 {
345 kvm_multiple_exception(vcpu, nr, false, 0, true);
346 }
347 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
348
349 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
350 {
351 if (err)
352 kvm_inject_gp(vcpu, 0);
353 else
354 kvm_x86_ops->skip_emulated_instruction(vcpu);
355 }
356 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
357
358 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360 ++vcpu->stat.pf_guest;
361 vcpu->arch.cr2 = fault->address;
362 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
363 }
364 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
365
366 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
367 {
368 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
370 else
371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
372 }
373
374 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
375 {
376 atomic_inc(&vcpu->arch.nmi_queued);
377 kvm_make_request(KVM_REQ_NMI, vcpu);
378 }
379 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
380
381 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
382 {
383 kvm_multiple_exception(vcpu, nr, true, error_code, false);
384 }
385 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
386
387 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388 {
389 kvm_multiple_exception(vcpu, nr, true, error_code, true);
390 }
391 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
392
393 /*
394 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
395 * a #GP and return false.
396 */
397 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
398 {
399 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
400 return true;
401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
402 return false;
403 }
404 EXPORT_SYMBOL_GPL(kvm_require_cpl);
405
406 /*
407 * This function will be used to read from the physical memory of the currently
408 * running guest. The difference to kvm_read_guest_page is that this function
409 * can read from guest physical or from the guest's guest physical memory.
410 */
411 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412 gfn_t ngfn, void *data, int offset, int len,
413 u32 access)
414 {
415 gfn_t real_gfn;
416 gpa_t ngpa;
417
418 ngpa = gfn_to_gpa(ngfn);
419 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420 if (real_gfn == UNMAPPED_GVA)
421 return -EFAULT;
422
423 real_gfn = gpa_to_gfn(real_gfn);
424
425 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
426 }
427 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
428
429 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430 void *data, int offset, int len, u32 access)
431 {
432 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433 data, offset, len, access);
434 }
435
436 /*
437 * Load the pae pdptrs. Return true is they are all valid.
438 */
439 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
440 {
441 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
443 int i;
444 int ret;
445 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
446
447 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448 offset * sizeof(u64), sizeof(pdpte),
449 PFERR_USER_MASK|PFERR_WRITE_MASK);
450 if (ret < 0) {
451 ret = 0;
452 goto out;
453 }
454 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
455 if (is_present_gpte(pdpte[i]) &&
456 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
457 ret = 0;
458 goto out;
459 }
460 }
461 ret = 1;
462
463 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
464 __set_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail);
466 __set_bit(VCPU_EXREG_PDPTR,
467 (unsigned long *)&vcpu->arch.regs_dirty);
468 out:
469
470 return ret;
471 }
472 EXPORT_SYMBOL_GPL(load_pdptrs);
473
474 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475 {
476 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
477 bool changed = true;
478 int offset;
479 gfn_t gfn;
480 int r;
481
482 if (is_long_mode(vcpu) || !is_pae(vcpu))
483 return false;
484
485 if (!test_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail))
487 return true;
488
489 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
491 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492 PFERR_USER_MASK | PFERR_WRITE_MASK);
493 if (r < 0)
494 goto out;
495 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
496 out:
497
498 return changed;
499 }
500
501 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
502 {
503 unsigned long old_cr0 = kvm_read_cr0(vcpu);
504 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505 X86_CR0_CD | X86_CR0_NW;
506
507 cr0 |= X86_CR0_ET;
508
509 #ifdef CONFIG_X86_64
510 if (cr0 & 0xffffffff00000000UL)
511 return 1;
512 #endif
513
514 cr0 &= ~CR0_RESERVED_BITS;
515
516 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
517 return 1;
518
519 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
520 return 1;
521
522 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
523 #ifdef CONFIG_X86_64
524 if ((vcpu->arch.efer & EFER_LME)) {
525 int cs_db, cs_l;
526
527 if (!is_pae(vcpu))
528 return 1;
529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
530 if (cs_l)
531 return 1;
532 } else
533 #endif
534 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
535 kvm_read_cr3(vcpu)))
536 return 1;
537 }
538
539 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
540 return 1;
541
542 kvm_x86_ops->set_cr0(vcpu, cr0);
543
544 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
545 kvm_clear_async_pf_completion_queue(vcpu);
546 kvm_async_pf_hash_reset(vcpu);
547 }
548
549 if ((cr0 ^ old_cr0) & update_bits)
550 kvm_mmu_reset_context(vcpu);
551 return 0;
552 }
553 EXPORT_SYMBOL_GPL(kvm_set_cr0);
554
555 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
556 {
557 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
558 }
559 EXPORT_SYMBOL_GPL(kvm_lmsw);
560
561 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
562 {
563 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564 !vcpu->guest_xcr0_loaded) {
565 /* kvm_set_xcr() also depends on this */
566 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567 vcpu->guest_xcr0_loaded = 1;
568 }
569 }
570
571 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
572 {
573 if (vcpu->guest_xcr0_loaded) {
574 if (vcpu->arch.xcr0 != host_xcr0)
575 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576 vcpu->guest_xcr0_loaded = 0;
577 }
578 }
579
580 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581 {
582 u64 xcr0;
583
584 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
585 if (index != XCR_XFEATURE_ENABLED_MASK)
586 return 1;
587 xcr0 = xcr;
588 if (!(xcr0 & XSTATE_FP))
589 return 1;
590 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
591 return 1;
592 if (xcr0 & ~host_xcr0)
593 return 1;
594 kvm_put_guest_xcr0(vcpu);
595 vcpu->arch.xcr0 = xcr0;
596 return 0;
597 }
598
599 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
600 {
601 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
602 __kvm_set_xcr(vcpu, index, xcr)) {
603 kvm_inject_gp(vcpu, 0);
604 return 1;
605 }
606 return 0;
607 }
608 EXPORT_SYMBOL_GPL(kvm_set_xcr);
609
610 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
611 {
612 unsigned long old_cr4 = kvm_read_cr4(vcpu);
613 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
614 X86_CR4_PAE | X86_CR4_SMEP;
615 if (cr4 & CR4_RESERVED_BITS)
616 return 1;
617
618 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
619 return 1;
620
621 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
622 return 1;
623
624 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
625 return 1;
626
627 if (is_long_mode(vcpu)) {
628 if (!(cr4 & X86_CR4_PAE))
629 return 1;
630 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
631 && ((cr4 ^ old_cr4) & pdptr_bits)
632 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
633 kvm_read_cr3(vcpu)))
634 return 1;
635
636 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
637 if (!guest_cpuid_has_pcid(vcpu))
638 return 1;
639
640 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
641 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
642 return 1;
643 }
644
645 if (kvm_x86_ops->set_cr4(vcpu, cr4))
646 return 1;
647
648 if (((cr4 ^ old_cr4) & pdptr_bits) ||
649 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
650 kvm_mmu_reset_context(vcpu);
651
652 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
653 kvm_update_cpuid(vcpu);
654
655 return 0;
656 }
657 EXPORT_SYMBOL_GPL(kvm_set_cr4);
658
659 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
660 {
661 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
662 kvm_mmu_sync_roots(vcpu);
663 kvm_mmu_flush_tlb(vcpu);
664 return 0;
665 }
666
667 if (is_long_mode(vcpu)) {
668 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
669 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
670 return 1;
671 } else
672 if (cr3 & CR3_L_MODE_RESERVED_BITS)
673 return 1;
674 } else {
675 if (is_pae(vcpu)) {
676 if (cr3 & CR3_PAE_RESERVED_BITS)
677 return 1;
678 if (is_paging(vcpu) &&
679 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
680 return 1;
681 }
682 /*
683 * We don't check reserved bits in nonpae mode, because
684 * this isn't enforced, and VMware depends on this.
685 */
686 }
687
688 vcpu->arch.cr3 = cr3;
689 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
690 vcpu->arch.mmu.new_cr3(vcpu);
691 return 0;
692 }
693 EXPORT_SYMBOL_GPL(kvm_set_cr3);
694
695 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
696 {
697 if (cr8 & CR8_RESERVED_BITS)
698 return 1;
699 if (irqchip_in_kernel(vcpu->kvm))
700 kvm_lapic_set_tpr(vcpu, cr8);
701 else
702 vcpu->arch.cr8 = cr8;
703 return 0;
704 }
705 EXPORT_SYMBOL_GPL(kvm_set_cr8);
706
707 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
708 {
709 if (irqchip_in_kernel(vcpu->kvm))
710 return kvm_lapic_get_cr8(vcpu);
711 else
712 return vcpu->arch.cr8;
713 }
714 EXPORT_SYMBOL_GPL(kvm_get_cr8);
715
716 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
717 {
718 unsigned long dr7;
719
720 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
721 dr7 = vcpu->arch.guest_debug_dr7;
722 else
723 dr7 = vcpu->arch.dr7;
724 kvm_x86_ops->set_dr7(vcpu, dr7);
725 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
726 }
727
728 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
729 {
730 switch (dr) {
731 case 0 ... 3:
732 vcpu->arch.db[dr] = val;
733 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
734 vcpu->arch.eff_db[dr] = val;
735 break;
736 case 4:
737 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
738 return 1; /* #UD */
739 /* fall through */
740 case 6:
741 if (val & 0xffffffff00000000ULL)
742 return -1; /* #GP */
743 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
744 break;
745 case 5:
746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747 return 1; /* #UD */
748 /* fall through */
749 default: /* 7 */
750 if (val & 0xffffffff00000000ULL)
751 return -1; /* #GP */
752 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
753 kvm_update_dr7(vcpu);
754 break;
755 }
756
757 return 0;
758 }
759
760 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
761 {
762 int res;
763
764 res = __kvm_set_dr(vcpu, dr, val);
765 if (res > 0)
766 kvm_queue_exception(vcpu, UD_VECTOR);
767 else if (res < 0)
768 kvm_inject_gp(vcpu, 0);
769
770 return res;
771 }
772 EXPORT_SYMBOL_GPL(kvm_set_dr);
773
774 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
775 {
776 switch (dr) {
777 case 0 ... 3:
778 *val = vcpu->arch.db[dr];
779 break;
780 case 4:
781 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
782 return 1;
783 /* fall through */
784 case 6:
785 *val = vcpu->arch.dr6;
786 break;
787 case 5:
788 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
789 return 1;
790 /* fall through */
791 default: /* 7 */
792 *val = vcpu->arch.dr7;
793 break;
794 }
795
796 return 0;
797 }
798
799 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
800 {
801 if (_kvm_get_dr(vcpu, dr, val)) {
802 kvm_queue_exception(vcpu, UD_VECTOR);
803 return 1;
804 }
805 return 0;
806 }
807 EXPORT_SYMBOL_GPL(kvm_get_dr);
808
809 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
810 {
811 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
812 u64 data;
813 int err;
814
815 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
816 if (err)
817 return err;
818 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
819 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
820 return err;
821 }
822 EXPORT_SYMBOL_GPL(kvm_rdpmc);
823
824 /*
825 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
826 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
827 *
828 * This list is modified at module load time to reflect the
829 * capabilities of the host cpu. This capabilities test skips MSRs that are
830 * kvm-specific. Those are put in the beginning of the list.
831 */
832
833 #define KVM_SAVE_MSRS_BEGIN 10
834 static u32 msrs_to_save[] = {
835 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
836 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
837 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
838 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
839 MSR_KVM_PV_EOI_EN,
840 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
841 MSR_STAR,
842 #ifdef CONFIG_X86_64
843 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
844 #endif
845 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
846 MSR_IA32_FEATURE_CONTROL
847 };
848
849 static unsigned num_msrs_to_save;
850
851 static const u32 emulated_msrs[] = {
852 MSR_IA32_TSC_ADJUST,
853 MSR_IA32_TSCDEADLINE,
854 MSR_IA32_MISC_ENABLE,
855 MSR_IA32_MCG_STATUS,
856 MSR_IA32_MCG_CTL,
857 };
858
859 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
860 {
861 if (efer & efer_reserved_bits)
862 return false;
863
864 if (efer & EFER_FFXSR) {
865 struct kvm_cpuid_entry2 *feat;
866
867 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
868 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
869 return false;
870 }
871
872 if (efer & EFER_SVME) {
873 struct kvm_cpuid_entry2 *feat;
874
875 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
876 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
877 return false;
878 }
879
880 return true;
881 }
882 EXPORT_SYMBOL_GPL(kvm_valid_efer);
883
884 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
885 {
886 u64 old_efer = vcpu->arch.efer;
887
888 if (!kvm_valid_efer(vcpu, efer))
889 return 1;
890
891 if (is_paging(vcpu)
892 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
893 return 1;
894
895 efer &= ~EFER_LMA;
896 efer |= vcpu->arch.efer & EFER_LMA;
897
898 kvm_x86_ops->set_efer(vcpu, efer);
899
900 /* Update reserved bits */
901 if ((efer ^ old_efer) & EFER_NX)
902 kvm_mmu_reset_context(vcpu);
903
904 return 0;
905 }
906
907 void kvm_enable_efer_bits(u64 mask)
908 {
909 efer_reserved_bits &= ~mask;
910 }
911 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
912
913
914 /*
915 * Writes msr value into into the appropriate "register".
916 * Returns 0 on success, non-0 otherwise.
917 * Assumes vcpu_load() was already called.
918 */
919 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
920 {
921 return kvm_x86_ops->set_msr(vcpu, msr);
922 }
923
924 /*
925 * Adapt set_msr() to msr_io()'s calling convention
926 */
927 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
928 {
929 struct msr_data msr;
930
931 msr.data = *data;
932 msr.index = index;
933 msr.host_initiated = true;
934 return kvm_set_msr(vcpu, &msr);
935 }
936
937 #ifdef CONFIG_X86_64
938 struct pvclock_gtod_data {
939 seqcount_t seq;
940
941 struct { /* extract of a clocksource struct */
942 int vclock_mode;
943 cycle_t cycle_last;
944 cycle_t mask;
945 u32 mult;
946 u32 shift;
947 } clock;
948
949 /* open coded 'struct timespec' */
950 u64 monotonic_time_snsec;
951 time_t monotonic_time_sec;
952 };
953
954 static struct pvclock_gtod_data pvclock_gtod_data;
955
956 static void update_pvclock_gtod(struct timekeeper *tk)
957 {
958 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
959
960 write_seqcount_begin(&vdata->seq);
961
962 /* copy pvclock gtod data */
963 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
964 vdata->clock.cycle_last = tk->clock->cycle_last;
965 vdata->clock.mask = tk->clock->mask;
966 vdata->clock.mult = tk->mult;
967 vdata->clock.shift = tk->shift;
968
969 vdata->monotonic_time_sec = tk->xtime_sec
970 + tk->wall_to_monotonic.tv_sec;
971 vdata->monotonic_time_snsec = tk->xtime_nsec
972 + (tk->wall_to_monotonic.tv_nsec
973 << tk->shift);
974 while (vdata->monotonic_time_snsec >=
975 (((u64)NSEC_PER_SEC) << tk->shift)) {
976 vdata->monotonic_time_snsec -=
977 ((u64)NSEC_PER_SEC) << tk->shift;
978 vdata->monotonic_time_sec++;
979 }
980
981 write_seqcount_end(&vdata->seq);
982 }
983 #endif
984
985
986 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
987 {
988 int version;
989 int r;
990 struct pvclock_wall_clock wc;
991 struct timespec boot;
992
993 if (!wall_clock)
994 return;
995
996 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
997 if (r)
998 return;
999
1000 if (version & 1)
1001 ++version; /* first time write, random junk */
1002
1003 ++version;
1004
1005 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1006
1007 /*
1008 * The guest calculates current wall clock time by adding
1009 * system time (updated by kvm_guest_time_update below) to the
1010 * wall clock specified here. guest system time equals host
1011 * system time for us, thus we must fill in host boot time here.
1012 */
1013 getboottime(&boot);
1014
1015 if (kvm->arch.kvmclock_offset) {
1016 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1017 boot = timespec_sub(boot, ts);
1018 }
1019 wc.sec = boot.tv_sec;
1020 wc.nsec = boot.tv_nsec;
1021 wc.version = version;
1022
1023 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1024
1025 version++;
1026 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1027 }
1028
1029 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1030 {
1031 uint32_t quotient, remainder;
1032
1033 /* Don't try to replace with do_div(), this one calculates
1034 * "(dividend << 32) / divisor" */
1035 __asm__ ( "divl %4"
1036 : "=a" (quotient), "=d" (remainder)
1037 : "0" (0), "1" (dividend), "r" (divisor) );
1038 return quotient;
1039 }
1040
1041 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1042 s8 *pshift, u32 *pmultiplier)
1043 {
1044 uint64_t scaled64;
1045 int32_t shift = 0;
1046 uint64_t tps64;
1047 uint32_t tps32;
1048
1049 tps64 = base_khz * 1000LL;
1050 scaled64 = scaled_khz * 1000LL;
1051 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1052 tps64 >>= 1;
1053 shift--;
1054 }
1055
1056 tps32 = (uint32_t)tps64;
1057 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1058 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1059 scaled64 >>= 1;
1060 else
1061 tps32 <<= 1;
1062 shift++;
1063 }
1064
1065 *pshift = shift;
1066 *pmultiplier = div_frac(scaled64, tps32);
1067
1068 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1069 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1070 }
1071
1072 static inline u64 get_kernel_ns(void)
1073 {
1074 struct timespec ts;
1075
1076 ktime_get_ts(&ts);
1077 monotonic_to_bootbased(&ts);
1078 return timespec_to_ns(&ts);
1079 }
1080
1081 #ifdef CONFIG_X86_64
1082 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1083 #endif
1084
1085 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1086 unsigned long max_tsc_khz;
1087
1088 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1089 {
1090 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1091 vcpu->arch.virtual_tsc_shift);
1092 }
1093
1094 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1095 {
1096 u64 v = (u64)khz * (1000000 + ppm);
1097 do_div(v, 1000000);
1098 return v;
1099 }
1100
1101 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1102 {
1103 u32 thresh_lo, thresh_hi;
1104 int use_scaling = 0;
1105
1106 /* tsc_khz can be zero if TSC calibration fails */
1107 if (this_tsc_khz == 0)
1108 return;
1109
1110 /* Compute a scale to convert nanoseconds in TSC cycles */
1111 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1112 &vcpu->arch.virtual_tsc_shift,
1113 &vcpu->arch.virtual_tsc_mult);
1114 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1115
1116 /*
1117 * Compute the variation in TSC rate which is acceptable
1118 * within the range of tolerance and decide if the
1119 * rate being applied is within that bounds of the hardware
1120 * rate. If so, no scaling or compensation need be done.
1121 */
1122 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1123 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1124 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1125 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1126 use_scaling = 1;
1127 }
1128 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1129 }
1130
1131 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1132 {
1133 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1134 vcpu->arch.virtual_tsc_mult,
1135 vcpu->arch.virtual_tsc_shift);
1136 tsc += vcpu->arch.this_tsc_write;
1137 return tsc;
1138 }
1139
1140 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1141 {
1142 #ifdef CONFIG_X86_64
1143 bool vcpus_matched;
1144 bool do_request = false;
1145 struct kvm_arch *ka = &vcpu->kvm->arch;
1146 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1147
1148 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1149 atomic_read(&vcpu->kvm->online_vcpus));
1150
1151 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1152 if (!ka->use_master_clock)
1153 do_request = 1;
1154
1155 if (!vcpus_matched && ka->use_master_clock)
1156 do_request = 1;
1157
1158 if (do_request)
1159 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1160
1161 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1162 atomic_read(&vcpu->kvm->online_vcpus),
1163 ka->use_master_clock, gtod->clock.vclock_mode);
1164 #endif
1165 }
1166
1167 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1168 {
1169 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1170 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1171 }
1172
1173 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1174 {
1175 struct kvm *kvm = vcpu->kvm;
1176 u64 offset, ns, elapsed;
1177 unsigned long flags;
1178 s64 usdiff;
1179 bool matched;
1180 u64 data = msr->data;
1181
1182 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1183 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1184 ns = get_kernel_ns();
1185 elapsed = ns - kvm->arch.last_tsc_nsec;
1186
1187 if (vcpu->arch.virtual_tsc_khz) {
1188 int faulted = 0;
1189
1190 /* n.b - signed multiplication and division required */
1191 usdiff = data - kvm->arch.last_tsc_write;
1192 #ifdef CONFIG_X86_64
1193 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1194 #else
1195 /* do_div() only does unsigned */
1196 asm("1: idivl %[divisor]\n"
1197 "2: xor %%edx, %%edx\n"
1198 " movl $0, %[faulted]\n"
1199 "3:\n"
1200 ".section .fixup,\"ax\"\n"
1201 "4: movl $1, %[faulted]\n"
1202 " jmp 3b\n"
1203 ".previous\n"
1204
1205 _ASM_EXTABLE(1b, 4b)
1206
1207 : "=A"(usdiff), [faulted] "=r" (faulted)
1208 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1209
1210 #endif
1211 do_div(elapsed, 1000);
1212 usdiff -= elapsed;
1213 if (usdiff < 0)
1214 usdiff = -usdiff;
1215
1216 /* idivl overflow => difference is larger than USEC_PER_SEC */
1217 if (faulted)
1218 usdiff = USEC_PER_SEC;
1219 } else
1220 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1221
1222 /*
1223 * Special case: TSC write with a small delta (1 second) of virtual
1224 * cycle time against real time is interpreted as an attempt to
1225 * synchronize the CPU.
1226 *
1227 * For a reliable TSC, we can match TSC offsets, and for an unstable
1228 * TSC, we add elapsed time in this computation. We could let the
1229 * compensation code attempt to catch up if we fall behind, but
1230 * it's better to try to match offsets from the beginning.
1231 */
1232 if (usdiff < USEC_PER_SEC &&
1233 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1234 if (!check_tsc_unstable()) {
1235 offset = kvm->arch.cur_tsc_offset;
1236 pr_debug("kvm: matched tsc offset for %llu\n", data);
1237 } else {
1238 u64 delta = nsec_to_cycles(vcpu, elapsed);
1239 data += delta;
1240 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1241 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1242 }
1243 matched = true;
1244 } else {
1245 /*
1246 * We split periods of matched TSC writes into generations.
1247 * For each generation, we track the original measured
1248 * nanosecond time, offset, and write, so if TSCs are in
1249 * sync, we can match exact offset, and if not, we can match
1250 * exact software computation in compute_guest_tsc()
1251 *
1252 * These values are tracked in kvm->arch.cur_xxx variables.
1253 */
1254 kvm->arch.cur_tsc_generation++;
1255 kvm->arch.cur_tsc_nsec = ns;
1256 kvm->arch.cur_tsc_write = data;
1257 kvm->arch.cur_tsc_offset = offset;
1258 matched = false;
1259 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1260 kvm->arch.cur_tsc_generation, data);
1261 }
1262
1263 /*
1264 * We also track th most recent recorded KHZ, write and time to
1265 * allow the matching interval to be extended at each write.
1266 */
1267 kvm->arch.last_tsc_nsec = ns;
1268 kvm->arch.last_tsc_write = data;
1269 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1270
1271 /* Reset of TSC must disable overshoot protection below */
1272 vcpu->arch.hv_clock.tsc_timestamp = 0;
1273 vcpu->arch.last_guest_tsc = data;
1274
1275 /* Keep track of which generation this VCPU has synchronized to */
1276 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1277 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1278 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1279
1280 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1281 update_ia32_tsc_adjust_msr(vcpu, offset);
1282 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1283 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1284
1285 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1286 if (matched)
1287 kvm->arch.nr_vcpus_matched_tsc++;
1288 else
1289 kvm->arch.nr_vcpus_matched_tsc = 0;
1290
1291 kvm_track_tsc_matching(vcpu);
1292 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1293 }
1294
1295 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1296
1297 #ifdef CONFIG_X86_64
1298
1299 static cycle_t read_tsc(void)
1300 {
1301 cycle_t ret;
1302 u64 last;
1303
1304 /*
1305 * Empirically, a fence (of type that depends on the CPU)
1306 * before rdtsc is enough to ensure that rdtsc is ordered
1307 * with respect to loads. The various CPU manuals are unclear
1308 * as to whether rdtsc can be reordered with later loads,
1309 * but no one has ever seen it happen.
1310 */
1311 rdtsc_barrier();
1312 ret = (cycle_t)vget_cycles();
1313
1314 last = pvclock_gtod_data.clock.cycle_last;
1315
1316 if (likely(ret >= last))
1317 return ret;
1318
1319 /*
1320 * GCC likes to generate cmov here, but this branch is extremely
1321 * predictable (it's just a funciton of time and the likely is
1322 * very likely) and there's a data dependence, so force GCC
1323 * to generate a branch instead. I don't barrier() because
1324 * we don't actually need a barrier, and if this function
1325 * ever gets inlined it will generate worse code.
1326 */
1327 asm volatile ("");
1328 return last;
1329 }
1330
1331 static inline u64 vgettsc(cycle_t *cycle_now)
1332 {
1333 long v;
1334 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1335
1336 *cycle_now = read_tsc();
1337
1338 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1339 return v * gtod->clock.mult;
1340 }
1341
1342 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1343 {
1344 unsigned long seq;
1345 u64 ns;
1346 int mode;
1347 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1348
1349 ts->tv_nsec = 0;
1350 do {
1351 seq = read_seqcount_begin(&gtod->seq);
1352 mode = gtod->clock.vclock_mode;
1353 ts->tv_sec = gtod->monotonic_time_sec;
1354 ns = gtod->monotonic_time_snsec;
1355 ns += vgettsc(cycle_now);
1356 ns >>= gtod->clock.shift;
1357 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1358 timespec_add_ns(ts, ns);
1359
1360 return mode;
1361 }
1362
1363 /* returns true if host is using tsc clocksource */
1364 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1365 {
1366 struct timespec ts;
1367
1368 /* checked again under seqlock below */
1369 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1370 return false;
1371
1372 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1373 return false;
1374
1375 monotonic_to_bootbased(&ts);
1376 *kernel_ns = timespec_to_ns(&ts);
1377
1378 return true;
1379 }
1380 #endif
1381
1382 /*
1383 *
1384 * Assuming a stable TSC across physical CPUS, and a stable TSC
1385 * across virtual CPUs, the following condition is possible.
1386 * Each numbered line represents an event visible to both
1387 * CPUs at the next numbered event.
1388 *
1389 * "timespecX" represents host monotonic time. "tscX" represents
1390 * RDTSC value.
1391 *
1392 * VCPU0 on CPU0 | VCPU1 on CPU1
1393 *
1394 * 1. read timespec0,tsc0
1395 * 2. | timespec1 = timespec0 + N
1396 * | tsc1 = tsc0 + M
1397 * 3. transition to guest | transition to guest
1398 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1399 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1400 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1401 *
1402 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1403 *
1404 * - ret0 < ret1
1405 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1406 * ...
1407 * - 0 < N - M => M < N
1408 *
1409 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1410 * always the case (the difference between two distinct xtime instances
1411 * might be smaller then the difference between corresponding TSC reads,
1412 * when updating guest vcpus pvclock areas).
1413 *
1414 * To avoid that problem, do not allow visibility of distinct
1415 * system_timestamp/tsc_timestamp values simultaneously: use a master
1416 * copy of host monotonic time values. Update that master copy
1417 * in lockstep.
1418 *
1419 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1420 *
1421 */
1422
1423 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1424 {
1425 #ifdef CONFIG_X86_64
1426 struct kvm_arch *ka = &kvm->arch;
1427 int vclock_mode;
1428 bool host_tsc_clocksource, vcpus_matched;
1429
1430 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1431 atomic_read(&kvm->online_vcpus));
1432
1433 /*
1434 * If the host uses TSC clock, then passthrough TSC as stable
1435 * to the guest.
1436 */
1437 host_tsc_clocksource = kvm_get_time_and_clockread(
1438 &ka->master_kernel_ns,
1439 &ka->master_cycle_now);
1440
1441 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1442
1443 if (ka->use_master_clock)
1444 atomic_set(&kvm_guest_has_master_clock, 1);
1445
1446 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1447 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1448 vcpus_matched);
1449 #endif
1450 }
1451
1452 static void kvm_gen_update_masterclock(struct kvm *kvm)
1453 {
1454 #ifdef CONFIG_X86_64
1455 int i;
1456 struct kvm_vcpu *vcpu;
1457 struct kvm_arch *ka = &kvm->arch;
1458
1459 spin_lock(&ka->pvclock_gtod_sync_lock);
1460 kvm_make_mclock_inprogress_request(kvm);
1461 /* no guest entries from this point */
1462 pvclock_update_vm_gtod_copy(kvm);
1463
1464 kvm_for_each_vcpu(i, vcpu, kvm)
1465 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1466
1467 /* guest entries allowed */
1468 kvm_for_each_vcpu(i, vcpu, kvm)
1469 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1470
1471 spin_unlock(&ka->pvclock_gtod_sync_lock);
1472 #endif
1473 }
1474
1475 static int kvm_guest_time_update(struct kvm_vcpu *v)
1476 {
1477 unsigned long flags, this_tsc_khz;
1478 struct kvm_vcpu_arch *vcpu = &v->arch;
1479 struct kvm_arch *ka = &v->kvm->arch;
1480 s64 kernel_ns, max_kernel_ns;
1481 u64 tsc_timestamp, host_tsc;
1482 struct pvclock_vcpu_time_info guest_hv_clock;
1483 u8 pvclock_flags;
1484 bool use_master_clock;
1485
1486 kernel_ns = 0;
1487 host_tsc = 0;
1488
1489 /*
1490 * If the host uses TSC clock, then passthrough TSC as stable
1491 * to the guest.
1492 */
1493 spin_lock(&ka->pvclock_gtod_sync_lock);
1494 use_master_clock = ka->use_master_clock;
1495 if (use_master_clock) {
1496 host_tsc = ka->master_cycle_now;
1497 kernel_ns = ka->master_kernel_ns;
1498 }
1499 spin_unlock(&ka->pvclock_gtod_sync_lock);
1500
1501 /* Keep irq disabled to prevent changes to the clock */
1502 local_irq_save(flags);
1503 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1504 if (unlikely(this_tsc_khz == 0)) {
1505 local_irq_restore(flags);
1506 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1507 return 1;
1508 }
1509 if (!use_master_clock) {
1510 host_tsc = native_read_tsc();
1511 kernel_ns = get_kernel_ns();
1512 }
1513
1514 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1515
1516 /*
1517 * We may have to catch up the TSC to match elapsed wall clock
1518 * time for two reasons, even if kvmclock is used.
1519 * 1) CPU could have been running below the maximum TSC rate
1520 * 2) Broken TSC compensation resets the base at each VCPU
1521 * entry to avoid unknown leaps of TSC even when running
1522 * again on the same CPU. This may cause apparent elapsed
1523 * time to disappear, and the guest to stand still or run
1524 * very slowly.
1525 */
1526 if (vcpu->tsc_catchup) {
1527 u64 tsc = compute_guest_tsc(v, kernel_ns);
1528 if (tsc > tsc_timestamp) {
1529 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1530 tsc_timestamp = tsc;
1531 }
1532 }
1533
1534 local_irq_restore(flags);
1535
1536 if (!vcpu->pv_time_enabled)
1537 return 0;
1538
1539 /*
1540 * Time as measured by the TSC may go backwards when resetting the base
1541 * tsc_timestamp. The reason for this is that the TSC resolution is
1542 * higher than the resolution of the other clock scales. Thus, many
1543 * possible measurments of the TSC correspond to one measurement of any
1544 * other clock, and so a spread of values is possible. This is not a
1545 * problem for the computation of the nanosecond clock; with TSC rates
1546 * around 1GHZ, there can only be a few cycles which correspond to one
1547 * nanosecond value, and any path through this code will inevitably
1548 * take longer than that. However, with the kernel_ns value itself,
1549 * the precision may be much lower, down to HZ granularity. If the
1550 * first sampling of TSC against kernel_ns ends in the low part of the
1551 * range, and the second in the high end of the range, we can get:
1552 *
1553 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1554 *
1555 * As the sampling errors potentially range in the thousands of cycles,
1556 * it is possible such a time value has already been observed by the
1557 * guest. To protect against this, we must compute the system time as
1558 * observed by the guest and ensure the new system time is greater.
1559 */
1560 max_kernel_ns = 0;
1561 if (vcpu->hv_clock.tsc_timestamp) {
1562 max_kernel_ns = vcpu->last_guest_tsc -
1563 vcpu->hv_clock.tsc_timestamp;
1564 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1565 vcpu->hv_clock.tsc_to_system_mul,
1566 vcpu->hv_clock.tsc_shift);
1567 max_kernel_ns += vcpu->last_kernel_ns;
1568 }
1569
1570 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1571 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1572 &vcpu->hv_clock.tsc_shift,
1573 &vcpu->hv_clock.tsc_to_system_mul);
1574 vcpu->hw_tsc_khz = this_tsc_khz;
1575 }
1576
1577 /* with a master <monotonic time, tsc value> tuple,
1578 * pvclock clock reads always increase at the (scaled) rate
1579 * of guest TSC - no need to deal with sampling errors.
1580 */
1581 if (!use_master_clock) {
1582 if (max_kernel_ns > kernel_ns)
1583 kernel_ns = max_kernel_ns;
1584 }
1585 /* With all the info we got, fill in the values */
1586 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1587 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1588 vcpu->last_kernel_ns = kernel_ns;
1589 vcpu->last_guest_tsc = tsc_timestamp;
1590
1591 /*
1592 * The interface expects us to write an even number signaling that the
1593 * update is finished. Since the guest won't see the intermediate
1594 * state, we just increase by 2 at the end.
1595 */
1596 vcpu->hv_clock.version += 2;
1597
1598 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1599 &guest_hv_clock, sizeof(guest_hv_clock))))
1600 return 0;
1601
1602 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1603 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1604
1605 if (vcpu->pvclock_set_guest_stopped_request) {
1606 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1607 vcpu->pvclock_set_guest_stopped_request = false;
1608 }
1609
1610 /* If the host uses TSC clocksource, then it is stable */
1611 if (use_master_clock)
1612 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1613
1614 vcpu->hv_clock.flags = pvclock_flags;
1615
1616 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1617 &vcpu->hv_clock,
1618 sizeof(vcpu->hv_clock));
1619 return 0;
1620 }
1621
1622 /*
1623 * kvmclock updates which are isolated to a given vcpu, such as
1624 * vcpu->cpu migration, should not allow system_timestamp from
1625 * the rest of the vcpus to remain static. Otherwise ntp frequency
1626 * correction applies to one vcpu's system_timestamp but not
1627 * the others.
1628 *
1629 * So in those cases, request a kvmclock update for all vcpus.
1630 * The worst case for a remote vcpu to update its kvmclock
1631 * is then bounded by maximum nohz sleep latency.
1632 */
1633
1634 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1635 {
1636 int i;
1637 struct kvm *kvm = v->kvm;
1638 struct kvm_vcpu *vcpu;
1639
1640 kvm_for_each_vcpu(i, vcpu, kvm) {
1641 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1642 kvm_vcpu_kick(vcpu);
1643 }
1644 }
1645
1646 static bool msr_mtrr_valid(unsigned msr)
1647 {
1648 switch (msr) {
1649 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1650 case MSR_MTRRfix64K_00000:
1651 case MSR_MTRRfix16K_80000:
1652 case MSR_MTRRfix16K_A0000:
1653 case MSR_MTRRfix4K_C0000:
1654 case MSR_MTRRfix4K_C8000:
1655 case MSR_MTRRfix4K_D0000:
1656 case MSR_MTRRfix4K_D8000:
1657 case MSR_MTRRfix4K_E0000:
1658 case MSR_MTRRfix4K_E8000:
1659 case MSR_MTRRfix4K_F0000:
1660 case MSR_MTRRfix4K_F8000:
1661 case MSR_MTRRdefType:
1662 case MSR_IA32_CR_PAT:
1663 return true;
1664 case 0x2f8:
1665 return true;
1666 }
1667 return false;
1668 }
1669
1670 static bool valid_pat_type(unsigned t)
1671 {
1672 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1673 }
1674
1675 static bool valid_mtrr_type(unsigned t)
1676 {
1677 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1678 }
1679
1680 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1681 {
1682 int i;
1683
1684 if (!msr_mtrr_valid(msr))
1685 return false;
1686
1687 if (msr == MSR_IA32_CR_PAT) {
1688 for (i = 0; i < 8; i++)
1689 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1690 return false;
1691 return true;
1692 } else if (msr == MSR_MTRRdefType) {
1693 if (data & ~0xcff)
1694 return false;
1695 return valid_mtrr_type(data & 0xff);
1696 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1697 for (i = 0; i < 8 ; i++)
1698 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1699 return false;
1700 return true;
1701 }
1702
1703 /* variable MTRRs */
1704 return valid_mtrr_type(data & 0xff);
1705 }
1706
1707 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1708 {
1709 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1710
1711 if (!mtrr_valid(vcpu, msr, data))
1712 return 1;
1713
1714 if (msr == MSR_MTRRdefType) {
1715 vcpu->arch.mtrr_state.def_type = data;
1716 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1717 } else if (msr == MSR_MTRRfix64K_00000)
1718 p[0] = data;
1719 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1720 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1721 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1722 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1723 else if (msr == MSR_IA32_CR_PAT)
1724 vcpu->arch.pat = data;
1725 else { /* Variable MTRRs */
1726 int idx, is_mtrr_mask;
1727 u64 *pt;
1728
1729 idx = (msr - 0x200) / 2;
1730 is_mtrr_mask = msr - 0x200 - 2 * idx;
1731 if (!is_mtrr_mask)
1732 pt =
1733 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1734 else
1735 pt =
1736 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1737 *pt = data;
1738 }
1739
1740 kvm_mmu_reset_context(vcpu);
1741 return 0;
1742 }
1743
1744 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1745 {
1746 u64 mcg_cap = vcpu->arch.mcg_cap;
1747 unsigned bank_num = mcg_cap & 0xff;
1748
1749 switch (msr) {
1750 case MSR_IA32_MCG_STATUS:
1751 vcpu->arch.mcg_status = data;
1752 break;
1753 case MSR_IA32_MCG_CTL:
1754 if (!(mcg_cap & MCG_CTL_P))
1755 return 1;
1756 if (data != 0 && data != ~(u64)0)
1757 return -1;
1758 vcpu->arch.mcg_ctl = data;
1759 break;
1760 default:
1761 if (msr >= MSR_IA32_MC0_CTL &&
1762 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1763 u32 offset = msr - MSR_IA32_MC0_CTL;
1764 /* only 0 or all 1s can be written to IA32_MCi_CTL
1765 * some Linux kernels though clear bit 10 in bank 4 to
1766 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1767 * this to avoid an uncatched #GP in the guest
1768 */
1769 if ((offset & 0x3) == 0 &&
1770 data != 0 && (data | (1 << 10)) != ~(u64)0)
1771 return -1;
1772 vcpu->arch.mce_banks[offset] = data;
1773 break;
1774 }
1775 return 1;
1776 }
1777 return 0;
1778 }
1779
1780 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1781 {
1782 struct kvm *kvm = vcpu->kvm;
1783 int lm = is_long_mode(vcpu);
1784 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1785 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1786 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1787 : kvm->arch.xen_hvm_config.blob_size_32;
1788 u32 page_num = data & ~PAGE_MASK;
1789 u64 page_addr = data & PAGE_MASK;
1790 u8 *page;
1791 int r;
1792
1793 r = -E2BIG;
1794 if (page_num >= blob_size)
1795 goto out;
1796 r = -ENOMEM;
1797 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1798 if (IS_ERR(page)) {
1799 r = PTR_ERR(page);
1800 goto out;
1801 }
1802 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1803 goto out_free;
1804 r = 0;
1805 out_free:
1806 kfree(page);
1807 out:
1808 return r;
1809 }
1810
1811 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1812 {
1813 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1814 }
1815
1816 static bool kvm_hv_msr_partition_wide(u32 msr)
1817 {
1818 bool r = false;
1819 switch (msr) {
1820 case HV_X64_MSR_GUEST_OS_ID:
1821 case HV_X64_MSR_HYPERCALL:
1822 r = true;
1823 break;
1824 }
1825
1826 return r;
1827 }
1828
1829 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1830 {
1831 struct kvm *kvm = vcpu->kvm;
1832
1833 switch (msr) {
1834 case HV_X64_MSR_GUEST_OS_ID:
1835 kvm->arch.hv_guest_os_id = data;
1836 /* setting guest os id to zero disables hypercall page */
1837 if (!kvm->arch.hv_guest_os_id)
1838 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1839 break;
1840 case HV_X64_MSR_HYPERCALL: {
1841 u64 gfn;
1842 unsigned long addr;
1843 u8 instructions[4];
1844
1845 /* if guest os id is not set hypercall should remain disabled */
1846 if (!kvm->arch.hv_guest_os_id)
1847 break;
1848 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1849 kvm->arch.hv_hypercall = data;
1850 break;
1851 }
1852 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1853 addr = gfn_to_hva(kvm, gfn);
1854 if (kvm_is_error_hva(addr))
1855 return 1;
1856 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1857 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1858 if (__copy_to_user((void __user *)addr, instructions, 4))
1859 return 1;
1860 kvm->arch.hv_hypercall = data;
1861 break;
1862 }
1863 default:
1864 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1865 "data 0x%llx\n", msr, data);
1866 return 1;
1867 }
1868 return 0;
1869 }
1870
1871 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1872 {
1873 switch (msr) {
1874 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1875 unsigned long addr;
1876
1877 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1878 vcpu->arch.hv_vapic = data;
1879 break;
1880 }
1881 addr = gfn_to_hva(vcpu->kvm, data >>
1882 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1883 if (kvm_is_error_hva(addr))
1884 return 1;
1885 if (__clear_user((void __user *)addr, PAGE_SIZE))
1886 return 1;
1887 vcpu->arch.hv_vapic = data;
1888 break;
1889 }
1890 case HV_X64_MSR_EOI:
1891 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1892 case HV_X64_MSR_ICR:
1893 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1894 case HV_X64_MSR_TPR:
1895 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1896 default:
1897 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1898 "data 0x%llx\n", msr, data);
1899 return 1;
1900 }
1901
1902 return 0;
1903 }
1904
1905 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1906 {
1907 gpa_t gpa = data & ~0x3f;
1908
1909 /* Bits 2:5 are reserved, Should be zero */
1910 if (data & 0x3c)
1911 return 1;
1912
1913 vcpu->arch.apf.msr_val = data;
1914
1915 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1916 kvm_clear_async_pf_completion_queue(vcpu);
1917 kvm_async_pf_hash_reset(vcpu);
1918 return 0;
1919 }
1920
1921 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1922 sizeof(u32)))
1923 return 1;
1924
1925 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1926 kvm_async_pf_wakeup_all(vcpu);
1927 return 0;
1928 }
1929
1930 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1931 {
1932 vcpu->arch.pv_time_enabled = false;
1933 }
1934
1935 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1936 {
1937 u64 delta;
1938
1939 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1940 return;
1941
1942 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1943 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1944 vcpu->arch.st.accum_steal = delta;
1945 }
1946
1947 static void record_steal_time(struct kvm_vcpu *vcpu)
1948 {
1949 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1950 return;
1951
1952 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1953 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1954 return;
1955
1956 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1957 vcpu->arch.st.steal.version += 2;
1958 vcpu->arch.st.accum_steal = 0;
1959
1960 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1961 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1962 }
1963
1964 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1965 {
1966 bool pr = false;
1967 u32 msr = msr_info->index;
1968 u64 data = msr_info->data;
1969
1970 switch (msr) {
1971 case MSR_AMD64_NB_CFG:
1972 case MSR_IA32_UCODE_REV:
1973 case MSR_IA32_UCODE_WRITE:
1974 case MSR_VM_HSAVE_PA:
1975 case MSR_AMD64_PATCH_LOADER:
1976 case MSR_AMD64_BU_CFG2:
1977 break;
1978
1979 case MSR_EFER:
1980 return set_efer(vcpu, data);
1981 case MSR_K7_HWCR:
1982 data &= ~(u64)0x40; /* ignore flush filter disable */
1983 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1984 data &= ~(u64)0x8; /* ignore TLB cache disable */
1985 if (data != 0) {
1986 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1987 data);
1988 return 1;
1989 }
1990 break;
1991 case MSR_FAM10H_MMIO_CONF_BASE:
1992 if (data != 0) {
1993 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1994 "0x%llx\n", data);
1995 return 1;
1996 }
1997 break;
1998 case MSR_IA32_DEBUGCTLMSR:
1999 if (!data) {
2000 /* We support the non-activated case already */
2001 break;
2002 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2003 /* Values other than LBR and BTF are vendor-specific,
2004 thus reserved and should throw a #GP */
2005 return 1;
2006 }
2007 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2008 __func__, data);
2009 break;
2010 case 0x200 ... 0x2ff:
2011 return set_msr_mtrr(vcpu, msr, data);
2012 case MSR_IA32_APICBASE:
2013 kvm_set_apic_base(vcpu, data);
2014 break;
2015 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2016 return kvm_x2apic_msr_write(vcpu, msr, data);
2017 case MSR_IA32_TSCDEADLINE:
2018 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2019 break;
2020 case MSR_IA32_TSC_ADJUST:
2021 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2022 if (!msr_info->host_initiated) {
2023 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2024 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2025 }
2026 vcpu->arch.ia32_tsc_adjust_msr = data;
2027 }
2028 break;
2029 case MSR_IA32_MISC_ENABLE:
2030 vcpu->arch.ia32_misc_enable_msr = data;
2031 break;
2032 case MSR_KVM_WALL_CLOCK_NEW:
2033 case MSR_KVM_WALL_CLOCK:
2034 vcpu->kvm->arch.wall_clock = data;
2035 kvm_write_wall_clock(vcpu->kvm, data);
2036 break;
2037 case MSR_KVM_SYSTEM_TIME_NEW:
2038 case MSR_KVM_SYSTEM_TIME: {
2039 u64 gpa_offset;
2040 kvmclock_reset(vcpu);
2041
2042 vcpu->arch.time = data;
2043 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2044
2045 /* we verify if the enable bit is set... */
2046 if (!(data & 1))
2047 break;
2048
2049 gpa_offset = data & ~(PAGE_MASK | 1);
2050
2051 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2052 &vcpu->arch.pv_time, data & ~1ULL,
2053 sizeof(struct pvclock_vcpu_time_info)))
2054 vcpu->arch.pv_time_enabled = false;
2055 else
2056 vcpu->arch.pv_time_enabled = true;
2057
2058 break;
2059 }
2060 case MSR_KVM_ASYNC_PF_EN:
2061 if (kvm_pv_enable_async_pf(vcpu, data))
2062 return 1;
2063 break;
2064 case MSR_KVM_STEAL_TIME:
2065
2066 if (unlikely(!sched_info_on()))
2067 return 1;
2068
2069 if (data & KVM_STEAL_RESERVED_MASK)
2070 return 1;
2071
2072 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2073 data & KVM_STEAL_VALID_BITS,
2074 sizeof(struct kvm_steal_time)))
2075 return 1;
2076
2077 vcpu->arch.st.msr_val = data;
2078
2079 if (!(data & KVM_MSR_ENABLED))
2080 break;
2081
2082 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2083
2084 preempt_disable();
2085 accumulate_steal_time(vcpu);
2086 preempt_enable();
2087
2088 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2089
2090 break;
2091 case MSR_KVM_PV_EOI_EN:
2092 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2093 return 1;
2094 break;
2095
2096 case MSR_IA32_MCG_CTL:
2097 case MSR_IA32_MCG_STATUS:
2098 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2099 return set_msr_mce(vcpu, msr, data);
2100
2101 /* Performance counters are not protected by a CPUID bit,
2102 * so we should check all of them in the generic path for the sake of
2103 * cross vendor migration.
2104 * Writing a zero into the event select MSRs disables them,
2105 * which we perfectly emulate ;-). Any other value should be at least
2106 * reported, some guests depend on them.
2107 */
2108 case MSR_K7_EVNTSEL0:
2109 case MSR_K7_EVNTSEL1:
2110 case MSR_K7_EVNTSEL2:
2111 case MSR_K7_EVNTSEL3:
2112 if (data != 0)
2113 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2114 "0x%x data 0x%llx\n", msr, data);
2115 break;
2116 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2117 * so we ignore writes to make it happy.
2118 */
2119 case MSR_K7_PERFCTR0:
2120 case MSR_K7_PERFCTR1:
2121 case MSR_K7_PERFCTR2:
2122 case MSR_K7_PERFCTR3:
2123 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2124 "0x%x data 0x%llx\n", msr, data);
2125 break;
2126 case MSR_P6_PERFCTR0:
2127 case MSR_P6_PERFCTR1:
2128 pr = true;
2129 case MSR_P6_EVNTSEL0:
2130 case MSR_P6_EVNTSEL1:
2131 if (kvm_pmu_msr(vcpu, msr))
2132 return kvm_pmu_set_msr(vcpu, msr_info);
2133
2134 if (pr || data != 0)
2135 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2136 "0x%x data 0x%llx\n", msr, data);
2137 break;
2138 case MSR_K7_CLK_CTL:
2139 /*
2140 * Ignore all writes to this no longer documented MSR.
2141 * Writes are only relevant for old K7 processors,
2142 * all pre-dating SVM, but a recommended workaround from
2143 * AMD for these chips. It is possible to specify the
2144 * affected processor models on the command line, hence
2145 * the need to ignore the workaround.
2146 */
2147 break;
2148 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2149 if (kvm_hv_msr_partition_wide(msr)) {
2150 int r;
2151 mutex_lock(&vcpu->kvm->lock);
2152 r = set_msr_hyperv_pw(vcpu, msr, data);
2153 mutex_unlock(&vcpu->kvm->lock);
2154 return r;
2155 } else
2156 return set_msr_hyperv(vcpu, msr, data);
2157 break;
2158 case MSR_IA32_BBL_CR_CTL3:
2159 /* Drop writes to this legacy MSR -- see rdmsr
2160 * counterpart for further detail.
2161 */
2162 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2163 break;
2164 case MSR_AMD64_OSVW_ID_LENGTH:
2165 if (!guest_cpuid_has_osvw(vcpu))
2166 return 1;
2167 vcpu->arch.osvw.length = data;
2168 break;
2169 case MSR_AMD64_OSVW_STATUS:
2170 if (!guest_cpuid_has_osvw(vcpu))
2171 return 1;
2172 vcpu->arch.osvw.status = data;
2173 break;
2174 default:
2175 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2176 return xen_hvm_config(vcpu, data);
2177 if (kvm_pmu_msr(vcpu, msr))
2178 return kvm_pmu_set_msr(vcpu, msr_info);
2179 if (!ignore_msrs) {
2180 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2181 msr, data);
2182 return 1;
2183 } else {
2184 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2185 msr, data);
2186 break;
2187 }
2188 }
2189 return 0;
2190 }
2191 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2192
2193
2194 /*
2195 * Reads an msr value (of 'msr_index') into 'pdata'.
2196 * Returns 0 on success, non-0 otherwise.
2197 * Assumes vcpu_load() was already called.
2198 */
2199 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2200 {
2201 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2202 }
2203
2204 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2205 {
2206 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2207
2208 if (!msr_mtrr_valid(msr))
2209 return 1;
2210
2211 if (msr == MSR_MTRRdefType)
2212 *pdata = vcpu->arch.mtrr_state.def_type +
2213 (vcpu->arch.mtrr_state.enabled << 10);
2214 else if (msr == MSR_MTRRfix64K_00000)
2215 *pdata = p[0];
2216 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2217 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2218 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2219 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2220 else if (msr == MSR_IA32_CR_PAT)
2221 *pdata = vcpu->arch.pat;
2222 else { /* Variable MTRRs */
2223 int idx, is_mtrr_mask;
2224 u64 *pt;
2225
2226 idx = (msr - 0x200) / 2;
2227 is_mtrr_mask = msr - 0x200 - 2 * idx;
2228 if (!is_mtrr_mask)
2229 pt =
2230 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2231 else
2232 pt =
2233 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2234 *pdata = *pt;
2235 }
2236
2237 return 0;
2238 }
2239
2240 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2241 {
2242 u64 data;
2243 u64 mcg_cap = vcpu->arch.mcg_cap;
2244 unsigned bank_num = mcg_cap & 0xff;
2245
2246 switch (msr) {
2247 case MSR_IA32_P5_MC_ADDR:
2248 case MSR_IA32_P5_MC_TYPE:
2249 data = 0;
2250 break;
2251 case MSR_IA32_MCG_CAP:
2252 data = vcpu->arch.mcg_cap;
2253 break;
2254 case MSR_IA32_MCG_CTL:
2255 if (!(mcg_cap & MCG_CTL_P))
2256 return 1;
2257 data = vcpu->arch.mcg_ctl;
2258 break;
2259 case MSR_IA32_MCG_STATUS:
2260 data = vcpu->arch.mcg_status;
2261 break;
2262 default:
2263 if (msr >= MSR_IA32_MC0_CTL &&
2264 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2265 u32 offset = msr - MSR_IA32_MC0_CTL;
2266 data = vcpu->arch.mce_banks[offset];
2267 break;
2268 }
2269 return 1;
2270 }
2271 *pdata = data;
2272 return 0;
2273 }
2274
2275 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2276 {
2277 u64 data = 0;
2278 struct kvm *kvm = vcpu->kvm;
2279
2280 switch (msr) {
2281 case HV_X64_MSR_GUEST_OS_ID:
2282 data = kvm->arch.hv_guest_os_id;
2283 break;
2284 case HV_X64_MSR_HYPERCALL:
2285 data = kvm->arch.hv_hypercall;
2286 break;
2287 default:
2288 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2289 return 1;
2290 }
2291
2292 *pdata = data;
2293 return 0;
2294 }
2295
2296 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2297 {
2298 u64 data = 0;
2299
2300 switch (msr) {
2301 case HV_X64_MSR_VP_INDEX: {
2302 int r;
2303 struct kvm_vcpu *v;
2304 kvm_for_each_vcpu(r, v, vcpu->kvm)
2305 if (v == vcpu)
2306 data = r;
2307 break;
2308 }
2309 case HV_X64_MSR_EOI:
2310 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2311 case HV_X64_MSR_ICR:
2312 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2313 case HV_X64_MSR_TPR:
2314 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2315 case HV_X64_MSR_APIC_ASSIST_PAGE:
2316 data = vcpu->arch.hv_vapic;
2317 break;
2318 default:
2319 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2320 return 1;
2321 }
2322 *pdata = data;
2323 return 0;
2324 }
2325
2326 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2327 {
2328 u64 data;
2329
2330 switch (msr) {
2331 case MSR_IA32_PLATFORM_ID:
2332 case MSR_IA32_EBL_CR_POWERON:
2333 case MSR_IA32_DEBUGCTLMSR:
2334 case MSR_IA32_LASTBRANCHFROMIP:
2335 case MSR_IA32_LASTBRANCHTOIP:
2336 case MSR_IA32_LASTINTFROMIP:
2337 case MSR_IA32_LASTINTTOIP:
2338 case MSR_K8_SYSCFG:
2339 case MSR_K7_HWCR:
2340 case MSR_VM_HSAVE_PA:
2341 case MSR_K7_EVNTSEL0:
2342 case MSR_K7_PERFCTR0:
2343 case MSR_K8_INT_PENDING_MSG:
2344 case MSR_AMD64_NB_CFG:
2345 case MSR_FAM10H_MMIO_CONF_BASE:
2346 case MSR_AMD64_BU_CFG2:
2347 data = 0;
2348 break;
2349 case MSR_P6_PERFCTR0:
2350 case MSR_P6_PERFCTR1:
2351 case MSR_P6_EVNTSEL0:
2352 case MSR_P6_EVNTSEL1:
2353 if (kvm_pmu_msr(vcpu, msr))
2354 return kvm_pmu_get_msr(vcpu, msr, pdata);
2355 data = 0;
2356 break;
2357 case MSR_IA32_UCODE_REV:
2358 data = 0x100000000ULL;
2359 break;
2360 case MSR_MTRRcap:
2361 data = 0x500 | KVM_NR_VAR_MTRR;
2362 break;
2363 case 0x200 ... 0x2ff:
2364 return get_msr_mtrr(vcpu, msr, pdata);
2365 case 0xcd: /* fsb frequency */
2366 data = 3;
2367 break;
2368 /*
2369 * MSR_EBC_FREQUENCY_ID
2370 * Conservative value valid for even the basic CPU models.
2371 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2372 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2373 * and 266MHz for model 3, or 4. Set Core Clock
2374 * Frequency to System Bus Frequency Ratio to 1 (bits
2375 * 31:24) even though these are only valid for CPU
2376 * models > 2, however guests may end up dividing or
2377 * multiplying by zero otherwise.
2378 */
2379 case MSR_EBC_FREQUENCY_ID:
2380 data = 1 << 24;
2381 break;
2382 case MSR_IA32_APICBASE:
2383 data = kvm_get_apic_base(vcpu);
2384 break;
2385 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2386 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2387 break;
2388 case MSR_IA32_TSCDEADLINE:
2389 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2390 break;
2391 case MSR_IA32_TSC_ADJUST:
2392 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2393 break;
2394 case MSR_IA32_MISC_ENABLE:
2395 data = vcpu->arch.ia32_misc_enable_msr;
2396 break;
2397 case MSR_IA32_PERF_STATUS:
2398 /* TSC increment by tick */
2399 data = 1000ULL;
2400 /* CPU multiplier */
2401 data |= (((uint64_t)4ULL) << 40);
2402 break;
2403 case MSR_EFER:
2404 data = vcpu->arch.efer;
2405 break;
2406 case MSR_KVM_WALL_CLOCK:
2407 case MSR_KVM_WALL_CLOCK_NEW:
2408 data = vcpu->kvm->arch.wall_clock;
2409 break;
2410 case MSR_KVM_SYSTEM_TIME:
2411 case MSR_KVM_SYSTEM_TIME_NEW:
2412 data = vcpu->arch.time;
2413 break;
2414 case MSR_KVM_ASYNC_PF_EN:
2415 data = vcpu->arch.apf.msr_val;
2416 break;
2417 case MSR_KVM_STEAL_TIME:
2418 data = vcpu->arch.st.msr_val;
2419 break;
2420 case MSR_KVM_PV_EOI_EN:
2421 data = vcpu->arch.pv_eoi.msr_val;
2422 break;
2423 case MSR_IA32_P5_MC_ADDR:
2424 case MSR_IA32_P5_MC_TYPE:
2425 case MSR_IA32_MCG_CAP:
2426 case MSR_IA32_MCG_CTL:
2427 case MSR_IA32_MCG_STATUS:
2428 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2429 return get_msr_mce(vcpu, msr, pdata);
2430 case MSR_K7_CLK_CTL:
2431 /*
2432 * Provide expected ramp-up count for K7. All other
2433 * are set to zero, indicating minimum divisors for
2434 * every field.
2435 *
2436 * This prevents guest kernels on AMD host with CPU
2437 * type 6, model 8 and higher from exploding due to
2438 * the rdmsr failing.
2439 */
2440 data = 0x20000000;
2441 break;
2442 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2443 if (kvm_hv_msr_partition_wide(msr)) {
2444 int r;
2445 mutex_lock(&vcpu->kvm->lock);
2446 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2447 mutex_unlock(&vcpu->kvm->lock);
2448 return r;
2449 } else
2450 return get_msr_hyperv(vcpu, msr, pdata);
2451 break;
2452 case MSR_IA32_BBL_CR_CTL3:
2453 /* This legacy MSR exists but isn't fully documented in current
2454 * silicon. It is however accessed by winxp in very narrow
2455 * scenarios where it sets bit #19, itself documented as
2456 * a "reserved" bit. Best effort attempt to source coherent
2457 * read data here should the balance of the register be
2458 * interpreted by the guest:
2459 *
2460 * L2 cache control register 3: 64GB range, 256KB size,
2461 * enabled, latency 0x1, configured
2462 */
2463 data = 0xbe702111;
2464 break;
2465 case MSR_AMD64_OSVW_ID_LENGTH:
2466 if (!guest_cpuid_has_osvw(vcpu))
2467 return 1;
2468 data = vcpu->arch.osvw.length;
2469 break;
2470 case MSR_AMD64_OSVW_STATUS:
2471 if (!guest_cpuid_has_osvw(vcpu))
2472 return 1;
2473 data = vcpu->arch.osvw.status;
2474 break;
2475 default:
2476 if (kvm_pmu_msr(vcpu, msr))
2477 return kvm_pmu_get_msr(vcpu, msr, pdata);
2478 if (!ignore_msrs) {
2479 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2480 return 1;
2481 } else {
2482 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2483 data = 0;
2484 }
2485 break;
2486 }
2487 *pdata = data;
2488 return 0;
2489 }
2490 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2491
2492 /*
2493 * Read or write a bunch of msrs. All parameters are kernel addresses.
2494 *
2495 * @return number of msrs set successfully.
2496 */
2497 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2498 struct kvm_msr_entry *entries,
2499 int (*do_msr)(struct kvm_vcpu *vcpu,
2500 unsigned index, u64 *data))
2501 {
2502 int i, idx;
2503
2504 idx = srcu_read_lock(&vcpu->kvm->srcu);
2505 for (i = 0; i < msrs->nmsrs; ++i)
2506 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2507 break;
2508 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2509
2510 return i;
2511 }
2512
2513 /*
2514 * Read or write a bunch of msrs. Parameters are user addresses.
2515 *
2516 * @return number of msrs set successfully.
2517 */
2518 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2519 int (*do_msr)(struct kvm_vcpu *vcpu,
2520 unsigned index, u64 *data),
2521 int writeback)
2522 {
2523 struct kvm_msrs msrs;
2524 struct kvm_msr_entry *entries;
2525 int r, n;
2526 unsigned size;
2527
2528 r = -EFAULT;
2529 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2530 goto out;
2531
2532 r = -E2BIG;
2533 if (msrs.nmsrs >= MAX_IO_MSRS)
2534 goto out;
2535
2536 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2537 entries = memdup_user(user_msrs->entries, size);
2538 if (IS_ERR(entries)) {
2539 r = PTR_ERR(entries);
2540 goto out;
2541 }
2542
2543 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2544 if (r < 0)
2545 goto out_free;
2546
2547 r = -EFAULT;
2548 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2549 goto out_free;
2550
2551 r = n;
2552
2553 out_free:
2554 kfree(entries);
2555 out:
2556 return r;
2557 }
2558
2559 int kvm_dev_ioctl_check_extension(long ext)
2560 {
2561 int r;
2562
2563 switch (ext) {
2564 case KVM_CAP_IRQCHIP:
2565 case KVM_CAP_HLT:
2566 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2567 case KVM_CAP_SET_TSS_ADDR:
2568 case KVM_CAP_EXT_CPUID:
2569 case KVM_CAP_CLOCKSOURCE:
2570 case KVM_CAP_PIT:
2571 case KVM_CAP_NOP_IO_DELAY:
2572 case KVM_CAP_MP_STATE:
2573 case KVM_CAP_SYNC_MMU:
2574 case KVM_CAP_USER_NMI:
2575 case KVM_CAP_REINJECT_CONTROL:
2576 case KVM_CAP_IRQ_INJECT_STATUS:
2577 case KVM_CAP_IRQFD:
2578 case KVM_CAP_IOEVENTFD:
2579 case KVM_CAP_PIT2:
2580 case KVM_CAP_PIT_STATE2:
2581 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2582 case KVM_CAP_XEN_HVM:
2583 case KVM_CAP_ADJUST_CLOCK:
2584 case KVM_CAP_VCPU_EVENTS:
2585 case KVM_CAP_HYPERV:
2586 case KVM_CAP_HYPERV_VAPIC:
2587 case KVM_CAP_HYPERV_SPIN:
2588 case KVM_CAP_PCI_SEGMENT:
2589 case KVM_CAP_DEBUGREGS:
2590 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2591 case KVM_CAP_XSAVE:
2592 case KVM_CAP_ASYNC_PF:
2593 case KVM_CAP_GET_TSC_KHZ:
2594 case KVM_CAP_KVMCLOCK_CTRL:
2595 case KVM_CAP_READONLY_MEM:
2596 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2597 case KVM_CAP_ASSIGN_DEV_IRQ:
2598 case KVM_CAP_PCI_2_3:
2599 #endif
2600 r = 1;
2601 break;
2602 case KVM_CAP_COALESCED_MMIO:
2603 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2604 break;
2605 case KVM_CAP_VAPIC:
2606 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2607 break;
2608 case KVM_CAP_NR_VCPUS:
2609 r = KVM_SOFT_MAX_VCPUS;
2610 break;
2611 case KVM_CAP_MAX_VCPUS:
2612 r = KVM_MAX_VCPUS;
2613 break;
2614 case KVM_CAP_NR_MEMSLOTS:
2615 r = KVM_USER_MEM_SLOTS;
2616 break;
2617 case KVM_CAP_PV_MMU: /* obsolete */
2618 r = 0;
2619 break;
2620 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2621 case KVM_CAP_IOMMU:
2622 r = iommu_present(&pci_bus_type);
2623 break;
2624 #endif
2625 case KVM_CAP_MCE:
2626 r = KVM_MAX_MCE_BANKS;
2627 break;
2628 case KVM_CAP_XCRS:
2629 r = cpu_has_xsave;
2630 break;
2631 case KVM_CAP_TSC_CONTROL:
2632 r = kvm_has_tsc_control;
2633 break;
2634 case KVM_CAP_TSC_DEADLINE_TIMER:
2635 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2636 break;
2637 default:
2638 r = 0;
2639 break;
2640 }
2641 return r;
2642
2643 }
2644
2645 long kvm_arch_dev_ioctl(struct file *filp,
2646 unsigned int ioctl, unsigned long arg)
2647 {
2648 void __user *argp = (void __user *)arg;
2649 long r;
2650
2651 switch (ioctl) {
2652 case KVM_GET_MSR_INDEX_LIST: {
2653 struct kvm_msr_list __user *user_msr_list = argp;
2654 struct kvm_msr_list msr_list;
2655 unsigned n;
2656
2657 r = -EFAULT;
2658 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2659 goto out;
2660 n = msr_list.nmsrs;
2661 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2662 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2663 goto out;
2664 r = -E2BIG;
2665 if (n < msr_list.nmsrs)
2666 goto out;
2667 r = -EFAULT;
2668 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2669 num_msrs_to_save * sizeof(u32)))
2670 goto out;
2671 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2672 &emulated_msrs,
2673 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2674 goto out;
2675 r = 0;
2676 break;
2677 }
2678 case KVM_GET_SUPPORTED_CPUID: {
2679 struct kvm_cpuid2 __user *cpuid_arg = argp;
2680 struct kvm_cpuid2 cpuid;
2681
2682 r = -EFAULT;
2683 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2684 goto out;
2685 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2686 cpuid_arg->entries);
2687 if (r)
2688 goto out;
2689
2690 r = -EFAULT;
2691 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2692 goto out;
2693 r = 0;
2694 break;
2695 }
2696 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2697 u64 mce_cap;
2698
2699 mce_cap = KVM_MCE_CAP_SUPPORTED;
2700 r = -EFAULT;
2701 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2702 goto out;
2703 r = 0;
2704 break;
2705 }
2706 default:
2707 r = -EINVAL;
2708 }
2709 out:
2710 return r;
2711 }
2712
2713 static void wbinvd_ipi(void *garbage)
2714 {
2715 wbinvd();
2716 }
2717
2718 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2719 {
2720 return vcpu->kvm->arch.iommu_domain &&
2721 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2722 }
2723
2724 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2725 {
2726 /* Address WBINVD may be executed by guest */
2727 if (need_emulate_wbinvd(vcpu)) {
2728 if (kvm_x86_ops->has_wbinvd_exit())
2729 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2730 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2731 smp_call_function_single(vcpu->cpu,
2732 wbinvd_ipi, NULL, 1);
2733 }
2734
2735 kvm_x86_ops->vcpu_load(vcpu, cpu);
2736
2737 /* Apply any externally detected TSC adjustments (due to suspend) */
2738 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2739 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2740 vcpu->arch.tsc_offset_adjustment = 0;
2741 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2742 }
2743
2744 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2745 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2746 native_read_tsc() - vcpu->arch.last_host_tsc;
2747 if (tsc_delta < 0)
2748 mark_tsc_unstable("KVM discovered backwards TSC");
2749 if (check_tsc_unstable()) {
2750 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2751 vcpu->arch.last_guest_tsc);
2752 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2753 vcpu->arch.tsc_catchup = 1;
2754 }
2755 /*
2756 * On a host with synchronized TSC, there is no need to update
2757 * kvmclock on vcpu->cpu migration
2758 */
2759 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2760 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2761 if (vcpu->cpu != cpu)
2762 kvm_migrate_timers(vcpu);
2763 vcpu->cpu = cpu;
2764 }
2765
2766 accumulate_steal_time(vcpu);
2767 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2768 }
2769
2770 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2771 {
2772 kvm_x86_ops->vcpu_put(vcpu);
2773 kvm_put_guest_fpu(vcpu);
2774 vcpu->arch.last_host_tsc = native_read_tsc();
2775 }
2776
2777 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2778 struct kvm_lapic_state *s)
2779 {
2780 kvm_x86_ops->sync_pir_to_irr(vcpu);
2781 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2782
2783 return 0;
2784 }
2785
2786 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2787 struct kvm_lapic_state *s)
2788 {
2789 kvm_apic_post_state_restore(vcpu, s);
2790 update_cr8_intercept(vcpu);
2791
2792 return 0;
2793 }
2794
2795 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2796 struct kvm_interrupt *irq)
2797 {
2798 if (irq->irq >= KVM_NR_INTERRUPTS)
2799 return -EINVAL;
2800 if (irqchip_in_kernel(vcpu->kvm))
2801 return -ENXIO;
2802
2803 kvm_queue_interrupt(vcpu, irq->irq, false);
2804 kvm_make_request(KVM_REQ_EVENT, vcpu);
2805
2806 return 0;
2807 }
2808
2809 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2810 {
2811 kvm_inject_nmi(vcpu);
2812
2813 return 0;
2814 }
2815
2816 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2817 struct kvm_tpr_access_ctl *tac)
2818 {
2819 if (tac->flags)
2820 return -EINVAL;
2821 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2822 return 0;
2823 }
2824
2825 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2826 u64 mcg_cap)
2827 {
2828 int r;
2829 unsigned bank_num = mcg_cap & 0xff, bank;
2830
2831 r = -EINVAL;
2832 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2833 goto out;
2834 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2835 goto out;
2836 r = 0;
2837 vcpu->arch.mcg_cap = mcg_cap;
2838 /* Init IA32_MCG_CTL to all 1s */
2839 if (mcg_cap & MCG_CTL_P)
2840 vcpu->arch.mcg_ctl = ~(u64)0;
2841 /* Init IA32_MCi_CTL to all 1s */
2842 for (bank = 0; bank < bank_num; bank++)
2843 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2844 out:
2845 return r;
2846 }
2847
2848 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2849 struct kvm_x86_mce *mce)
2850 {
2851 u64 mcg_cap = vcpu->arch.mcg_cap;
2852 unsigned bank_num = mcg_cap & 0xff;
2853 u64 *banks = vcpu->arch.mce_banks;
2854
2855 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2856 return -EINVAL;
2857 /*
2858 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2859 * reporting is disabled
2860 */
2861 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2862 vcpu->arch.mcg_ctl != ~(u64)0)
2863 return 0;
2864 banks += 4 * mce->bank;
2865 /*
2866 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2867 * reporting is disabled for the bank
2868 */
2869 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2870 return 0;
2871 if (mce->status & MCI_STATUS_UC) {
2872 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2873 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2874 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2875 return 0;
2876 }
2877 if (banks[1] & MCI_STATUS_VAL)
2878 mce->status |= MCI_STATUS_OVER;
2879 banks[2] = mce->addr;
2880 banks[3] = mce->misc;
2881 vcpu->arch.mcg_status = mce->mcg_status;
2882 banks[1] = mce->status;
2883 kvm_queue_exception(vcpu, MC_VECTOR);
2884 } else if (!(banks[1] & MCI_STATUS_VAL)
2885 || !(banks[1] & MCI_STATUS_UC)) {
2886 if (banks[1] & MCI_STATUS_VAL)
2887 mce->status |= MCI_STATUS_OVER;
2888 banks[2] = mce->addr;
2889 banks[3] = mce->misc;
2890 banks[1] = mce->status;
2891 } else
2892 banks[1] |= MCI_STATUS_OVER;
2893 return 0;
2894 }
2895
2896 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2897 struct kvm_vcpu_events *events)
2898 {
2899 process_nmi(vcpu);
2900 events->exception.injected =
2901 vcpu->arch.exception.pending &&
2902 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2903 events->exception.nr = vcpu->arch.exception.nr;
2904 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2905 events->exception.pad = 0;
2906 events->exception.error_code = vcpu->arch.exception.error_code;
2907
2908 events->interrupt.injected =
2909 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2910 events->interrupt.nr = vcpu->arch.interrupt.nr;
2911 events->interrupt.soft = 0;
2912 events->interrupt.shadow =
2913 kvm_x86_ops->get_interrupt_shadow(vcpu,
2914 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2915
2916 events->nmi.injected = vcpu->arch.nmi_injected;
2917 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2918 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2919 events->nmi.pad = 0;
2920
2921 events->sipi_vector = 0; /* never valid when reporting to user space */
2922
2923 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2924 | KVM_VCPUEVENT_VALID_SHADOW);
2925 memset(&events->reserved, 0, sizeof(events->reserved));
2926 }
2927
2928 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2929 struct kvm_vcpu_events *events)
2930 {
2931 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2932 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2933 | KVM_VCPUEVENT_VALID_SHADOW))
2934 return -EINVAL;
2935
2936 process_nmi(vcpu);
2937 vcpu->arch.exception.pending = events->exception.injected;
2938 vcpu->arch.exception.nr = events->exception.nr;
2939 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2940 vcpu->arch.exception.error_code = events->exception.error_code;
2941
2942 vcpu->arch.interrupt.pending = events->interrupt.injected;
2943 vcpu->arch.interrupt.nr = events->interrupt.nr;
2944 vcpu->arch.interrupt.soft = events->interrupt.soft;
2945 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2946 kvm_x86_ops->set_interrupt_shadow(vcpu,
2947 events->interrupt.shadow);
2948
2949 vcpu->arch.nmi_injected = events->nmi.injected;
2950 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2951 vcpu->arch.nmi_pending = events->nmi.pending;
2952 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2953
2954 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2955 kvm_vcpu_has_lapic(vcpu))
2956 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2957
2958 kvm_make_request(KVM_REQ_EVENT, vcpu);
2959
2960 return 0;
2961 }
2962
2963 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2964 struct kvm_debugregs *dbgregs)
2965 {
2966 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2967 dbgregs->dr6 = vcpu->arch.dr6;
2968 dbgregs->dr7 = vcpu->arch.dr7;
2969 dbgregs->flags = 0;
2970 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2971 }
2972
2973 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2974 struct kvm_debugregs *dbgregs)
2975 {
2976 if (dbgregs->flags)
2977 return -EINVAL;
2978
2979 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2980 vcpu->arch.dr6 = dbgregs->dr6;
2981 vcpu->arch.dr7 = dbgregs->dr7;
2982
2983 return 0;
2984 }
2985
2986 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2987 struct kvm_xsave *guest_xsave)
2988 {
2989 if (cpu_has_xsave)
2990 memcpy(guest_xsave->region,
2991 &vcpu->arch.guest_fpu.state->xsave,
2992 xstate_size);
2993 else {
2994 memcpy(guest_xsave->region,
2995 &vcpu->arch.guest_fpu.state->fxsave,
2996 sizeof(struct i387_fxsave_struct));
2997 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2998 XSTATE_FPSSE;
2999 }
3000 }
3001
3002 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3003 struct kvm_xsave *guest_xsave)
3004 {
3005 u64 xstate_bv =
3006 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3007
3008 if (cpu_has_xsave)
3009 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3010 guest_xsave->region, xstate_size);
3011 else {
3012 if (xstate_bv & ~XSTATE_FPSSE)
3013 return -EINVAL;
3014 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3015 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3016 }
3017 return 0;
3018 }
3019
3020 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3021 struct kvm_xcrs *guest_xcrs)
3022 {
3023 if (!cpu_has_xsave) {
3024 guest_xcrs->nr_xcrs = 0;
3025 return;
3026 }
3027
3028 guest_xcrs->nr_xcrs = 1;
3029 guest_xcrs->flags = 0;
3030 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3031 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3032 }
3033
3034 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3035 struct kvm_xcrs *guest_xcrs)
3036 {
3037 int i, r = 0;
3038
3039 if (!cpu_has_xsave)
3040 return -EINVAL;
3041
3042 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3043 return -EINVAL;
3044
3045 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3046 /* Only support XCR0 currently */
3047 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3048 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3049 guest_xcrs->xcrs[0].value);
3050 break;
3051 }
3052 if (r)
3053 r = -EINVAL;
3054 return r;
3055 }
3056
3057 /*
3058 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3059 * stopped by the hypervisor. This function will be called from the host only.
3060 * EINVAL is returned when the host attempts to set the flag for a guest that
3061 * does not support pv clocks.
3062 */
3063 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3064 {
3065 if (!vcpu->arch.pv_time_enabled)
3066 return -EINVAL;
3067 vcpu->arch.pvclock_set_guest_stopped_request = true;
3068 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3069 return 0;
3070 }
3071
3072 long kvm_arch_vcpu_ioctl(struct file *filp,
3073 unsigned int ioctl, unsigned long arg)
3074 {
3075 struct kvm_vcpu *vcpu = filp->private_data;
3076 void __user *argp = (void __user *)arg;
3077 int r;
3078 union {
3079 struct kvm_lapic_state *lapic;
3080 struct kvm_xsave *xsave;
3081 struct kvm_xcrs *xcrs;
3082 void *buffer;
3083 } u;
3084
3085 u.buffer = NULL;
3086 switch (ioctl) {
3087 case KVM_GET_LAPIC: {
3088 r = -EINVAL;
3089 if (!vcpu->arch.apic)
3090 goto out;
3091 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3092
3093 r = -ENOMEM;
3094 if (!u.lapic)
3095 goto out;
3096 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3097 if (r)
3098 goto out;
3099 r = -EFAULT;
3100 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3101 goto out;
3102 r = 0;
3103 break;
3104 }
3105 case KVM_SET_LAPIC: {
3106 r = -EINVAL;
3107 if (!vcpu->arch.apic)
3108 goto out;
3109 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3110 if (IS_ERR(u.lapic))
3111 return PTR_ERR(u.lapic);
3112
3113 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3114 break;
3115 }
3116 case KVM_INTERRUPT: {
3117 struct kvm_interrupt irq;
3118
3119 r = -EFAULT;
3120 if (copy_from_user(&irq, argp, sizeof irq))
3121 goto out;
3122 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3123 break;
3124 }
3125 case KVM_NMI: {
3126 r = kvm_vcpu_ioctl_nmi(vcpu);
3127 break;
3128 }
3129 case KVM_SET_CPUID: {
3130 struct kvm_cpuid __user *cpuid_arg = argp;
3131 struct kvm_cpuid cpuid;
3132
3133 r = -EFAULT;
3134 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3135 goto out;
3136 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3137 break;
3138 }
3139 case KVM_SET_CPUID2: {
3140 struct kvm_cpuid2 __user *cpuid_arg = argp;
3141 struct kvm_cpuid2 cpuid;
3142
3143 r = -EFAULT;
3144 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3145 goto out;
3146 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3147 cpuid_arg->entries);
3148 break;
3149 }
3150 case KVM_GET_CPUID2: {
3151 struct kvm_cpuid2 __user *cpuid_arg = argp;
3152 struct kvm_cpuid2 cpuid;
3153
3154 r = -EFAULT;
3155 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3156 goto out;
3157 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3158 cpuid_arg->entries);
3159 if (r)
3160 goto out;
3161 r = -EFAULT;
3162 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3163 goto out;
3164 r = 0;
3165 break;
3166 }
3167 case KVM_GET_MSRS:
3168 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3169 break;
3170 case KVM_SET_MSRS:
3171 r = msr_io(vcpu, argp, do_set_msr, 0);
3172 break;
3173 case KVM_TPR_ACCESS_REPORTING: {
3174 struct kvm_tpr_access_ctl tac;
3175
3176 r = -EFAULT;
3177 if (copy_from_user(&tac, argp, sizeof tac))
3178 goto out;
3179 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3180 if (r)
3181 goto out;
3182 r = -EFAULT;
3183 if (copy_to_user(argp, &tac, sizeof tac))
3184 goto out;
3185 r = 0;
3186 break;
3187 };
3188 case KVM_SET_VAPIC_ADDR: {
3189 struct kvm_vapic_addr va;
3190
3191 r = -EINVAL;
3192 if (!irqchip_in_kernel(vcpu->kvm))
3193 goto out;
3194 r = -EFAULT;
3195 if (copy_from_user(&va, argp, sizeof va))
3196 goto out;
3197 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3198 break;
3199 }
3200 case KVM_X86_SETUP_MCE: {
3201 u64 mcg_cap;
3202
3203 r = -EFAULT;
3204 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3205 goto out;
3206 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3207 break;
3208 }
3209 case KVM_X86_SET_MCE: {
3210 struct kvm_x86_mce mce;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&mce, argp, sizeof mce))
3214 goto out;
3215 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3216 break;
3217 }
3218 case KVM_GET_VCPU_EVENTS: {
3219 struct kvm_vcpu_events events;
3220
3221 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3222
3223 r = -EFAULT;
3224 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3225 break;
3226 r = 0;
3227 break;
3228 }
3229 case KVM_SET_VCPU_EVENTS: {
3230 struct kvm_vcpu_events events;
3231
3232 r = -EFAULT;
3233 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3234 break;
3235
3236 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3237 break;
3238 }
3239 case KVM_GET_DEBUGREGS: {
3240 struct kvm_debugregs dbgregs;
3241
3242 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3243
3244 r = -EFAULT;
3245 if (copy_to_user(argp, &dbgregs,
3246 sizeof(struct kvm_debugregs)))
3247 break;
3248 r = 0;
3249 break;
3250 }
3251 case KVM_SET_DEBUGREGS: {
3252 struct kvm_debugregs dbgregs;
3253
3254 r = -EFAULT;
3255 if (copy_from_user(&dbgregs, argp,
3256 sizeof(struct kvm_debugregs)))
3257 break;
3258
3259 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3260 break;
3261 }
3262 case KVM_GET_XSAVE: {
3263 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3264 r = -ENOMEM;
3265 if (!u.xsave)
3266 break;
3267
3268 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3269
3270 r = -EFAULT;
3271 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3272 break;
3273 r = 0;
3274 break;
3275 }
3276 case KVM_SET_XSAVE: {
3277 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3278 if (IS_ERR(u.xsave))
3279 return PTR_ERR(u.xsave);
3280
3281 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3282 break;
3283 }
3284 case KVM_GET_XCRS: {
3285 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3286 r = -ENOMEM;
3287 if (!u.xcrs)
3288 break;
3289
3290 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3291
3292 r = -EFAULT;
3293 if (copy_to_user(argp, u.xcrs,
3294 sizeof(struct kvm_xcrs)))
3295 break;
3296 r = 0;
3297 break;
3298 }
3299 case KVM_SET_XCRS: {
3300 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3301 if (IS_ERR(u.xcrs))
3302 return PTR_ERR(u.xcrs);
3303
3304 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3305 break;
3306 }
3307 case KVM_SET_TSC_KHZ: {
3308 u32 user_tsc_khz;
3309
3310 r = -EINVAL;
3311 user_tsc_khz = (u32)arg;
3312
3313 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3314 goto out;
3315
3316 if (user_tsc_khz == 0)
3317 user_tsc_khz = tsc_khz;
3318
3319 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3320
3321 r = 0;
3322 goto out;
3323 }
3324 case KVM_GET_TSC_KHZ: {
3325 r = vcpu->arch.virtual_tsc_khz;
3326 goto out;
3327 }
3328 case KVM_KVMCLOCK_CTRL: {
3329 r = kvm_set_guest_paused(vcpu);
3330 goto out;
3331 }
3332 default:
3333 r = -EINVAL;
3334 }
3335 out:
3336 kfree(u.buffer);
3337 return r;
3338 }
3339
3340 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3341 {
3342 return VM_FAULT_SIGBUS;
3343 }
3344
3345 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3346 {
3347 int ret;
3348
3349 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3350 return -EINVAL;
3351 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3352 return ret;
3353 }
3354
3355 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3356 u64 ident_addr)
3357 {
3358 kvm->arch.ept_identity_map_addr = ident_addr;
3359 return 0;
3360 }
3361
3362 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3363 u32 kvm_nr_mmu_pages)
3364 {
3365 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3366 return -EINVAL;
3367
3368 mutex_lock(&kvm->slots_lock);
3369
3370 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3371 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3372
3373 mutex_unlock(&kvm->slots_lock);
3374 return 0;
3375 }
3376
3377 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3378 {
3379 return kvm->arch.n_max_mmu_pages;
3380 }
3381
3382 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3383 {
3384 int r;
3385
3386 r = 0;
3387 switch (chip->chip_id) {
3388 case KVM_IRQCHIP_PIC_MASTER:
3389 memcpy(&chip->chip.pic,
3390 &pic_irqchip(kvm)->pics[0],
3391 sizeof(struct kvm_pic_state));
3392 break;
3393 case KVM_IRQCHIP_PIC_SLAVE:
3394 memcpy(&chip->chip.pic,
3395 &pic_irqchip(kvm)->pics[1],
3396 sizeof(struct kvm_pic_state));
3397 break;
3398 case KVM_IRQCHIP_IOAPIC:
3399 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3400 break;
3401 default:
3402 r = -EINVAL;
3403 break;
3404 }
3405 return r;
3406 }
3407
3408 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3409 {
3410 int r;
3411
3412 r = 0;
3413 switch (chip->chip_id) {
3414 case KVM_IRQCHIP_PIC_MASTER:
3415 spin_lock(&pic_irqchip(kvm)->lock);
3416 memcpy(&pic_irqchip(kvm)->pics[0],
3417 &chip->chip.pic,
3418 sizeof(struct kvm_pic_state));
3419 spin_unlock(&pic_irqchip(kvm)->lock);
3420 break;
3421 case KVM_IRQCHIP_PIC_SLAVE:
3422 spin_lock(&pic_irqchip(kvm)->lock);
3423 memcpy(&pic_irqchip(kvm)->pics[1],
3424 &chip->chip.pic,
3425 sizeof(struct kvm_pic_state));
3426 spin_unlock(&pic_irqchip(kvm)->lock);
3427 break;
3428 case KVM_IRQCHIP_IOAPIC:
3429 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3430 break;
3431 default:
3432 r = -EINVAL;
3433 break;
3434 }
3435 kvm_pic_update_irq(pic_irqchip(kvm));
3436 return r;
3437 }
3438
3439 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3440 {
3441 int r = 0;
3442
3443 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3444 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3445 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3446 return r;
3447 }
3448
3449 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3450 {
3451 int r = 0;
3452
3453 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3454 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3455 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3456 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3457 return r;
3458 }
3459
3460 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3461 {
3462 int r = 0;
3463
3464 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3465 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3466 sizeof(ps->channels));
3467 ps->flags = kvm->arch.vpit->pit_state.flags;
3468 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3469 memset(&ps->reserved, 0, sizeof(ps->reserved));
3470 return r;
3471 }
3472
3473 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3474 {
3475 int r = 0, start = 0;
3476 u32 prev_legacy, cur_legacy;
3477 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3478 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3479 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3480 if (!prev_legacy && cur_legacy)
3481 start = 1;
3482 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3483 sizeof(kvm->arch.vpit->pit_state.channels));
3484 kvm->arch.vpit->pit_state.flags = ps->flags;
3485 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3486 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3487 return r;
3488 }
3489
3490 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3491 struct kvm_reinject_control *control)
3492 {
3493 if (!kvm->arch.vpit)
3494 return -ENXIO;
3495 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3496 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3497 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3498 return 0;
3499 }
3500
3501 /**
3502 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3503 * @kvm: kvm instance
3504 * @log: slot id and address to which we copy the log
3505 *
3506 * We need to keep it in mind that VCPU threads can write to the bitmap
3507 * concurrently. So, to avoid losing data, we keep the following order for
3508 * each bit:
3509 *
3510 * 1. Take a snapshot of the bit and clear it if needed.
3511 * 2. Write protect the corresponding page.
3512 * 3. Flush TLB's if needed.
3513 * 4. Copy the snapshot to the userspace.
3514 *
3515 * Between 2 and 3, the guest may write to the page using the remaining TLB
3516 * entry. This is not a problem because the page will be reported dirty at
3517 * step 4 using the snapshot taken before and step 3 ensures that successive
3518 * writes will be logged for the next call.
3519 */
3520 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3521 {
3522 int r;
3523 struct kvm_memory_slot *memslot;
3524 unsigned long n, i;
3525 unsigned long *dirty_bitmap;
3526 unsigned long *dirty_bitmap_buffer;
3527 bool is_dirty = false;
3528
3529 mutex_lock(&kvm->slots_lock);
3530
3531 r = -EINVAL;
3532 if (log->slot >= KVM_USER_MEM_SLOTS)
3533 goto out;
3534
3535 memslot = id_to_memslot(kvm->memslots, log->slot);
3536
3537 dirty_bitmap = memslot->dirty_bitmap;
3538 r = -ENOENT;
3539 if (!dirty_bitmap)
3540 goto out;
3541
3542 n = kvm_dirty_bitmap_bytes(memslot);
3543
3544 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3545 memset(dirty_bitmap_buffer, 0, n);
3546
3547 spin_lock(&kvm->mmu_lock);
3548
3549 for (i = 0; i < n / sizeof(long); i++) {
3550 unsigned long mask;
3551 gfn_t offset;
3552
3553 if (!dirty_bitmap[i])
3554 continue;
3555
3556 is_dirty = true;
3557
3558 mask = xchg(&dirty_bitmap[i], 0);
3559 dirty_bitmap_buffer[i] = mask;
3560
3561 offset = i * BITS_PER_LONG;
3562 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3563 }
3564 if (is_dirty)
3565 kvm_flush_remote_tlbs(kvm);
3566
3567 spin_unlock(&kvm->mmu_lock);
3568
3569 r = -EFAULT;
3570 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3571 goto out;
3572
3573 r = 0;
3574 out:
3575 mutex_unlock(&kvm->slots_lock);
3576 return r;
3577 }
3578
3579 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3580 bool line_status)
3581 {
3582 if (!irqchip_in_kernel(kvm))
3583 return -ENXIO;
3584
3585 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3586 irq_event->irq, irq_event->level,
3587 line_status);
3588 return 0;
3589 }
3590
3591 long kvm_arch_vm_ioctl(struct file *filp,
3592 unsigned int ioctl, unsigned long arg)
3593 {
3594 struct kvm *kvm = filp->private_data;
3595 void __user *argp = (void __user *)arg;
3596 int r = -ENOTTY;
3597 /*
3598 * This union makes it completely explicit to gcc-3.x
3599 * that these two variables' stack usage should be
3600 * combined, not added together.
3601 */
3602 union {
3603 struct kvm_pit_state ps;
3604 struct kvm_pit_state2 ps2;
3605 struct kvm_pit_config pit_config;
3606 } u;
3607
3608 switch (ioctl) {
3609 case KVM_SET_TSS_ADDR:
3610 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3611 break;
3612 case KVM_SET_IDENTITY_MAP_ADDR: {
3613 u64 ident_addr;
3614
3615 r = -EFAULT;
3616 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3617 goto out;
3618 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3619 break;
3620 }
3621 case KVM_SET_NR_MMU_PAGES:
3622 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3623 break;
3624 case KVM_GET_NR_MMU_PAGES:
3625 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3626 break;
3627 case KVM_CREATE_IRQCHIP: {
3628 struct kvm_pic *vpic;
3629
3630 mutex_lock(&kvm->lock);
3631 r = -EEXIST;
3632 if (kvm->arch.vpic)
3633 goto create_irqchip_unlock;
3634 r = -EINVAL;
3635 if (atomic_read(&kvm->online_vcpus))
3636 goto create_irqchip_unlock;
3637 r = -ENOMEM;
3638 vpic = kvm_create_pic(kvm);
3639 if (vpic) {
3640 r = kvm_ioapic_init(kvm);
3641 if (r) {
3642 mutex_lock(&kvm->slots_lock);
3643 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3644 &vpic->dev_master);
3645 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3646 &vpic->dev_slave);
3647 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3648 &vpic->dev_eclr);
3649 mutex_unlock(&kvm->slots_lock);
3650 kfree(vpic);
3651 goto create_irqchip_unlock;
3652 }
3653 } else
3654 goto create_irqchip_unlock;
3655 smp_wmb();
3656 kvm->arch.vpic = vpic;
3657 smp_wmb();
3658 r = kvm_setup_default_irq_routing(kvm);
3659 if (r) {
3660 mutex_lock(&kvm->slots_lock);
3661 mutex_lock(&kvm->irq_lock);
3662 kvm_ioapic_destroy(kvm);
3663 kvm_destroy_pic(kvm);
3664 mutex_unlock(&kvm->irq_lock);
3665 mutex_unlock(&kvm->slots_lock);
3666 }
3667 create_irqchip_unlock:
3668 mutex_unlock(&kvm->lock);
3669 break;
3670 }
3671 case KVM_CREATE_PIT:
3672 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3673 goto create_pit;
3674 case KVM_CREATE_PIT2:
3675 r = -EFAULT;
3676 if (copy_from_user(&u.pit_config, argp,
3677 sizeof(struct kvm_pit_config)))
3678 goto out;
3679 create_pit:
3680 mutex_lock(&kvm->slots_lock);
3681 r = -EEXIST;
3682 if (kvm->arch.vpit)
3683 goto create_pit_unlock;
3684 r = -ENOMEM;
3685 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3686 if (kvm->arch.vpit)
3687 r = 0;
3688 create_pit_unlock:
3689 mutex_unlock(&kvm->slots_lock);
3690 break;
3691 case KVM_GET_IRQCHIP: {
3692 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3693 struct kvm_irqchip *chip;
3694
3695 chip = memdup_user(argp, sizeof(*chip));
3696 if (IS_ERR(chip)) {
3697 r = PTR_ERR(chip);
3698 goto out;
3699 }
3700
3701 r = -ENXIO;
3702 if (!irqchip_in_kernel(kvm))
3703 goto get_irqchip_out;
3704 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3705 if (r)
3706 goto get_irqchip_out;
3707 r = -EFAULT;
3708 if (copy_to_user(argp, chip, sizeof *chip))
3709 goto get_irqchip_out;
3710 r = 0;
3711 get_irqchip_out:
3712 kfree(chip);
3713 break;
3714 }
3715 case KVM_SET_IRQCHIP: {
3716 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3717 struct kvm_irqchip *chip;
3718
3719 chip = memdup_user(argp, sizeof(*chip));
3720 if (IS_ERR(chip)) {
3721 r = PTR_ERR(chip);
3722 goto out;
3723 }
3724
3725 r = -ENXIO;
3726 if (!irqchip_in_kernel(kvm))
3727 goto set_irqchip_out;
3728 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3729 if (r)
3730 goto set_irqchip_out;
3731 r = 0;
3732 set_irqchip_out:
3733 kfree(chip);
3734 break;
3735 }
3736 case KVM_GET_PIT: {
3737 r = -EFAULT;
3738 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3739 goto out;
3740 r = -ENXIO;
3741 if (!kvm->arch.vpit)
3742 goto out;
3743 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3744 if (r)
3745 goto out;
3746 r = -EFAULT;
3747 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3748 goto out;
3749 r = 0;
3750 break;
3751 }
3752 case KVM_SET_PIT: {
3753 r = -EFAULT;
3754 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3755 goto out;
3756 r = -ENXIO;
3757 if (!kvm->arch.vpit)
3758 goto out;
3759 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3760 break;
3761 }
3762 case KVM_GET_PIT2: {
3763 r = -ENXIO;
3764 if (!kvm->arch.vpit)
3765 goto out;
3766 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3767 if (r)
3768 goto out;
3769 r = -EFAULT;
3770 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3771 goto out;
3772 r = 0;
3773 break;
3774 }
3775 case KVM_SET_PIT2: {
3776 r = -EFAULT;
3777 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3778 goto out;
3779 r = -ENXIO;
3780 if (!kvm->arch.vpit)
3781 goto out;
3782 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3783 break;
3784 }
3785 case KVM_REINJECT_CONTROL: {
3786 struct kvm_reinject_control control;
3787 r = -EFAULT;
3788 if (copy_from_user(&control, argp, sizeof(control)))
3789 goto out;
3790 r = kvm_vm_ioctl_reinject(kvm, &control);
3791 break;
3792 }
3793 case KVM_XEN_HVM_CONFIG: {
3794 r = -EFAULT;
3795 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3796 sizeof(struct kvm_xen_hvm_config)))
3797 goto out;
3798 r = -EINVAL;
3799 if (kvm->arch.xen_hvm_config.flags)
3800 goto out;
3801 r = 0;
3802 break;
3803 }
3804 case KVM_SET_CLOCK: {
3805 struct kvm_clock_data user_ns;
3806 u64 now_ns;
3807 s64 delta;
3808
3809 r = -EFAULT;
3810 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3811 goto out;
3812
3813 r = -EINVAL;
3814 if (user_ns.flags)
3815 goto out;
3816
3817 r = 0;
3818 local_irq_disable();
3819 now_ns = get_kernel_ns();
3820 delta = user_ns.clock - now_ns;
3821 local_irq_enable();
3822 kvm->arch.kvmclock_offset = delta;
3823 kvm_gen_update_masterclock(kvm);
3824 break;
3825 }
3826 case KVM_GET_CLOCK: {
3827 struct kvm_clock_data user_ns;
3828 u64 now_ns;
3829
3830 local_irq_disable();
3831 now_ns = get_kernel_ns();
3832 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3833 local_irq_enable();
3834 user_ns.flags = 0;
3835 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3836
3837 r = -EFAULT;
3838 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3839 goto out;
3840 r = 0;
3841 break;
3842 }
3843
3844 default:
3845 ;
3846 }
3847 out:
3848 return r;
3849 }
3850
3851 static void kvm_init_msr_list(void)
3852 {
3853 u32 dummy[2];
3854 unsigned i, j;
3855
3856 /* skip the first msrs in the list. KVM-specific */
3857 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3858 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3859 continue;
3860 if (j < i)
3861 msrs_to_save[j] = msrs_to_save[i];
3862 j++;
3863 }
3864 num_msrs_to_save = j;
3865 }
3866
3867 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3868 const void *v)
3869 {
3870 int handled = 0;
3871 int n;
3872
3873 do {
3874 n = min(len, 8);
3875 if (!(vcpu->arch.apic &&
3876 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3877 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3878 break;
3879 handled += n;
3880 addr += n;
3881 len -= n;
3882 v += n;
3883 } while (len);
3884
3885 return handled;
3886 }
3887
3888 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3889 {
3890 int handled = 0;
3891 int n;
3892
3893 do {
3894 n = min(len, 8);
3895 if (!(vcpu->arch.apic &&
3896 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3897 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3898 break;
3899 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3900 handled += n;
3901 addr += n;
3902 len -= n;
3903 v += n;
3904 } while (len);
3905
3906 return handled;
3907 }
3908
3909 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3910 struct kvm_segment *var, int seg)
3911 {
3912 kvm_x86_ops->set_segment(vcpu, var, seg);
3913 }
3914
3915 void kvm_get_segment(struct kvm_vcpu *vcpu,
3916 struct kvm_segment *var, int seg)
3917 {
3918 kvm_x86_ops->get_segment(vcpu, var, seg);
3919 }
3920
3921 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3922 {
3923 gpa_t t_gpa;
3924 struct x86_exception exception;
3925
3926 BUG_ON(!mmu_is_nested(vcpu));
3927
3928 /* NPT walks are always user-walks */
3929 access |= PFERR_USER_MASK;
3930 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3931
3932 return t_gpa;
3933 }
3934
3935 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3936 struct x86_exception *exception)
3937 {
3938 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3939 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3940 }
3941
3942 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3943 struct x86_exception *exception)
3944 {
3945 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3946 access |= PFERR_FETCH_MASK;
3947 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3948 }
3949
3950 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3951 struct x86_exception *exception)
3952 {
3953 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3954 access |= PFERR_WRITE_MASK;
3955 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3956 }
3957
3958 /* uses this to access any guest's mapped memory without checking CPL */
3959 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3960 struct x86_exception *exception)
3961 {
3962 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3963 }
3964
3965 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3966 struct kvm_vcpu *vcpu, u32 access,
3967 struct x86_exception *exception)
3968 {
3969 void *data = val;
3970 int r = X86EMUL_CONTINUE;
3971
3972 while (bytes) {
3973 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3974 exception);
3975 unsigned offset = addr & (PAGE_SIZE-1);
3976 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3977 int ret;
3978
3979 if (gpa == UNMAPPED_GVA)
3980 return X86EMUL_PROPAGATE_FAULT;
3981 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3982 if (ret < 0) {
3983 r = X86EMUL_IO_NEEDED;
3984 goto out;
3985 }
3986
3987 bytes -= toread;
3988 data += toread;
3989 addr += toread;
3990 }
3991 out:
3992 return r;
3993 }
3994
3995 /* used for instruction fetching */
3996 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3997 gva_t addr, void *val, unsigned int bytes,
3998 struct x86_exception *exception)
3999 {
4000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4001 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4002
4003 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4004 access | PFERR_FETCH_MASK,
4005 exception);
4006 }
4007
4008 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4009 gva_t addr, void *val, unsigned int bytes,
4010 struct x86_exception *exception)
4011 {
4012 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4013 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4014
4015 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4016 exception);
4017 }
4018 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4019
4020 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4021 gva_t addr, void *val, unsigned int bytes,
4022 struct x86_exception *exception)
4023 {
4024 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4025 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4026 }
4027
4028 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4029 gva_t addr, void *val,
4030 unsigned int bytes,
4031 struct x86_exception *exception)
4032 {
4033 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4034 void *data = val;
4035 int r = X86EMUL_CONTINUE;
4036
4037 while (bytes) {
4038 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4039 PFERR_WRITE_MASK,
4040 exception);
4041 unsigned offset = addr & (PAGE_SIZE-1);
4042 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4043 int ret;
4044
4045 if (gpa == UNMAPPED_GVA)
4046 return X86EMUL_PROPAGATE_FAULT;
4047 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4048 if (ret < 0) {
4049 r = X86EMUL_IO_NEEDED;
4050 goto out;
4051 }
4052
4053 bytes -= towrite;
4054 data += towrite;
4055 addr += towrite;
4056 }
4057 out:
4058 return r;
4059 }
4060 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4061
4062 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4063 gpa_t *gpa, struct x86_exception *exception,
4064 bool write)
4065 {
4066 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4067 | (write ? PFERR_WRITE_MASK : 0);
4068
4069 if (vcpu_match_mmio_gva(vcpu, gva)
4070 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4071 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4072 (gva & (PAGE_SIZE - 1));
4073 trace_vcpu_match_mmio(gva, *gpa, write, false);
4074 return 1;
4075 }
4076
4077 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4078
4079 if (*gpa == UNMAPPED_GVA)
4080 return -1;
4081
4082 /* For APIC access vmexit */
4083 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4084 return 1;
4085
4086 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4087 trace_vcpu_match_mmio(gva, *gpa, write, true);
4088 return 1;
4089 }
4090
4091 return 0;
4092 }
4093
4094 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4095 const void *val, int bytes)
4096 {
4097 int ret;
4098
4099 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4100 if (ret < 0)
4101 return 0;
4102 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4103 return 1;
4104 }
4105
4106 struct read_write_emulator_ops {
4107 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4108 int bytes);
4109 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4110 void *val, int bytes);
4111 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4112 int bytes, void *val);
4113 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4114 void *val, int bytes);
4115 bool write;
4116 };
4117
4118 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4119 {
4120 if (vcpu->mmio_read_completed) {
4121 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4122 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4123 vcpu->mmio_read_completed = 0;
4124 return 1;
4125 }
4126
4127 return 0;
4128 }
4129
4130 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4131 void *val, int bytes)
4132 {
4133 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4134 }
4135
4136 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4137 void *val, int bytes)
4138 {
4139 return emulator_write_phys(vcpu, gpa, val, bytes);
4140 }
4141
4142 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4143 {
4144 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4145 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4146 }
4147
4148 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4149 void *val, int bytes)
4150 {
4151 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4152 return X86EMUL_IO_NEEDED;
4153 }
4154
4155 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4156 void *val, int bytes)
4157 {
4158 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4159
4160 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4161 return X86EMUL_CONTINUE;
4162 }
4163
4164 static const struct read_write_emulator_ops read_emultor = {
4165 .read_write_prepare = read_prepare,
4166 .read_write_emulate = read_emulate,
4167 .read_write_mmio = vcpu_mmio_read,
4168 .read_write_exit_mmio = read_exit_mmio,
4169 };
4170
4171 static const struct read_write_emulator_ops write_emultor = {
4172 .read_write_emulate = write_emulate,
4173 .read_write_mmio = write_mmio,
4174 .read_write_exit_mmio = write_exit_mmio,
4175 .write = true,
4176 };
4177
4178 static int emulator_read_write_onepage(unsigned long addr, void *val,
4179 unsigned int bytes,
4180 struct x86_exception *exception,
4181 struct kvm_vcpu *vcpu,
4182 const struct read_write_emulator_ops *ops)
4183 {
4184 gpa_t gpa;
4185 int handled, ret;
4186 bool write = ops->write;
4187 struct kvm_mmio_fragment *frag;
4188
4189 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4190
4191 if (ret < 0)
4192 return X86EMUL_PROPAGATE_FAULT;
4193
4194 /* For APIC access vmexit */
4195 if (ret)
4196 goto mmio;
4197
4198 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4199 return X86EMUL_CONTINUE;
4200
4201 mmio:
4202 /*
4203 * Is this MMIO handled locally?
4204 */
4205 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4206 if (handled == bytes)
4207 return X86EMUL_CONTINUE;
4208
4209 gpa += handled;
4210 bytes -= handled;
4211 val += handled;
4212
4213 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4214 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4215 frag->gpa = gpa;
4216 frag->data = val;
4217 frag->len = bytes;
4218 return X86EMUL_CONTINUE;
4219 }
4220
4221 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4222 void *val, unsigned int bytes,
4223 struct x86_exception *exception,
4224 const struct read_write_emulator_ops *ops)
4225 {
4226 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4227 gpa_t gpa;
4228 int rc;
4229
4230 if (ops->read_write_prepare &&
4231 ops->read_write_prepare(vcpu, val, bytes))
4232 return X86EMUL_CONTINUE;
4233
4234 vcpu->mmio_nr_fragments = 0;
4235
4236 /* Crossing a page boundary? */
4237 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4238 int now;
4239
4240 now = -addr & ~PAGE_MASK;
4241 rc = emulator_read_write_onepage(addr, val, now, exception,
4242 vcpu, ops);
4243
4244 if (rc != X86EMUL_CONTINUE)
4245 return rc;
4246 addr += now;
4247 val += now;
4248 bytes -= now;
4249 }
4250
4251 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4252 vcpu, ops);
4253 if (rc != X86EMUL_CONTINUE)
4254 return rc;
4255
4256 if (!vcpu->mmio_nr_fragments)
4257 return rc;
4258
4259 gpa = vcpu->mmio_fragments[0].gpa;
4260
4261 vcpu->mmio_needed = 1;
4262 vcpu->mmio_cur_fragment = 0;
4263
4264 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4265 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4266 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4267 vcpu->run->mmio.phys_addr = gpa;
4268
4269 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4270 }
4271
4272 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4273 unsigned long addr,
4274 void *val,
4275 unsigned int bytes,
4276 struct x86_exception *exception)
4277 {
4278 return emulator_read_write(ctxt, addr, val, bytes,
4279 exception, &read_emultor);
4280 }
4281
4282 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4283 unsigned long addr,
4284 const void *val,
4285 unsigned int bytes,
4286 struct x86_exception *exception)
4287 {
4288 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4289 exception, &write_emultor);
4290 }
4291
4292 #define CMPXCHG_TYPE(t, ptr, old, new) \
4293 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4294
4295 #ifdef CONFIG_X86_64
4296 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4297 #else
4298 # define CMPXCHG64(ptr, old, new) \
4299 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4300 #endif
4301
4302 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4303 unsigned long addr,
4304 const void *old,
4305 const void *new,
4306 unsigned int bytes,
4307 struct x86_exception *exception)
4308 {
4309 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4310 gpa_t gpa;
4311 struct page *page;
4312 char *kaddr;
4313 bool exchanged;
4314
4315 /* guests cmpxchg8b have to be emulated atomically */
4316 if (bytes > 8 || (bytes & (bytes - 1)))
4317 goto emul_write;
4318
4319 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4320
4321 if (gpa == UNMAPPED_GVA ||
4322 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4323 goto emul_write;
4324
4325 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4326 goto emul_write;
4327
4328 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4329 if (is_error_page(page))
4330 goto emul_write;
4331
4332 kaddr = kmap_atomic(page);
4333 kaddr += offset_in_page(gpa);
4334 switch (bytes) {
4335 case 1:
4336 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4337 break;
4338 case 2:
4339 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4340 break;
4341 case 4:
4342 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4343 break;
4344 case 8:
4345 exchanged = CMPXCHG64(kaddr, old, new);
4346 break;
4347 default:
4348 BUG();
4349 }
4350 kunmap_atomic(kaddr);
4351 kvm_release_page_dirty(page);
4352
4353 if (!exchanged)
4354 return X86EMUL_CMPXCHG_FAILED;
4355
4356 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4357
4358 return X86EMUL_CONTINUE;
4359
4360 emul_write:
4361 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4362
4363 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4364 }
4365
4366 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4367 {
4368 /* TODO: String I/O for in kernel device */
4369 int r;
4370
4371 if (vcpu->arch.pio.in)
4372 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4373 vcpu->arch.pio.size, pd);
4374 else
4375 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4376 vcpu->arch.pio.port, vcpu->arch.pio.size,
4377 pd);
4378 return r;
4379 }
4380
4381 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4382 unsigned short port, void *val,
4383 unsigned int count, bool in)
4384 {
4385 trace_kvm_pio(!in, port, size, count);
4386
4387 vcpu->arch.pio.port = port;
4388 vcpu->arch.pio.in = in;
4389 vcpu->arch.pio.count = count;
4390 vcpu->arch.pio.size = size;
4391
4392 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4393 vcpu->arch.pio.count = 0;
4394 return 1;
4395 }
4396
4397 vcpu->run->exit_reason = KVM_EXIT_IO;
4398 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4399 vcpu->run->io.size = size;
4400 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4401 vcpu->run->io.count = count;
4402 vcpu->run->io.port = port;
4403
4404 return 0;
4405 }
4406
4407 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4408 int size, unsigned short port, void *val,
4409 unsigned int count)
4410 {
4411 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4412 int ret;
4413
4414 if (vcpu->arch.pio.count)
4415 goto data_avail;
4416
4417 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4418 if (ret) {
4419 data_avail:
4420 memcpy(val, vcpu->arch.pio_data, size * count);
4421 vcpu->arch.pio.count = 0;
4422 return 1;
4423 }
4424
4425 return 0;
4426 }
4427
4428 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4429 int size, unsigned short port,
4430 const void *val, unsigned int count)
4431 {
4432 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4433
4434 memcpy(vcpu->arch.pio_data, val, size * count);
4435 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4436 }
4437
4438 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4439 {
4440 return kvm_x86_ops->get_segment_base(vcpu, seg);
4441 }
4442
4443 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4444 {
4445 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4446 }
4447
4448 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4449 {
4450 if (!need_emulate_wbinvd(vcpu))
4451 return X86EMUL_CONTINUE;
4452
4453 if (kvm_x86_ops->has_wbinvd_exit()) {
4454 int cpu = get_cpu();
4455
4456 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4457 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4458 wbinvd_ipi, NULL, 1);
4459 put_cpu();
4460 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4461 } else
4462 wbinvd();
4463 return X86EMUL_CONTINUE;
4464 }
4465 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4466
4467 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4468 {
4469 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4470 }
4471
4472 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4473 {
4474 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4475 }
4476
4477 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4478 {
4479
4480 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4481 }
4482
4483 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4484 {
4485 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4486 }
4487
4488 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4489 {
4490 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4491 unsigned long value;
4492
4493 switch (cr) {
4494 case 0:
4495 value = kvm_read_cr0(vcpu);
4496 break;
4497 case 2:
4498 value = vcpu->arch.cr2;
4499 break;
4500 case 3:
4501 value = kvm_read_cr3(vcpu);
4502 break;
4503 case 4:
4504 value = kvm_read_cr4(vcpu);
4505 break;
4506 case 8:
4507 value = kvm_get_cr8(vcpu);
4508 break;
4509 default:
4510 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4511 return 0;
4512 }
4513
4514 return value;
4515 }
4516
4517 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4518 {
4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4520 int res = 0;
4521
4522 switch (cr) {
4523 case 0:
4524 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4525 break;
4526 case 2:
4527 vcpu->arch.cr2 = val;
4528 break;
4529 case 3:
4530 res = kvm_set_cr3(vcpu, val);
4531 break;
4532 case 4:
4533 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4534 break;
4535 case 8:
4536 res = kvm_set_cr8(vcpu, val);
4537 break;
4538 default:
4539 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4540 res = -1;
4541 }
4542
4543 return res;
4544 }
4545
4546 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4547 {
4548 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4549 }
4550
4551 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4552 {
4553 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4554 }
4555
4556 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4557 {
4558 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4559 }
4560
4561 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4562 {
4563 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4564 }
4565
4566 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4567 {
4568 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4569 }
4570
4571 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4572 {
4573 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4574 }
4575
4576 static unsigned long emulator_get_cached_segment_base(
4577 struct x86_emulate_ctxt *ctxt, int seg)
4578 {
4579 return get_segment_base(emul_to_vcpu(ctxt), seg);
4580 }
4581
4582 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4583 struct desc_struct *desc, u32 *base3,
4584 int seg)
4585 {
4586 struct kvm_segment var;
4587
4588 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4589 *selector = var.selector;
4590
4591 if (var.unusable) {
4592 memset(desc, 0, sizeof(*desc));
4593 return false;
4594 }
4595
4596 if (var.g)
4597 var.limit >>= 12;
4598 set_desc_limit(desc, var.limit);
4599 set_desc_base(desc, (unsigned long)var.base);
4600 #ifdef CONFIG_X86_64
4601 if (base3)
4602 *base3 = var.base >> 32;
4603 #endif
4604 desc->type = var.type;
4605 desc->s = var.s;
4606 desc->dpl = var.dpl;
4607 desc->p = var.present;
4608 desc->avl = var.avl;
4609 desc->l = var.l;
4610 desc->d = var.db;
4611 desc->g = var.g;
4612
4613 return true;
4614 }
4615
4616 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4617 struct desc_struct *desc, u32 base3,
4618 int seg)
4619 {
4620 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4621 struct kvm_segment var;
4622
4623 var.selector = selector;
4624 var.base = get_desc_base(desc);
4625 #ifdef CONFIG_X86_64
4626 var.base |= ((u64)base3) << 32;
4627 #endif
4628 var.limit = get_desc_limit(desc);
4629 if (desc->g)
4630 var.limit = (var.limit << 12) | 0xfff;
4631 var.type = desc->type;
4632 var.present = desc->p;
4633 var.dpl = desc->dpl;
4634 var.db = desc->d;
4635 var.s = desc->s;
4636 var.l = desc->l;
4637 var.g = desc->g;
4638 var.avl = desc->avl;
4639 var.present = desc->p;
4640 var.unusable = !var.present;
4641 var.padding = 0;
4642
4643 kvm_set_segment(vcpu, &var, seg);
4644 return;
4645 }
4646
4647 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4648 u32 msr_index, u64 *pdata)
4649 {
4650 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4651 }
4652
4653 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4654 u32 msr_index, u64 data)
4655 {
4656 struct msr_data msr;
4657
4658 msr.data = data;
4659 msr.index = msr_index;
4660 msr.host_initiated = false;
4661 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4662 }
4663
4664 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4665 u32 pmc, u64 *pdata)
4666 {
4667 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4668 }
4669
4670 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4671 {
4672 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4673 }
4674
4675 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4676 {
4677 preempt_disable();
4678 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4679 /*
4680 * CR0.TS may reference the host fpu state, not the guest fpu state,
4681 * so it may be clear at this point.
4682 */
4683 clts();
4684 }
4685
4686 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4687 {
4688 preempt_enable();
4689 }
4690
4691 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4692 struct x86_instruction_info *info,
4693 enum x86_intercept_stage stage)
4694 {
4695 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4696 }
4697
4698 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4699 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4700 {
4701 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4702 }
4703
4704 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4705 {
4706 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4707 }
4708
4709 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4710 {
4711 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4712 }
4713
4714 static const struct x86_emulate_ops emulate_ops = {
4715 .read_gpr = emulator_read_gpr,
4716 .write_gpr = emulator_write_gpr,
4717 .read_std = kvm_read_guest_virt_system,
4718 .write_std = kvm_write_guest_virt_system,
4719 .fetch = kvm_fetch_guest_virt,
4720 .read_emulated = emulator_read_emulated,
4721 .write_emulated = emulator_write_emulated,
4722 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4723 .invlpg = emulator_invlpg,
4724 .pio_in_emulated = emulator_pio_in_emulated,
4725 .pio_out_emulated = emulator_pio_out_emulated,
4726 .get_segment = emulator_get_segment,
4727 .set_segment = emulator_set_segment,
4728 .get_cached_segment_base = emulator_get_cached_segment_base,
4729 .get_gdt = emulator_get_gdt,
4730 .get_idt = emulator_get_idt,
4731 .set_gdt = emulator_set_gdt,
4732 .set_idt = emulator_set_idt,
4733 .get_cr = emulator_get_cr,
4734 .set_cr = emulator_set_cr,
4735 .set_rflags = emulator_set_rflags,
4736 .cpl = emulator_get_cpl,
4737 .get_dr = emulator_get_dr,
4738 .set_dr = emulator_set_dr,
4739 .set_msr = emulator_set_msr,
4740 .get_msr = emulator_get_msr,
4741 .read_pmc = emulator_read_pmc,
4742 .halt = emulator_halt,
4743 .wbinvd = emulator_wbinvd,
4744 .fix_hypercall = emulator_fix_hypercall,
4745 .get_fpu = emulator_get_fpu,
4746 .put_fpu = emulator_put_fpu,
4747 .intercept = emulator_intercept,
4748 .get_cpuid = emulator_get_cpuid,
4749 };
4750
4751 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4752 {
4753 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4754 /*
4755 * an sti; sti; sequence only disable interrupts for the first
4756 * instruction. So, if the last instruction, be it emulated or
4757 * not, left the system with the INT_STI flag enabled, it
4758 * means that the last instruction is an sti. We should not
4759 * leave the flag on in this case. The same goes for mov ss
4760 */
4761 if (!(int_shadow & mask))
4762 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4763 }
4764
4765 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4766 {
4767 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4768 if (ctxt->exception.vector == PF_VECTOR)
4769 kvm_propagate_fault(vcpu, &ctxt->exception);
4770 else if (ctxt->exception.error_code_valid)
4771 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4772 ctxt->exception.error_code);
4773 else
4774 kvm_queue_exception(vcpu, ctxt->exception.vector);
4775 }
4776
4777 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4778 {
4779 memset(&ctxt->twobyte, 0,
4780 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4781
4782 ctxt->fetch.start = 0;
4783 ctxt->fetch.end = 0;
4784 ctxt->io_read.pos = 0;
4785 ctxt->io_read.end = 0;
4786 ctxt->mem_read.pos = 0;
4787 ctxt->mem_read.end = 0;
4788 }
4789
4790 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4791 {
4792 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4793 int cs_db, cs_l;
4794
4795 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4796
4797 ctxt->eflags = kvm_get_rflags(vcpu);
4798 ctxt->eip = kvm_rip_read(vcpu);
4799 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4800 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4801 cs_l ? X86EMUL_MODE_PROT64 :
4802 cs_db ? X86EMUL_MODE_PROT32 :
4803 X86EMUL_MODE_PROT16;
4804 ctxt->guest_mode = is_guest_mode(vcpu);
4805
4806 init_decode_cache(ctxt);
4807 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4808 }
4809
4810 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4811 {
4812 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4813 int ret;
4814
4815 init_emulate_ctxt(vcpu);
4816
4817 ctxt->op_bytes = 2;
4818 ctxt->ad_bytes = 2;
4819 ctxt->_eip = ctxt->eip + inc_eip;
4820 ret = emulate_int_real(ctxt, irq);
4821
4822 if (ret != X86EMUL_CONTINUE)
4823 return EMULATE_FAIL;
4824
4825 ctxt->eip = ctxt->_eip;
4826 kvm_rip_write(vcpu, ctxt->eip);
4827 kvm_set_rflags(vcpu, ctxt->eflags);
4828
4829 if (irq == NMI_VECTOR)
4830 vcpu->arch.nmi_pending = 0;
4831 else
4832 vcpu->arch.interrupt.pending = false;
4833
4834 return EMULATE_DONE;
4835 }
4836 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4837
4838 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4839 {
4840 int r = EMULATE_DONE;
4841
4842 ++vcpu->stat.insn_emulation_fail;
4843 trace_kvm_emulate_insn_failed(vcpu);
4844 if (!is_guest_mode(vcpu)) {
4845 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4846 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4847 vcpu->run->internal.ndata = 0;
4848 r = EMULATE_FAIL;
4849 }
4850 kvm_queue_exception(vcpu, UD_VECTOR);
4851
4852 return r;
4853 }
4854
4855 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4856 bool write_fault_to_shadow_pgtable,
4857 int emulation_type)
4858 {
4859 gpa_t gpa = cr2;
4860 pfn_t pfn;
4861
4862 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4863 return false;
4864
4865 if (!vcpu->arch.mmu.direct_map) {
4866 /*
4867 * Write permission should be allowed since only
4868 * write access need to be emulated.
4869 */
4870 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4871
4872 /*
4873 * If the mapping is invalid in guest, let cpu retry
4874 * it to generate fault.
4875 */
4876 if (gpa == UNMAPPED_GVA)
4877 return true;
4878 }
4879
4880 /*
4881 * Do not retry the unhandleable instruction if it faults on the
4882 * readonly host memory, otherwise it will goto a infinite loop:
4883 * retry instruction -> write #PF -> emulation fail -> retry
4884 * instruction -> ...
4885 */
4886 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4887
4888 /*
4889 * If the instruction failed on the error pfn, it can not be fixed,
4890 * report the error to userspace.
4891 */
4892 if (is_error_noslot_pfn(pfn))
4893 return false;
4894
4895 kvm_release_pfn_clean(pfn);
4896
4897 /* The instructions are well-emulated on direct mmu. */
4898 if (vcpu->arch.mmu.direct_map) {
4899 unsigned int indirect_shadow_pages;
4900
4901 spin_lock(&vcpu->kvm->mmu_lock);
4902 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4903 spin_unlock(&vcpu->kvm->mmu_lock);
4904
4905 if (indirect_shadow_pages)
4906 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4907
4908 return true;
4909 }
4910
4911 /*
4912 * if emulation was due to access to shadowed page table
4913 * and it failed try to unshadow page and re-enter the
4914 * guest to let CPU execute the instruction.
4915 */
4916 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4917
4918 /*
4919 * If the access faults on its page table, it can not
4920 * be fixed by unprotecting shadow page and it should
4921 * be reported to userspace.
4922 */
4923 return !write_fault_to_shadow_pgtable;
4924 }
4925
4926 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4927 unsigned long cr2, int emulation_type)
4928 {
4929 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4930 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4931
4932 last_retry_eip = vcpu->arch.last_retry_eip;
4933 last_retry_addr = vcpu->arch.last_retry_addr;
4934
4935 /*
4936 * If the emulation is caused by #PF and it is non-page_table
4937 * writing instruction, it means the VM-EXIT is caused by shadow
4938 * page protected, we can zap the shadow page and retry this
4939 * instruction directly.
4940 *
4941 * Note: if the guest uses a non-page-table modifying instruction
4942 * on the PDE that points to the instruction, then we will unmap
4943 * the instruction and go to an infinite loop. So, we cache the
4944 * last retried eip and the last fault address, if we meet the eip
4945 * and the address again, we can break out of the potential infinite
4946 * loop.
4947 */
4948 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4949
4950 if (!(emulation_type & EMULTYPE_RETRY))
4951 return false;
4952
4953 if (x86_page_table_writing_insn(ctxt))
4954 return false;
4955
4956 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4957 return false;
4958
4959 vcpu->arch.last_retry_eip = ctxt->eip;
4960 vcpu->arch.last_retry_addr = cr2;
4961
4962 if (!vcpu->arch.mmu.direct_map)
4963 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4964
4965 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4966
4967 return true;
4968 }
4969
4970 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4971 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4972
4973 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4974 unsigned long *db)
4975 {
4976 u32 dr6 = 0;
4977 int i;
4978 u32 enable, rwlen;
4979
4980 enable = dr7;
4981 rwlen = dr7 >> 16;
4982 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4983 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4984 dr6 |= (1 << i);
4985 return dr6;
4986 }
4987
4988 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
4989 {
4990 struct kvm_run *kvm_run = vcpu->run;
4991
4992 /*
4993 * Use the "raw" value to see if TF was passed to the processor.
4994 * Note that the new value of the flags has not been saved yet.
4995 *
4996 * This is correct even for TF set by the guest, because "the
4997 * processor will not generate this exception after the instruction
4998 * that sets the TF flag".
4999 */
5000 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5001
5002 if (unlikely(rflags & X86_EFLAGS_TF)) {
5003 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5004 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5005 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5006 kvm_run->debug.arch.exception = DB_VECTOR;
5007 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5008 *r = EMULATE_USER_EXIT;
5009 } else {
5010 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5011 /*
5012 * "Certain debug exceptions may clear bit 0-3. The
5013 * remaining contents of the DR6 register are never
5014 * cleared by the processor".
5015 */
5016 vcpu->arch.dr6 &= ~15;
5017 vcpu->arch.dr6 |= DR6_BS;
5018 kvm_queue_exception(vcpu, DB_VECTOR);
5019 }
5020 }
5021 }
5022
5023 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5024 {
5025 struct kvm_run *kvm_run = vcpu->run;
5026 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5027 u32 dr6 = 0;
5028
5029 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5030 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5031 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5032 vcpu->arch.guest_debug_dr7,
5033 vcpu->arch.eff_db);
5034
5035 if (dr6 != 0) {
5036 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5037 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5038 get_segment_base(vcpu, VCPU_SREG_CS);
5039
5040 kvm_run->debug.arch.exception = DB_VECTOR;
5041 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5042 *r = EMULATE_USER_EXIT;
5043 return true;
5044 }
5045 }
5046
5047 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5048 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5049 vcpu->arch.dr7,
5050 vcpu->arch.db);
5051
5052 if (dr6 != 0) {
5053 vcpu->arch.dr6 &= ~15;
5054 vcpu->arch.dr6 |= dr6;
5055 kvm_queue_exception(vcpu, DB_VECTOR);
5056 *r = EMULATE_DONE;
5057 return true;
5058 }
5059 }
5060
5061 return false;
5062 }
5063
5064 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5065 unsigned long cr2,
5066 int emulation_type,
5067 void *insn,
5068 int insn_len)
5069 {
5070 int r;
5071 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5072 bool writeback = true;
5073 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5074
5075 /*
5076 * Clear write_fault_to_shadow_pgtable here to ensure it is
5077 * never reused.
5078 */
5079 vcpu->arch.write_fault_to_shadow_pgtable = false;
5080 kvm_clear_exception_queue(vcpu);
5081
5082 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5083 init_emulate_ctxt(vcpu);
5084
5085 /*
5086 * We will reenter on the same instruction since
5087 * we do not set complete_userspace_io. This does not
5088 * handle watchpoints yet, those would be handled in
5089 * the emulate_ops.
5090 */
5091 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5092 return r;
5093
5094 ctxt->interruptibility = 0;
5095 ctxt->have_exception = false;
5096 ctxt->perm_ok = false;
5097
5098 ctxt->only_vendor_specific_insn
5099 = emulation_type & EMULTYPE_TRAP_UD;
5100
5101 r = x86_decode_insn(ctxt, insn, insn_len);
5102
5103 trace_kvm_emulate_insn_start(vcpu);
5104 ++vcpu->stat.insn_emulation;
5105 if (r != EMULATION_OK) {
5106 if (emulation_type & EMULTYPE_TRAP_UD)
5107 return EMULATE_FAIL;
5108 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5109 emulation_type))
5110 return EMULATE_DONE;
5111 if (emulation_type & EMULTYPE_SKIP)
5112 return EMULATE_FAIL;
5113 return handle_emulation_failure(vcpu);
5114 }
5115 }
5116
5117 if (emulation_type & EMULTYPE_SKIP) {
5118 kvm_rip_write(vcpu, ctxt->_eip);
5119 return EMULATE_DONE;
5120 }
5121
5122 if (retry_instruction(ctxt, cr2, emulation_type))
5123 return EMULATE_DONE;
5124
5125 /* this is needed for vmware backdoor interface to work since it
5126 changes registers values during IO operation */
5127 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5128 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5129 emulator_invalidate_register_cache(ctxt);
5130 }
5131
5132 restart:
5133 r = x86_emulate_insn(ctxt);
5134
5135 if (r == EMULATION_INTERCEPTED)
5136 return EMULATE_DONE;
5137
5138 if (r == EMULATION_FAILED) {
5139 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5140 emulation_type))
5141 return EMULATE_DONE;
5142
5143 return handle_emulation_failure(vcpu);
5144 }
5145
5146 if (ctxt->have_exception) {
5147 inject_emulated_exception(vcpu);
5148 r = EMULATE_DONE;
5149 } else if (vcpu->arch.pio.count) {
5150 if (!vcpu->arch.pio.in) {
5151 /* FIXME: return into emulator if single-stepping. */
5152 vcpu->arch.pio.count = 0;
5153 } else {
5154 writeback = false;
5155 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5156 }
5157 r = EMULATE_USER_EXIT;
5158 } else if (vcpu->mmio_needed) {
5159 if (!vcpu->mmio_is_write)
5160 writeback = false;
5161 r = EMULATE_USER_EXIT;
5162 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5163 } else if (r == EMULATION_RESTART)
5164 goto restart;
5165 else
5166 r = EMULATE_DONE;
5167
5168 if (writeback) {
5169 toggle_interruptibility(vcpu, ctxt->interruptibility);
5170 kvm_make_request(KVM_REQ_EVENT, vcpu);
5171 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5172 kvm_rip_write(vcpu, ctxt->eip);
5173 if (r == EMULATE_DONE)
5174 kvm_vcpu_check_singlestep(vcpu, &r);
5175 kvm_set_rflags(vcpu, ctxt->eflags);
5176 } else
5177 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5178
5179 return r;
5180 }
5181 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5182
5183 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5184 {
5185 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5186 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5187 size, port, &val, 1);
5188 /* do not return to emulator after return from userspace */
5189 vcpu->arch.pio.count = 0;
5190 return ret;
5191 }
5192 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5193
5194 static void tsc_bad(void *info)
5195 {
5196 __this_cpu_write(cpu_tsc_khz, 0);
5197 }
5198
5199 static void tsc_khz_changed(void *data)
5200 {
5201 struct cpufreq_freqs *freq = data;
5202 unsigned long khz = 0;
5203
5204 if (data)
5205 khz = freq->new;
5206 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5207 khz = cpufreq_quick_get(raw_smp_processor_id());
5208 if (!khz)
5209 khz = tsc_khz;
5210 __this_cpu_write(cpu_tsc_khz, khz);
5211 }
5212
5213 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5214 void *data)
5215 {
5216 struct cpufreq_freqs *freq = data;
5217 struct kvm *kvm;
5218 struct kvm_vcpu *vcpu;
5219 int i, send_ipi = 0;
5220
5221 /*
5222 * We allow guests to temporarily run on slowing clocks,
5223 * provided we notify them after, or to run on accelerating
5224 * clocks, provided we notify them before. Thus time never
5225 * goes backwards.
5226 *
5227 * However, we have a problem. We can't atomically update
5228 * the frequency of a given CPU from this function; it is
5229 * merely a notifier, which can be called from any CPU.
5230 * Changing the TSC frequency at arbitrary points in time
5231 * requires a recomputation of local variables related to
5232 * the TSC for each VCPU. We must flag these local variables
5233 * to be updated and be sure the update takes place with the
5234 * new frequency before any guests proceed.
5235 *
5236 * Unfortunately, the combination of hotplug CPU and frequency
5237 * change creates an intractable locking scenario; the order
5238 * of when these callouts happen is undefined with respect to
5239 * CPU hotplug, and they can race with each other. As such,
5240 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5241 * undefined; you can actually have a CPU frequency change take
5242 * place in between the computation of X and the setting of the
5243 * variable. To protect against this problem, all updates of
5244 * the per_cpu tsc_khz variable are done in an interrupt
5245 * protected IPI, and all callers wishing to update the value
5246 * must wait for a synchronous IPI to complete (which is trivial
5247 * if the caller is on the CPU already). This establishes the
5248 * necessary total order on variable updates.
5249 *
5250 * Note that because a guest time update may take place
5251 * anytime after the setting of the VCPU's request bit, the
5252 * correct TSC value must be set before the request. However,
5253 * to ensure the update actually makes it to any guest which
5254 * starts running in hardware virtualization between the set
5255 * and the acquisition of the spinlock, we must also ping the
5256 * CPU after setting the request bit.
5257 *
5258 */
5259
5260 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5261 return 0;
5262 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5263 return 0;
5264
5265 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5266
5267 raw_spin_lock(&kvm_lock);
5268 list_for_each_entry(kvm, &vm_list, vm_list) {
5269 kvm_for_each_vcpu(i, vcpu, kvm) {
5270 if (vcpu->cpu != freq->cpu)
5271 continue;
5272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5273 if (vcpu->cpu != smp_processor_id())
5274 send_ipi = 1;
5275 }
5276 }
5277 raw_spin_unlock(&kvm_lock);
5278
5279 if (freq->old < freq->new && send_ipi) {
5280 /*
5281 * We upscale the frequency. Must make the guest
5282 * doesn't see old kvmclock values while running with
5283 * the new frequency, otherwise we risk the guest sees
5284 * time go backwards.
5285 *
5286 * In case we update the frequency for another cpu
5287 * (which might be in guest context) send an interrupt
5288 * to kick the cpu out of guest context. Next time
5289 * guest context is entered kvmclock will be updated,
5290 * so the guest will not see stale values.
5291 */
5292 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5293 }
5294 return 0;
5295 }
5296
5297 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5298 .notifier_call = kvmclock_cpufreq_notifier
5299 };
5300
5301 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5302 unsigned long action, void *hcpu)
5303 {
5304 unsigned int cpu = (unsigned long)hcpu;
5305
5306 switch (action) {
5307 case CPU_ONLINE:
5308 case CPU_DOWN_FAILED:
5309 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5310 break;
5311 case CPU_DOWN_PREPARE:
5312 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5313 break;
5314 }
5315 return NOTIFY_OK;
5316 }
5317
5318 static struct notifier_block kvmclock_cpu_notifier_block = {
5319 .notifier_call = kvmclock_cpu_notifier,
5320 .priority = -INT_MAX
5321 };
5322
5323 static void kvm_timer_init(void)
5324 {
5325 int cpu;
5326
5327 max_tsc_khz = tsc_khz;
5328 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5329 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5330 #ifdef CONFIG_CPU_FREQ
5331 struct cpufreq_policy policy;
5332 memset(&policy, 0, sizeof(policy));
5333 cpu = get_cpu();
5334 cpufreq_get_policy(&policy, cpu);
5335 if (policy.cpuinfo.max_freq)
5336 max_tsc_khz = policy.cpuinfo.max_freq;
5337 put_cpu();
5338 #endif
5339 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5340 CPUFREQ_TRANSITION_NOTIFIER);
5341 }
5342 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5343 for_each_online_cpu(cpu)
5344 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5345 }
5346
5347 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5348
5349 int kvm_is_in_guest(void)
5350 {
5351 return __this_cpu_read(current_vcpu) != NULL;
5352 }
5353
5354 static int kvm_is_user_mode(void)
5355 {
5356 int user_mode = 3;
5357
5358 if (__this_cpu_read(current_vcpu))
5359 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5360
5361 return user_mode != 0;
5362 }
5363
5364 static unsigned long kvm_get_guest_ip(void)
5365 {
5366 unsigned long ip = 0;
5367
5368 if (__this_cpu_read(current_vcpu))
5369 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5370
5371 return ip;
5372 }
5373
5374 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5375 .is_in_guest = kvm_is_in_guest,
5376 .is_user_mode = kvm_is_user_mode,
5377 .get_guest_ip = kvm_get_guest_ip,
5378 };
5379
5380 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5381 {
5382 __this_cpu_write(current_vcpu, vcpu);
5383 }
5384 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5385
5386 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5387 {
5388 __this_cpu_write(current_vcpu, NULL);
5389 }
5390 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5391
5392 static void kvm_set_mmio_spte_mask(void)
5393 {
5394 u64 mask;
5395 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5396
5397 /*
5398 * Set the reserved bits and the present bit of an paging-structure
5399 * entry to generate page fault with PFER.RSV = 1.
5400 */
5401 /* Mask the reserved physical address bits. */
5402 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5403
5404 /* Bit 62 is always reserved for 32bit host. */
5405 mask |= 0x3ull << 62;
5406
5407 /* Set the present bit. */
5408 mask |= 1ull;
5409
5410 #ifdef CONFIG_X86_64
5411 /*
5412 * If reserved bit is not supported, clear the present bit to disable
5413 * mmio page fault.
5414 */
5415 if (maxphyaddr == 52)
5416 mask &= ~1ull;
5417 #endif
5418
5419 kvm_mmu_set_mmio_spte_mask(mask);
5420 }
5421
5422 #ifdef CONFIG_X86_64
5423 static void pvclock_gtod_update_fn(struct work_struct *work)
5424 {
5425 struct kvm *kvm;
5426
5427 struct kvm_vcpu *vcpu;
5428 int i;
5429
5430 raw_spin_lock(&kvm_lock);
5431 list_for_each_entry(kvm, &vm_list, vm_list)
5432 kvm_for_each_vcpu(i, vcpu, kvm)
5433 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5434 atomic_set(&kvm_guest_has_master_clock, 0);
5435 raw_spin_unlock(&kvm_lock);
5436 }
5437
5438 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5439
5440 /*
5441 * Notification about pvclock gtod data update.
5442 */
5443 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5444 void *priv)
5445 {
5446 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5447 struct timekeeper *tk = priv;
5448
5449 update_pvclock_gtod(tk);
5450
5451 /* disable master clock if host does not trust, or does not
5452 * use, TSC clocksource
5453 */
5454 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5455 atomic_read(&kvm_guest_has_master_clock) != 0)
5456 queue_work(system_long_wq, &pvclock_gtod_work);
5457
5458 return 0;
5459 }
5460
5461 static struct notifier_block pvclock_gtod_notifier = {
5462 .notifier_call = pvclock_gtod_notify,
5463 };
5464 #endif
5465
5466 int kvm_arch_init(void *opaque)
5467 {
5468 int r;
5469 struct kvm_x86_ops *ops = opaque;
5470
5471 if (kvm_x86_ops) {
5472 printk(KERN_ERR "kvm: already loaded the other module\n");
5473 r = -EEXIST;
5474 goto out;
5475 }
5476
5477 if (!ops->cpu_has_kvm_support()) {
5478 printk(KERN_ERR "kvm: no hardware support\n");
5479 r = -EOPNOTSUPP;
5480 goto out;
5481 }
5482 if (ops->disabled_by_bios()) {
5483 printk(KERN_ERR "kvm: disabled by bios\n");
5484 r = -EOPNOTSUPP;
5485 goto out;
5486 }
5487
5488 r = -ENOMEM;
5489 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5490 if (!shared_msrs) {
5491 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5492 goto out;
5493 }
5494
5495 r = kvm_mmu_module_init();
5496 if (r)
5497 goto out_free_percpu;
5498
5499 kvm_set_mmio_spte_mask();
5500 kvm_init_msr_list();
5501
5502 kvm_x86_ops = ops;
5503 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5504 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5505
5506 kvm_timer_init();
5507
5508 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5509
5510 if (cpu_has_xsave)
5511 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5512
5513 kvm_lapic_init();
5514 #ifdef CONFIG_X86_64
5515 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5516 #endif
5517
5518 return 0;
5519
5520 out_free_percpu:
5521 free_percpu(shared_msrs);
5522 out:
5523 return r;
5524 }
5525
5526 void kvm_arch_exit(void)
5527 {
5528 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5529
5530 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5531 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5532 CPUFREQ_TRANSITION_NOTIFIER);
5533 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5534 #ifdef CONFIG_X86_64
5535 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5536 #endif
5537 kvm_x86_ops = NULL;
5538 kvm_mmu_module_exit();
5539 free_percpu(shared_msrs);
5540 }
5541
5542 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5543 {
5544 ++vcpu->stat.halt_exits;
5545 if (irqchip_in_kernel(vcpu->kvm)) {
5546 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5547 return 1;
5548 } else {
5549 vcpu->run->exit_reason = KVM_EXIT_HLT;
5550 return 0;
5551 }
5552 }
5553 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5554
5555 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5556 {
5557 u64 param, ingpa, outgpa, ret;
5558 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5559 bool fast, longmode;
5560 int cs_db, cs_l;
5561
5562 /*
5563 * hypercall generates UD from non zero cpl and real mode
5564 * per HYPER-V spec
5565 */
5566 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5567 kvm_queue_exception(vcpu, UD_VECTOR);
5568 return 0;
5569 }
5570
5571 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5572 longmode = is_long_mode(vcpu) && cs_l == 1;
5573
5574 if (!longmode) {
5575 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5576 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5577 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5578 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5579 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5580 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5581 }
5582 #ifdef CONFIG_X86_64
5583 else {
5584 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5585 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5586 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5587 }
5588 #endif
5589
5590 code = param & 0xffff;
5591 fast = (param >> 16) & 0x1;
5592 rep_cnt = (param >> 32) & 0xfff;
5593 rep_idx = (param >> 48) & 0xfff;
5594
5595 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5596
5597 switch (code) {
5598 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5599 kvm_vcpu_on_spin(vcpu);
5600 break;
5601 default:
5602 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5603 break;
5604 }
5605
5606 ret = res | (((u64)rep_done & 0xfff) << 32);
5607 if (longmode) {
5608 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5609 } else {
5610 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5611 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5612 }
5613
5614 return 1;
5615 }
5616
5617 /*
5618 * kvm_pv_kick_cpu_op: Kick a vcpu.
5619 *
5620 * @apicid - apicid of vcpu to be kicked.
5621 */
5622 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5623 {
5624 struct kvm_lapic_irq lapic_irq;
5625
5626 lapic_irq.shorthand = 0;
5627 lapic_irq.dest_mode = 0;
5628 lapic_irq.dest_id = apicid;
5629
5630 lapic_irq.delivery_mode = APIC_DM_REMRD;
5631 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5632 }
5633
5634 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5635 {
5636 unsigned long nr, a0, a1, a2, a3, ret;
5637 int r = 1;
5638
5639 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5640 return kvm_hv_hypercall(vcpu);
5641
5642 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5643 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5644 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5645 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5646 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5647
5648 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5649
5650 if (!is_long_mode(vcpu)) {
5651 nr &= 0xFFFFFFFF;
5652 a0 &= 0xFFFFFFFF;
5653 a1 &= 0xFFFFFFFF;
5654 a2 &= 0xFFFFFFFF;
5655 a3 &= 0xFFFFFFFF;
5656 }
5657
5658 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5659 ret = -KVM_EPERM;
5660 goto out;
5661 }
5662
5663 switch (nr) {
5664 case KVM_HC_VAPIC_POLL_IRQ:
5665 ret = 0;
5666 break;
5667 case KVM_HC_KICK_CPU:
5668 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5669 ret = 0;
5670 break;
5671 default:
5672 ret = -KVM_ENOSYS;
5673 break;
5674 }
5675 out:
5676 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5677 ++vcpu->stat.hypercalls;
5678 return r;
5679 }
5680 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5681
5682 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5683 {
5684 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5685 char instruction[3];
5686 unsigned long rip = kvm_rip_read(vcpu);
5687
5688 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5689
5690 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5691 }
5692
5693 /*
5694 * Check if userspace requested an interrupt window, and that the
5695 * interrupt window is open.
5696 *
5697 * No need to exit to userspace if we already have an interrupt queued.
5698 */
5699 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5700 {
5701 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5702 vcpu->run->request_interrupt_window &&
5703 kvm_arch_interrupt_allowed(vcpu));
5704 }
5705
5706 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5707 {
5708 struct kvm_run *kvm_run = vcpu->run;
5709
5710 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5711 kvm_run->cr8 = kvm_get_cr8(vcpu);
5712 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5713 if (irqchip_in_kernel(vcpu->kvm))
5714 kvm_run->ready_for_interrupt_injection = 1;
5715 else
5716 kvm_run->ready_for_interrupt_injection =
5717 kvm_arch_interrupt_allowed(vcpu) &&
5718 !kvm_cpu_has_interrupt(vcpu) &&
5719 !kvm_event_needs_reinjection(vcpu);
5720 }
5721
5722 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5723 {
5724 int max_irr, tpr;
5725
5726 if (!kvm_x86_ops->update_cr8_intercept)
5727 return;
5728
5729 if (!vcpu->arch.apic)
5730 return;
5731
5732 if (!vcpu->arch.apic->vapic_addr)
5733 max_irr = kvm_lapic_find_highest_irr(vcpu);
5734 else
5735 max_irr = -1;
5736
5737 if (max_irr != -1)
5738 max_irr >>= 4;
5739
5740 tpr = kvm_lapic_get_cr8(vcpu);
5741
5742 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5743 }
5744
5745 static void inject_pending_event(struct kvm_vcpu *vcpu)
5746 {
5747 /* try to reinject previous events if any */
5748 if (vcpu->arch.exception.pending) {
5749 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5750 vcpu->arch.exception.has_error_code,
5751 vcpu->arch.exception.error_code);
5752 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5753 vcpu->arch.exception.has_error_code,
5754 vcpu->arch.exception.error_code,
5755 vcpu->arch.exception.reinject);
5756 return;
5757 }
5758
5759 if (vcpu->arch.nmi_injected) {
5760 kvm_x86_ops->set_nmi(vcpu);
5761 return;
5762 }
5763
5764 if (vcpu->arch.interrupt.pending) {
5765 kvm_x86_ops->set_irq(vcpu);
5766 return;
5767 }
5768
5769 /* try to inject new event if pending */
5770 if (vcpu->arch.nmi_pending) {
5771 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5772 --vcpu->arch.nmi_pending;
5773 vcpu->arch.nmi_injected = true;
5774 kvm_x86_ops->set_nmi(vcpu);
5775 }
5776 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5777 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5778 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5779 false);
5780 kvm_x86_ops->set_irq(vcpu);
5781 }
5782 }
5783 }
5784
5785 static void process_nmi(struct kvm_vcpu *vcpu)
5786 {
5787 unsigned limit = 2;
5788
5789 /*
5790 * x86 is limited to one NMI running, and one NMI pending after it.
5791 * If an NMI is already in progress, limit further NMIs to just one.
5792 * Otherwise, allow two (and we'll inject the first one immediately).
5793 */
5794 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5795 limit = 1;
5796
5797 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5798 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5799 kvm_make_request(KVM_REQ_EVENT, vcpu);
5800 }
5801
5802 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5803 {
5804 u64 eoi_exit_bitmap[4];
5805 u32 tmr[8];
5806
5807 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5808 return;
5809
5810 memset(eoi_exit_bitmap, 0, 32);
5811 memset(tmr, 0, 32);
5812
5813 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5814 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5815 kvm_apic_update_tmr(vcpu, tmr);
5816 }
5817
5818 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5819 {
5820 int r;
5821 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5822 vcpu->run->request_interrupt_window;
5823 bool req_immediate_exit = false;
5824
5825 if (vcpu->requests) {
5826 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5827 kvm_mmu_unload(vcpu);
5828 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5829 __kvm_migrate_timers(vcpu);
5830 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5831 kvm_gen_update_masterclock(vcpu->kvm);
5832 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5833 kvm_gen_kvmclock_update(vcpu);
5834 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5835 r = kvm_guest_time_update(vcpu);
5836 if (unlikely(r))
5837 goto out;
5838 }
5839 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5840 kvm_mmu_sync_roots(vcpu);
5841 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5842 kvm_x86_ops->tlb_flush(vcpu);
5843 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5844 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5845 r = 0;
5846 goto out;
5847 }
5848 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5849 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5850 r = 0;
5851 goto out;
5852 }
5853 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5854 vcpu->fpu_active = 0;
5855 kvm_x86_ops->fpu_deactivate(vcpu);
5856 }
5857 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5858 /* Page is swapped out. Do synthetic halt */
5859 vcpu->arch.apf.halted = true;
5860 r = 1;
5861 goto out;
5862 }
5863 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5864 record_steal_time(vcpu);
5865 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5866 process_nmi(vcpu);
5867 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5868 kvm_handle_pmu_event(vcpu);
5869 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5870 kvm_deliver_pmi(vcpu);
5871 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5872 vcpu_scan_ioapic(vcpu);
5873 }
5874
5875 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5876 kvm_apic_accept_events(vcpu);
5877 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5878 r = 1;
5879 goto out;
5880 }
5881
5882 inject_pending_event(vcpu);
5883
5884 /* enable NMI/IRQ window open exits if needed */
5885 if (vcpu->arch.nmi_pending)
5886 req_immediate_exit =
5887 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5888 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5889 req_immediate_exit =
5890 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5891
5892 if (kvm_lapic_enabled(vcpu)) {
5893 /*
5894 * Update architecture specific hints for APIC
5895 * virtual interrupt delivery.
5896 */
5897 if (kvm_x86_ops->hwapic_irr_update)
5898 kvm_x86_ops->hwapic_irr_update(vcpu,
5899 kvm_lapic_find_highest_irr(vcpu));
5900 update_cr8_intercept(vcpu);
5901 kvm_lapic_sync_to_vapic(vcpu);
5902 }
5903 }
5904
5905 r = kvm_mmu_reload(vcpu);
5906 if (unlikely(r)) {
5907 goto cancel_injection;
5908 }
5909
5910 preempt_disable();
5911
5912 kvm_x86_ops->prepare_guest_switch(vcpu);
5913 if (vcpu->fpu_active)
5914 kvm_load_guest_fpu(vcpu);
5915 kvm_load_guest_xcr0(vcpu);
5916
5917 vcpu->mode = IN_GUEST_MODE;
5918
5919 /* We should set ->mode before check ->requests,
5920 * see the comment in make_all_cpus_request.
5921 */
5922 smp_mb();
5923
5924 local_irq_disable();
5925
5926 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5927 || need_resched() || signal_pending(current)) {
5928 vcpu->mode = OUTSIDE_GUEST_MODE;
5929 smp_wmb();
5930 local_irq_enable();
5931 preempt_enable();
5932 r = 1;
5933 goto cancel_injection;
5934 }
5935
5936 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5937
5938 if (req_immediate_exit)
5939 smp_send_reschedule(vcpu->cpu);
5940
5941 kvm_guest_enter();
5942
5943 if (unlikely(vcpu->arch.switch_db_regs)) {
5944 set_debugreg(0, 7);
5945 set_debugreg(vcpu->arch.eff_db[0], 0);
5946 set_debugreg(vcpu->arch.eff_db[1], 1);
5947 set_debugreg(vcpu->arch.eff_db[2], 2);
5948 set_debugreg(vcpu->arch.eff_db[3], 3);
5949 }
5950
5951 trace_kvm_entry(vcpu->vcpu_id);
5952 kvm_x86_ops->run(vcpu);
5953
5954 /*
5955 * If the guest has used debug registers, at least dr7
5956 * will be disabled while returning to the host.
5957 * If we don't have active breakpoints in the host, we don't
5958 * care about the messed up debug address registers. But if
5959 * we have some of them active, restore the old state.
5960 */
5961 if (hw_breakpoint_active())
5962 hw_breakpoint_restore();
5963
5964 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5965 native_read_tsc());
5966
5967 vcpu->mode = OUTSIDE_GUEST_MODE;
5968 smp_wmb();
5969
5970 /* Interrupt is enabled by handle_external_intr() */
5971 kvm_x86_ops->handle_external_intr(vcpu);
5972
5973 ++vcpu->stat.exits;
5974
5975 /*
5976 * We must have an instruction between local_irq_enable() and
5977 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5978 * the interrupt shadow. The stat.exits increment will do nicely.
5979 * But we need to prevent reordering, hence this barrier():
5980 */
5981 barrier();
5982
5983 kvm_guest_exit();
5984
5985 preempt_enable();
5986
5987 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5988
5989 /*
5990 * Profile KVM exit RIPs:
5991 */
5992 if (unlikely(prof_on == KVM_PROFILING)) {
5993 unsigned long rip = kvm_rip_read(vcpu);
5994 profile_hit(KVM_PROFILING, (void *)rip);
5995 }
5996
5997 if (unlikely(vcpu->arch.tsc_always_catchup))
5998 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5999
6000 if (vcpu->arch.apic_attention)
6001 kvm_lapic_sync_from_vapic(vcpu);
6002
6003 r = kvm_x86_ops->handle_exit(vcpu);
6004 return r;
6005
6006 cancel_injection:
6007 kvm_x86_ops->cancel_injection(vcpu);
6008 if (unlikely(vcpu->arch.apic_attention))
6009 kvm_lapic_sync_from_vapic(vcpu);
6010 out:
6011 return r;
6012 }
6013
6014
6015 static int __vcpu_run(struct kvm_vcpu *vcpu)
6016 {
6017 int r;
6018 struct kvm *kvm = vcpu->kvm;
6019
6020 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6021
6022 r = 1;
6023 while (r > 0) {
6024 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6025 !vcpu->arch.apf.halted)
6026 r = vcpu_enter_guest(vcpu);
6027 else {
6028 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6029 kvm_vcpu_block(vcpu);
6030 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6031 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6032 kvm_apic_accept_events(vcpu);
6033 switch(vcpu->arch.mp_state) {
6034 case KVM_MP_STATE_HALTED:
6035 vcpu->arch.pv.pv_unhalted = false;
6036 vcpu->arch.mp_state =
6037 KVM_MP_STATE_RUNNABLE;
6038 case KVM_MP_STATE_RUNNABLE:
6039 vcpu->arch.apf.halted = false;
6040 break;
6041 case KVM_MP_STATE_INIT_RECEIVED:
6042 break;
6043 default:
6044 r = -EINTR;
6045 break;
6046 }
6047 }
6048 }
6049
6050 if (r <= 0)
6051 break;
6052
6053 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6054 if (kvm_cpu_has_pending_timer(vcpu))
6055 kvm_inject_pending_timer_irqs(vcpu);
6056
6057 if (dm_request_for_irq_injection(vcpu)) {
6058 r = -EINTR;
6059 vcpu->run->exit_reason = KVM_EXIT_INTR;
6060 ++vcpu->stat.request_irq_exits;
6061 }
6062
6063 kvm_check_async_pf_completion(vcpu);
6064
6065 if (signal_pending(current)) {
6066 r = -EINTR;
6067 vcpu->run->exit_reason = KVM_EXIT_INTR;
6068 ++vcpu->stat.signal_exits;
6069 }
6070 if (need_resched()) {
6071 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6072 kvm_resched(vcpu);
6073 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6074 }
6075 }
6076
6077 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6078
6079 return r;
6080 }
6081
6082 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6083 {
6084 int r;
6085 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6086 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6087 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6088 if (r != EMULATE_DONE)
6089 return 0;
6090 return 1;
6091 }
6092
6093 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6094 {
6095 BUG_ON(!vcpu->arch.pio.count);
6096
6097 return complete_emulated_io(vcpu);
6098 }
6099
6100 /*
6101 * Implements the following, as a state machine:
6102 *
6103 * read:
6104 * for each fragment
6105 * for each mmio piece in the fragment
6106 * write gpa, len
6107 * exit
6108 * copy data
6109 * execute insn
6110 *
6111 * write:
6112 * for each fragment
6113 * for each mmio piece in the fragment
6114 * write gpa, len
6115 * copy data
6116 * exit
6117 */
6118 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6119 {
6120 struct kvm_run *run = vcpu->run;
6121 struct kvm_mmio_fragment *frag;
6122 unsigned len;
6123
6124 BUG_ON(!vcpu->mmio_needed);
6125
6126 /* Complete previous fragment */
6127 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6128 len = min(8u, frag->len);
6129 if (!vcpu->mmio_is_write)
6130 memcpy(frag->data, run->mmio.data, len);
6131
6132 if (frag->len <= 8) {
6133 /* Switch to the next fragment. */
6134 frag++;
6135 vcpu->mmio_cur_fragment++;
6136 } else {
6137 /* Go forward to the next mmio piece. */
6138 frag->data += len;
6139 frag->gpa += len;
6140 frag->len -= len;
6141 }
6142
6143 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6144 vcpu->mmio_needed = 0;
6145
6146 /* FIXME: return into emulator if single-stepping. */
6147 if (vcpu->mmio_is_write)
6148 return 1;
6149 vcpu->mmio_read_completed = 1;
6150 return complete_emulated_io(vcpu);
6151 }
6152
6153 run->exit_reason = KVM_EXIT_MMIO;
6154 run->mmio.phys_addr = frag->gpa;
6155 if (vcpu->mmio_is_write)
6156 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6157 run->mmio.len = min(8u, frag->len);
6158 run->mmio.is_write = vcpu->mmio_is_write;
6159 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6160 return 0;
6161 }
6162
6163
6164 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6165 {
6166 int r;
6167 sigset_t sigsaved;
6168
6169 if (!tsk_used_math(current) && init_fpu(current))
6170 return -ENOMEM;
6171
6172 if (vcpu->sigset_active)
6173 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6174
6175 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6176 kvm_vcpu_block(vcpu);
6177 kvm_apic_accept_events(vcpu);
6178 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6179 r = -EAGAIN;
6180 goto out;
6181 }
6182
6183 /* re-sync apic's tpr */
6184 if (!irqchip_in_kernel(vcpu->kvm)) {
6185 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6186 r = -EINVAL;
6187 goto out;
6188 }
6189 }
6190
6191 if (unlikely(vcpu->arch.complete_userspace_io)) {
6192 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6193 vcpu->arch.complete_userspace_io = NULL;
6194 r = cui(vcpu);
6195 if (r <= 0)
6196 goto out;
6197 } else
6198 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6199
6200 r = __vcpu_run(vcpu);
6201
6202 out:
6203 post_kvm_run_save(vcpu);
6204 if (vcpu->sigset_active)
6205 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6206
6207 return r;
6208 }
6209
6210 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6211 {
6212 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6213 /*
6214 * We are here if userspace calls get_regs() in the middle of
6215 * instruction emulation. Registers state needs to be copied
6216 * back from emulation context to vcpu. Userspace shouldn't do
6217 * that usually, but some bad designed PV devices (vmware
6218 * backdoor interface) need this to work
6219 */
6220 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6221 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6222 }
6223 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6224 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6225 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6226 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6227 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6228 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6229 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6230 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6231 #ifdef CONFIG_X86_64
6232 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6233 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6234 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6235 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6236 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6237 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6238 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6239 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6240 #endif
6241
6242 regs->rip = kvm_rip_read(vcpu);
6243 regs->rflags = kvm_get_rflags(vcpu);
6244
6245 return 0;
6246 }
6247
6248 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6249 {
6250 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6251 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6252
6253 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6254 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6255 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6256 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6257 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6258 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6259 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6260 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6261 #ifdef CONFIG_X86_64
6262 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6263 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6264 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6265 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6266 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6267 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6268 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6269 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6270 #endif
6271
6272 kvm_rip_write(vcpu, regs->rip);
6273 kvm_set_rflags(vcpu, regs->rflags);
6274
6275 vcpu->arch.exception.pending = false;
6276
6277 kvm_make_request(KVM_REQ_EVENT, vcpu);
6278
6279 return 0;
6280 }
6281
6282 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6283 {
6284 struct kvm_segment cs;
6285
6286 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6287 *db = cs.db;
6288 *l = cs.l;
6289 }
6290 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6291
6292 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6293 struct kvm_sregs *sregs)
6294 {
6295 struct desc_ptr dt;
6296
6297 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6298 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6299 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6300 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6301 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6302 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6303
6304 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6305 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6306
6307 kvm_x86_ops->get_idt(vcpu, &dt);
6308 sregs->idt.limit = dt.size;
6309 sregs->idt.base = dt.address;
6310 kvm_x86_ops->get_gdt(vcpu, &dt);
6311 sregs->gdt.limit = dt.size;
6312 sregs->gdt.base = dt.address;
6313
6314 sregs->cr0 = kvm_read_cr0(vcpu);
6315 sregs->cr2 = vcpu->arch.cr2;
6316 sregs->cr3 = kvm_read_cr3(vcpu);
6317 sregs->cr4 = kvm_read_cr4(vcpu);
6318 sregs->cr8 = kvm_get_cr8(vcpu);
6319 sregs->efer = vcpu->arch.efer;
6320 sregs->apic_base = kvm_get_apic_base(vcpu);
6321
6322 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6323
6324 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6325 set_bit(vcpu->arch.interrupt.nr,
6326 (unsigned long *)sregs->interrupt_bitmap);
6327
6328 return 0;
6329 }
6330
6331 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6332 struct kvm_mp_state *mp_state)
6333 {
6334 kvm_apic_accept_events(vcpu);
6335 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6336 vcpu->arch.pv.pv_unhalted)
6337 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6338 else
6339 mp_state->mp_state = vcpu->arch.mp_state;
6340
6341 return 0;
6342 }
6343
6344 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6345 struct kvm_mp_state *mp_state)
6346 {
6347 if (!kvm_vcpu_has_lapic(vcpu) &&
6348 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6349 return -EINVAL;
6350
6351 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6352 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6353 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6354 } else
6355 vcpu->arch.mp_state = mp_state->mp_state;
6356 kvm_make_request(KVM_REQ_EVENT, vcpu);
6357 return 0;
6358 }
6359
6360 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6361 int reason, bool has_error_code, u32 error_code)
6362 {
6363 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6364 int ret;
6365
6366 init_emulate_ctxt(vcpu);
6367
6368 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6369 has_error_code, error_code);
6370
6371 if (ret)
6372 return EMULATE_FAIL;
6373
6374 kvm_rip_write(vcpu, ctxt->eip);
6375 kvm_set_rflags(vcpu, ctxt->eflags);
6376 kvm_make_request(KVM_REQ_EVENT, vcpu);
6377 return EMULATE_DONE;
6378 }
6379 EXPORT_SYMBOL_GPL(kvm_task_switch);
6380
6381 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6382 struct kvm_sregs *sregs)
6383 {
6384 int mmu_reset_needed = 0;
6385 int pending_vec, max_bits, idx;
6386 struct desc_ptr dt;
6387
6388 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6389 return -EINVAL;
6390
6391 dt.size = sregs->idt.limit;
6392 dt.address = sregs->idt.base;
6393 kvm_x86_ops->set_idt(vcpu, &dt);
6394 dt.size = sregs->gdt.limit;
6395 dt.address = sregs->gdt.base;
6396 kvm_x86_ops->set_gdt(vcpu, &dt);
6397
6398 vcpu->arch.cr2 = sregs->cr2;
6399 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6400 vcpu->arch.cr3 = sregs->cr3;
6401 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6402
6403 kvm_set_cr8(vcpu, sregs->cr8);
6404
6405 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6406 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6407 kvm_set_apic_base(vcpu, sregs->apic_base);
6408
6409 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6410 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6411 vcpu->arch.cr0 = sregs->cr0;
6412
6413 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6414 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6415 if (sregs->cr4 & X86_CR4_OSXSAVE)
6416 kvm_update_cpuid(vcpu);
6417
6418 idx = srcu_read_lock(&vcpu->kvm->srcu);
6419 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6420 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6421 mmu_reset_needed = 1;
6422 }
6423 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6424
6425 if (mmu_reset_needed)
6426 kvm_mmu_reset_context(vcpu);
6427
6428 max_bits = KVM_NR_INTERRUPTS;
6429 pending_vec = find_first_bit(
6430 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6431 if (pending_vec < max_bits) {
6432 kvm_queue_interrupt(vcpu, pending_vec, false);
6433 pr_debug("Set back pending irq %d\n", pending_vec);
6434 }
6435
6436 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6437 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6438 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6439 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6440 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6441 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6442
6443 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6444 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6445
6446 update_cr8_intercept(vcpu);
6447
6448 /* Older userspace won't unhalt the vcpu on reset. */
6449 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6450 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6451 !is_protmode(vcpu))
6452 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6453
6454 kvm_make_request(KVM_REQ_EVENT, vcpu);
6455
6456 return 0;
6457 }
6458
6459 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6460 struct kvm_guest_debug *dbg)
6461 {
6462 unsigned long rflags;
6463 int i, r;
6464
6465 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6466 r = -EBUSY;
6467 if (vcpu->arch.exception.pending)
6468 goto out;
6469 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6470 kvm_queue_exception(vcpu, DB_VECTOR);
6471 else
6472 kvm_queue_exception(vcpu, BP_VECTOR);
6473 }
6474
6475 /*
6476 * Read rflags as long as potentially injected trace flags are still
6477 * filtered out.
6478 */
6479 rflags = kvm_get_rflags(vcpu);
6480
6481 vcpu->guest_debug = dbg->control;
6482 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6483 vcpu->guest_debug = 0;
6484
6485 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6486 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6487 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6488 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6489 } else {
6490 for (i = 0; i < KVM_NR_DB_REGS; i++)
6491 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6492 }
6493 kvm_update_dr7(vcpu);
6494
6495 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6496 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6497 get_segment_base(vcpu, VCPU_SREG_CS);
6498
6499 /*
6500 * Trigger an rflags update that will inject or remove the trace
6501 * flags.
6502 */
6503 kvm_set_rflags(vcpu, rflags);
6504
6505 kvm_x86_ops->update_db_bp_intercept(vcpu);
6506
6507 r = 0;
6508
6509 out:
6510
6511 return r;
6512 }
6513
6514 /*
6515 * Translate a guest virtual address to a guest physical address.
6516 */
6517 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6518 struct kvm_translation *tr)
6519 {
6520 unsigned long vaddr = tr->linear_address;
6521 gpa_t gpa;
6522 int idx;
6523
6524 idx = srcu_read_lock(&vcpu->kvm->srcu);
6525 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6526 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6527 tr->physical_address = gpa;
6528 tr->valid = gpa != UNMAPPED_GVA;
6529 tr->writeable = 1;
6530 tr->usermode = 0;
6531
6532 return 0;
6533 }
6534
6535 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6536 {
6537 struct i387_fxsave_struct *fxsave =
6538 &vcpu->arch.guest_fpu.state->fxsave;
6539
6540 memcpy(fpu->fpr, fxsave->st_space, 128);
6541 fpu->fcw = fxsave->cwd;
6542 fpu->fsw = fxsave->swd;
6543 fpu->ftwx = fxsave->twd;
6544 fpu->last_opcode = fxsave->fop;
6545 fpu->last_ip = fxsave->rip;
6546 fpu->last_dp = fxsave->rdp;
6547 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6548
6549 return 0;
6550 }
6551
6552 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6553 {
6554 struct i387_fxsave_struct *fxsave =
6555 &vcpu->arch.guest_fpu.state->fxsave;
6556
6557 memcpy(fxsave->st_space, fpu->fpr, 128);
6558 fxsave->cwd = fpu->fcw;
6559 fxsave->swd = fpu->fsw;
6560 fxsave->twd = fpu->ftwx;
6561 fxsave->fop = fpu->last_opcode;
6562 fxsave->rip = fpu->last_ip;
6563 fxsave->rdp = fpu->last_dp;
6564 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6565
6566 return 0;
6567 }
6568
6569 int fx_init(struct kvm_vcpu *vcpu)
6570 {
6571 int err;
6572
6573 err = fpu_alloc(&vcpu->arch.guest_fpu);
6574 if (err)
6575 return err;
6576
6577 fpu_finit(&vcpu->arch.guest_fpu);
6578
6579 /*
6580 * Ensure guest xcr0 is valid for loading
6581 */
6582 vcpu->arch.xcr0 = XSTATE_FP;
6583
6584 vcpu->arch.cr0 |= X86_CR0_ET;
6585
6586 return 0;
6587 }
6588 EXPORT_SYMBOL_GPL(fx_init);
6589
6590 static void fx_free(struct kvm_vcpu *vcpu)
6591 {
6592 fpu_free(&vcpu->arch.guest_fpu);
6593 }
6594
6595 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6596 {
6597 if (vcpu->guest_fpu_loaded)
6598 return;
6599
6600 /*
6601 * Restore all possible states in the guest,
6602 * and assume host would use all available bits.
6603 * Guest xcr0 would be loaded later.
6604 */
6605 kvm_put_guest_xcr0(vcpu);
6606 vcpu->guest_fpu_loaded = 1;
6607 __kernel_fpu_begin();
6608 fpu_restore_checking(&vcpu->arch.guest_fpu);
6609 trace_kvm_fpu(1);
6610 }
6611
6612 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6613 {
6614 kvm_put_guest_xcr0(vcpu);
6615
6616 if (!vcpu->guest_fpu_loaded)
6617 return;
6618
6619 vcpu->guest_fpu_loaded = 0;
6620 fpu_save_init(&vcpu->arch.guest_fpu);
6621 __kernel_fpu_end();
6622 ++vcpu->stat.fpu_reload;
6623 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6624 trace_kvm_fpu(0);
6625 }
6626
6627 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6628 {
6629 kvmclock_reset(vcpu);
6630
6631 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6632 fx_free(vcpu);
6633 kvm_x86_ops->vcpu_free(vcpu);
6634 }
6635
6636 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6637 unsigned int id)
6638 {
6639 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6640 printk_once(KERN_WARNING
6641 "kvm: SMP vm created on host with unstable TSC; "
6642 "guest TSC will not be reliable\n");
6643 return kvm_x86_ops->vcpu_create(kvm, id);
6644 }
6645
6646 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6647 {
6648 int r;
6649
6650 vcpu->arch.mtrr_state.have_fixed = 1;
6651 r = vcpu_load(vcpu);
6652 if (r)
6653 return r;
6654 kvm_vcpu_reset(vcpu);
6655 r = kvm_mmu_setup(vcpu);
6656 vcpu_put(vcpu);
6657
6658 return r;
6659 }
6660
6661 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6662 {
6663 int r;
6664 struct msr_data msr;
6665
6666 r = vcpu_load(vcpu);
6667 if (r)
6668 return r;
6669 msr.data = 0x0;
6670 msr.index = MSR_IA32_TSC;
6671 msr.host_initiated = true;
6672 kvm_write_tsc(vcpu, &msr);
6673 vcpu_put(vcpu);
6674
6675 return r;
6676 }
6677
6678 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6679 {
6680 int r;
6681 vcpu->arch.apf.msr_val = 0;
6682
6683 r = vcpu_load(vcpu);
6684 BUG_ON(r);
6685 kvm_mmu_unload(vcpu);
6686 vcpu_put(vcpu);
6687
6688 fx_free(vcpu);
6689 kvm_x86_ops->vcpu_free(vcpu);
6690 }
6691
6692 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6693 {
6694 atomic_set(&vcpu->arch.nmi_queued, 0);
6695 vcpu->arch.nmi_pending = 0;
6696 vcpu->arch.nmi_injected = false;
6697
6698 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6699 vcpu->arch.dr6 = DR6_FIXED_1;
6700 vcpu->arch.dr7 = DR7_FIXED_1;
6701 kvm_update_dr7(vcpu);
6702
6703 kvm_make_request(KVM_REQ_EVENT, vcpu);
6704 vcpu->arch.apf.msr_val = 0;
6705 vcpu->arch.st.msr_val = 0;
6706
6707 kvmclock_reset(vcpu);
6708
6709 kvm_clear_async_pf_completion_queue(vcpu);
6710 kvm_async_pf_hash_reset(vcpu);
6711 vcpu->arch.apf.halted = false;
6712
6713 kvm_pmu_reset(vcpu);
6714
6715 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6716 vcpu->arch.regs_avail = ~0;
6717 vcpu->arch.regs_dirty = ~0;
6718
6719 kvm_x86_ops->vcpu_reset(vcpu);
6720 }
6721
6722 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6723 {
6724 struct kvm_segment cs;
6725
6726 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6727 cs.selector = vector << 8;
6728 cs.base = vector << 12;
6729 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6730 kvm_rip_write(vcpu, 0);
6731 }
6732
6733 int kvm_arch_hardware_enable(void *garbage)
6734 {
6735 struct kvm *kvm;
6736 struct kvm_vcpu *vcpu;
6737 int i;
6738 int ret;
6739 u64 local_tsc;
6740 u64 max_tsc = 0;
6741 bool stable, backwards_tsc = false;
6742
6743 kvm_shared_msr_cpu_online();
6744 ret = kvm_x86_ops->hardware_enable(garbage);
6745 if (ret != 0)
6746 return ret;
6747
6748 local_tsc = native_read_tsc();
6749 stable = !check_tsc_unstable();
6750 list_for_each_entry(kvm, &vm_list, vm_list) {
6751 kvm_for_each_vcpu(i, vcpu, kvm) {
6752 if (!stable && vcpu->cpu == smp_processor_id())
6753 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6754 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6755 backwards_tsc = true;
6756 if (vcpu->arch.last_host_tsc > max_tsc)
6757 max_tsc = vcpu->arch.last_host_tsc;
6758 }
6759 }
6760 }
6761
6762 /*
6763 * Sometimes, even reliable TSCs go backwards. This happens on
6764 * platforms that reset TSC during suspend or hibernate actions, but
6765 * maintain synchronization. We must compensate. Fortunately, we can
6766 * detect that condition here, which happens early in CPU bringup,
6767 * before any KVM threads can be running. Unfortunately, we can't
6768 * bring the TSCs fully up to date with real time, as we aren't yet far
6769 * enough into CPU bringup that we know how much real time has actually
6770 * elapsed; our helper function, get_kernel_ns() will be using boot
6771 * variables that haven't been updated yet.
6772 *
6773 * So we simply find the maximum observed TSC above, then record the
6774 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6775 * the adjustment will be applied. Note that we accumulate
6776 * adjustments, in case multiple suspend cycles happen before some VCPU
6777 * gets a chance to run again. In the event that no KVM threads get a
6778 * chance to run, we will miss the entire elapsed period, as we'll have
6779 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6780 * loose cycle time. This isn't too big a deal, since the loss will be
6781 * uniform across all VCPUs (not to mention the scenario is extremely
6782 * unlikely). It is possible that a second hibernate recovery happens
6783 * much faster than a first, causing the observed TSC here to be
6784 * smaller; this would require additional padding adjustment, which is
6785 * why we set last_host_tsc to the local tsc observed here.
6786 *
6787 * N.B. - this code below runs only on platforms with reliable TSC,
6788 * as that is the only way backwards_tsc is set above. Also note
6789 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6790 * have the same delta_cyc adjustment applied if backwards_tsc
6791 * is detected. Note further, this adjustment is only done once,
6792 * as we reset last_host_tsc on all VCPUs to stop this from being
6793 * called multiple times (one for each physical CPU bringup).
6794 *
6795 * Platforms with unreliable TSCs don't have to deal with this, they
6796 * will be compensated by the logic in vcpu_load, which sets the TSC to
6797 * catchup mode. This will catchup all VCPUs to real time, but cannot
6798 * guarantee that they stay in perfect synchronization.
6799 */
6800 if (backwards_tsc) {
6801 u64 delta_cyc = max_tsc - local_tsc;
6802 list_for_each_entry(kvm, &vm_list, vm_list) {
6803 kvm_for_each_vcpu(i, vcpu, kvm) {
6804 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6805 vcpu->arch.last_host_tsc = local_tsc;
6806 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6807 &vcpu->requests);
6808 }
6809
6810 /*
6811 * We have to disable TSC offset matching.. if you were
6812 * booting a VM while issuing an S4 host suspend....
6813 * you may have some problem. Solving this issue is
6814 * left as an exercise to the reader.
6815 */
6816 kvm->arch.last_tsc_nsec = 0;
6817 kvm->arch.last_tsc_write = 0;
6818 }
6819
6820 }
6821 return 0;
6822 }
6823
6824 void kvm_arch_hardware_disable(void *garbage)
6825 {
6826 kvm_x86_ops->hardware_disable(garbage);
6827 drop_user_return_notifiers(garbage);
6828 }
6829
6830 int kvm_arch_hardware_setup(void)
6831 {
6832 return kvm_x86_ops->hardware_setup();
6833 }
6834
6835 void kvm_arch_hardware_unsetup(void)
6836 {
6837 kvm_x86_ops->hardware_unsetup();
6838 }
6839
6840 void kvm_arch_check_processor_compat(void *rtn)
6841 {
6842 kvm_x86_ops->check_processor_compatibility(rtn);
6843 }
6844
6845 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6846 {
6847 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6848 }
6849
6850 struct static_key kvm_no_apic_vcpu __read_mostly;
6851
6852 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6853 {
6854 struct page *page;
6855 struct kvm *kvm;
6856 int r;
6857
6858 BUG_ON(vcpu->kvm == NULL);
6859 kvm = vcpu->kvm;
6860
6861 vcpu->arch.pv.pv_unhalted = false;
6862 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6863 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6864 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6865 else
6866 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6867
6868 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6869 if (!page) {
6870 r = -ENOMEM;
6871 goto fail;
6872 }
6873 vcpu->arch.pio_data = page_address(page);
6874
6875 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6876
6877 r = kvm_mmu_create(vcpu);
6878 if (r < 0)
6879 goto fail_free_pio_data;
6880
6881 if (irqchip_in_kernel(kvm)) {
6882 r = kvm_create_lapic(vcpu);
6883 if (r < 0)
6884 goto fail_mmu_destroy;
6885 } else
6886 static_key_slow_inc(&kvm_no_apic_vcpu);
6887
6888 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6889 GFP_KERNEL);
6890 if (!vcpu->arch.mce_banks) {
6891 r = -ENOMEM;
6892 goto fail_free_lapic;
6893 }
6894 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6895
6896 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6897 r = -ENOMEM;
6898 goto fail_free_mce_banks;
6899 }
6900
6901 r = fx_init(vcpu);
6902 if (r)
6903 goto fail_free_wbinvd_dirty_mask;
6904
6905 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6906 vcpu->arch.pv_time_enabled = false;
6907 kvm_async_pf_hash_reset(vcpu);
6908 kvm_pmu_init(vcpu);
6909
6910 return 0;
6911 fail_free_wbinvd_dirty_mask:
6912 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6913 fail_free_mce_banks:
6914 kfree(vcpu->arch.mce_banks);
6915 fail_free_lapic:
6916 kvm_free_lapic(vcpu);
6917 fail_mmu_destroy:
6918 kvm_mmu_destroy(vcpu);
6919 fail_free_pio_data:
6920 free_page((unsigned long)vcpu->arch.pio_data);
6921 fail:
6922 return r;
6923 }
6924
6925 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6926 {
6927 int idx;
6928
6929 kvm_pmu_destroy(vcpu);
6930 kfree(vcpu->arch.mce_banks);
6931 kvm_free_lapic(vcpu);
6932 idx = srcu_read_lock(&vcpu->kvm->srcu);
6933 kvm_mmu_destroy(vcpu);
6934 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6935 free_page((unsigned long)vcpu->arch.pio_data);
6936 if (!irqchip_in_kernel(vcpu->kvm))
6937 static_key_slow_dec(&kvm_no_apic_vcpu);
6938 }
6939
6940 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6941 {
6942 if (type)
6943 return -EINVAL;
6944
6945 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6946 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
6947 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6948
6949 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6950 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6951 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6952 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6953 &kvm->arch.irq_sources_bitmap);
6954
6955 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6956 mutex_init(&kvm->arch.apic_map_lock);
6957 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6958
6959 pvclock_update_vm_gtod_copy(kvm);
6960
6961 return 0;
6962 }
6963
6964 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6965 {
6966 int r;
6967 r = vcpu_load(vcpu);
6968 BUG_ON(r);
6969 kvm_mmu_unload(vcpu);
6970 vcpu_put(vcpu);
6971 }
6972
6973 static void kvm_free_vcpus(struct kvm *kvm)
6974 {
6975 unsigned int i;
6976 struct kvm_vcpu *vcpu;
6977
6978 /*
6979 * Unpin any mmu pages first.
6980 */
6981 kvm_for_each_vcpu(i, vcpu, kvm) {
6982 kvm_clear_async_pf_completion_queue(vcpu);
6983 kvm_unload_vcpu_mmu(vcpu);
6984 }
6985 kvm_for_each_vcpu(i, vcpu, kvm)
6986 kvm_arch_vcpu_free(vcpu);
6987
6988 mutex_lock(&kvm->lock);
6989 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6990 kvm->vcpus[i] = NULL;
6991
6992 atomic_set(&kvm->online_vcpus, 0);
6993 mutex_unlock(&kvm->lock);
6994 }
6995
6996 void kvm_arch_sync_events(struct kvm *kvm)
6997 {
6998 kvm_free_all_assigned_devices(kvm);
6999 kvm_free_pit(kvm);
7000 }
7001
7002 void kvm_arch_destroy_vm(struct kvm *kvm)
7003 {
7004 if (current->mm == kvm->mm) {
7005 /*
7006 * Free memory regions allocated on behalf of userspace,
7007 * unless the the memory map has changed due to process exit
7008 * or fd copying.
7009 */
7010 struct kvm_userspace_memory_region mem;
7011 memset(&mem, 0, sizeof(mem));
7012 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7013 kvm_set_memory_region(kvm, &mem);
7014
7015 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7016 kvm_set_memory_region(kvm, &mem);
7017
7018 mem.slot = TSS_PRIVATE_MEMSLOT;
7019 kvm_set_memory_region(kvm, &mem);
7020 }
7021 kvm_iommu_unmap_guest(kvm);
7022 kfree(kvm->arch.vpic);
7023 kfree(kvm->arch.vioapic);
7024 kvm_free_vcpus(kvm);
7025 if (kvm->arch.apic_access_page)
7026 put_page(kvm->arch.apic_access_page);
7027 if (kvm->arch.ept_identity_pagetable)
7028 put_page(kvm->arch.ept_identity_pagetable);
7029 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7030 }
7031
7032 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
7033 struct kvm_memory_slot *dont)
7034 {
7035 int i;
7036
7037 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7038 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7039 kvm_kvfree(free->arch.rmap[i]);
7040 free->arch.rmap[i] = NULL;
7041 }
7042 if (i == 0)
7043 continue;
7044
7045 if (!dont || free->arch.lpage_info[i - 1] !=
7046 dont->arch.lpage_info[i - 1]) {
7047 kvm_kvfree(free->arch.lpage_info[i - 1]);
7048 free->arch.lpage_info[i - 1] = NULL;
7049 }
7050 }
7051 }
7052
7053 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
7054 {
7055 int i;
7056
7057 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7058 unsigned long ugfn;
7059 int lpages;
7060 int level = i + 1;
7061
7062 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7063 slot->base_gfn, level) + 1;
7064
7065 slot->arch.rmap[i] =
7066 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7067 if (!slot->arch.rmap[i])
7068 goto out_free;
7069 if (i == 0)
7070 continue;
7071
7072 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7073 sizeof(*slot->arch.lpage_info[i - 1]));
7074 if (!slot->arch.lpage_info[i - 1])
7075 goto out_free;
7076
7077 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7078 slot->arch.lpage_info[i - 1][0].write_count = 1;
7079 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7080 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7081 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7082 /*
7083 * If the gfn and userspace address are not aligned wrt each
7084 * other, or if explicitly asked to, disable large page
7085 * support for this slot
7086 */
7087 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7088 !kvm_largepages_enabled()) {
7089 unsigned long j;
7090
7091 for (j = 0; j < lpages; ++j)
7092 slot->arch.lpage_info[i - 1][j].write_count = 1;
7093 }
7094 }
7095
7096 return 0;
7097
7098 out_free:
7099 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7100 kvm_kvfree(slot->arch.rmap[i]);
7101 slot->arch.rmap[i] = NULL;
7102 if (i == 0)
7103 continue;
7104
7105 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7106 slot->arch.lpage_info[i - 1] = NULL;
7107 }
7108 return -ENOMEM;
7109 }
7110
7111 void kvm_arch_memslots_updated(struct kvm *kvm)
7112 {
7113 /*
7114 * memslots->generation has been incremented.
7115 * mmio generation may have reached its maximum value.
7116 */
7117 kvm_mmu_invalidate_mmio_sptes(kvm);
7118 }
7119
7120 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7121 struct kvm_memory_slot *memslot,
7122 struct kvm_userspace_memory_region *mem,
7123 enum kvm_mr_change change)
7124 {
7125 /*
7126 * Only private memory slots need to be mapped here since
7127 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7128 */
7129 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7130 unsigned long userspace_addr;
7131
7132 /*
7133 * MAP_SHARED to prevent internal slot pages from being moved
7134 * by fork()/COW.
7135 */
7136 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7137 PROT_READ | PROT_WRITE,
7138 MAP_SHARED | MAP_ANONYMOUS, 0);
7139
7140 if (IS_ERR((void *)userspace_addr))
7141 return PTR_ERR((void *)userspace_addr);
7142
7143 memslot->userspace_addr = userspace_addr;
7144 }
7145
7146 return 0;
7147 }
7148
7149 void kvm_arch_commit_memory_region(struct kvm *kvm,
7150 struct kvm_userspace_memory_region *mem,
7151 const struct kvm_memory_slot *old,
7152 enum kvm_mr_change change)
7153 {
7154
7155 int nr_mmu_pages = 0;
7156
7157 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7158 int ret;
7159
7160 ret = vm_munmap(old->userspace_addr,
7161 old->npages * PAGE_SIZE);
7162 if (ret < 0)
7163 printk(KERN_WARNING
7164 "kvm_vm_ioctl_set_memory_region: "
7165 "failed to munmap memory\n");
7166 }
7167
7168 if (!kvm->arch.n_requested_mmu_pages)
7169 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7170
7171 if (nr_mmu_pages)
7172 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7173 /*
7174 * Write protect all pages for dirty logging.
7175 * Existing largepage mappings are destroyed here and new ones will
7176 * not be created until the end of the logging.
7177 */
7178 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7179 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7180 }
7181
7182 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7183 {
7184 kvm_mmu_invalidate_zap_all_pages(kvm);
7185 }
7186
7187 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7188 struct kvm_memory_slot *slot)
7189 {
7190 kvm_mmu_invalidate_zap_all_pages(kvm);
7191 }
7192
7193 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7194 {
7195 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7196 !vcpu->arch.apf.halted)
7197 || !list_empty_careful(&vcpu->async_pf.done)
7198 || kvm_apic_has_events(vcpu)
7199 || vcpu->arch.pv.pv_unhalted
7200 || atomic_read(&vcpu->arch.nmi_queued) ||
7201 (kvm_arch_interrupt_allowed(vcpu) &&
7202 kvm_cpu_has_interrupt(vcpu));
7203 }
7204
7205 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7206 {
7207 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7208 }
7209
7210 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7211 {
7212 return kvm_x86_ops->interrupt_allowed(vcpu);
7213 }
7214
7215 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7216 {
7217 unsigned long current_rip = kvm_rip_read(vcpu) +
7218 get_segment_base(vcpu, VCPU_SREG_CS);
7219
7220 return current_rip == linear_rip;
7221 }
7222 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7223
7224 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7225 {
7226 unsigned long rflags;
7227
7228 rflags = kvm_x86_ops->get_rflags(vcpu);
7229 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7230 rflags &= ~X86_EFLAGS_TF;
7231 return rflags;
7232 }
7233 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7234
7235 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7236 {
7237 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7238 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7239 rflags |= X86_EFLAGS_TF;
7240 kvm_x86_ops->set_rflags(vcpu, rflags);
7241 kvm_make_request(KVM_REQ_EVENT, vcpu);
7242 }
7243 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7244
7245 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7246 {
7247 int r;
7248
7249 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7250 is_error_page(work->page))
7251 return;
7252
7253 r = kvm_mmu_reload(vcpu);
7254 if (unlikely(r))
7255 return;
7256
7257 if (!vcpu->arch.mmu.direct_map &&
7258 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7259 return;
7260
7261 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7262 }
7263
7264 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7265 {
7266 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7267 }
7268
7269 static inline u32 kvm_async_pf_next_probe(u32 key)
7270 {
7271 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7272 }
7273
7274 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7275 {
7276 u32 key = kvm_async_pf_hash_fn(gfn);
7277
7278 while (vcpu->arch.apf.gfns[key] != ~0)
7279 key = kvm_async_pf_next_probe(key);
7280
7281 vcpu->arch.apf.gfns[key] = gfn;
7282 }
7283
7284 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7285 {
7286 int i;
7287 u32 key = kvm_async_pf_hash_fn(gfn);
7288
7289 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7290 (vcpu->arch.apf.gfns[key] != gfn &&
7291 vcpu->arch.apf.gfns[key] != ~0); i++)
7292 key = kvm_async_pf_next_probe(key);
7293
7294 return key;
7295 }
7296
7297 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7298 {
7299 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7300 }
7301
7302 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7303 {
7304 u32 i, j, k;
7305
7306 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7307 while (true) {
7308 vcpu->arch.apf.gfns[i] = ~0;
7309 do {
7310 j = kvm_async_pf_next_probe(j);
7311 if (vcpu->arch.apf.gfns[j] == ~0)
7312 return;
7313 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7314 /*
7315 * k lies cyclically in ]i,j]
7316 * | i.k.j |
7317 * |....j i.k.| or |.k..j i...|
7318 */
7319 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7320 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7321 i = j;
7322 }
7323 }
7324
7325 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7326 {
7327
7328 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7329 sizeof(val));
7330 }
7331
7332 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7333 struct kvm_async_pf *work)
7334 {
7335 struct x86_exception fault;
7336
7337 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7338 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7339
7340 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7341 (vcpu->arch.apf.send_user_only &&
7342 kvm_x86_ops->get_cpl(vcpu) == 0))
7343 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7344 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7345 fault.vector = PF_VECTOR;
7346 fault.error_code_valid = true;
7347 fault.error_code = 0;
7348 fault.nested_page_fault = false;
7349 fault.address = work->arch.token;
7350 kvm_inject_page_fault(vcpu, &fault);
7351 }
7352 }
7353
7354 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7355 struct kvm_async_pf *work)
7356 {
7357 struct x86_exception fault;
7358
7359 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7360 if (is_error_page(work->page))
7361 work->arch.token = ~0; /* broadcast wakeup */
7362 else
7363 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7364
7365 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7366 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7367 fault.vector = PF_VECTOR;
7368 fault.error_code_valid = true;
7369 fault.error_code = 0;
7370 fault.nested_page_fault = false;
7371 fault.address = work->arch.token;
7372 kvm_inject_page_fault(vcpu, &fault);
7373 }
7374 vcpu->arch.apf.halted = false;
7375 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7376 }
7377
7378 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7379 {
7380 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7381 return true;
7382 else
7383 return !kvm_event_needs_reinjection(vcpu) &&
7384 kvm_x86_ops->interrupt_allowed(vcpu);
7385 }
7386
7387 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7388 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7389 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7390 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7391 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7392 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7393 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7394 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7395 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7396 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7397 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7398 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7399 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux with added FPC-III support