drivers/edac/e7xxx_edac.c

   1 /*
   2  * Intel e7xxx Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e7xxx_chips" below for supported chipsets
   8  *
   9  * Written by Thayne Harbaugh
  10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  11  *      http://www.anime.net/~goemon/linux-ecc/
  12  *
  13  * Contributors:
  14  *      Eric Biederman (Linux Networx)
  15  *      Tom Zimmerman (Linux Networx)
  16  *      Jim Garlick (Lawrence Livermore National Labs)
  17  *      Dave Peterson (Lawrence Livermore National Labs)
  18  *      That One Guy (Some other place)
  19  *      Wang Zhenyu (intel.com)
  20  *
  21  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/pci_ids.h>
  29 #include <linux/slab.h>
  30 #include <linux/edac.h>
  31 #include "edac_core.h"
  32
  33 #define E7XXX_REVISION " Ver: 2.0.2 " __DATE__
  34 #define EDAC_MOD_STR    "e7xxx_edac"
  35
  36 #define e7xxx_printk(level, fmt, arg...) \
  37         edac_printk(level, "e7xxx", fmt, ##arg)
  38
  39 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
  40         edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
  41
  42 #ifndef PCI_DEVICE_ID_INTEL_7205_0
  43 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
  44 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
  45
  46 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
  47 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
  48 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
  49
  50 #ifndef PCI_DEVICE_ID_INTEL_7500_0
  51 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
  52 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
  53
  54 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
  55 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
  56 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
  57
  58 #ifndef PCI_DEVICE_ID_INTEL_7501_0
  59 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
  60 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
  61
  62 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
  63 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
  64 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
  65
  66 #ifndef PCI_DEVICE_ID_INTEL_7505_0
  67 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
  68 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
  69
  70 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
  71 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
  72 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
  73
  74 #define E7XXX_NR_CSROWS         8       /* number of csrows */
  75 #define E7XXX_NR_DIMMS          8       /* FIXME - is this correct? */
  76
  77 /* E7XXX register addresses - device 0 function 0 */
  78 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
  79 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
  80                                         /*
  81                                          * 31   Device width row 7 0=x8 1=x4
  82                                          * 27   Device width row 6
  83                                          * 23   Device width row 5
  84                                          * 19   Device width row 4
  85                                          * 15   Device width row 3
  86                                          * 11   Device width row 2
  87                                          *  7   Device width row 1
  88                                          *  3   Device width row 0
  89                                          */
  90 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
  91                                         /*
  92                                          * 22    Number channels 0=1,1=2
  93                                          * 19:18 DRB Granularity 32/64MB
  94                                          */
  95 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  96 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
  97 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
  98
  99 /* E7XXX register addresses - device 0 function 1 */
 100 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
 101 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
 102 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
 103                                         /*     error address register (32b) */
 104                                         /*
 105                                          * 31:28 Reserved
 106                                          * 27:6  CE address (4k block 33:12)
 107                                          *  5:0  Reserved
 108                                          */
 109 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
 110                                         /*     error address register (32b) */
 111                                         /*
 112                                          * 31:28 Reserved
 113                                          * 27:6  CE address (4k block 33:12)
 114                                          *  5:0  Reserved
 115                                          */
 116 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
 117                                         /*     error syndrome register (16b) */
 118
 119 enum e7xxx_chips {
 120         E7500 = 0,
 121         E7501,
 122         E7505,
 123         E7205,
 124 };
 125
 126 struct e7xxx_pvt {
 127         struct pci_dev *bridge_ck;
 128         u32 tolm;
 129         u32 remapbase;
 130         u32 remaplimit;
 131         const struct e7xxx_dev_info *dev_info;
 132 };
 133
 134 struct e7xxx_dev_info {
 135         u16 err_dev;
 136         const char *ctl_name;
 137 };
 138
 139 struct e7xxx_error_info {
 140         u8 dram_ferr;
 141         u8 dram_nerr;
 142         u32 dram_celog_add;
 143         u16 dram_celog_syndrome;
 144         u32 dram_uelog_add;
 145 };
 146
 147 static struct edac_pci_ctl_info *e7xxx_pci;
 148
 149 static const struct e7xxx_dev_info e7xxx_devs[] = {
 150         [E7500] = {
 151                 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
 152                 .ctl_name = "E7500"},
 153         [E7501] = {
 154                 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
 155                 .ctl_name = "E7501"},
 156         [E7505] = {
 157                 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
 158                 .ctl_name = "E7505"},
 159         [E7205] = {
 160                 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
 161                 .ctl_name = "E7205"},
 162 };
 163
 164 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
 165 static inline int e7xxx_find_channel(u16 syndrome)
 166 {
 167         debugf3("%s()\n", __func__);
 168
 169         if ((syndrome & 0xff00) == 0)
 170                 return 0;
 171
 172         if ((syndrome & 0x00ff) == 0)
 173                 return 1;
 174
 175         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
 176                 return 0;
 177
 178         return 1;
 179 }
 180
 181 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
 182                                 unsigned long page)
 183 {
 184         u32 remap;
 185         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
 186
 187         debugf3("%s()\n", __func__);
 188
 189         if ((page < pvt->tolm) ||
 190                 ((page >= 0x100000) && (page < pvt->remapbase)))
 191                 return page;
 192
 193         remap = (page - pvt->tolm) + pvt->remapbase;
 194
 195         if (remap < pvt->remaplimit)
 196                 return remap;
 197
 198         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 199         return pvt->tolm - 1;
 200 }
 201
 202 static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
 203 {
 204         u32 error_1b, page;
 205         u16 syndrome;
 206         int row;
 207         int channel;
 208
 209         debugf3("%s()\n", __func__);
 210         /* read the error address */
 211         error_1b = info->dram_celog_add;
 212         /* FIXME - should use PAGE_SHIFT */
 213         page = error_1b >> 6;   /* convert the address to 4k page */
 214         /* read the syndrome */
 215         syndrome = info->dram_celog_syndrome;
 216         /* FIXME - check for -1 */
 217         row = edac_mc_find_csrow_by_page(mci, page);
 218         /* convert syndrome to channel */
 219         channel = e7xxx_find_channel(syndrome);
 220         edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE");
 221 }
 222
 223 static void process_ce_no_info(struct mem_ctl_info *mci)
 224 {
 225         debugf3("%s()\n", __func__);
 226         edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
 227 }
 228
 229 static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
 230 {
 231         u32 error_2b, block_page;
 232         int row;
 233
 234         debugf3("%s()\n", __func__);
 235         /* read the error address */
 236         error_2b = info->dram_uelog_add;
 237         /* FIXME - should use PAGE_SHIFT */
 238         block_page = error_2b >> 6;     /* convert to 4k address */
 239         row = edac_mc_find_csrow_by_page(mci, block_page);
 240         edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
 241 }
 242
 243 static void process_ue_no_info(struct mem_ctl_info *mci)
 244 {
 245         debugf3("%s()\n", __func__);
 246         edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
 247 }
 248
 249 static void e7xxx_get_error_info(struct mem_ctl_info *mci,
 250                                  struct e7xxx_error_info *info)
 251 {
 252         struct e7xxx_pvt *pvt;
 253
 254         pvt = (struct e7xxx_pvt *)mci->pvt_info;
 255         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
 256         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
 257
 258         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
 259                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
 260                                 &info->dram_celog_add);
 261                 pci_read_config_word(pvt->bridge_ck,
 262                                 E7XXX_DRAM_CELOG_SYNDROME,
 263                                 &info->dram_celog_syndrome);
 264         }
 265
 266         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
 267                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
 268                                 &info->dram_uelog_add);
 269
 270         if (info->dram_ferr & 3)
 271                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
 272
 273         if (info->dram_nerr & 3)
 274                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
 275 }
 276
 277 static int e7xxx_process_error_info(struct mem_ctl_info *mci,
 278                                 struct e7xxx_error_info *info,
 279                                 int handle_errors)
 280 {
 281         int error_found;
 282
 283         error_found = 0;
 284
 285         /* decode and report errors */
 286         if (info->dram_ferr & 1) {      /* check first error correctable */
 287                 error_found = 1;
 288
 289                 if (handle_errors)
 290                         process_ce(mci, info);
 291         }
 292
 293         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
 294                 error_found = 1;
 295
 296                 if (handle_errors)
 297                         process_ue(mci, info);
 298         }
 299
 300         if (info->dram_nerr & 1) {      /* check next error correctable */
 301                 error_found = 1;
 302
 303                 if (handle_errors) {
 304                         if (info->dram_ferr & 1)
 305                                 process_ce_no_info(mci);
 306                         else
 307                                 process_ce(mci, info);
 308                 }
 309         }
 310
 311         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
 312                 error_found = 1;
 313
 314                 if (handle_errors) {
 315                         if (info->dram_ferr & 2)
 316                                 process_ue_no_info(mci);
 317                         else
 318                                 process_ue(mci, info);
 319                 }
 320         }
 321
 322         return error_found;
 323 }
 324
 325 static void e7xxx_check(struct mem_ctl_info *mci)
 326 {
 327         struct e7xxx_error_info info;
 328
 329         debugf3("%s()\n", __func__);
 330         e7xxx_get_error_info(mci, &info);
 331         e7xxx_process_error_info(mci, &info, 1);
 332 }
 333
 334 /* Return 1 if dual channel mode is active.  Else return 0. */
 335 static inline int dual_channel_active(u32 drc, int dev_idx)
 336 {
 337         return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
 338 }
 339
 340 /* Return DRB granularity (0=32mb, 1=64mb). */
 341 static inline int drb_granularity(u32 drc, int dev_idx)
 342 {
 343         /* only e7501 can be single channel */
 344         return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
 345 }
 346
 347 static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 348                         int dev_idx, u32 drc)
 349 {
 350         unsigned long last_cumul_size;
 351         int index;
 352         u8 value;
 353         u32 dra, cumul_size;
 354         int drc_chan, drc_drbg, drc_ddim, mem_dev;
 355         struct csrow_info *csrow;
 356
 357         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
 358         drc_chan = dual_channel_active(drc, dev_idx);
 359         drc_drbg = drb_granularity(drc, dev_idx);
 360         drc_ddim = (drc >> 20) & 0x3;
 361         last_cumul_size = 0;
 362
 363         /* The dram row boundary (DRB) reg values are boundary address
 364          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 365          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 366          * contain the total memory contained in all eight rows.
 367          */
 368         for (index = 0; index < mci->nr_csrows; index++) {
 369                 /* mem_dev 0=x8, 1=x4 */
 370                 mem_dev = (dra >> (index * 4 + 3)) & 0x1;
 371                 csrow = &mci->csrows[index];
 372
 373                 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
 374                 /* convert a 64 or 32 MiB DRB to a page size. */
 375                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 376                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 377                         cumul_size);
 378                 if (cumul_size == last_cumul_size)
 379                         continue;       /* not populated */
 380
 381                 csrow->first_page = last_cumul_size;
 382                 csrow->last_page = cumul_size - 1;
 383                 csrow->nr_pages = cumul_size - last_cumul_size;
 384                 last_cumul_size = cumul_size;
 385                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 386                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 387                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 388
 389                 /*
 390                  * if single channel or x8 devices then SECDED
 391                  * if dual channel and x4 then S4ECD4ED
 392                  */
 393                 if (drc_ddim) {
 394                         if (drc_chan && mem_dev) {
 395                                 csrow->edac_mode = EDAC_S4ECD4ED;
 396                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 397                         } else {
 398                                 csrow->edac_mode = EDAC_SECDED;
 399                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 400                         }
 401                 } else
 402                         csrow->edac_mode = EDAC_NONE;
 403         }
 404 }
 405
 406 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
 407 {
 408         u16 pci_data;
 409         struct mem_ctl_info *mci = NULL;
 410         struct e7xxx_pvt *pvt = NULL;
 411         u32 drc;
 412         int drc_chan;
 413         struct e7xxx_error_info discard;
 414
 415         debugf0("%s(): mci\n", __func__);
 416
 417         /* make sure error reporting method is sane */
 418         switch (edac_op_state) {
 419         case EDAC_OPSTATE_POLL:
 420         case EDAC_OPSTATE_NMI:
 421                 break;
 422         default:
 423                 edac_op_state = EDAC_OPSTATE_POLL;
 424                 break;
 425         }
 426
 427         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
 428
 429         drc_chan = dual_channel_active(drc, dev_idx);
 430         mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1, 0);
 431
 432         if (mci == NULL)
 433                 return -ENOMEM;
 434
 435         debugf3("%s(): init mci\n", __func__);
 436         mci->mtype_cap = MEM_FLAG_RDDR;
 437         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
 438                 EDAC_FLAG_S4ECD4ED;
 439         /* FIXME - what if different memory types are in different csrows? */
 440         mci->mod_name = EDAC_MOD_STR;
 441         mci->mod_ver = E7XXX_REVISION;
 442         mci->dev = &pdev->dev;
 443         debugf3("%s(): init pvt\n", __func__);
 444         pvt = (struct e7xxx_pvt *)mci->pvt_info;
 445         pvt->dev_info = &e7xxx_devs[dev_idx];
 446         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 447                                         pvt->dev_info->err_dev, pvt->bridge_ck);
 448
 449         if (!pvt->bridge_ck) {
 450                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
 451                         "vendor %x device 0x%x (broken BIOS?)\n",
 452                         PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
 453                 goto fail0;
 454         }
 455
 456         debugf3("%s(): more mci init\n", __func__);
 457         mci->ctl_name = pvt->dev_info->ctl_name;
 458         mci->dev_name = pci_name(pdev);
 459         mci->edac_check = e7xxx_check;
 460         mci->ctl_page_to_phys = ctl_page_to_phys;
 461         e7xxx_init_csrows(mci, pdev, dev_idx, drc);
 462         mci->edac_cap |= EDAC_FLAG_NONE;
 463         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
 464         /* load the top of low memory, remap base, and remap limit vars */
 465         pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
 466         pvt->tolm = ((u32) pci_data) << 4;
 467         pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
 468         pvt->remapbase = ((u32) pci_data) << 14;
 469         pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
 470         pvt->remaplimit = ((u32) pci_data) << 14;
 471         e7xxx_printk(KERN_INFO,
 472                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
 473                 pvt->remapbase, pvt->remaplimit);
 474
 475         /* clear any pending errors, or initial state bits */
 476         e7xxx_get_error_info(mci, &discard);
 477
 478         /* Here we assume that we will never see multiple instances of this
 479          * type of memory controller.  The ID is therefore hardcoded to 0.
 480          */
 481         if (edac_mc_add_mc(mci)) {
 482                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 483                 goto fail1;
 484         }
 485
 486         /* allocating generic PCI control info */
 487         e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
 488         if (!e7xxx_pci) {
 489                 printk(KERN_WARNING
 490                         "%s(): Unable to create PCI control\n",
 491                         __func__);
 492                 printk(KERN_WARNING
 493                         "%s(): PCI error report via EDAC not setup\n",
 494                         __func__);
 495         }
 496
 497         /* get this far and it's successful */
 498         debugf3("%s(): success\n", __func__);
 499         return 0;
 500
 501 fail1:
 502         pci_dev_put(pvt->bridge_ck);
 503
 504 fail0:
 505         edac_mc_free(mci);
 506
 507         return -ENODEV;
 508 }
 509
 510 /* returns count (>= 0), or negative on error */
 511 static int __devinit e7xxx_init_one(struct pci_dev *pdev,
 512                                 const struct pci_device_id *ent)
 513 {
 514         debugf0("%s()\n", __func__);
 515
 516         /* wake up and enable device */
 517         return pci_enable_device(pdev) ?
 518                 -EIO : e7xxx_probe1(pdev, ent->driver_data);
 519 }
 520
 521 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
 522 {
 523         struct mem_ctl_info *mci;
 524         struct e7xxx_pvt *pvt;
 525
 526         debugf0("%s()\n", __func__);
 527
 528         if (e7xxx_pci)
 529                 edac_pci_release_generic_ctl(e7xxx_pci);
 530
 531         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 532                 return;
 533
 534         pvt = (struct e7xxx_pvt *)mci->pvt_info;
 535         pci_dev_put(pvt->bridge_ck);
 536         edac_mc_free(mci);
 537 }
 538
 539 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
 540         {
 541          PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 542          E7205},
 543         {
 544          PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 545          E7500},
 546         {
 547          PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 548          E7501},
 549         {
 550          PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 551          E7505},
 552         {
 553          0,
 554          }                      /* 0 terminated list. */
 555 };
 556
 557 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
 558
 559 static struct pci_driver e7xxx_driver = {
 560         .name = EDAC_MOD_STR,
 561         .probe = e7xxx_init_one,
 562         .remove = __devexit_p(e7xxx_remove_one),
 563         .id_table = e7xxx_pci_tbl,
 564 };
 565
 566 static int __init e7xxx_init(void)
 567 {
 568         return pci_register_driver(&e7xxx_driver);
 569 }
 570
 571 static void __exit e7xxx_exit(void)
 572 {
 573         pci_unregister_driver(&e7xxx_driver);
 574 }
 575
 576 module_init(e7xxx_init);
 577 module_exit(e7xxx_exit);
 578
 579 MODULE_LICENSE("GPL");
 580 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
 581                 "Based on.work by Dan Hollis et al");
 582 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
 583 module_param(edac_op_state, int, 0444);
 584 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");