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iwlwifi: introduce host commands callbacks
[linux/fpc-iii.git] / drivers / ide / pci / pdc202xx_old.c
blob150422ec3cfabc6685d8f6a8bf5b82804cf969b4
1 /*
2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 *
6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com)
8 * Released under terms of General Public License
9 */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/hdreg.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ide.h>
20
21 #include <asm/io.h>
22
23 #define PDC202XX_DEBUG_DRIVE_INFO 0
24
25 static const char *pdc_quirk_drives[] = {
26 "QUANTUM FIREBALLlct08 08",
27 "QUANTUM FIREBALLP KA6.4",
28 "QUANTUM FIREBALLP KA9.1",
29 "QUANTUM FIREBALLP LM20.4",
30 "QUANTUM FIREBALLP KX13.6",
31 "QUANTUM FIREBALLP KX20.5",
32 "QUANTUM FIREBALLP KX27.3",
33 "QUANTUM FIREBALLP LM20.5",
34 NULL
35 };
36
37 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
38
39 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
40 {
41 ide_hwif_t *hwif = HWIF(drive);
42 struct pci_dev *dev = to_pci_dev(hwif->dev);
43 u8 drive_pci = 0x60 + (drive->dn << 2);
44
45 u8 AP = 0, BP = 0, CP = 0;
46 u8 TA = 0, TB = 0, TC = 0;
47
48 #if PDC202XX_DEBUG_DRIVE_INFO
49 u32 drive_conf = 0;
50 pci_read_config_dword(dev, drive_pci, &drive_conf);
51 #endif
52
53 /*
54 * TODO: do this once per channel
55 */
56 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
57 pdc_old_disable_66MHz_clock(hwif);
58
59 pci_read_config_byte(dev, drive_pci, &AP);
60 pci_read_config_byte(dev, drive_pci + 1, &BP);
61 pci_read_config_byte(dev, drive_pci + 2, &CP);
62
63 switch(speed) {
64 case XFER_UDMA_5:
65 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
66 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
67 case XFER_UDMA_3:
68 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
69 case XFER_UDMA_0:
70 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
71 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
72 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
73 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
74 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
75 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
76 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
77 case XFER_PIO_0:
78 default: TA = 0x09; TB = 0x13; break;
79 }
80
81 if (speed < XFER_SW_DMA_0) {
82 /*
83 * preserve SYNC_INT / ERDDY_EN bits while clearing
84 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
85 */
86 AP &= ~0x3f;
87 if (drive->id->capability & 4)
88 AP |= 0x20; /* set IORDY_EN bit */
89 if (drive->media == ide_disk)
90 AP |= 0x10; /* set Prefetch_EN bit */
91 /* clear PB[4:0] bits of register B */
92 BP &= ~0x1f;
93 pci_write_config_byte(dev, drive_pci, AP | TA);
94 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
95 } else {
96 /* clear MB[2:0] bits of register B */
97 BP &= ~0xe0;
98 /* clear MC[3:0] bits of register C */
99 CP &= ~0x0f;
100 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
101 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
102 }
103
104 #if PDC202XX_DEBUG_DRIVE_INFO
105 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
106 drive->name, ide_xfer_verbose(speed),
107 drive->dn, drive_conf);
108 pci_read_config_dword(dev, drive_pci, &drive_conf);
109 printk("0x%08x\n", drive_conf);
110 #endif
111 }
112
113 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
114 {
115 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
116 }
117
118 static u8 __devinit pdc2026x_old_cable_detect(ide_hwif_t *hwif)
119 {
120 struct pci_dev *dev = to_pci_dev(hwif->dev);
121 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
122
123 pci_read_config_word(dev, 0x50, &CIS);
124
125 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
126 }
127
128 /*
129 * Set the control register to use the 66MHz system
130 * clock for UDMA 3/4/5 mode operation when necessary.
131 *
132 * FIXME: this register is shared by both channels, some locking is needed
133 *
134 * It may also be possible to leave the 66MHz clock on
135 * and readjust the timing parameters.
136 */
137 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
138 {
139 unsigned long clock_reg = hwif->extra_base + 0x01;
140 u8 clock = inb(clock_reg);
141
142 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
143 }
144
145 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
146 {
147 unsigned long clock_reg = hwif->extra_base + 0x01;
148 u8 clock = inb(clock_reg);
149
150 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
151 }
152
153 static void pdc202xx_quirkproc(ide_drive_t *drive)
154 {
155 const char **list, *model = drive->id->model;
156
157 for (list = pdc_quirk_drives; *list != NULL; list++)
158 if (strstr(model, *list) != NULL) {
159 drive->quirk_list = 2;
160 return;
161 }
162
163 drive->quirk_list = 0;
164 }
165
166 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
167 {
168 if (drive->current_speed > XFER_UDMA_2)
169 pdc_old_enable_66MHz_clock(drive->hwif);
170 if (drive->media != ide_disk || drive->addressing == 1) {
171 struct request *rq = HWGROUP(drive)->rq;
172 ide_hwif_t *hwif = HWIF(drive);
173 unsigned long high_16 = hwif->extra_base - 16;
174 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
175 u32 word_count = 0;
176 u8 clock = inb(high_16 + 0x11);
177
178 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
179 word_count = (rq->nr_sectors << 8);
180 word_count = (rq_data_dir(rq) == READ) ?
181 word_count | 0x05000000 :
182 word_count | 0x06000000;
183 outl(word_count, atapi_reg);
184 }
185 ide_dma_start(drive);
186 }
187
188 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
189 {
190 if (drive->media != ide_disk || drive->addressing == 1) {
191 ide_hwif_t *hwif = HWIF(drive);
192 unsigned long high_16 = hwif->extra_base - 16;
193 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
194 u8 clock = 0;
195
196 outl(0, atapi_reg); /* zero out extra */
197 clock = inb(high_16 + 0x11);
198 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
199 }
200 if (drive->current_speed > XFER_UDMA_2)
201 pdc_old_disable_66MHz_clock(drive->hwif);
202 return __ide_dma_end(drive);
203 }
204
205 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
206 {
207 ide_hwif_t *hwif = HWIF(drive);
208 unsigned long high_16 = hwif->extra_base - 16;
209 u8 dma_stat = inb(hwif->dma_status);
210 u8 sc1d = inb(high_16 + 0x001d);
211
212 if (hwif->channel) {
213 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
214 if ((sc1d & 0x50) == 0x50)
215 goto somebody_else;
216 else if ((sc1d & 0x40) == 0x40)
217 return (dma_stat & 4) == 4;
218 } else {
219 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
220 if ((sc1d & 0x05) == 0x05)
221 goto somebody_else;
222 else if ((sc1d & 0x04) == 0x04)
223 return (dma_stat & 4) == 4;
224 }
225 somebody_else:
226 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
227 }
228
229 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
230 {
231 ide_hwif_t *hwif = HWIF(drive);
232
233 if (hwif->resetproc != NULL)
234 hwif->resetproc(drive);
235
236 ide_dma_lost_irq(drive);
237 }
238
239 static void pdc202xx_dma_timeout(ide_drive_t *drive)
240 {
241 ide_hwif_t *hwif = HWIF(drive);
242
243 if (hwif->resetproc != NULL)
244 hwif->resetproc(drive);
245
246 ide_dma_timeout(drive);
247 }
248
249 static void pdc202xx_reset_host (ide_hwif_t *hwif)
250 {
251 unsigned long high_16 = hwif->extra_base - 16;
252 u8 udma_speed_flag = inb(high_16 | 0x001f);
253
254 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
255 mdelay(100);
256 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
257 mdelay(2000); /* 2 seconds ?! */
258
259 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
260 hwif->channel ? "Secondary" : "Primary");
261 }
262
263 static void pdc202xx_reset (ide_drive_t *drive)
264 {
265 ide_hwif_t *hwif = HWIF(drive);
266 ide_hwif_t *mate = hwif->mate;
267
268 pdc202xx_reset_host(hwif);
269 pdc202xx_reset_host(mate);
270
271 ide_set_max_pio(drive);
272 }
273
274 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
275 const char *name)
276 {
277 return dev->irq;
278 }
279
280 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
281 {
282 struct pci_dev *dev = to_pci_dev(hwif->dev);
283
284 hwif->set_pio_mode = &pdc202xx_set_pio_mode;
285 hwif->set_dma_mode = &pdc202xx_set_mode;
286
287 hwif->quirkproc = &pdc202xx_quirkproc;
288
289 if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
290 hwif->resetproc = &pdc202xx_reset;
291
292 hwif->cable_detect = pdc2026x_old_cable_detect;
293 }
294
295 if (hwif->dma_base == 0)
296 return;
297
298 hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
299 hwif->dma_timeout = &pdc202xx_dma_timeout;
300
301 if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
302 hwif->dma_start = &pdc202xx_old_ide_dma_start;
303 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
304 }
305 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
306 }
307
308 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
309 {
310 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
311
312 if (hwif->channel) {
313 ide_setup_dma(hwif, dmabase);
314 return;
315 }
316
317 udma_speed_flag = inb(dmabase | 0x1f);
318 primary_mode = inb(dmabase | 0x1a);
319 secondary_mode = inb(dmabase | 0x1b);
320 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
321 "Primary %s Mode " \
322 "Secondary %s Mode.\n", hwif->cds->name,
323 (udma_speed_flag & 1) ? "EN" : "DIS",
324 (primary_mode & 1) ? "MASTER" : "PCI",
325 (secondary_mode & 1) ? "MASTER" : "PCI" );
326
327 if (!(udma_speed_flag & 1)) {
328 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
329 hwif->cds->name, udma_speed_flag,
330 (udma_speed_flag|1));
331 outb(udma_speed_flag | 1, dmabase | 0x1f);
332 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
333 }
334
335 ide_setup_dma(hwif, dmabase);
336 }
337
338 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
339 const char *name)
340 {
341 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
342 u8 irq = 0, irq2 = 0;
343 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
344 /* 0xbc */
345 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
346 if (irq != irq2) {
347 pci_write_config_byte(dev,
348 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
349 printk(KERN_INFO "%s: PCI config space interrupt "
350 "mirror fixed\n", name);
351 }
352 }
353 }
354
355 #define IDE_HFLAGS_PDC202XX \
356 (IDE_HFLAG_ERROR_STOPS_FIFO | \
357 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
358 IDE_HFLAG_OFF_BOARD)
359
360 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
361 { \
362 .name = name_str, \
363 .init_chipset = init_chipset_pdc202xx, \
364 .init_hwif = init_hwif_pdc202xx, \
365 .init_dma = init_dma_pdc202xx, \
366 .extra = 48, \
367 .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
368 .pio_mask = ATA_PIO4, \
369 .mwdma_mask = ATA_MWDMA2, \
370 .udma_mask = udma, \
371 }
372
373 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
374 { /* 0 */
375 .name = "PDC20246",
376 .init_chipset = init_chipset_pdc202xx,
377 .init_hwif = init_hwif_pdc202xx,
378 .init_dma = init_dma_pdc202xx,
379 .extra = 16,
380 .host_flags = IDE_HFLAGS_PDC202XX,
381 .pio_mask = ATA_PIO4,
382 .mwdma_mask = ATA_MWDMA2,
383 .udma_mask = ATA_UDMA2,
384 },
385
386 /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
387 /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
388 /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
389 /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
390 };
391
392 /**
393 * pdc202xx_init_one - called when a PDC202xx is found
394 * @dev: the pdc202xx device
395 * @id: the matching pci id
396 *
397 * Called when the PCI registration layer (or the IDE initialization)
398 * finds a device matching our IDE device tables.
399 */
400
401 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
402 {
403 const struct ide_port_info *d;
404 u8 idx = id->driver_data;
405
406 d = &pdc202xx_chipsets[idx];
407
408 if (idx < 3)
409 pdc202ata4_fixup_irq(dev, d->name);
410
411 if (idx == 3) {
412 struct pci_dev *bridge = dev->bus->self;
413
414 if (bridge &&
415 bridge->vendor == PCI_VENDOR_ID_INTEL &&
416 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
417 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
418 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
419 "attached to I2O RAID controller\n");
420 return -ENODEV;
421 }
422 }
423
424 return ide_setup_pci_device(dev, d);
425 }
426
427 static const struct pci_device_id pdc202xx_pci_tbl[] = {
428 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
429 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
430 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
431 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
432 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
433 { 0, },
434 };
435 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
436
437 static struct pci_driver driver = {
438 .name = "Promise_Old_IDE",
439 .id_table = pdc202xx_pci_tbl,
440 .probe = pdc202xx_init_one,
441 };
442
443 static int __init pdc202xx_ide_init(void)
444 {
445 return ide_pci_register_driver(&driver);
446 }
447
448 module_init(pdc202xx_ide_init);
449
450 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
451 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
452 MODULE_LICENSE("GPL");
Linux with added FPC-III support