| blob | 92ad73a7fff0f20f353a1f63e2efe0bd265e0ce3 |
1 /*
2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
34 #ifndef _IPATH_REGISTERS_H
35 #define _IPATH_REGISTERS_H
37 /*
38 * This file should only be included by kernel source, and by the diags. It
39 * defines the registers, and their contents, for InfiniPath chips.
40 */
42 /*
43 * These are the InfiniPath register and buffer bit definitions,
44 * that are visible to software, and needed only by the kernel
45 * and diag code. A few, that are visible to protocol and user
46 * code are in ipath_common.h. Some bits are specific
47 * to a given chip implementation, and have been moved to the
48 * chip-specific source file
49 */
51 /* kr_revision bits */
52 #define INFINIPATH_R_CHIPREVMINOR_MASK 0xFF
53 #define INFINIPATH_R_CHIPREVMINOR_SHIFT 0
54 #define INFINIPATH_R_CHIPREVMAJOR_MASK 0xFF
55 #define INFINIPATH_R_CHIPREVMAJOR_SHIFT 8
56 #define INFINIPATH_R_ARCH_MASK 0xFF
57 #define INFINIPATH_R_ARCH_SHIFT 16
58 #define INFINIPATH_R_SOFTWARE_MASK 0xFF
59 #define INFINIPATH_R_SOFTWARE_SHIFT 24
60 #define INFINIPATH_R_BOARDID_MASK 0xFF
61 #define INFINIPATH_R_BOARDID_SHIFT 32
63 /* kr_control bits */
64 #define INFINIPATH_C_FREEZEMODE 0x00000002
65 #define INFINIPATH_C_LINKENABLE 0x00000004
66 #define INFINIPATH_C_RESET 0x00000001
68 /* kr_sendctrl bits */
69 #define INFINIPATH_S_DISARMPIOBUF_SHIFT 16
71 #define IPATH_S_ABORT 0
72 #define IPATH_S_PIOINTBUFAVAIL 1
73 #define IPATH_S_PIOBUFAVAILUPD 2
74 #define IPATH_S_PIOENABLE 3
75 #define IPATH_S_DISARM 31
77 #define INFINIPATH_S_ABORT (1U << IPATH_S_ABORT)
78 #define INFINIPATH_S_PIOINTBUFAVAIL (1U << IPATH_S_PIOINTBUFAVAIL)
79 #define INFINIPATH_S_PIOBUFAVAILUPD (1U << IPATH_S_PIOBUFAVAILUPD)
80 #define INFINIPATH_S_PIOENABLE (1U << IPATH_S_PIOENABLE)
81 #define INFINIPATH_S_DISARM (1U << IPATH_S_DISARM)
83 /* kr_rcvctrl bits */
84 #define INFINIPATH_R_PORTENABLE_SHIFT 0
85 #define INFINIPATH_R_QPMAP_ENABLE (1ULL << 38)
87 /* kr_intstatus, kr_intclear, kr_intmask bits */
88 #define INFINIPATH_I_RCVURG_SHIFT 0
89 #define INFINIPATH_I_RCVAVAIL_SHIFT 12
90 #define INFINIPATH_I_ERROR 0x80000000
91 #define INFINIPATH_I_SPIOSENT 0x40000000
92 #define INFINIPATH_I_SPIOBUFAVAIL 0x20000000
93 #define INFINIPATH_I_GPIO 0x10000000
95 /* kr_errorstatus, kr_errorclear, kr_errormask bits */
96 #define INFINIPATH_E_RFORMATERR 0x0000000000000001ULL
97 #define INFINIPATH_E_RVCRC 0x0000000000000002ULL
98 #define INFINIPATH_E_RICRC 0x0000000000000004ULL
99 #define INFINIPATH_E_RMINPKTLEN 0x0000000000000008ULL
100 #define INFINIPATH_E_RMAXPKTLEN 0x0000000000000010ULL
101 #define INFINIPATH_E_RLONGPKTLEN 0x0000000000000020ULL
102 #define INFINIPATH_E_RSHORTPKTLEN 0x0000000000000040ULL
103 #define INFINIPATH_E_RUNEXPCHAR 0x0000000000000080ULL
104 #define INFINIPATH_E_RUNSUPVL 0x0000000000000100ULL
105 #define INFINIPATH_E_REBP 0x0000000000000200ULL
106 #define INFINIPATH_E_RIBFLOW 0x0000000000000400ULL
107 #define INFINIPATH_E_RBADVERSION 0x0000000000000800ULL
108 #define INFINIPATH_E_RRCVEGRFULL 0x0000000000001000ULL
109 #define INFINIPATH_E_RRCVHDRFULL 0x0000000000002000ULL
110 #define INFINIPATH_E_RBADTID 0x0000000000004000ULL
111 #define INFINIPATH_E_RHDRLEN 0x0000000000008000ULL
112 #define INFINIPATH_E_RHDR 0x0000000000010000ULL
113 #define INFINIPATH_E_RIBLOSTLINK 0x0000000000020000ULL
114 #define INFINIPATH_E_SMINPKTLEN 0x0000000020000000ULL
115 #define INFINIPATH_E_SMAXPKTLEN 0x0000000040000000ULL
116 #define INFINIPATH_E_SUNDERRUN 0x0000000080000000ULL
117 #define INFINIPATH_E_SPKTLEN 0x0000000100000000ULL
118 #define INFINIPATH_E_SDROPPEDSMPPKT 0x0000000200000000ULL
119 #define INFINIPATH_E_SDROPPEDDATAPKT 0x0000000400000000ULL
120 #define INFINIPATH_E_SPIOARMLAUNCH 0x0000000800000000ULL
121 #define INFINIPATH_E_SUNEXPERRPKTNUM 0x0000001000000000ULL
122 #define INFINIPATH_E_SUNSUPVL 0x0000002000000000ULL
123 #define INFINIPATH_E_IBSTATUSCHANGED 0x0001000000000000ULL
124 #define INFINIPATH_E_INVALIDADDR 0x0002000000000000ULL
125 #define INFINIPATH_E_RESET 0x0004000000000000ULL
126 #define INFINIPATH_E_HARDWARE 0x0008000000000000ULL
128 /*
129 * this is used to print "common" packet errors only when the
130 * __IPATH_ERRPKTDBG bit is set in ipath_debug.
131 */
132 #define INFINIPATH_E_PKTERRS ( INFINIPATH_E_SPKTLEN \
133 | INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_RVCRC \
134 | INFINIPATH_E_RICRC | INFINIPATH_E_RSHORTPKTLEN \
135 | INFINIPATH_E_REBP )
137 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
138 /* TXEMEMPARITYERR bit 0: PIObuf, 1: PIOpbc, 2: launchfifo
139 * RXEMEMPARITYERR bit 0: rcvbuf, 1: lookupq, 2: expTID, 3: eagerTID
140 * bit 4: flag buffer, 5: datainfo, 6: header info */
141 #define INFINIPATH_HWE_TXEMEMPARITYERR_MASK 0xFULL
142 #define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40
143 #define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL
144 #define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44
145 #define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL
146 #define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL
147 /* txe mem parity errors (shift by INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) */
148 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF 0x1ULL
149 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC 0x2ULL
150 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOLAUNCHFIFO 0x4ULL
151 /* rxe mem parity errors (shift by INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) */
152 #define INFINIPATH_HWE_RXEMEMPARITYERR_RCVBUF 0x01ULL
153 #define INFINIPATH_HWE_RXEMEMPARITYERR_LOOKUPQ 0x02ULL
154 #define INFINIPATH_HWE_RXEMEMPARITYERR_EXPTID 0x04ULL
155 #define INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID 0x08ULL
156 #define INFINIPATH_HWE_RXEMEMPARITYERR_FLAGBUF 0x10ULL
157 #define INFINIPATH_HWE_RXEMEMPARITYERR_DATAINFO 0x20ULL
158 #define INFINIPATH_HWE_RXEMEMPARITYERR_HDRINFO 0x40ULL
159 /* waldo specific -- find the rest in ipath_6110.c */
160 #define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL
161 /* monty specific -- find the rest in ipath_6120.c */
162 #define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL
164 /* kr_hwdiagctrl bits */
165 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL
166 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_SHIFT 40
167 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_MASK 0x7FULL
168 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_SHIFT 44
169 #define INFINIPATH_DC_FORCERXDSYNCMEMPARITYERR 0x0000000400000000ULL
170 #define INFINIPATH_DC_COUNTERDISABLE 0x1000000000000000ULL
171 #define INFINIPATH_DC_COUNTERWREN 0x2000000000000000ULL
172 #define INFINIPATH_DC_FORCEIBCBUSTOSPCPARITYERR 0x4000000000000000ULL
173 #define INFINIPATH_DC_FORCEIBCBUSFRSPCPARITYERR 0x8000000000000000ULL
175 /* kr_ibcctrl bits */
176 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_MASK 0xFFULL
177 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT 0
178 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_MASK 0xFFULL
179 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8
180 #define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL
181 #define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1
182 /* cycle through TS1/TS2 till OK */
183 #define INFINIPATH_IBCC_LINKINITCMD_POLL 2
184 /* wait for TS1, then go on */
185 #define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3
186 #define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
187 #define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
191 #define INFINIPATH_IBCC_LINKCMD_SHIFT 18
192 #define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL
193 #define INFINIPATH_IBCC_MAXPKTLEN_SHIFT 20
194 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK 0xFULL
195 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT 32
196 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_MASK 0xFULL
197 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT 36
198 #define INFINIPATH_IBCC_CREDITSCALE_MASK 0x7ULL
199 #define INFINIPATH_IBCC_CREDITSCALE_SHIFT 40
200 #define INFINIPATH_IBCC_LOOPBACK 0x8000000000000000ULL
201 #define INFINIPATH_IBCC_LINKDOWNDEFAULTSTATE 0x4000000000000000ULL
203 /* kr_ibcstatus bits */
204 #define INFINIPATH_IBCS_LINKTRAININGSTATE_MASK 0xF
205 #define INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT 0
206 #define INFINIPATH_IBCS_LINKSTATE_MASK 0x7
207 #define INFINIPATH_IBCS_LINKSTATE_SHIFT 4
208 #define INFINIPATH_IBCS_TXREADY 0x40000000
209 #define INFINIPATH_IBCS_TXCREDITOK 0x80000000
210 /* link training states (shift by
211 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
212 #define INFINIPATH_IBCS_LT_STATE_DISABLED 0x00
213 #define INFINIPATH_IBCS_LT_STATE_LINKUP 0x01
214 #define INFINIPATH_IBCS_LT_STATE_POLLACTIVE 0x02
215 #define INFINIPATH_IBCS_LT_STATE_POLLQUIET 0x03
216 #define INFINIPATH_IBCS_LT_STATE_SLEEPDELAY 0x04
217 #define INFINIPATH_IBCS_LT_STATE_SLEEPQUIET 0x05
218 #define INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE 0x08
219 #define INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG 0x09
220 #define INFINIPATH_IBCS_LT_STATE_CFGWAITRMT 0x0a
221 #define INFINIPATH_IBCS_LT_STATE_CFGIDLE 0x0b
222 #define INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN 0x0c
223 #define INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT 0x0e
224 #define INFINIPATH_IBCS_LT_STATE_RECOVERIDLE 0x0f
225 /* link state machine states (shift by INFINIPATH_IBCS_LINKSTATE_SHIFT) */
226 #define INFINIPATH_IBCS_L_STATE_DOWN 0x0
227 #define INFINIPATH_IBCS_L_STATE_INIT 0x1
228 #define INFINIPATH_IBCS_L_STATE_ARM 0x2
229 #define INFINIPATH_IBCS_L_STATE_ACTIVE 0x3
230 #define INFINIPATH_IBCS_L_STATE_ACT_DEFER 0x4
232 /* combination link status states that we use with some frequency */
233 #define IPATH_IBSTATE_MASK ((INFINIPATH_IBCS_LINKTRAININGSTATE_MASK \
234 << INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) | \
235 (INFINIPATH_IBCS_LINKSTATE_MASK \
236 <<INFINIPATH_IBCS_LINKSTATE_SHIFT))
237 #define IPATH_IBSTATE_INIT ((INFINIPATH_IBCS_L_STATE_INIT \
238 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
239 (INFINIPATH_IBCS_LT_STATE_LINKUP \
240 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
241 #define IPATH_IBSTATE_ARM ((INFINIPATH_IBCS_L_STATE_ARM \
242 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
243 (INFINIPATH_IBCS_LT_STATE_LINKUP \
244 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
245 #define IPATH_IBSTATE_ACTIVE ((INFINIPATH_IBCS_L_STATE_ACTIVE \
246 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
247 (INFINIPATH_IBCS_LT_STATE_LINKUP \
248 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
250 /* kr_extstatus bits */
251 #define INFINIPATH_EXTS_SERDESPLLLOCK 0x1
252 #define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL
253 #define INFINIPATH_EXTS_GPIOIN_SHIFT 48
255 /* kr_extctrl bits */
256 #define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL
257 #define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32
258 #define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL
259 #define INFINIPATH_EXTC_GPIOOE_SHIFT 48
260 #define INFINIPATH_EXTC_SERDESENABLE 0x80000000ULL
261 #define INFINIPATH_EXTC_SERDESCONNECT 0x40000000ULL
262 #define INFINIPATH_EXTC_SERDESENTRUNKING 0x20000000ULL
263 #define INFINIPATH_EXTC_SERDESDISRXFIFO 0x10000000ULL
264 #define INFINIPATH_EXTC_SERDESENPLPBK1 0x08000000ULL
265 #define INFINIPATH_EXTC_SERDESENPLPBK2 0x04000000ULL
266 #define INFINIPATH_EXTC_SERDESENENCDEC 0x02000000ULL
267 #define INFINIPATH_EXTC_LED1SECPORT_ON 0x00000020ULL
268 #define INFINIPATH_EXTC_LED2SECPORT_ON 0x00000010ULL
269 #define INFINIPATH_EXTC_LED1PRIPORT_ON 0x00000008ULL
270 #define INFINIPATH_EXTC_LED2PRIPORT_ON 0x00000004ULL
271 #define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL
272 #define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL
274 /* kr_partitionkey bits */
275 #define INFINIPATH_PKEY_SIZE 16
276 #define INFINIPATH_PKEY_MASK 0xFFFF
277 #define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF
279 /* kr_serdesconfig0 bits */
282 /* tx idle enables (per lane) */
283 #define INFINIPATH_SERDC0_TXIDLE 0xF000ULL
284 /* rx detect enables (per lane) */
285 #define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL
286 /* L1 Power down; use with RXDETECT, Otherwise not used on IB side */
287 #define INFINIPATH_SERDC0_L1PWR_DN 0xF0ULL
289 /* kr_xgxsconfig bits */
290 #define INFINIPATH_XGXS_RESET 0x7ULL
291 #define INFINIPATH_XGXS_RX_POL_SHIFT 19
292 #define INFINIPATH_XGXS_RX_POL_MASK 0xfULL
295 /*
296 * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our
297 * PIO send buffers. This is well beyond anything currently
298 * defined in the InfiniBand spec.
299 */
300 #define IPATH_PIO_MAXIBHDR 128
304 /* The following change with the type of device, so
305 * need to be part of the ipath_devdata struct, or
306 * we could have problems plugging in devices of
307 * different types (e.g. one HT, one PCIE)
308 * in one system, to be managed by one driver.
309 * On the other hand, this file is may also be included
310 * by other code, so leave the declarations here
311 * temporarily. Minor footprint issue if common-model
312 * linker used, none if C89+ linker used.
313 */
315 /* mask of defined bits for various registers */
319 /* masks that are different in various chips, or only exist in some chips */
322 /*
323 * These are the infinipath general register numbers (not offsets).
324 * The kernel registers are used directly, those beyond the kernel
325 * registers are calculated from one of the base registers. The use of
326 * an integer type doesn't allow type-checking as thorough as, say,
327 * an enum but allows for better hiding of chip differences.
328 */
333 /*
334 * These are the chip registers common to all infinipath chips, and
335 * used both by the kernel and the diagnostics or other user code.
336 * They are all implemented such that 64 bit accesses work.
337 * Some implement no more than 32 bits. Because 64 bit reads
338 * require 2 HT cmds on opteron, we access those with 32 bit
339 * reads for efficiency (they are written as 64 bits, since
340 * the extra 32 bits are nearly free on writes, and it slightly reduces
341 * complexity). The rest are all accessed as 64 bits.
342 */
344 /* These are the 32 bit group */
345 ipath_kreg kr_control;
346 ipath_kreg kr_counterregbase;
347 ipath_kreg kr_intmask;
348 ipath_kreg kr_intstatus;
349 ipath_kreg kr_pagealign;
350 ipath_kreg kr_portcnt;
351 ipath_kreg kr_rcvtidbase;
352 ipath_kreg kr_rcvtidcnt;
353 ipath_kreg kr_rcvegrbase;
354 ipath_kreg kr_rcvegrcnt;
355 ipath_kreg kr_scratch;
356 ipath_kreg kr_sendctrl;
357 ipath_kreg kr_sendpiobufbase;
358 ipath_kreg kr_sendpiobufcnt;
359 ipath_kreg kr_sendpiosize;
360 ipath_kreg kr_sendregbase;
361 ipath_kreg kr_userregbase;
362 /* These are the 64 bit group */
363 ipath_kreg kr_debugport;
364 ipath_kreg kr_debugportselect;
365 ipath_kreg kr_errorclear;
366 ipath_kreg kr_errormask;
367 ipath_kreg kr_errorstatus;
368 ipath_kreg kr_extctrl;
369 ipath_kreg kr_extstatus;
370 ipath_kreg kr_gpio_clear;
371 ipath_kreg kr_gpio_mask;
372 ipath_kreg kr_gpio_out;
373 ipath_kreg kr_gpio_status;
374 ipath_kreg kr_hwdiagctrl;
375 ipath_kreg kr_hwerrclear;
376 ipath_kreg kr_hwerrmask;
377 ipath_kreg kr_hwerrstatus;
378 ipath_kreg kr_ibcctrl;
379 ipath_kreg kr_ibcstatus;
380 ipath_kreg kr_intblocked;
381 ipath_kreg kr_intclear;
382 ipath_kreg kr_interruptconfig;
383 ipath_kreg kr_mdio;
384 ipath_kreg kr_partitionkey;
385 ipath_kreg kr_rcvbthqp;
386 ipath_kreg kr_rcvbufbase;
387 ipath_kreg kr_rcvbufsize;
388 ipath_kreg kr_rcvctrl;
389 ipath_kreg kr_rcvhdrcnt;
390 ipath_kreg kr_rcvhdrentsize;
391 ipath_kreg kr_rcvhdrsize;
392 ipath_kreg kr_rcvintmembase;
393 ipath_kreg kr_rcvintmemsize;
394 ipath_kreg kr_revision;
395 ipath_kreg kr_sendbuffererror;
396 ipath_kreg kr_sendpioavailaddr;
397 ipath_kreg kr_serdesconfig0;
398 ipath_kreg kr_serdesconfig1;
399 ipath_kreg kr_serdesstatus;
400 ipath_kreg kr_txintmembase;
401 ipath_kreg kr_txintmemsize;
402 ipath_kreg kr_xgxsconfig;
403 ipath_kreg kr_ibpllcfg;
404 /* use these two (and the following N ports) only with
405 * ipath_k*_kreg64_port(); not *kreg64() */
406 ipath_kreg kr_rcvhdraddr;
407 ipath_kreg kr_rcvhdrtailaddr;
409 /* remaining registers are not present on all types of infinipath
410 chips */
411 ipath_kreg kr_rcvpktledcnt;
412 ipath_kreg kr_pcierbuftestreg0;
413 ipath_kreg kr_pcierbuftestreg1;
414 ipath_kreg kr_pcieq0serdesconfig0;
415 ipath_kreg kr_pcieq0serdesconfig1;
416 ipath_kreg kr_pcieq0serdesstatus;
417 ipath_kreg kr_pcieq1serdesconfig0;
418 ipath_kreg kr_pcieq1serdesconfig1;
419 ipath_kreg kr_pcieq1serdesstatus;
420 };
423 ipath_creg cr_badformatcnt;
424 ipath_creg cr_erricrccnt;
425 ipath_creg cr_errlinkcnt;
426 ipath_creg cr_errlpcrccnt;
427 ipath_creg cr_errpkey;
428 ipath_creg cr_errrcvflowctrlcnt;
429 ipath_creg cr_err_rlencnt;
430 ipath_creg cr_errslencnt;
431 ipath_creg cr_errtidfull;
432 ipath_creg cr_errtidvalid;
433 ipath_creg cr_errvcrccnt;
434 ipath_creg cr_ibstatuschange;
435 ipath_creg cr_intcnt;
436 ipath_creg cr_invalidrlencnt;
437 ipath_creg cr_invalidslencnt;
438 ipath_creg cr_lbflowstallcnt;
439 ipath_creg cr_iblinkdowncnt;
440 ipath_creg cr_iblinkerrrecovcnt;
441 ipath_creg cr_ibsymbolerrcnt;
442 ipath_creg cr_pktrcvcnt;
443 ipath_creg cr_pktrcvflowctrlcnt;
444 ipath_creg cr_pktsendcnt;
445 ipath_creg cr_pktsendflowcnt;
446 ipath_creg cr_portovflcnt;
447 ipath_creg cr_rcvebpcnt;
448 ipath_creg cr_rcvovflcnt;
449 ipath_creg cr_rxdroppktcnt;
450 ipath_creg cr_senddropped;
451 ipath_creg cr_sendstallcnt;
452 ipath_creg cr_sendunderruncnt;
453 ipath_creg cr_unsupvlcnt;
454 ipath_creg cr_wordrcvcnt;
455 ipath_creg cr_wordsendcnt;
456 ipath_creg cr_vl15droppedpktcnt;
457 ipath_creg cr_rxotherlocalphyerrcnt;
458 ipath_creg cr_excessbufferovflcnt;
459 ipath_creg cr_locallinkintegrityerrcnt;
460 ipath_creg cr_rxvlerrcnt;
461 ipath_creg cr_rxdlidfltrcnt;
462 ipath_creg cr_psstat;
463 ipath_creg cr_psstart;
464 ipath_creg cr_psinterval;
465 ipath_creg cr_psrcvdatacount;
466 ipath_creg cr_psrcvpktscount;
467 ipath_creg cr_psxmitdatacount;
468 ipath_creg cr_psxmitpktscount;
469 ipath_creg cr_psxmitwaitcount;
470 };