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iwlwifi: introduce host commands callbacks
[linux/fpc-iii.git] / drivers / infiniband / hw / mthca / mthca_qp.c
blobdb5595bbf7f08fb30e5993a301e063b2df21ee05
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 *
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 */
37
38 #include <linux/string.h>
39 #include <linux/slab.h>
40 #include <linux/sched.h>
41
42 #include <asm/io.h>
43
44 #include <rdma/ib_verbs.h>
45 #include <rdma/ib_cache.h>
46 #include <rdma/ib_pack.h>
47
48 #include "mthca_dev.h"
49 #include "mthca_cmd.h"
50 #include "mthca_memfree.h"
51 #include "mthca_wqe.h"
52
53 enum {
54 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
55 MTHCA_ACK_REQ_FREQ = 10,
56 MTHCA_FLIGHT_LIMIT = 9,
57 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
58 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
59 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
60 };
61
62 enum {
63 MTHCA_QP_STATE_RST = 0,
64 MTHCA_QP_STATE_INIT = 1,
65 MTHCA_QP_STATE_RTR = 2,
66 MTHCA_QP_STATE_RTS = 3,
67 MTHCA_QP_STATE_SQE = 4,
68 MTHCA_QP_STATE_SQD = 5,
69 MTHCA_QP_STATE_ERR = 6,
70 MTHCA_QP_STATE_DRAINING = 7
71 };
72
73 enum {
74 MTHCA_QP_ST_RC = 0x0,
75 MTHCA_QP_ST_UC = 0x1,
76 MTHCA_QP_ST_RD = 0x2,
77 MTHCA_QP_ST_UD = 0x3,
78 MTHCA_QP_ST_MLX = 0x7
79 };
80
81 enum {
82 MTHCA_QP_PM_MIGRATED = 0x3,
83 MTHCA_QP_PM_ARMED = 0x0,
84 MTHCA_QP_PM_REARM = 0x1
85 };
86
87 enum {
88 /* qp_context flags */
89 MTHCA_QP_BIT_DE = 1 << 8,
90 /* params1 */
91 MTHCA_QP_BIT_SRE = 1 << 15,
92 MTHCA_QP_BIT_SWE = 1 << 14,
93 MTHCA_QP_BIT_SAE = 1 << 13,
94 MTHCA_QP_BIT_SIC = 1 << 4,
95 MTHCA_QP_BIT_SSC = 1 << 3,
96 /* params2 */
97 MTHCA_QP_BIT_RRE = 1 << 15,
98 MTHCA_QP_BIT_RWE = 1 << 14,
99 MTHCA_QP_BIT_RAE = 1 << 13,
100 MTHCA_QP_BIT_RIC = 1 << 4,
101 MTHCA_QP_BIT_RSC = 1 << 3
102 };
103
104 enum {
105 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
106 };
107
108 struct mthca_qp_path {
109 __be32 port_pkey;
110 u8 rnr_retry;
111 u8 g_mylmc;
112 __be16 rlid;
113 u8 ackto;
114 u8 mgid_index;
115 u8 static_rate;
116 u8 hop_limit;
117 __be32 sl_tclass_flowlabel;
118 u8 rgid[16];
119 } __attribute__((packed));
120
121 struct mthca_qp_context {
122 __be32 flags;
123 __be32 tavor_sched_queue; /* Reserved on Arbel */
124 u8 mtu_msgmax;
125 u8 rq_size_stride; /* Reserved on Tavor */
126 u8 sq_size_stride; /* Reserved on Tavor */
127 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
128 __be32 usr_page;
129 __be32 local_qpn;
130 __be32 remote_qpn;
131 u32 reserved1[2];
132 struct mthca_qp_path pri_path;
133 struct mthca_qp_path alt_path;
134 __be32 rdd;
135 __be32 pd;
136 __be32 wqe_base;
137 __be32 wqe_lkey;
138 __be32 params1;
139 __be32 reserved2;
140 __be32 next_send_psn;
141 __be32 cqn_snd;
142 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
143 __be32 snd_db_index; /* (debugging only entries) */
144 __be32 last_acked_psn;
145 __be32 ssn;
146 __be32 params2;
147 __be32 rnr_nextrecvpsn;
148 __be32 ra_buff_indx;
149 __be32 cqn_rcv;
150 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
151 __be32 rcv_db_index; /* (debugging only entries) */
152 __be32 qkey;
153 __be32 srqn;
154 __be32 rmsn;
155 __be16 rq_wqe_counter; /* reserved on Tavor */
156 __be16 sq_wqe_counter; /* reserved on Tavor */
157 u32 reserved3[18];
158 } __attribute__((packed));
159
160 struct mthca_qp_param {
161 __be32 opt_param_mask;
162 u32 reserved1;
163 struct mthca_qp_context context;
164 u32 reserved2[62];
165 } __attribute__((packed));
166
167 enum {
168 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
169 MTHCA_QP_OPTPAR_RRE = 1 << 1,
170 MTHCA_QP_OPTPAR_RAE = 1 << 2,
171 MTHCA_QP_OPTPAR_RWE = 1 << 3,
172 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
173 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
174 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
175 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
176 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
177 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
178 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
179 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
180 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
181 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
182 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
183 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
184 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
185 };
186
187 static const u8 mthca_opcode[] = {
188 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
189 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
190 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
191 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
192 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
193 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
194 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
195 };
196
197 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
198 {
199 return qp->qpn >= dev->qp_table.sqp_start &&
200 qp->qpn <= dev->qp_table.sqp_start + 3;
201 }
202
203 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
204 {
205 return qp->qpn >= dev->qp_table.sqp_start &&
206 qp->qpn <= dev->qp_table.sqp_start + 1;
207 }
208
209 static void *get_recv_wqe(struct mthca_qp *qp, int n)
210 {
211 if (qp->is_direct)
212 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
213 else
214 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
215 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
216 }
217
218 static void *get_send_wqe(struct mthca_qp *qp, int n)
219 {
220 if (qp->is_direct)
221 return qp->queue.direct.buf + qp->send_wqe_offset +
222 (n << qp->sq.wqe_shift);
223 else
224 return qp->queue.page_list[(qp->send_wqe_offset +
225 (n << qp->sq.wqe_shift)) >>
226 PAGE_SHIFT].buf +
227 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
228 (PAGE_SIZE - 1));
229 }
230
231 static void mthca_wq_reset(struct mthca_wq *wq)
232 {
233 wq->next_ind = 0;
234 wq->last_comp = wq->max - 1;
235 wq->head = 0;
236 wq->tail = 0;
237 }
238
239 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
240 enum ib_event_type event_type)
241 {
242 struct mthca_qp *qp;
243 struct ib_event event;
244
245 spin_lock(&dev->qp_table.lock);
246 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
247 if (qp)
248 ++qp->refcount;
249 spin_unlock(&dev->qp_table.lock);
250
251 if (!qp) {
252 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
253 return;
254 }
255
256 if (event_type == IB_EVENT_PATH_MIG)
257 qp->port = qp->alt_port;
258
259 event.device = &dev->ib_dev;
260 event.event = event_type;
261 event.element.qp = &qp->ibqp;
262 if (qp->ibqp.event_handler)
263 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
264
265 spin_lock(&dev->qp_table.lock);
266 if (!--qp->refcount)
267 wake_up(&qp->wait);
268 spin_unlock(&dev->qp_table.lock);
269 }
270
271 static int to_mthca_state(enum ib_qp_state ib_state)
272 {
273 switch (ib_state) {
274 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
275 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
276 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
277 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
278 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
279 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
280 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
281 default: return -1;
282 }
283 }
284
285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
286
287 static int to_mthca_st(int transport)
288 {
289 switch (transport) {
290 case RC: return MTHCA_QP_ST_RC;
291 case UC: return MTHCA_QP_ST_UC;
292 case UD: return MTHCA_QP_ST_UD;
293 case RD: return MTHCA_QP_ST_RD;
294 case MLX: return MTHCA_QP_ST_MLX;
295 default: return -1;
296 }
297 }
298
299 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
300 int attr_mask)
301 {
302 if (attr_mask & IB_QP_PKEY_INDEX)
303 sqp->pkey_index = attr->pkey_index;
304 if (attr_mask & IB_QP_QKEY)
305 sqp->qkey = attr->qkey;
306 if (attr_mask & IB_QP_SQ_PSN)
307 sqp->send_psn = attr->sq_psn;
308 }
309
310 static void init_port(struct mthca_dev *dev, int port)
311 {
312 int err;
313 u8 status;
314 struct mthca_init_ib_param param;
315
316 memset(&param, 0, sizeof param);
317
318 param.port_width = dev->limits.port_width_cap;
319 param.vl_cap = dev->limits.vl_cap;
320 param.mtu_cap = dev->limits.mtu_cap;
321 param.gid_cap = dev->limits.gid_table_len;
322 param.pkey_cap = dev->limits.pkey_table_len;
323
324 err = mthca_INIT_IB(dev, &param, port, &status);
325 if (err)
326 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
327 if (status)
328 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
329 }
330
331 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
332 int attr_mask)
333 {
334 u8 dest_rd_atomic;
335 u32 access_flags;
336 u32 hw_access_flags = 0;
337
338 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
339 dest_rd_atomic = attr->max_dest_rd_atomic;
340 else
341 dest_rd_atomic = qp->resp_depth;
342
343 if (attr_mask & IB_QP_ACCESS_FLAGS)
344 access_flags = attr->qp_access_flags;
345 else
346 access_flags = qp->atomic_rd_en;
347
348 if (!dest_rd_atomic)
349 access_flags &= IB_ACCESS_REMOTE_WRITE;
350
351 if (access_flags & IB_ACCESS_REMOTE_READ)
352 hw_access_flags |= MTHCA_QP_BIT_RRE;
353 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
354 hw_access_flags |= MTHCA_QP_BIT_RAE;
355 if (access_flags & IB_ACCESS_REMOTE_WRITE)
356 hw_access_flags |= MTHCA_QP_BIT_RWE;
357
358 return cpu_to_be32(hw_access_flags);
359 }
360
361 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
362 {
363 switch (mthca_state) {
364 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
365 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
366 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
367 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
368 case MTHCA_QP_STATE_DRAINING:
369 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
370 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
371 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
372 default: return -1;
373 }
374 }
375
376 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
377 {
378 switch (mthca_mig_state) {
379 case 0: return IB_MIG_ARMED;
380 case 1: return IB_MIG_REARM;
381 case 3: return IB_MIG_MIGRATED;
382 default: return -1;
383 }
384 }
385
386 static int to_ib_qp_access_flags(int mthca_flags)
387 {
388 int ib_flags = 0;
389
390 if (mthca_flags & MTHCA_QP_BIT_RRE)
391 ib_flags |= IB_ACCESS_REMOTE_READ;
392 if (mthca_flags & MTHCA_QP_BIT_RWE)
393 ib_flags |= IB_ACCESS_REMOTE_WRITE;
394 if (mthca_flags & MTHCA_QP_BIT_RAE)
395 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
396
397 return ib_flags;
398 }
399
400 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
401 struct mthca_qp_path *path)
402 {
403 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
404 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
405
406 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
407 return;
408
409 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
410 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
411 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
412 ib_ah_attr->static_rate = mthca_rate_to_ib(dev,
413 path->static_rate & 0xf,
414 ib_ah_attr->port_num);
415 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
416 if (ib_ah_attr->ah_flags) {
417 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
418 ib_ah_attr->grh.hop_limit = path->hop_limit;
419 ib_ah_attr->grh.traffic_class =
420 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
421 ib_ah_attr->grh.flow_label =
422 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
423 memcpy(ib_ah_attr->grh.dgid.raw,
424 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
425 }
426 }
427
428 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
429 struct ib_qp_init_attr *qp_init_attr)
430 {
431 struct mthca_dev *dev = to_mdev(ibqp->device);
432 struct mthca_qp *qp = to_mqp(ibqp);
433 int err = 0;
434 struct mthca_mailbox *mailbox = NULL;
435 struct mthca_qp_param *qp_param;
436 struct mthca_qp_context *context;
437 int mthca_state;
438 u8 status;
439
440 if (qp->state == IB_QPS_RESET) {
441 qp_attr->qp_state = IB_QPS_RESET;
442 goto done;
443 }
444
445 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
446 if (IS_ERR(mailbox))
447 return PTR_ERR(mailbox);
448
449 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
450 if (err)
451 goto out;
452 if (status) {
453 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
454 err = -EINVAL;
455 goto out;
456 }
457
458 qp_param = mailbox->buf;
459 context = &qp_param->context;
460 mthca_state = be32_to_cpu(context->flags) >> 28;
461
462 qp_attr->qp_state = to_ib_qp_state(mthca_state);
463 qp_attr->path_mtu = context->mtu_msgmax >> 5;
464 qp_attr->path_mig_state =
465 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
466 qp_attr->qkey = be32_to_cpu(context->qkey);
467 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
468 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
469 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
470 qp_attr->qp_access_flags =
471 to_ib_qp_access_flags(be32_to_cpu(context->params2));
472
473 if (qp->transport == RC || qp->transport == UC) {
474 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
475 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
476 qp_attr->alt_pkey_index =
477 be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
478 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
479 }
480
481 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
482 qp_attr->port_num =
483 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
484
485 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
486 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
487
488 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
489
490 qp_attr->max_dest_rd_atomic =
491 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
492 qp_attr->min_rnr_timer =
493 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
494 qp_attr->timeout = context->pri_path.ackto >> 3;
495 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
496 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
497 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
498
499 done:
500 qp_attr->cur_qp_state = qp_attr->qp_state;
501 qp_attr->cap.max_send_wr = qp->sq.max;
502 qp_attr->cap.max_recv_wr = qp->rq.max;
503 qp_attr->cap.max_send_sge = qp->sq.max_gs;
504 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
505 qp_attr->cap.max_inline_data = qp->max_inline_data;
506
507 qp_init_attr->cap = qp_attr->cap;
508
509 out:
510 mthca_free_mailbox(dev, mailbox);
511 return err;
512 }
513
514 static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah,
515 struct mthca_qp_path *path, u8 port)
516 {
517 path->g_mylmc = ah->src_path_bits & 0x7f;
518 path->rlid = cpu_to_be16(ah->dlid);
519 path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
520
521 if (ah->ah_flags & IB_AH_GRH) {
522 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
523 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
524 ah->grh.sgid_index, dev->limits.gid_table_len-1);
525 return -1;
526 }
527
528 path->g_mylmc |= 1 << 7;
529 path->mgid_index = ah->grh.sgid_index;
530 path->hop_limit = ah->grh.hop_limit;
531 path->sl_tclass_flowlabel =
532 cpu_to_be32((ah->sl << 28) |
533 (ah->grh.traffic_class << 20) |
534 (ah->grh.flow_label));
535 memcpy(path->rgid, ah->grh.dgid.raw, 16);
536 } else
537 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
538
539 return 0;
540 }
541
542 static int __mthca_modify_qp(struct ib_qp *ibqp,
543 const struct ib_qp_attr *attr, int attr_mask,
544 enum ib_qp_state cur_state, enum ib_qp_state new_state)
545 {
546 struct mthca_dev *dev = to_mdev(ibqp->device);
547 struct mthca_qp *qp = to_mqp(ibqp);
548 struct mthca_mailbox *mailbox;
549 struct mthca_qp_param *qp_param;
550 struct mthca_qp_context *qp_context;
551 u32 sqd_event = 0;
552 u8 status;
553 int err = -EINVAL;
554
555 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
556 if (IS_ERR(mailbox)) {
557 err = PTR_ERR(mailbox);
558 goto out;
559 }
560 qp_param = mailbox->buf;
561 qp_context = &qp_param->context;
562 memset(qp_param, 0, sizeof *qp_param);
563
564 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
565 (to_mthca_st(qp->transport) << 16));
566 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
567 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
568 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
569 else {
570 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
571 switch (attr->path_mig_state) {
572 case IB_MIG_MIGRATED:
573 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
574 break;
575 case IB_MIG_REARM:
576 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
577 break;
578 case IB_MIG_ARMED:
579 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
580 break;
581 }
582 }
583
584 /* leave tavor_sched_queue as 0 */
585
586 if (qp->transport == MLX || qp->transport == UD)
587 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
588 else if (attr_mask & IB_QP_PATH_MTU) {
589 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
590 mthca_dbg(dev, "path MTU (%u) is invalid\n",
591 attr->path_mtu);
592 goto out_mailbox;
593 }
594 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
595 }
596
597 if (mthca_is_memfree(dev)) {
598 if (qp->rq.max)
599 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
600 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
601
602 if (qp->sq.max)
603 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
604 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
605 }
606
607 /* leave arbel_sched_queue as 0 */
608
609 if (qp->ibqp.uobject)
610 qp_context->usr_page =
611 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
612 else
613 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
614 qp_context->local_qpn = cpu_to_be32(qp->qpn);
615 if (attr_mask & IB_QP_DEST_QPN) {
616 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
617 }
618
619 if (qp->transport == MLX)
620 qp_context->pri_path.port_pkey |=
621 cpu_to_be32(qp->port << 24);
622 else {
623 if (attr_mask & IB_QP_PORT) {
624 qp_context->pri_path.port_pkey |=
625 cpu_to_be32(attr->port_num << 24);
626 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
627 }
628 }
629
630 if (attr_mask & IB_QP_PKEY_INDEX) {
631 qp_context->pri_path.port_pkey |=
632 cpu_to_be32(attr->pkey_index);
633 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
634 }
635
636 if (attr_mask & IB_QP_RNR_RETRY) {
637 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
638 attr->rnr_retry << 5;
639 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
640 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
641 }
642
643 if (attr_mask & IB_QP_AV) {
644 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
645 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
646 goto out_mailbox;
647
648 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
649 }
650
651 if (ibqp->qp_type == IB_QPT_RC &&
652 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
653 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
654
655 if (mthca_is_memfree(dev))
656 qp_context->rlkey_arbel_sched_queue |= sched_queue;
657 else
658 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
659
660 qp_param->opt_param_mask |=
661 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
662 }
663
664 if (attr_mask & IB_QP_TIMEOUT) {
665 qp_context->pri_path.ackto = attr->timeout << 3;
666 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
667 }
668
669 if (attr_mask & IB_QP_ALT_PATH) {
670 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
671 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
672 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
673 goto out_mailbox;
674 }
675
676 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
677 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
678 attr->alt_port_num);
679 goto out_mailbox;
680 }
681
682 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
683 attr->alt_ah_attr.port_num))
684 goto out_mailbox;
685
686 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
687 attr->alt_port_num << 24);
688 qp_context->alt_path.ackto = attr->alt_timeout << 3;
689 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
690 }
691
692 /* leave rdd as 0 */
693 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
694 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
695 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
696 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
697 (MTHCA_FLIGHT_LIMIT << 24) |
698 MTHCA_QP_BIT_SWE);
699 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
700 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
701 if (attr_mask & IB_QP_RETRY_CNT) {
702 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
703 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
704 }
705
706 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
707 if (attr->max_rd_atomic) {
708 qp_context->params1 |=
709 cpu_to_be32(MTHCA_QP_BIT_SRE |
710 MTHCA_QP_BIT_SAE);
711 qp_context->params1 |=
712 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
713 }
714 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
715 }
716
717 if (attr_mask & IB_QP_SQ_PSN)
718 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
719 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
720
721 if (mthca_is_memfree(dev)) {
722 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
723 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
724 }
725
726 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
727 if (attr->max_dest_rd_atomic)
728 qp_context->params2 |=
729 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
730
731 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
732 }
733
734 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
735 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
736 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
737 MTHCA_QP_OPTPAR_RRE |
738 MTHCA_QP_OPTPAR_RAE);
739 }
740
741 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
742
743 if (ibqp->srq)
744 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
745
746 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
747 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
748 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
749 }
750 if (attr_mask & IB_QP_RQ_PSN)
751 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
752
753 qp_context->ra_buff_indx =
754 cpu_to_be32(dev->qp_table.rdb_base +
755 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
756 dev->qp_table.rdb_shift));
757
758 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
759
760 if (mthca_is_memfree(dev))
761 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
762
763 if (attr_mask & IB_QP_QKEY) {
764 qp_context->qkey = cpu_to_be32(attr->qkey);
765 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
766 }
767
768 if (ibqp->srq)
769 qp_context->srqn = cpu_to_be32(1 << 24 |
770 to_msrq(ibqp->srq)->srqn);
771
772 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
773 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
774 attr->en_sqd_async_notify)
775 sqd_event = 1 << 31;
776
777 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
778 mailbox, sqd_event, &status);
779 if (err)
780 goto out_mailbox;
781 if (status) {
782 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
783 cur_state, new_state, status);
784 err = -EINVAL;
785 goto out_mailbox;
786 }
787
788 qp->state = new_state;
789 if (attr_mask & IB_QP_ACCESS_FLAGS)
790 qp->atomic_rd_en = attr->qp_access_flags;
791 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
792 qp->resp_depth = attr->max_dest_rd_atomic;
793 if (attr_mask & IB_QP_PORT)
794 qp->port = attr->port_num;
795 if (attr_mask & IB_QP_ALT_PATH)
796 qp->alt_port = attr->alt_port_num;
797
798 if (is_sqp(dev, qp))
799 store_attrs(to_msqp(qp), attr, attr_mask);
800
801 /*
802 * If we moved QP0 to RTR, bring the IB link up; if we moved
803 * QP0 to RESET or ERROR, bring the link back down.
804 */
805 if (is_qp0(dev, qp)) {
806 if (cur_state != IB_QPS_RTR &&
807 new_state == IB_QPS_RTR)
808 init_port(dev, qp->port);
809
810 if (cur_state != IB_QPS_RESET &&
811 cur_state != IB_QPS_ERR &&
812 (new_state == IB_QPS_RESET ||
813 new_state == IB_QPS_ERR))
814 mthca_CLOSE_IB(dev, qp->port, &status);
815 }
816
817 /*
818 * If we moved a kernel QP to RESET, clean up all old CQ
819 * entries and reinitialize the QP.
820 */
821 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
822 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
823 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
824 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
825 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
826
827 mthca_wq_reset(&qp->sq);
828 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
829
830 mthca_wq_reset(&qp->rq);
831 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
832
833 if (mthca_is_memfree(dev)) {
834 *qp->sq.db = 0;
835 *qp->rq.db = 0;
836 }
837 }
838
839 out_mailbox:
840 mthca_free_mailbox(dev, mailbox);
841 out:
842 return err;
843 }
844
845 static const struct ib_qp_attr dummy_init_attr = { .port_num = 1 };
846 static const int dummy_init_attr_mask[] = {
847 [IB_QPT_UD] = (IB_QP_PKEY_INDEX |
848 IB_QP_PORT |
849 IB_QP_QKEY),
850 [IB_QPT_UC] = (IB_QP_PKEY_INDEX |
851 IB_QP_PORT |
852 IB_QP_ACCESS_FLAGS),
853 [IB_QPT_RC] = (IB_QP_PKEY_INDEX |
854 IB_QP_PORT |
855 IB_QP_ACCESS_FLAGS),
856 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX |
857 IB_QP_QKEY),
858 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX |
859 IB_QP_QKEY),
860 };
861
862 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
863 struct ib_udata *udata)
864 {
865 struct mthca_dev *dev = to_mdev(ibqp->device);
866 struct mthca_qp *qp = to_mqp(ibqp);
867 enum ib_qp_state cur_state, new_state;
868 int err = -EINVAL;
869
870 mutex_lock(&qp->mutex);
871 if (attr_mask & IB_QP_CUR_STATE) {
872 cur_state = attr->cur_qp_state;
873 } else {
874 spin_lock_irq(&qp->sq.lock);
875 spin_lock(&qp->rq.lock);
876 cur_state = qp->state;
877 spin_unlock(&qp->rq.lock);
878 spin_unlock_irq(&qp->sq.lock);
879 }
880
881 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
882
883 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
884 mthca_dbg(dev, "Bad QP transition (transport %d) "
885 "%d->%d with attr 0x%08x\n",
886 qp->transport, cur_state, new_state,
887 attr_mask);
888 goto out;
889 }
890
891 if ((attr_mask & IB_QP_PKEY_INDEX) &&
892 attr->pkey_index >= dev->limits.pkey_table_len) {
893 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
894 attr->pkey_index, dev->limits.pkey_table_len-1);
895 goto out;
896 }
897
898 if ((attr_mask & IB_QP_PORT) &&
899 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
900 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
901 goto out;
902 }
903
904 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
905 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
906 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
907 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
908 goto out;
909 }
910
911 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
912 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
913 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
914 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
915 goto out;
916 }
917
918 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
919 err = 0;
920 goto out;
921 }
922
923 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
924 err = __mthca_modify_qp(ibqp, &dummy_init_attr,
925 dummy_init_attr_mask[ibqp->qp_type],
926 IB_QPS_RESET, IB_QPS_INIT);
927 if (err)
928 goto out;
929 cur_state = IB_QPS_INIT;
930 }
931
932 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
933
934 out:
935 mutex_unlock(&qp->mutex);
936 return err;
937 }
938
939 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
940 {
941 /*
942 * Calculate the maximum size of WQE s/g segments, excluding
943 * the next segment and other non-data segments.
944 */
945 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
946
947 switch (qp->transport) {
948 case MLX:
949 max_data_size -= 2 * sizeof (struct mthca_data_seg);
950 break;
951
952 case UD:
953 if (mthca_is_memfree(dev))
954 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
955 else
956 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
957 break;
958
959 default:
960 max_data_size -= sizeof (struct mthca_raddr_seg);
961 break;
962 }
963
964 return max_data_size;
965 }
966
967 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
968 {
969 /* We don't support inline data for kernel QPs (yet). */
970 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
971 }
972
973 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
974 struct mthca_pd *pd,
975 struct mthca_qp *qp)
976 {
977 int max_data_size = mthca_max_data_size(dev, qp,
978 min(dev->limits.max_desc_sz,
979 1 << qp->sq.wqe_shift));
980
981 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
982
983 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
984 max_data_size / sizeof (struct mthca_data_seg));
985 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
986 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
987 sizeof (struct mthca_next_seg)) /
988 sizeof (struct mthca_data_seg));
989 }
990
991 /*
992 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
993 * rq.max_gs and sq.max_gs must all be assigned.
994 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
995 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
996 * queue)
997 */
998 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
999 struct mthca_pd *pd,
1000 struct mthca_qp *qp)
1001 {
1002 int size;
1003 int err = -ENOMEM;
1004
1005 size = sizeof (struct mthca_next_seg) +
1006 qp->rq.max_gs * sizeof (struct mthca_data_seg);
1007
1008 if (size > dev->limits.max_desc_sz)
1009 return -EINVAL;
1010
1011 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
1012 qp->rq.wqe_shift++)
1013 ; /* nothing */
1014
1015 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1016 switch (qp->transport) {
1017 case MLX:
1018 size += 2 * sizeof (struct mthca_data_seg);
1019 break;
1020
1021 case UD:
1022 size += mthca_is_memfree(dev) ?
1023 sizeof (struct mthca_arbel_ud_seg) :
1024 sizeof (struct mthca_tavor_ud_seg);
1025 break;
1026
1027 case UC:
1028 size += sizeof (struct mthca_raddr_seg);
1029 break;
1030
1031 case RC:
1032 size += sizeof (struct mthca_raddr_seg);
1033 /*
1034 * An atomic op will require an atomic segment, a
1035 * remote address segment and one scatter entry.
1036 */
1037 size = max_t(int, size,
1038 sizeof (struct mthca_atomic_seg) +
1039 sizeof (struct mthca_raddr_seg) +
1040 sizeof (struct mthca_data_seg));
1041 break;
1042
1043 default:
1044 break;
1045 }
1046
1047 /* Make sure that we have enough space for a bind request */
1048 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1049
1050 size += sizeof (struct mthca_next_seg);
1051
1052 if (size > dev->limits.max_desc_sz)
1053 return -EINVAL;
1054
1055 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1056 qp->sq.wqe_shift++)
1057 ; /* nothing */
1058
1059 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1060 1 << qp->sq.wqe_shift);
1061
1062 /*
1063 * If this is a userspace QP, we don't actually have to
1064 * allocate anything. All we need is to calculate the WQE
1065 * sizes and the send_wqe_offset, so we're done now.
1066 */
1067 if (pd->ibpd.uobject)
1068 return 0;
1069
1070 size = PAGE_ALIGN(qp->send_wqe_offset +
1071 (qp->sq.max << qp->sq.wqe_shift));
1072
1073 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1074 GFP_KERNEL);
1075 if (!qp->wrid)
1076 goto err_out;
1077
1078 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1079 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1080 if (err)
1081 goto err_out;
1082
1083 return 0;
1084
1085 err_out:
1086 kfree(qp->wrid);
1087 return err;
1088 }
1089
1090 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1091 struct mthca_qp *qp)
1092 {
1093 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1094 (qp->sq.max << qp->sq.wqe_shift)),
1095 &qp->queue, qp->is_direct, &qp->mr);
1096 kfree(qp->wrid);
1097 }
1098
1099 static int mthca_map_memfree(struct mthca_dev *dev,
1100 struct mthca_qp *qp)
1101 {
1102 int ret;
1103
1104 if (mthca_is_memfree(dev)) {
1105 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1106 if (ret)
1107 return ret;
1108
1109 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1110 if (ret)
1111 goto err_qpc;
1112
1113 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1114 qp->qpn << dev->qp_table.rdb_shift);
1115 if (ret)
1116 goto err_eqpc;
1117
1118 }
1119
1120 return 0;
1121
1122 err_eqpc:
1123 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1124
1125 err_qpc:
1126 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1127
1128 return ret;
1129 }
1130
1131 static void mthca_unmap_memfree(struct mthca_dev *dev,
1132 struct mthca_qp *qp)
1133 {
1134 mthca_table_put(dev, dev->qp_table.rdb_table,
1135 qp->qpn << dev->qp_table.rdb_shift);
1136 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1137 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1138 }
1139
1140 static int mthca_alloc_memfree(struct mthca_dev *dev,
1141 struct mthca_qp *qp)
1142 {
1143 if (mthca_is_memfree(dev)) {
1144 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1145 qp->qpn, &qp->rq.db);
1146 if (qp->rq.db_index < 0)
1147 return -ENOMEM;
1148
1149 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1150 qp->qpn, &qp->sq.db);
1151 if (qp->sq.db_index < 0) {
1152 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1153 return -ENOMEM;
1154 }
1155 }
1156
1157 return 0;
1158 }
1159
1160 static void mthca_free_memfree(struct mthca_dev *dev,
1161 struct mthca_qp *qp)
1162 {
1163 if (mthca_is_memfree(dev)) {
1164 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1165 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1166 }
1167 }
1168
1169 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1170 struct mthca_pd *pd,
1171 struct mthca_cq *send_cq,
1172 struct mthca_cq *recv_cq,
1173 enum ib_sig_type send_policy,
1174 struct mthca_qp *qp)
1175 {
1176 int ret;
1177 int i;
1178 struct mthca_next_seg *next;
1179
1180 qp->refcount = 1;
1181 init_waitqueue_head(&qp->wait);
1182 mutex_init(&qp->mutex);
1183 qp->state = IB_QPS_RESET;
1184 qp->atomic_rd_en = 0;
1185 qp->resp_depth = 0;
1186 qp->sq_policy = send_policy;
1187 mthca_wq_reset(&qp->sq);
1188 mthca_wq_reset(&qp->rq);
1189
1190 spin_lock_init(&qp->sq.lock);
1191 spin_lock_init(&qp->rq.lock);
1192
1193 ret = mthca_map_memfree(dev, qp);
1194 if (ret)
1195 return ret;
1196
1197 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1198 if (ret) {
1199 mthca_unmap_memfree(dev, qp);
1200 return ret;
1201 }
1202
1203 mthca_adjust_qp_caps(dev, pd, qp);
1204
1205 /*
1206 * If this is a userspace QP, we're done now. The doorbells
1207 * will be allocated and buffers will be initialized in
1208 * userspace.
1209 */
1210 if (pd->ibpd.uobject)
1211 return 0;
1212
1213 ret = mthca_alloc_memfree(dev, qp);
1214 if (ret) {
1215 mthca_free_wqe_buf(dev, qp);
1216 mthca_unmap_memfree(dev, qp);
1217 return ret;
1218 }
1219
1220 if (mthca_is_memfree(dev)) {
1221 struct mthca_data_seg *scatter;
1222 int size = (sizeof (struct mthca_next_seg) +
1223 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1224
1225 for (i = 0; i < qp->rq.max; ++i) {
1226 next = get_recv_wqe(qp, i);
1227 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1228 qp->rq.wqe_shift);
1229 next->ee_nds = cpu_to_be32(size);
1230
1231 for (scatter = (void *) (next + 1);
1232 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1233 ++scatter)
1234 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1235 }
1236
1237 for (i = 0; i < qp->sq.max; ++i) {
1238 next = get_send_wqe(qp, i);
1239 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1240 qp->sq.wqe_shift) +
1241 qp->send_wqe_offset);
1242 }
1243 } else {
1244 for (i = 0; i < qp->rq.max; ++i) {
1245 next = get_recv_wqe(qp, i);
1246 next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1247 qp->rq.wqe_shift) | 1);
1248 }
1249
1250 }
1251
1252 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1253 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1254
1255 return 0;
1256 }
1257
1258 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1259 struct mthca_pd *pd, struct mthca_qp *qp)
1260 {
1261 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1262
1263 /* Sanity check QP size before proceeding */
1264 if (cap->max_send_wr > dev->limits.max_wqes ||
1265 cap->max_recv_wr > dev->limits.max_wqes ||
1266 cap->max_send_sge > dev->limits.max_sg ||
1267 cap->max_recv_sge > dev->limits.max_sg ||
1268 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1269 return -EINVAL;
1270
1271 /*
1272 * For MLX transport we need 2 extra S/G entries:
1273 * one for the header and one for the checksum at the end
1274 */
1275 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1276 return -EINVAL;
1277
1278 if (mthca_is_memfree(dev)) {
1279 qp->rq.max = cap->max_recv_wr ?
1280 roundup_pow_of_two(cap->max_recv_wr) : 0;
1281 qp->sq.max = cap->max_send_wr ?
1282 roundup_pow_of_two(cap->max_send_wr) : 0;
1283 } else {
1284 qp->rq.max = cap->max_recv_wr;
1285 qp->sq.max = cap->max_send_wr;
1286 }
1287
1288 qp->rq.max_gs = cap->max_recv_sge;
1289 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1290 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1291 MTHCA_INLINE_CHUNK_SIZE) /
1292 sizeof (struct mthca_data_seg));
1293
1294 return 0;
1295 }
1296
1297 int mthca_alloc_qp(struct mthca_dev *dev,
1298 struct mthca_pd *pd,
1299 struct mthca_cq *send_cq,
1300 struct mthca_cq *recv_cq,
1301 enum ib_qp_type type,
1302 enum ib_sig_type send_policy,
1303 struct ib_qp_cap *cap,
1304 struct mthca_qp *qp)
1305 {
1306 int err;
1307
1308 switch (type) {
1309 case IB_QPT_RC: qp->transport = RC; break;
1310 case IB_QPT_UC: qp->transport = UC; break;
1311 case IB_QPT_UD: qp->transport = UD; break;
1312 default: return -EINVAL;
1313 }
1314
1315 err = mthca_set_qp_size(dev, cap, pd, qp);
1316 if (err)
1317 return err;
1318
1319 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1320 if (qp->qpn == -1)
1321 return -ENOMEM;
1322
1323 /* initialize port to zero for error-catching. */
1324 qp->port = 0;
1325
1326 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1327 send_policy, qp);
1328 if (err) {
1329 mthca_free(&dev->qp_table.alloc, qp->qpn);
1330 return err;
1331 }
1332
1333 spin_lock_irq(&dev->qp_table.lock);
1334 mthca_array_set(&dev->qp_table.qp,
1335 qp->qpn & (dev->limits.num_qps - 1), qp);
1336 spin_unlock_irq(&dev->qp_table.lock);
1337
1338 return 0;
1339 }
1340
1341 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1342 {
1343 if (send_cq == recv_cq)
1344 spin_lock_irq(&send_cq->lock);
1345 else if (send_cq->cqn < recv_cq->cqn) {
1346 spin_lock_irq(&send_cq->lock);
1347 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1348 } else {
1349 spin_lock_irq(&recv_cq->lock);
1350 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1351 }
1352 }
1353
1354 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1355 {
1356 if (send_cq == recv_cq)
1357 spin_unlock_irq(&send_cq->lock);
1358 else if (send_cq->cqn < recv_cq->cqn) {
1359 spin_unlock(&recv_cq->lock);
1360 spin_unlock_irq(&send_cq->lock);
1361 } else {
1362 spin_unlock(&send_cq->lock);
1363 spin_unlock_irq(&recv_cq->lock);
1364 }
1365 }
1366
1367 int mthca_alloc_sqp(struct mthca_dev *dev,
1368 struct mthca_pd *pd,
1369 struct mthca_cq *send_cq,
1370 struct mthca_cq *recv_cq,
1371 enum ib_sig_type send_policy,
1372 struct ib_qp_cap *cap,
1373 int qpn,
1374 int port,
1375 struct mthca_sqp *sqp)
1376 {
1377 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1378 int err;
1379
1380 sqp->qp.transport = MLX;
1381 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1382 if (err)
1383 return err;
1384
1385 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1386 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1387 &sqp->header_dma, GFP_KERNEL);
1388 if (!sqp->header_buf)
1389 return -ENOMEM;
1390
1391 spin_lock_irq(&dev->qp_table.lock);
1392 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1393 err = -EBUSY;
1394 else
1395 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1396 spin_unlock_irq(&dev->qp_table.lock);
1397
1398 if (err)
1399 goto err_out;
1400
1401 sqp->qp.port = port;
1402 sqp->qp.qpn = mqpn;
1403 sqp->qp.transport = MLX;
1404
1405 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1406 send_policy, &sqp->qp);
1407 if (err)
1408 goto err_out_free;
1409
1410 atomic_inc(&pd->sqp_count);
1411
1412 return 0;
1413
1414 err_out_free:
1415 /*
1416 * Lock CQs here, so that CQ polling code can do QP lookup
1417 * without taking a lock.
1418 */
1419 mthca_lock_cqs(send_cq, recv_cq);
1420
1421 spin_lock(&dev->qp_table.lock);
1422 mthca_array_clear(&dev->qp_table.qp, mqpn);
1423 spin_unlock(&dev->qp_table.lock);
1424
1425 mthca_unlock_cqs(send_cq, recv_cq);
1426
1427 err_out:
1428 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1429 sqp->header_buf, sqp->header_dma);
1430
1431 return err;
1432 }
1433
1434 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1435 {
1436 int c;
1437
1438 spin_lock_irq(&dev->qp_table.lock);
1439 c = qp->refcount;
1440 spin_unlock_irq(&dev->qp_table.lock);
1441
1442 return c;
1443 }
1444
1445 void mthca_free_qp(struct mthca_dev *dev,
1446 struct mthca_qp *qp)
1447 {
1448 u8 status;
1449 struct mthca_cq *send_cq;
1450 struct mthca_cq *recv_cq;
1451
1452 send_cq = to_mcq(qp->ibqp.send_cq);
1453 recv_cq = to_mcq(qp->ibqp.recv_cq);
1454
1455 /*
1456 * Lock CQs here, so that CQ polling code can do QP lookup
1457 * without taking a lock.
1458 */
1459 mthca_lock_cqs(send_cq, recv_cq);
1460
1461 spin_lock(&dev->qp_table.lock);
1462 mthca_array_clear(&dev->qp_table.qp,
1463 qp->qpn & (dev->limits.num_qps - 1));
1464 --qp->refcount;
1465 spin_unlock(&dev->qp_table.lock);
1466
1467 mthca_unlock_cqs(send_cq, recv_cq);
1468
1469 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1470
1471 if (qp->state != IB_QPS_RESET)
1472 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1473 NULL, 0, &status);
1474
1475 /*
1476 * If this is a userspace QP, the buffers, MR, CQs and so on
1477 * will be cleaned up in userspace, so all we have to do is
1478 * unref the mem-free tables and free the QPN in our table.
1479 */
1480 if (!qp->ibqp.uobject) {
1481 mthca_cq_clean(dev, recv_cq, qp->qpn,
1482 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1483 if (send_cq != recv_cq)
1484 mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1485
1486 mthca_free_memfree(dev, qp);
1487 mthca_free_wqe_buf(dev, qp);
1488 }
1489
1490 mthca_unmap_memfree(dev, qp);
1491
1492 if (is_sqp(dev, qp)) {
1493 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1494 dma_free_coherent(&dev->pdev->dev,
1495 to_msqp(qp)->header_buf_size,
1496 to_msqp(qp)->header_buf,
1497 to_msqp(qp)->header_dma);
1498 } else
1499 mthca_free(&dev->qp_table.alloc, qp->qpn);
1500 }
1501
1502 /* Create UD header for an MLX send and build a data segment for it */
1503 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1504 int ind, struct ib_send_wr *wr,
1505 struct mthca_mlx_seg *mlx,
1506 struct mthca_data_seg *data)
1507 {
1508 int header_size;
1509 int err;
1510 u16 pkey;
1511
1512 ib_ud_header_init(256, /* assume a MAD */
1513 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1514 &sqp->ud_header);
1515
1516 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1517 if (err)
1518 return err;
1519 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1520 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1521 (sqp->ud_header.lrh.destination_lid ==
1522 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1523 (sqp->ud_header.lrh.service_level << 8));
1524 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1525 mlx->vcrc = 0;
1526
1527 switch (wr->opcode) {
1528 case IB_WR_SEND:
1529 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1530 sqp->ud_header.immediate_present = 0;
1531 break;
1532 case IB_WR_SEND_WITH_IMM:
1533 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1534 sqp->ud_header.immediate_present = 1;
1535 sqp->ud_header.immediate_data = wr->imm_data;
1536 break;
1537 default:
1538 return -EINVAL;
1539 }
1540
1541 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1542 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1543 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1544 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1545 if (!sqp->qp.ibqp.qp_num)
1546 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1547 sqp->pkey_index, &pkey);
1548 else
1549 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1550 wr->wr.ud.pkey_index, &pkey);
1551 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1552 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1553 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1554 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1555 sqp->qkey : wr->wr.ud.remote_qkey);
1556 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1557
1558 header_size = ib_ud_header_pack(&sqp->ud_header,
1559 sqp->header_buf +
1560 ind * MTHCA_UD_HEADER_SIZE);
1561
1562 data->byte_count = cpu_to_be32(header_size);
1563 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1564 data->addr = cpu_to_be64(sqp->header_dma +
1565 ind * MTHCA_UD_HEADER_SIZE);
1566
1567 return 0;
1568 }
1569
1570 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1571 struct ib_cq *ib_cq)
1572 {
1573 unsigned cur;
1574 struct mthca_cq *cq;
1575
1576 cur = wq->head - wq->tail;
1577 if (likely(cur + nreq < wq->max))
1578 return 0;
1579
1580 cq = to_mcq(ib_cq);
1581 spin_lock(&cq->lock);
1582 cur = wq->head - wq->tail;
1583 spin_unlock(&cq->lock);
1584
1585 return cur + nreq >= wq->max;
1586 }
1587
1588 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1589 u64 remote_addr, u32 rkey)
1590 {
1591 rseg->raddr = cpu_to_be64(remote_addr);
1592 rseg->rkey = cpu_to_be32(rkey);
1593 rseg->reserved = 0;
1594 }
1595
1596 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1597 struct ib_send_wr *wr)
1598 {
1599 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1600 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1601 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1602 } else {
1603 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1604 aseg->compare = 0;
1605 }
1606
1607 }
1608
1609 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1610 struct ib_send_wr *wr)
1611 {
1612 useg->lkey = cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1613 useg->av_addr = cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1614 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1615 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1616
1617 }
1618
1619 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1620 struct ib_send_wr *wr)
1621 {
1622 memcpy(useg->av, to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1623 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1624 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1625 }
1626
1627 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1628 struct ib_send_wr **bad_wr)
1629 {
1630 struct mthca_dev *dev = to_mdev(ibqp->device);
1631 struct mthca_qp *qp = to_mqp(ibqp);
1632 void *wqe;
1633 void *prev_wqe;
1634 unsigned long flags;
1635 int err = 0;
1636 int nreq;
1637 int i;
1638 int size;
1639 /*
1640 * f0 and size0 are only used if nreq != 0, and they will
1641 * always be initialized the first time through the main loop
1642 * before nreq is incremented. So nreq cannot become non-zero
1643 * without initializing f0 and size0, and they are in fact
1644 * never used uninitialized.
1645 */
1646 int uninitialized_var(size0);
1647 u32 uninitialized_var(f0);
1648 int ind;
1649 u8 op0 = 0;
1650
1651 spin_lock_irqsave(&qp->sq.lock, flags);
1652
1653 /* XXX check that state is OK to post send */
1654
1655 ind = qp->sq.next_ind;
1656
1657 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1658 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1659 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1660 " %d max, %d nreq)\n", qp->qpn,
1661 qp->sq.head, qp->sq.tail,
1662 qp->sq.max, nreq);
1663 err = -ENOMEM;
1664 *bad_wr = wr;
1665 goto out;
1666 }
1667
1668 wqe = get_send_wqe(qp, ind);
1669 prev_wqe = qp->sq.last;
1670 qp->sq.last = wqe;
1671
1672 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1673 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1674 ((struct mthca_next_seg *) wqe)->flags =
1675 ((wr->send_flags & IB_SEND_SIGNALED) ?
1676 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1677 ((wr->send_flags & IB_SEND_SOLICITED) ?
1678 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1679 cpu_to_be32(1);
1680 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1681 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1682 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1683
1684 wqe += sizeof (struct mthca_next_seg);
1685 size = sizeof (struct mthca_next_seg) / 16;
1686
1687 switch (qp->transport) {
1688 case RC:
1689 switch (wr->opcode) {
1690 case IB_WR_ATOMIC_CMP_AND_SWP:
1691 case IB_WR_ATOMIC_FETCH_AND_ADD:
1692 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1693 wr->wr.atomic.rkey);
1694 wqe += sizeof (struct mthca_raddr_seg);
1695
1696 set_atomic_seg(wqe, wr);
1697 wqe += sizeof (struct mthca_atomic_seg);
1698 size += (sizeof (struct mthca_raddr_seg) +
1699 sizeof (struct mthca_atomic_seg)) / 16;
1700 break;
1701
1702 case IB_WR_RDMA_WRITE:
1703 case IB_WR_RDMA_WRITE_WITH_IMM:
1704 case IB_WR_RDMA_READ:
1705 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1706 wr->wr.rdma.rkey);
1707 wqe += sizeof (struct mthca_raddr_seg);
1708 size += sizeof (struct mthca_raddr_seg) / 16;
1709 break;
1710
1711 default:
1712 /* No extra segments required for sends */
1713 break;
1714 }
1715
1716 break;
1717
1718 case UC:
1719 switch (wr->opcode) {
1720 case IB_WR_RDMA_WRITE:
1721 case IB_WR_RDMA_WRITE_WITH_IMM:
1722 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1723 wr->wr.rdma.rkey);
1724 wqe += sizeof (struct mthca_raddr_seg);
1725 size += sizeof (struct mthca_raddr_seg) / 16;
1726 break;
1727
1728 default:
1729 /* No extra segments required for sends */
1730 break;
1731 }
1732
1733 break;
1734
1735 case UD:
1736 set_tavor_ud_seg(wqe, wr);
1737 wqe += sizeof (struct mthca_tavor_ud_seg);
1738 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1739 break;
1740
1741 case MLX:
1742 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1743 wqe - sizeof (struct mthca_next_seg),
1744 wqe);
1745 if (err) {
1746 *bad_wr = wr;
1747 goto out;
1748 }
1749 wqe += sizeof (struct mthca_data_seg);
1750 size += sizeof (struct mthca_data_seg) / 16;
1751 break;
1752 }
1753
1754 if (wr->num_sge > qp->sq.max_gs) {
1755 mthca_err(dev, "too many gathers\n");
1756 err = -EINVAL;
1757 *bad_wr = wr;
1758 goto out;
1759 }
1760
1761 for (i = 0; i < wr->num_sge; ++i) {
1762 mthca_set_data_seg(wqe, wr->sg_list + i);
1763 wqe += sizeof (struct mthca_data_seg);
1764 size += sizeof (struct mthca_data_seg) / 16;
1765 }
1766
1767 /* Add one more inline data segment for ICRC */
1768 if (qp->transport == MLX) {
1769 ((struct mthca_data_seg *) wqe)->byte_count =
1770 cpu_to_be32((1 << 31) | 4);
1771 ((u32 *) wqe)[1] = 0;
1772 wqe += sizeof (struct mthca_data_seg);
1773 size += sizeof (struct mthca_data_seg) / 16;
1774 }
1775
1776 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1777
1778 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1779 mthca_err(dev, "opcode invalid\n");
1780 err = -EINVAL;
1781 *bad_wr = wr;
1782 goto out;
1783 }
1784
1785 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1786 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1787 qp->send_wqe_offset) |
1788 mthca_opcode[wr->opcode]);
1789 wmb();
1790 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1791 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1792 ((wr->send_flags & IB_SEND_FENCE) ?
1793 MTHCA_NEXT_FENCE : 0));
1794
1795 if (!nreq) {
1796 size0 = size;
1797 op0 = mthca_opcode[wr->opcode];
1798 f0 = wr->send_flags & IB_SEND_FENCE ?
1799 MTHCA_SEND_DOORBELL_FENCE : 0;
1800 }
1801
1802 ++ind;
1803 if (unlikely(ind >= qp->sq.max))
1804 ind -= qp->sq.max;
1805 }
1806
1807 out:
1808 if (likely(nreq)) {
1809 wmb();
1810
1811 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1812 qp->send_wqe_offset) | f0 | op0,
1813 (qp->qpn << 8) | size0,
1814 dev->kar + MTHCA_SEND_DOORBELL,
1815 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1816 /*
1817 * Make sure doorbells don't leak out of SQ spinlock
1818 * and reach the HCA out of order:
1819 */
1820 mmiowb();
1821 }
1822
1823 qp->sq.next_ind = ind;
1824 qp->sq.head += nreq;
1825
1826 spin_unlock_irqrestore(&qp->sq.lock, flags);
1827 return err;
1828 }
1829
1830 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1831 struct ib_recv_wr **bad_wr)
1832 {
1833 struct mthca_dev *dev = to_mdev(ibqp->device);
1834 struct mthca_qp *qp = to_mqp(ibqp);
1835 unsigned long flags;
1836 int err = 0;
1837 int nreq;
1838 int i;
1839 int size;
1840 /*
1841 * size0 is only used if nreq != 0, and it will always be
1842 * initialized the first time through the main loop before
1843 * nreq is incremented. So nreq cannot become non-zero
1844 * without initializing size0, and it is in fact never used
1845 * uninitialized.
1846 */
1847 int uninitialized_var(size0);
1848 int ind;
1849 void *wqe;
1850 void *prev_wqe;
1851
1852 spin_lock_irqsave(&qp->rq.lock, flags);
1853
1854 /* XXX check that state is OK to post receive */
1855
1856 ind = qp->rq.next_ind;
1857
1858 for (nreq = 0; wr; wr = wr->next) {
1859 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1860 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1861 " %d max, %d nreq)\n", qp->qpn,
1862 qp->rq.head, qp->rq.tail,
1863 qp->rq.max, nreq);
1864 err = -ENOMEM;
1865 *bad_wr = wr;
1866 goto out;
1867 }
1868
1869 wqe = get_recv_wqe(qp, ind);
1870 prev_wqe = qp->rq.last;
1871 qp->rq.last = wqe;
1872
1873 ((struct mthca_next_seg *) wqe)->ee_nds =
1874 cpu_to_be32(MTHCA_NEXT_DBD);
1875 ((struct mthca_next_seg *) wqe)->flags = 0;
1876
1877 wqe += sizeof (struct mthca_next_seg);
1878 size = sizeof (struct mthca_next_seg) / 16;
1879
1880 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1881 err = -EINVAL;
1882 *bad_wr = wr;
1883 goto out;
1884 }
1885
1886 for (i = 0; i < wr->num_sge; ++i) {
1887 mthca_set_data_seg(wqe, wr->sg_list + i);
1888 wqe += sizeof (struct mthca_data_seg);
1889 size += sizeof (struct mthca_data_seg) / 16;
1890 }
1891
1892 qp->wrid[ind] = wr->wr_id;
1893
1894 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1895 cpu_to_be32(MTHCA_NEXT_DBD | size);
1896
1897 if (!nreq)
1898 size0 = size;
1899
1900 ++ind;
1901 if (unlikely(ind >= qp->rq.max))
1902 ind -= qp->rq.max;
1903
1904 ++nreq;
1905 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1906 nreq = 0;
1907
1908 wmb();
1909
1910 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1911 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1912 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1913
1914 qp->rq.next_ind = ind;
1915 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1916 }
1917 }
1918
1919 out:
1920 if (likely(nreq)) {
1921 wmb();
1922
1923 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1924 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1925 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1926 }
1927
1928 qp->rq.next_ind = ind;
1929 qp->rq.head += nreq;
1930
1931 /*
1932 * Make sure doorbells don't leak out of RQ spinlock and reach
1933 * the HCA out of order:
1934 */
1935 mmiowb();
1936
1937 spin_unlock_irqrestore(&qp->rq.lock, flags);
1938 return err;
1939 }
1940
1941 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1942 struct ib_send_wr **bad_wr)
1943 {
1944 struct mthca_dev *dev = to_mdev(ibqp->device);
1945 struct mthca_qp *qp = to_mqp(ibqp);
1946 u32 dbhi;
1947 void *wqe;
1948 void *prev_wqe;
1949 unsigned long flags;
1950 int err = 0;
1951 int nreq;
1952 int i;
1953 int size;
1954 /*
1955 * f0 and size0 are only used if nreq != 0, and they will
1956 * always be initialized the first time through the main loop
1957 * before nreq is incremented. So nreq cannot become non-zero
1958 * without initializing f0 and size0, and they are in fact
1959 * never used uninitialized.
1960 */
1961 int uninitialized_var(size0);
1962 u32 uninitialized_var(f0);
1963 int ind;
1964 u8 op0 = 0;
1965
1966 spin_lock_irqsave(&qp->sq.lock, flags);
1967
1968 /* XXX check that state is OK to post send */
1969
1970 ind = qp->sq.head & (qp->sq.max - 1);
1971
1972 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1973 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1974 nreq = 0;
1975
1976 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1977 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1978
1979 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1980
1981 /*
1982 * Make sure that descriptors are written before
1983 * doorbell record.
1984 */
1985 wmb();
1986 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1987
1988 /*
1989 * Make sure doorbell record is written before we
1990 * write MMIO send doorbell.
1991 */
1992 wmb();
1993
1994 mthca_write64(dbhi, (qp->qpn << 8) | size0,
1995 dev->kar + MTHCA_SEND_DOORBELL,
1996 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1997 }
1998
1999 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2000 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
2001 " %d max, %d nreq)\n", qp->qpn,
2002 qp->sq.head, qp->sq.tail,
2003 qp->sq.max, nreq);
2004 err = -ENOMEM;
2005 *bad_wr = wr;
2006 goto out;
2007 }
2008
2009 wqe = get_send_wqe(qp, ind);
2010 prev_wqe = qp->sq.last;
2011 qp->sq.last = wqe;
2012
2013 ((struct mthca_next_seg *) wqe)->flags =
2014 ((wr->send_flags & IB_SEND_SIGNALED) ?
2015 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2016 ((wr->send_flags & IB_SEND_SOLICITED) ?
2017 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
2018 cpu_to_be32(1);
2019 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2020 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2021 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
2022
2023 wqe += sizeof (struct mthca_next_seg);
2024 size = sizeof (struct mthca_next_seg) / 16;
2025
2026 switch (qp->transport) {
2027 case RC:
2028 switch (wr->opcode) {
2029 case IB_WR_ATOMIC_CMP_AND_SWP:
2030 case IB_WR_ATOMIC_FETCH_AND_ADD:
2031 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2032 wr->wr.atomic.rkey);
2033 wqe += sizeof (struct mthca_raddr_seg);
2034
2035 set_atomic_seg(wqe, wr);
2036 wqe += sizeof (struct mthca_atomic_seg);
2037 size += (sizeof (struct mthca_raddr_seg) +
2038 sizeof (struct mthca_atomic_seg)) / 16;
2039 break;
2040
2041 case IB_WR_RDMA_READ:
2042 case IB_WR_RDMA_WRITE:
2043 case IB_WR_RDMA_WRITE_WITH_IMM:
2044 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2045 wr->wr.rdma.rkey);
2046 wqe += sizeof (struct mthca_raddr_seg);
2047 size += sizeof (struct mthca_raddr_seg) / 16;
2048 break;
2049
2050 default:
2051 /* No extra segments required for sends */
2052 break;
2053 }
2054
2055 break;
2056
2057 case UC:
2058 switch (wr->opcode) {
2059 case IB_WR_RDMA_WRITE:
2060 case IB_WR_RDMA_WRITE_WITH_IMM:
2061 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2062 wr->wr.rdma.rkey);
2063 wqe += sizeof (struct mthca_raddr_seg);
2064 size += sizeof (struct mthca_raddr_seg) / 16;
2065 break;
2066
2067 default:
2068 /* No extra segments required for sends */
2069 break;
2070 }
2071
2072 break;
2073
2074 case UD:
2075 set_arbel_ud_seg(wqe, wr);
2076 wqe += sizeof (struct mthca_arbel_ud_seg);
2077 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2078 break;
2079
2080 case MLX:
2081 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2082 wqe - sizeof (struct mthca_next_seg),
2083 wqe);
2084 if (err) {
2085 *bad_wr = wr;
2086 goto out;
2087 }
2088 wqe += sizeof (struct mthca_data_seg);
2089 size += sizeof (struct mthca_data_seg) / 16;
2090 break;
2091 }
2092
2093 if (wr->num_sge > qp->sq.max_gs) {
2094 mthca_err(dev, "too many gathers\n");
2095 err = -EINVAL;
2096 *bad_wr = wr;
2097 goto out;
2098 }
2099
2100 for (i = 0; i < wr->num_sge; ++i) {
2101 mthca_set_data_seg(wqe, wr->sg_list + i);
2102 wqe += sizeof (struct mthca_data_seg);
2103 size += sizeof (struct mthca_data_seg) / 16;
2104 }
2105
2106 /* Add one more inline data segment for ICRC */
2107 if (qp->transport == MLX) {
2108 ((struct mthca_data_seg *) wqe)->byte_count =
2109 cpu_to_be32((1 << 31) | 4);
2110 ((u32 *) wqe)[1] = 0;
2111 wqe += sizeof (struct mthca_data_seg);
2112 size += sizeof (struct mthca_data_seg) / 16;
2113 }
2114
2115 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2116
2117 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2118 mthca_err(dev, "opcode invalid\n");
2119 err = -EINVAL;
2120 *bad_wr = wr;
2121 goto out;
2122 }
2123
2124 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2125 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2126 qp->send_wqe_offset) |
2127 mthca_opcode[wr->opcode]);
2128 wmb();
2129 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2130 cpu_to_be32(MTHCA_NEXT_DBD | size |
2131 ((wr->send_flags & IB_SEND_FENCE) ?
2132 MTHCA_NEXT_FENCE : 0));
2133
2134 if (!nreq) {
2135 size0 = size;
2136 op0 = mthca_opcode[wr->opcode];
2137 f0 = wr->send_flags & IB_SEND_FENCE ?
2138 MTHCA_SEND_DOORBELL_FENCE : 0;
2139 }
2140
2141 ++ind;
2142 if (unlikely(ind >= qp->sq.max))
2143 ind -= qp->sq.max;
2144 }
2145
2146 out:
2147 if (likely(nreq)) {
2148 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2149
2150 qp->sq.head += nreq;
2151
2152 /*
2153 * Make sure that descriptors are written before
2154 * doorbell record.
2155 */
2156 wmb();
2157 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2158
2159 /*
2160 * Make sure doorbell record is written before we
2161 * write MMIO send doorbell.
2162 */
2163 wmb();
2164
2165 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2166 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2167 }
2168
2169 /*
2170 * Make sure doorbells don't leak out of SQ spinlock and reach
2171 * the HCA out of order:
2172 */
2173 mmiowb();
2174
2175 spin_unlock_irqrestore(&qp->sq.lock, flags);
2176 return err;
2177 }
2178
2179 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2180 struct ib_recv_wr **bad_wr)
2181 {
2182 struct mthca_dev *dev = to_mdev(ibqp->device);
2183 struct mthca_qp *qp = to_mqp(ibqp);
2184 unsigned long flags;
2185 int err = 0;
2186 int nreq;
2187 int ind;
2188 int i;
2189 void *wqe;
2190
2191 spin_lock_irqsave(&qp->rq.lock, flags);
2192
2193 /* XXX check that state is OK to post receive */
2194
2195 ind = qp->rq.head & (qp->rq.max - 1);
2196
2197 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2198 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2199 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2200 " %d max, %d nreq)\n", qp->qpn,
2201 qp->rq.head, qp->rq.tail,
2202 qp->rq.max, nreq);
2203 err = -ENOMEM;
2204 *bad_wr = wr;
2205 goto out;
2206 }
2207
2208 wqe = get_recv_wqe(qp, ind);
2209
2210 ((struct mthca_next_seg *) wqe)->flags = 0;
2211
2212 wqe += sizeof (struct mthca_next_seg);
2213
2214 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2215 err = -EINVAL;
2216 *bad_wr = wr;
2217 goto out;
2218 }
2219
2220 for (i = 0; i < wr->num_sge; ++i) {
2221 mthca_set_data_seg(wqe, wr->sg_list + i);
2222 wqe += sizeof (struct mthca_data_seg);
2223 }
2224
2225 if (i < qp->rq.max_gs)
2226 mthca_set_data_seg_inval(wqe);
2227
2228 qp->wrid[ind] = wr->wr_id;
2229
2230 ++ind;
2231 if (unlikely(ind >= qp->rq.max))
2232 ind -= qp->rq.max;
2233 }
2234 out:
2235 if (likely(nreq)) {
2236 qp->rq.head += nreq;
2237
2238 /*
2239 * Make sure that descriptors are written before
2240 * doorbell record.
2241 */
2242 wmb();
2243 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2244 }
2245
2246 spin_unlock_irqrestore(&qp->rq.lock, flags);
2247 return err;
2248 }
2249
2250 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2251 int index, int *dbd, __be32 *new_wqe)
2252 {
2253 struct mthca_next_seg *next;
2254
2255 /*
2256 * For SRQs, all receive WQEs generate a CQE, so we're always
2257 * at the end of the doorbell chain.
2258 */
2259 if (qp->ibqp.srq && !is_send) {
2260 *new_wqe = 0;
2261 return;
2262 }
2263
2264 if (is_send)
2265 next = get_send_wqe(qp, index);
2266 else
2267 next = get_recv_wqe(qp, index);
2268
2269 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2270 if (next->ee_nds & cpu_to_be32(0x3f))
2271 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2272 (next->ee_nds & cpu_to_be32(0x3f));
2273 else
2274 *new_wqe = 0;
2275 }
2276
2277 int mthca_init_qp_table(struct mthca_dev *dev)
2278 {
2279 int err;
2280 u8 status;
2281 int i;
2282
2283 spin_lock_init(&dev->qp_table.lock);
2284
2285 /*
2286 * We reserve 2 extra QPs per port for the special QPs. The
2287 * special QP for port 1 has to be even, so round up.
2288 */
2289 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2290 err = mthca_alloc_init(&dev->qp_table.alloc,
2291 dev->limits.num_qps,
2292 (1 << 24) - 1,
2293 dev->qp_table.sqp_start +
2294 MTHCA_MAX_PORTS * 2);
2295 if (err)
2296 return err;
2297
2298 err = mthca_array_init(&dev->qp_table.qp,
2299 dev->limits.num_qps);
2300 if (err) {
2301 mthca_alloc_cleanup(&dev->qp_table.alloc);
2302 return err;
2303 }
2304
2305 for (i = 0; i < 2; ++i) {
2306 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2307 dev->qp_table.sqp_start + i * 2,
2308 &status);
2309 if (err)
2310 goto err_out;
2311 if (status) {
2312 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2313 "status %02x, aborting.\n",
2314 status);
2315 err = -EINVAL;
2316 goto err_out;
2317 }
2318 }
2319 return 0;
2320
2321 err_out:
2322 for (i = 0; i < 2; ++i)
2323 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2324
2325 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2326 mthca_alloc_cleanup(&dev->qp_table.alloc);
2327
2328 return err;
2329 }
2330
2331 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2332 {
2333 int i;
2334 u8 status;
2335
2336 for (i = 0; i < 2; ++i)
2337 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2338
2339 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2340 mthca_alloc_cleanup(&dev->qp_table.alloc);
2341 }
Linux with added FPC-III support