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iwlwifi: introduce host commands callbacks
[linux/fpc-iii.git] / drivers / mfd / sm501.c
blob13bac53db69a1ffe58726720a461ee0bbac9edd0
1 /* linux/drivers/mfd/sm501.c
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * SM501 MFD driver
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/list.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pci.h>
22
23 #include <linux/sm501.h>
24 #include <linux/sm501-regs.h>
25
26 #include <asm/io.h>
27
28 struct sm501_device {
29 struct list_head list;
30 struct platform_device pdev;
31 };
32
33 struct sm501_devdata {
34 spinlock_t reg_lock;
35 struct mutex clock_lock;
36 struct list_head devices;
37
38 struct device *dev;
39 struct resource *io_res;
40 struct resource *mem_res;
41 struct resource *regs_claim;
42 struct sm501_platdata *platdata;
43
44 unsigned int in_suspend;
45 unsigned long pm_misc;
46
47 int unit_power[20];
48 unsigned int pdev_id;
49 unsigned int irq;
50 void __iomem *regs;
51 unsigned int rev;
52 };
53
54 #define MHZ (1000 * 1000)
55
56 #ifdef DEBUG
57 static const unsigned int div_tab[] = {
58 [0] = 1,
59 [1] = 2,
60 [2] = 4,
61 [3] = 8,
62 [4] = 16,
63 [5] = 32,
64 [6] = 64,
65 [7] = 128,
66 [8] = 3,
67 [9] = 6,
68 [10] = 12,
69 [11] = 24,
70 [12] = 48,
71 [13] = 96,
72 [14] = 192,
73 [15] = 384,
74 [16] = 5,
75 [17] = 10,
76 [18] = 20,
77 [19] = 40,
78 [20] = 80,
79 [21] = 160,
80 [22] = 320,
81 [23] = 604,
82 };
83
84 static unsigned long decode_div(unsigned long pll2, unsigned long val,
85 unsigned int lshft, unsigned int selbit,
86 unsigned long mask)
87 {
88 if (val & selbit)
89 pll2 = 288 * MHZ;
90
91 return pll2 / div_tab[(val >> lshft) & mask];
92 }
93
94 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
95
96 /* sm501_dump_clk
97 *
98 * Print out the current clock configuration for the device
99 */
100
101 static void sm501_dump_clk(struct sm501_devdata *sm)
102 {
103 unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
104 unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
105 unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
106 unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
107 unsigned long sdclk0, sdclk1;
108 unsigned long pll2 = 0;
109
110 switch (misct & 0x30) {
111 case 0x00:
112 pll2 = 336 * MHZ;
113 break;
114 case 0x10:
115 pll2 = 288 * MHZ;
116 break;
117 case 0x20:
118 pll2 = 240 * MHZ;
119 break;
120 case 0x30:
121 pll2 = 192 * MHZ;
122 break;
123 }
124
125 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
126 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
127
128 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
129 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
130
131 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
132 misct, pm0, pm1);
133
134 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
135 fmt_freq(pll2), sdclk0, sdclk1);
136
137 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
138
139 dev_dbg(sm->dev, "PM0[%c]: "
140 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
141 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
142 (pmc & 3 ) == 0 ? '*' : '-',
143 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
144 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
145 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
146 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
147
148 dev_dbg(sm->dev, "PM1[%c]: "
149 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
150 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
151 (pmc & 3 ) == 1 ? '*' : '-',
152 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
153 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
154 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
155 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
156 }
157
158 static void sm501_dump_regs(struct sm501_devdata *sm)
159 {
160 void __iomem *regs = sm->regs;
161
162 dev_info(sm->dev, "System Control %08x\n",
163 readl(regs + SM501_SYSTEM_CONTROL));
164 dev_info(sm->dev, "Misc Control %08x\n",
165 readl(regs + SM501_MISC_CONTROL));
166 dev_info(sm->dev, "GPIO Control Low %08x\n",
167 readl(regs + SM501_GPIO31_0_CONTROL));
168 dev_info(sm->dev, "GPIO Control Hi %08x\n",
169 readl(regs + SM501_GPIO63_32_CONTROL));
170 dev_info(sm->dev, "DRAM Control %08x\n",
171 readl(regs + SM501_DRAM_CONTROL));
172 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
173 readl(regs + SM501_ARBTRTN_CONTROL));
174 dev_info(sm->dev, "Misc Timing %08x\n",
175 readl(regs + SM501_MISC_TIMING));
176 }
177
178 static void sm501_dump_gate(struct sm501_devdata *sm)
179 {
180 dev_info(sm->dev, "CurrentGate %08x\n",
181 readl(sm->regs + SM501_CURRENT_GATE));
182 dev_info(sm->dev, "CurrentClock %08x\n",
183 readl(sm->regs + SM501_CURRENT_CLOCK));
184 dev_info(sm->dev, "PowerModeControl %08x\n",
185 readl(sm->regs + SM501_POWER_MODE_CONTROL));
186 }
187
188 #else
189 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
190 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
191 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
192 #endif
193
194 /* sm501_sync_regs
195 *
196 * ensure the
197 */
198
199 static void sm501_sync_regs(struct sm501_devdata *sm)
200 {
201 readl(sm->regs);
202 }
203
204 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
205 {
206 /* during suspend/resume, we are currently not allowed to sleep,
207 * so change to using mdelay() instead of msleep() if we
208 * are in one of these paths */
209
210 if (sm->in_suspend)
211 mdelay(delay);
212 else
213 msleep(delay);
214 }
215
216 /* sm501_misc_control
217 *
218 * alters the miscellaneous control parameters
219 */
220
221 int sm501_misc_control(struct device *dev,
222 unsigned long set, unsigned long clear)
223 {
224 struct sm501_devdata *sm = dev_get_drvdata(dev);
225 unsigned long misc;
226 unsigned long save;
227 unsigned long to;
228
229 spin_lock_irqsave(&sm->reg_lock, save);
230
231 misc = readl(sm->regs + SM501_MISC_CONTROL);
232 to = (misc & ~clear) | set;
233
234 if (to != misc) {
235 writel(to, sm->regs + SM501_MISC_CONTROL);
236 sm501_sync_regs(sm);
237
238 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
239 }
240
241 spin_unlock_irqrestore(&sm->reg_lock, save);
242 return to;
243 }
244
245 EXPORT_SYMBOL_GPL(sm501_misc_control);
246
247 /* sm501_modify_reg
248 *
249 * Modify a register in the SM501 which may be shared with other
250 * drivers.
251 */
252
253 unsigned long sm501_modify_reg(struct device *dev,
254 unsigned long reg,
255 unsigned long set,
256 unsigned long clear)
257 {
258 struct sm501_devdata *sm = dev_get_drvdata(dev);
259 unsigned long data;
260 unsigned long save;
261
262 spin_lock_irqsave(&sm->reg_lock, save);
263
264 data = readl(sm->regs + reg);
265 data |= set;
266 data &= ~clear;
267
268 writel(data, sm->regs + reg);
269 sm501_sync_regs(sm);
270
271 spin_unlock_irqrestore(&sm->reg_lock, save);
272
273 return data;
274 }
275
276 EXPORT_SYMBOL_GPL(sm501_modify_reg);
277
278 unsigned long sm501_gpio_get(struct device *dev,
279 unsigned long gpio)
280 {
281 struct sm501_devdata *sm = dev_get_drvdata(dev);
282 unsigned long result;
283 unsigned long reg;
284
285 reg = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW;
286 result = readl(sm->regs + reg);
287
288 result >>= (gpio & 31);
289 return result & 1UL;
290 }
291
292 EXPORT_SYMBOL_GPL(sm501_gpio_get);
293
294 void sm501_gpio_set(struct device *dev,
295 unsigned long gpio,
296 unsigned int to,
297 unsigned int dir)
298 {
299 struct sm501_devdata *sm = dev_get_drvdata(dev);
300
301 unsigned long bit = 1 << (gpio & 31);
302 unsigned long base;
303 unsigned long save;
304 unsigned long val;
305
306 base = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW;
307 base += SM501_GPIO;
308
309 spin_lock_irqsave(&sm->reg_lock, save);
310
311 val = readl(sm->regs + base) & ~bit;
312 if (to)
313 val |= bit;
314 writel(val, sm->regs + base);
315
316 val = readl(sm->regs + SM501_GPIO_DDR_LOW) & ~bit;
317 if (dir)
318 val |= bit;
319
320 writel(val, sm->regs + SM501_GPIO_DDR_LOW);
321 sm501_sync_regs(sm);
322
323 spin_unlock_irqrestore(&sm->reg_lock, save);
324
325 }
326
327 EXPORT_SYMBOL_GPL(sm501_gpio_set);
328
329
330 /* sm501_unit_power
331 *
332 * alters the power active gate to set specific units on or off
333 */
334
335 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
336 {
337 struct sm501_devdata *sm = dev_get_drvdata(dev);
338 unsigned long mode;
339 unsigned long gate;
340 unsigned long clock;
341
342 mutex_lock(&sm->clock_lock);
343
344 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
345 gate = readl(sm->regs + SM501_CURRENT_GATE);
346 clock = readl(sm->regs + SM501_CURRENT_CLOCK);
347
348 mode &= 3; /* get current power mode */
349
350 if (unit >= ARRAY_SIZE(sm->unit_power)) {
351 dev_err(dev, "%s: bad unit %d\n", __FUNCTION__, unit);
352 goto already;
353 }
354
355 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __FUNCTION__, unit,
356 sm->unit_power[unit], to);
357
358 if (to == 0 && sm->unit_power[unit] == 0) {
359 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
360 goto already;
361 }
362
363 sm->unit_power[unit] += to ? 1 : -1;
364 to = sm->unit_power[unit] ? 1 : 0;
365
366 if (to) {
367 if (gate & (1 << unit))
368 goto already;
369 gate |= (1 << unit);
370 } else {
371 if (!(gate & (1 << unit)))
372 goto already;
373 gate &= ~(1 << unit);
374 }
375
376 switch (mode) {
377 case 1:
378 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
379 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
380 mode = 0;
381 break;
382 case 2:
383 case 0:
384 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
385 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
386 mode = 1;
387 break;
388
389 default:
390 return -1;
391 }
392
393 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
394 sm501_sync_regs(sm);
395
396 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
397 gate, clock, mode);
398
399 sm501_mdelay(sm, 16);
400
401 already:
402 mutex_unlock(&sm->clock_lock);
403 return gate;
404 }
405
406 EXPORT_SYMBOL_GPL(sm501_unit_power);
407
408
409 /* Perform a rounded division. */
410 static long sm501fb_round_div(long num, long denom)
411 {
412 /* n / d + 1 / 2 = (2n + d) / 2d */
413 return (2 * num + denom) / (2 * denom);
414 }
415
416 /* clock value structure. */
417 struct sm501_clock {
418 unsigned long mclk;
419 int divider;
420 int shift;
421 unsigned int m, n, k;
422 };
423
424 /* sm501_calc_clock
425 *
426 * Calculates the nearest discrete clock frequency that
427 * can be achieved with the specified input clock.
428 * the maximum divisor is 3 or 5
429 */
430
431 static int sm501_calc_clock(unsigned long freq,
432 struct sm501_clock *clock,
433 int max_div,
434 unsigned long mclk,
435 long *best_diff)
436 {
437 int ret = 0;
438 int divider;
439 int shift;
440 long diff;
441
442 /* try dividers 1 and 3 for CRT and for panel,
443 try divider 5 for panel only.*/
444
445 for (divider = 1; divider <= max_div; divider += 2) {
446 /* try all 8 shift values.*/
447 for (shift = 0; shift < 8; shift++) {
448 /* Calculate difference to requested clock */
449 diff = sm501fb_round_div(mclk, divider << shift) - freq;
450 if (diff < 0)
451 diff = -diff;
452
453 /* If it is less than the current, use it */
454 if (diff < *best_diff) {
455 *best_diff = diff;
456
457 clock->mclk = mclk;
458 clock->divider = divider;
459 clock->shift = shift;
460 ret = 1;
461 }
462 }
463 }
464
465 return ret;
466 }
467
468 /* sm501_calc_pll
469 *
470 * Calculates the nearest discrete clock frequency that can be
471 * achieved using the programmable PLL.
472 * the maximum divisor is 3 or 5
473 */
474
475 static unsigned long sm501_calc_pll(unsigned long freq,
476 struct sm501_clock *clock,
477 int max_div)
478 {
479 unsigned long mclk;
480 unsigned int m, n, k;
481 long best_diff = 999999999;
482
483 /*
484 * The SM502 datasheet doesn't specify the min/max values for M and N.
485 * N = 1 at least doesn't work in practice.
486 */
487 for (m = 2; m <= 255; m++) {
488 for (n = 2; n <= 127; n++) {
489 for (k = 0; k <= 1; k++) {
490 mclk = (24000000UL * m / n) >> k;
491
492 if (sm501_calc_clock(freq, clock, max_div,
493 mclk, &best_diff)) {
494 clock->m = m;
495 clock->n = n;
496 clock->k = k;
497 }
498 }
499 }
500 }
501
502 /* Return best clock. */
503 return clock->mclk / (clock->divider << clock->shift);
504 }
505
506 /* sm501_select_clock
507 *
508 * Calculates the nearest discrete clock frequency that can be
509 * achieved using the 288MHz and 336MHz PLLs.
510 * the maximum divisor is 3 or 5
511 */
512
513 static unsigned long sm501_select_clock(unsigned long freq,
514 struct sm501_clock *clock,
515 int max_div)
516 {
517 unsigned long mclk;
518 long best_diff = 999999999;
519
520 /* Try 288MHz and 336MHz clocks. */
521 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
522 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
523 }
524
525 /* Return best clock. */
526 return clock->mclk / (clock->divider << clock->shift);
527 }
528
529 /* sm501_set_clock
530 *
531 * set one of the four clock sources to the closest available frequency to
532 * the one specified
533 */
534
535 unsigned long sm501_set_clock(struct device *dev,
536 int clksrc,
537 unsigned long req_freq)
538 {
539 struct sm501_devdata *sm = dev_get_drvdata(dev);
540 unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
541 unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
542 unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
543 unsigned char reg;
544 unsigned int pll_reg = 0;
545 unsigned long sm501_freq; /* the actual frequency acheived */
546
547 struct sm501_clock to;
548
549 /* find achivable discrete frequency and setup register value
550 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
551 * has an extra bit for the divider */
552
553 switch (clksrc) {
554 case SM501_CLOCK_P2XCLK:
555 /* This clock is divided in half so to achive the
556 * requested frequency the value must be multiplied by
557 * 2. This clock also has an additional pre divisor */
558
559 if (sm->rev >= 0xC0) {
560 /* SM502 -> use the programmable PLL */
561 sm501_freq = (sm501_calc_pll(2 * req_freq,
562 &to, 5) / 2);
563 reg = to.shift & 0x07;/* bottom 3 bits are shift */
564 if (to.divider == 3)
565 reg |= 0x08; /* /3 divider required */
566 else if (to.divider == 5)
567 reg |= 0x10; /* /5 divider required */
568 reg |= 0x40; /* select the programmable PLL */
569 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
570 } else {
571 sm501_freq = (sm501_select_clock(2 * req_freq,
572 &to, 5) / 2);
573 reg = to.shift & 0x07;/* bottom 3 bits are shift */
574 if (to.divider == 3)
575 reg |= 0x08; /* /3 divider required */
576 else if (to.divider == 5)
577 reg |= 0x10; /* /5 divider required */
578 if (to.mclk != 288000000)
579 reg |= 0x20; /* which mclk pll is source */
580 }
581 break;
582
583 case SM501_CLOCK_V2XCLK:
584 /* This clock is divided in half so to achive the
585 * requested frequency the value must be multiplied by 2. */
586
587 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
588 reg=to.shift & 0x07; /* bottom 3 bits are shift */
589 if (to.divider == 3)
590 reg |= 0x08; /* /3 divider required */
591 if (to.mclk != 288000000)
592 reg |= 0x10; /* which mclk pll is source */
593 break;
594
595 case SM501_CLOCK_MCLK:
596 case SM501_CLOCK_M1XCLK:
597 /* These clocks are the same and not further divided */
598
599 sm501_freq = sm501_select_clock( req_freq, &to, 3);
600 reg=to.shift & 0x07; /* bottom 3 bits are shift */
601 if (to.divider == 3)
602 reg |= 0x08; /* /3 divider required */
603 if (to.mclk != 288000000)
604 reg |= 0x10; /* which mclk pll is source */
605 break;
606
607 default:
608 return 0; /* this is bad */
609 }
610
611 mutex_lock(&sm->clock_lock);
612
613 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
614 gate = readl(sm->regs + SM501_CURRENT_GATE);
615 clock = readl(sm->regs + SM501_CURRENT_CLOCK);
616
617 clock = clock & ~(0xFF << clksrc);
618 clock |= reg<<clksrc;
619
620 mode &= 3; /* find current mode */
621
622 switch (mode) {
623 case 1:
624 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
625 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
626 mode = 0;
627 break;
628 case 2:
629 case 0:
630 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
631 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
632 mode = 1;
633 break;
634
635 default:
636 mutex_unlock(&sm->clock_lock);
637 return -1;
638 }
639
640 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
641
642 if (pll_reg)
643 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
644
645 sm501_sync_regs(sm);
646
647 dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
648 gate, clock, mode);
649
650 sm501_mdelay(sm, 16);
651 mutex_unlock(&sm->clock_lock);
652
653 sm501_dump_clk(sm);
654
655 return sm501_freq;
656 }
657
658 EXPORT_SYMBOL_GPL(sm501_set_clock);
659
660 /* sm501_find_clock
661 *
662 * finds the closest available frequency for a given clock
663 */
664
665 unsigned long sm501_find_clock(struct device *dev,
666 int clksrc,
667 unsigned long req_freq)
668 {
669 struct sm501_devdata *sm = dev_get_drvdata(dev);
670 unsigned long sm501_freq; /* the frequency achiveable by the 501 */
671 struct sm501_clock to;
672
673 switch (clksrc) {
674 case SM501_CLOCK_P2XCLK:
675 if (sm->rev >= 0xC0) {
676 /* SM502 -> use the programmable PLL */
677 sm501_freq = (sm501_calc_pll(2 * req_freq,
678 &to, 5) / 2);
679 } else {
680 sm501_freq = (sm501_select_clock(2 * req_freq,
681 &to, 5) / 2);
682 }
683 break;
684
685 case SM501_CLOCK_V2XCLK:
686 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
687 break;
688
689 case SM501_CLOCK_MCLK:
690 case SM501_CLOCK_M1XCLK:
691 sm501_freq = sm501_select_clock(req_freq, &to, 3);
692 break;
693
694 default:
695 sm501_freq = 0; /* error */
696 }
697
698 return sm501_freq;
699 }
700
701 EXPORT_SYMBOL_GPL(sm501_find_clock);
702
703 static struct sm501_device *to_sm_device(struct platform_device *pdev)
704 {
705 return container_of(pdev, struct sm501_device, pdev);
706 }
707
708 /* sm501_device_release
709 *
710 * A release function for the platform devices we create to allow us to
711 * free any items we allocated
712 */
713
714 static void sm501_device_release(struct device *dev)
715 {
716 kfree(to_sm_device(to_platform_device(dev)));
717 }
718
719 /* sm501_create_subdev
720 *
721 * Create a skeleton platform device with resources for passing to a
722 * sub-driver
723 */
724
725 static struct platform_device *
726 sm501_create_subdev(struct sm501_devdata *sm,
727 char *name, unsigned int res_count)
728 {
729 struct sm501_device *smdev;
730
731 smdev = kzalloc(sizeof(struct sm501_device) +
732 sizeof(struct resource) * res_count, GFP_KERNEL);
733 if (!smdev)
734 return NULL;
735
736 smdev->pdev.dev.release = sm501_device_release;
737
738 smdev->pdev.name = name;
739 smdev->pdev.id = sm->pdev_id;
740 smdev->pdev.resource = (struct resource *)(smdev+1);
741 smdev->pdev.num_resources = res_count;
742
743 smdev->pdev.dev.parent = sm->dev;
744
745 return &smdev->pdev;
746 }
747
748 /* sm501_register_device
749 *
750 * Register a platform device created with sm501_create_subdev()
751 */
752
753 static int sm501_register_device(struct sm501_devdata *sm,
754 struct platform_device *pdev)
755 {
756 struct sm501_device *smdev = to_sm_device(pdev);
757 int ptr;
758 int ret;
759
760 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
761 printk("%s[%d] flags %08lx: %08llx..%08llx\n",
762 pdev->name, ptr,
763 pdev->resource[ptr].flags,
764 (unsigned long long)pdev->resource[ptr].start,
765 (unsigned long long)pdev->resource[ptr].end);
766 }
767
768 ret = platform_device_register(pdev);
769
770 if (ret >= 0) {
771 dev_dbg(sm->dev, "registered %s\n", pdev->name);
772 list_add_tail(&smdev->list, &sm->devices);
773 } else
774 dev_err(sm->dev, "error registering %s (%d)\n",
775 pdev->name, ret);
776
777 return ret;
778 }
779
780 /* sm501_create_subio
781 *
782 * Fill in an IO resource for a sub device
783 */
784
785 static void sm501_create_subio(struct sm501_devdata *sm,
786 struct resource *res,
787 resource_size_t offs,
788 resource_size_t size)
789 {
790 res->flags = IORESOURCE_MEM;
791 res->parent = sm->io_res;
792 res->start = sm->io_res->start + offs;
793 res->end = res->start + size - 1;
794 }
795
796 /* sm501_create_mem
797 *
798 * Fill in an MEM resource for a sub device
799 */
800
801 static void sm501_create_mem(struct sm501_devdata *sm,
802 struct resource *res,
803 resource_size_t *offs,
804 resource_size_t size)
805 {
806 *offs -= size; /* adjust memory size */
807
808 res->flags = IORESOURCE_MEM;
809 res->parent = sm->mem_res;
810 res->start = sm->mem_res->start + *offs;
811 res->end = res->start + size - 1;
812 }
813
814 /* sm501_create_irq
815 *
816 * Fill in an IRQ resource for a sub device
817 */
818
819 static void sm501_create_irq(struct sm501_devdata *sm,
820 struct resource *res)
821 {
822 res->flags = IORESOURCE_IRQ;
823 res->parent = NULL;
824 res->start = res->end = sm->irq;
825 }
826
827 static int sm501_register_usbhost(struct sm501_devdata *sm,
828 resource_size_t *mem_avail)
829 {
830 struct platform_device *pdev;
831
832 pdev = sm501_create_subdev(sm, "sm501-usb", 3);
833 if (!pdev)
834 return -ENOMEM;
835
836 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
837 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
838 sm501_create_irq(sm, &pdev->resource[2]);
839
840 return sm501_register_device(sm, pdev);
841 }
842
843 static int sm501_register_display(struct sm501_devdata *sm,
844 resource_size_t *mem_avail)
845 {
846 struct platform_device *pdev;
847
848 pdev = sm501_create_subdev(sm, "sm501-fb", 4);
849 if (!pdev)
850 return -ENOMEM;
851
852 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
853 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
854 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
855 sm501_create_irq(sm, &pdev->resource[3]);
856
857 return sm501_register_device(sm, pdev);
858 }
859
860 /* sm501_dbg_regs
861 *
862 * Debug attribute to attach to parent device to show core registers
863 */
864
865 static ssize_t sm501_dbg_regs(struct device *dev,
866 struct device_attribute *attr, char *buff)
867 {
868 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
869 unsigned int reg;
870 char *ptr = buff;
871 int ret;
872
873 for (reg = 0x00; reg < 0x70; reg += 4) {
874 ret = sprintf(ptr, "%08x = %08x\n",
875 reg, readl(sm->regs + reg));
876 ptr += ret;
877 }
878
879 return ptr - buff;
880 }
881
882
883 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
884
885 /* sm501_init_reg
886 *
887 * Helper function for the init code to setup a register
888 *
889 * clear the bits which are set in r->mask, and then set
890 * the bits set in r->set.
891 */
892
893 static inline void sm501_init_reg(struct sm501_devdata *sm,
894 unsigned long reg,
895 struct sm501_reg_init *r)
896 {
897 unsigned long tmp;
898
899 tmp = readl(sm->regs + reg);
900 tmp &= ~r->mask;
901 tmp |= r->set;
902 writel(tmp, sm->regs + reg);
903 }
904
905 /* sm501_init_regs
906 *
907 * Setup core register values
908 */
909
910 static void sm501_init_regs(struct sm501_devdata *sm,
911 struct sm501_initdata *init)
912 {
913 sm501_misc_control(sm->dev,
914 init->misc_control.set,
915 init->misc_control.mask);
916
917 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
918 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
919 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
920
921 if (init->m1xclk) {
922 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
923 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
924 }
925
926 if (init->mclk) {
927 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
928 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
929 }
930
931 }
932
933 /* Check the PLL sources for the M1CLK and M1XCLK
934 *
935 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
936 * there is a risk (see errata AB-5) that the SM501 will cease proper
937 * function. If this happens, then it is likely the SM501 will
938 * hang the system.
939 */
940
941 static int sm501_check_clocks(struct sm501_devdata *sm)
942 {
943 unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
944 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
945 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
946
947 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
948 }
949
950 static unsigned int sm501_mem_local[] = {
951 [0] = 4*1024*1024,
952 [1] = 8*1024*1024,
953 [2] = 16*1024*1024,
954 [3] = 32*1024*1024,
955 [4] = 64*1024*1024,
956 [5] = 2*1024*1024,
957 };
958
959 /* sm501_init_dev
960 *
961 * Common init code for an SM501
962 */
963
964 static int sm501_init_dev(struct sm501_devdata *sm)
965 {
966 resource_size_t mem_avail;
967 unsigned long dramctrl;
968 unsigned long devid;
969 int ret;
970
971 mutex_init(&sm->clock_lock);
972 spin_lock_init(&sm->reg_lock);
973
974 INIT_LIST_HEAD(&sm->devices);
975
976 devid = readl(sm->regs + SM501_DEVICEID);
977
978 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
979 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
980 return -EINVAL;
981 }
982
983 dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
984 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
985
986 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
987 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
988
989 sm->rev = devid & SM501_DEVICEID_REVMASK;
990
991 sm501_dump_gate(sm);
992
993 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
994 if (ret)
995 dev_err(sm->dev, "failed to create debug regs file\n");
996
997 sm501_dump_clk(sm);
998
999 /* check to see if we have some device initialisation */
1000
1001 if (sm->platdata) {
1002 struct sm501_platdata *pdata = sm->platdata;
1003
1004 if (pdata->init) {
1005 sm501_init_regs(sm, sm->platdata->init);
1006
1007 if (pdata->init->devices & SM501_USE_USB_HOST)
1008 sm501_register_usbhost(sm, &mem_avail);
1009 }
1010 }
1011
1012 ret = sm501_check_clocks(sm);
1013 if (ret) {
1014 dev_err(sm->dev, "M1X and M clocks sourced from different "
1015 "PLLs\n");
1016 return -EINVAL;
1017 }
1018
1019 /* always create a framebuffer */
1020 sm501_register_display(sm, &mem_avail);
1021
1022 return 0;
1023 }
1024
1025 static int sm501_plat_probe(struct platform_device *dev)
1026 {
1027 struct sm501_devdata *sm;
1028 int err;
1029
1030 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1031 if (sm == NULL) {
1032 dev_err(&dev->dev, "no memory for device data\n");
1033 err = -ENOMEM;
1034 goto err1;
1035 }
1036
1037 sm->dev = &dev->dev;
1038 sm->pdev_id = dev->id;
1039 sm->irq = platform_get_irq(dev, 0);
1040 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1041 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1042 sm->platdata = dev->dev.platform_data;
1043
1044 if (sm->irq < 0) {
1045 dev_err(&dev->dev, "failed to get irq resource\n");
1046 err = sm->irq;
1047 goto err_res;
1048 }
1049
1050 if (sm->io_res == NULL || sm->mem_res == NULL) {
1051 dev_err(&dev->dev, "failed to get IO resource\n");
1052 err = -ENOENT;
1053 goto err_res;
1054 }
1055
1056 sm->regs_claim = request_mem_region(sm->io_res->start,
1057 0x100, "sm501");
1058
1059 if (sm->regs_claim == NULL) {
1060 dev_err(&dev->dev, "cannot claim registers\n");
1061 err= -EBUSY;
1062 goto err_res;
1063 }
1064
1065 platform_set_drvdata(dev, sm);
1066
1067 sm->regs = ioremap(sm->io_res->start,
1068 (sm->io_res->end - sm->io_res->start) - 1);
1069
1070 if (sm->regs == NULL) {
1071 dev_err(&dev->dev, "cannot remap registers\n");
1072 err = -EIO;
1073 goto err_claim;
1074 }
1075
1076 return sm501_init_dev(sm);
1077
1078 err_claim:
1079 release_resource(sm->regs_claim);
1080 kfree(sm->regs_claim);
1081 err_res:
1082 kfree(sm);
1083 err1:
1084 return err;
1085
1086 }
1087
1088 #ifdef CONFIG_PM
1089 /* power management support */
1090
1091 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1092 {
1093 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1094
1095 sm->in_suspend = 1;
1096 sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
1097
1098 sm501_dump_regs(sm);
1099 return 0;
1100 }
1101
1102 static int sm501_plat_resume(struct platform_device *pdev)
1103 {
1104 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1105
1106 sm501_dump_regs(sm);
1107 sm501_dump_gate(sm);
1108 sm501_dump_clk(sm);
1109
1110 /* check to see if we are in the same state as when suspended */
1111
1112 if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1113 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1114 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1115
1116 /* our suspend causes the controller state to change,
1117 * either by something attempting setup, power loss,
1118 * or an external reset event on power change */
1119
1120 if (sm->platdata && sm->platdata->init) {
1121 sm501_init_regs(sm, sm->platdata->init);
1122 }
1123 }
1124
1125 /* dump our state from resume */
1126
1127 sm501_dump_regs(sm);
1128 sm501_dump_clk(sm);
1129
1130 sm->in_suspend = 0;
1131
1132 return 0;
1133 }
1134 #else
1135 #define sm501_plat_suspend NULL
1136 #define sm501_plat_resume NULL
1137 #endif
1138
1139 /* Initialisation data for PCI devices */
1140
1141 static struct sm501_initdata sm501_pci_initdata = {
1142 .gpio_high = {
1143 .set = 0x3F000000, /* 24bit panel */
1144 .mask = 0x0,
1145 },
1146 .misc_timing = {
1147 .set = 0x010100, /* SDRAM timing */
1148 .mask = 0x1F1F00,
1149 },
1150 .misc_control = {
1151 .set = SM501_MISC_PNL_24BIT,
1152 .mask = 0,
1153 },
1154
1155 .devices = SM501_USE_ALL,
1156
1157 /* Errata AB-3 says that 72MHz is the fastest available
1158 * for 33MHZ PCI with proper bus-mastering operation */
1159
1160 .mclk = 72 * MHZ,
1161 .m1xclk = 144 * MHZ,
1162 };
1163
1164 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1165 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1166 SM501FB_FLAG_USE_HWCURSOR |
1167 SM501FB_FLAG_USE_HWACCEL |
1168 SM501FB_FLAG_DISABLE_AT_EXIT),
1169 };
1170
1171 static struct sm501_platdata_fb sm501_fb_pdata = {
1172 .fb_route = SM501_FB_OWN,
1173 .fb_crt = &sm501_pdata_fbsub,
1174 .fb_pnl = &sm501_pdata_fbsub,
1175 };
1176
1177 static struct sm501_platdata sm501_pci_platdata = {
1178 .init = &sm501_pci_initdata,
1179 .fb = &sm501_fb_pdata,
1180 };
1181
1182 static int sm501_pci_probe(struct pci_dev *dev,
1183 const struct pci_device_id *id)
1184 {
1185 struct sm501_devdata *sm;
1186 int err;
1187
1188 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1189 if (sm == NULL) {
1190 dev_err(&dev->dev, "no memory for device data\n");
1191 err = -ENOMEM;
1192 goto err1;
1193 }
1194
1195 /* set a default set of platform data */
1196 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1197
1198 /* set a hopefully unique id for our child platform devices */
1199 sm->pdev_id = 32 + dev->devfn;
1200
1201 pci_set_drvdata(dev, sm);
1202
1203 err = pci_enable_device(dev);
1204 if (err) {
1205 dev_err(&dev->dev, "cannot enable device\n");
1206 goto err2;
1207 }
1208
1209 sm->dev = &dev->dev;
1210 sm->irq = dev->irq;
1211
1212 #ifdef __BIG_ENDIAN
1213 /* if the system is big-endian, we most probably have a
1214 * translation in the IO layer making the PCI bus little endian
1215 * so make the framebuffer swapped pixels */
1216
1217 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1218 #endif
1219
1220 /* check our resources */
1221
1222 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1223 dev_err(&dev->dev, "region #0 is not memory?\n");
1224 err = -EINVAL;
1225 goto err3;
1226 }
1227
1228 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1229 dev_err(&dev->dev, "region #1 is not memory?\n");
1230 err = -EINVAL;
1231 goto err3;
1232 }
1233
1234 /* make our resources ready for sharing */
1235
1236 sm->io_res = &dev->resource[1];
1237 sm->mem_res = &dev->resource[0];
1238
1239 sm->regs_claim = request_mem_region(sm->io_res->start,
1240 0x100, "sm501");
1241 if (sm->regs_claim == NULL) {
1242 dev_err(&dev->dev, "cannot claim registers\n");
1243 err= -EBUSY;
1244 goto err3;
1245 }
1246
1247 sm->regs = ioremap(pci_resource_start(dev, 1),
1248 pci_resource_len(dev, 1));
1249
1250 if (sm->regs == NULL) {
1251 dev_err(&dev->dev, "cannot remap registers\n");
1252 err = -EIO;
1253 goto err4;
1254 }
1255
1256 sm501_init_dev(sm);
1257 return 0;
1258
1259 err4:
1260 release_resource(sm->regs_claim);
1261 kfree(sm->regs_claim);
1262 err3:
1263 pci_disable_device(dev);
1264 err2:
1265 pci_set_drvdata(dev, NULL);
1266 kfree(sm);
1267 err1:
1268 return err;
1269 }
1270
1271 static void sm501_remove_sub(struct sm501_devdata *sm,
1272 struct sm501_device *smdev)
1273 {
1274 list_del(&smdev->list);
1275 platform_device_unregister(&smdev->pdev);
1276 }
1277
1278 static void sm501_dev_remove(struct sm501_devdata *sm)
1279 {
1280 struct sm501_device *smdev, *tmp;
1281
1282 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1283 sm501_remove_sub(sm, smdev);
1284
1285 device_remove_file(sm->dev, &dev_attr_dbg_regs);
1286 }
1287
1288 static void sm501_pci_remove(struct pci_dev *dev)
1289 {
1290 struct sm501_devdata *sm = pci_get_drvdata(dev);
1291
1292 sm501_dev_remove(sm);
1293 iounmap(sm->regs);
1294
1295 release_resource(sm->regs_claim);
1296 kfree(sm->regs_claim);
1297
1298 pci_set_drvdata(dev, NULL);
1299 pci_disable_device(dev);
1300 }
1301
1302 static int sm501_plat_remove(struct platform_device *dev)
1303 {
1304 struct sm501_devdata *sm = platform_get_drvdata(dev);
1305
1306 sm501_dev_remove(sm);
1307 iounmap(sm->regs);
1308
1309 release_resource(sm->regs_claim);
1310 kfree(sm->regs_claim);
1311
1312 return 0;
1313 }
1314
1315 static struct pci_device_id sm501_pci_tbl[] = {
1316 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1317 { 0, },
1318 };
1319
1320 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1321
1322 static struct pci_driver sm501_pci_drv = {
1323 .name = "sm501",
1324 .id_table = sm501_pci_tbl,
1325 .probe = sm501_pci_probe,
1326 .remove = sm501_pci_remove,
1327 };
1328
1329 static struct platform_driver sm501_plat_drv = {
1330 .driver = {
1331 .name = "sm501",
1332 .owner = THIS_MODULE,
1333 },
1334 .probe = sm501_plat_probe,
1335 .remove = sm501_plat_remove,
1336 .suspend = sm501_plat_suspend,
1337 .resume = sm501_plat_resume,
1338 };
1339
1340 static int __init sm501_base_init(void)
1341 {
1342 platform_driver_register(&sm501_plat_drv);
1343 return pci_register_driver(&sm501_pci_drv);
1344 }
1345
1346 static void __exit sm501_base_exit(void)
1347 {
1348 platform_driver_unregister(&sm501_plat_drv);
1349 pci_unregister_driver(&sm501_pci_drv);
1350 }
1351
1352 module_init(sm501_base_init);
1353 module_exit(sm501_base_exit);
1354
1355 MODULE_DESCRIPTION("SM501 Core Driver");
1356 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1357 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support