drivers/net/wireless/ath5k/ath5k.h

   1 /*
   2  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _ATH5K_H
  19 #define _ATH5K_H
  20
  21 /* Set this to 1 to disable regulatory domain restrictions for channel tests.
  22  * WARNING: This is for debuging only and has side effects (eg. scan takes too
  23  * long and results timeouts). It's also illegal to tune to some of the
  24  * supported frequencies in some countries, so use this at your own risk,
  25  * you've been warned. */
  26 #define CHAN_DEBUG      0
  27
  28 #include <linux/io.h>
  29 #include <linux/types.h>
  30 #include <net/mac80211.h>
  31
  32 #include "hw.h"
  33
  34 /* PCI IDs */
  35 #define PCI_DEVICE_ID_ATHEROS_AR5210            0x0007 /* AR5210 */
  36 #define PCI_DEVICE_ID_ATHEROS_AR5311            0x0011 /* AR5311 */
  37 #define PCI_DEVICE_ID_ATHEROS_AR5211            0x0012 /* AR5211 */
  38 #define PCI_DEVICE_ID_ATHEROS_AR5212            0x0013 /* AR5212 */
  39 #define PCI_DEVICE_ID_3COM_3CRDAG675            0x0013 /* 3CRDAG675 (Atheros AR5212) */
  40 #define PCI_DEVICE_ID_3COM_2_3CRPAG175          0x0013 /* 3CRPAG175 (Atheros AR5212) */
  41 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP         0x0207 /* AR5210 (Early) */
  42 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM        0x1014 /* AR5212 (IBM MiniPCI) */
  43 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT    0x1107 /* AR5210 (no eeprom) */
  44 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT    0x1113 /* AR5212 (no eeprom) */
  45 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT    0x1112 /* AR5211 (no eeprom) */
  46 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA       0xf013 /* AR5212 (emulation board) */
  47 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY     0xff12 /* AR5211 (emulation board) */
  48 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B    0xf11b /* AR5211 (emulation board) */
  49 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2       0x0052 /* AR5312 WMAC (AP31) */
  50 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7       0x0057 /* AR5312 WMAC (AP30-040) */
  51 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8       0x0058 /* AR5312 WMAC (AP43-030) */
  52 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014       0x0014 /* AR5212 compatible */
  53 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015       0x0015 /* AR5212 compatible */
  54 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016       0x0016 /* AR5212 compatible */
  55 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017       0x0017 /* AR5212 compatible */
  56 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018       0x0018 /* AR5212 compatible */
  57 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019       0x0019 /* AR5212 compatible */
  58 #define PCI_DEVICE_ID_ATHEROS_AR2413            0x001a /* AR2413 (Griffin-lite) */
  59 #define PCI_DEVICE_ID_ATHEROS_AR5413            0x001b /* AR5413 (Eagle) */
  60 #define PCI_DEVICE_ID_ATHEROS_AR5424            0x001c /* AR5424 (Condor PCI-E) */
  61 #define PCI_DEVICE_ID_ATHEROS_AR5416            0x0023 /* AR5416 */
  62 #define PCI_DEVICE_ID_ATHEROS_AR5418            0x0024 /* AR5418 */
  63
  64 /****************************\
  65   GENERIC DRIVER DEFINITIONS
  66 \****************************/
  67
  68 #define ATH5K_PRINTF(fmt, ...)   printk("%s: " fmt, __func__, ##__VA_ARGS__)
  69
  70 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
  71         printk(_level "ath5k %s: " _fmt, \
  72                 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
  73                 ##__VA_ARGS__)
  74
  75 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
  76         if (net_ratelimit()) \
  77                 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
  78         } while (0)
  79
  80 #define ATH5K_INFO(_sc, _fmt, ...) \
  81         ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
  82
  83 #define ATH5K_WARN(_sc, _fmt, ...) \
  84         ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
  85
  86 #define ATH5K_ERR(_sc, _fmt, ...) \
  87         ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
  88
  89 /*
  90  * Some tuneable values (these should be changeable by the user)
  91  */
  92 #define AR5K_TUNE_DMA_BEACON_RESP               2
  93 #define AR5K_TUNE_SW_BEACON_RESP                10
  94 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF       0
  95 #define AR5K_TUNE_RADAR_ALERT                   false
  96 #define AR5K_TUNE_MIN_TX_FIFO_THRES             1
  97 #define AR5K_TUNE_MAX_TX_FIFO_THRES             ((IEEE80211_MAX_LEN / 64) + 1)
  98 #define AR5K_TUNE_REGISTER_TIMEOUT              20000
  99 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
 100  * be the max value. */
 101 #define AR5K_TUNE_RSSI_THRES                   129
 102 /* This must be set when setting the RSSI threshold otherwise it can
 103  * prevent a reset. If AR5K_RSSI_THR is read after writing to it
 104  * the BMISS_THRES will be seen as 0, seems harware doesn't keep
 105  * track of it. Max value depends on harware. For AR5210 this is just 7.
 106  * For AR5211+ this seems to be up to 255. */
 107 #define AR5K_TUNE_BMISS_THRES                  7
 108 #define AR5K_TUNE_REGISTER_DWELL_TIME           20000
 109 #define AR5K_TUNE_BEACON_INTERVAL               100
 110 #define AR5K_TUNE_AIFS                          2
 111 #define AR5K_TUNE_AIFS_11B                      2
 112 #define AR5K_TUNE_AIFS_XR                       0
 113 #define AR5K_TUNE_CWMIN                         15
 114 #define AR5K_TUNE_CWMIN_11B                     31
 115 #define AR5K_TUNE_CWMIN_XR                      3
 116 #define AR5K_TUNE_CWMAX                         1023
 117 #define AR5K_TUNE_CWMAX_11B                     1023
 118 #define AR5K_TUNE_CWMAX_XR                      7
 119 #define AR5K_TUNE_NOISE_FLOOR                   -72
 120 #define AR5K_TUNE_MAX_TXPOWER                   60
 121 #define AR5K_TUNE_DEFAULT_TXPOWER               30
 122 #define AR5K_TUNE_TPC_TXPOWER                   true
 123 #define AR5K_TUNE_ANT_DIVERSITY                 true
 124 #define AR5K_TUNE_HWTXTRIES                     4
 125
 126 /* token to use for aifs, cwmin, cwmax in MadWiFi */
 127 #define AR5K_TXQ_USEDEFAULT     ((u32) -1)
 128
 129 /* GENERIC CHIPSET DEFINITIONS */
 130
 131 /* MAC Chips */
 132 enum ath5k_version {
 133         AR5K_AR5210     = 0,
 134         AR5K_AR5211     = 1,
 135         AR5K_AR5212     = 2,
 136 };
 137
 138 /* PHY Chips */
 139 enum ath5k_radio {
 140         AR5K_RF5110     = 0,
 141         AR5K_RF5111     = 1,
 142         AR5K_RF5112     = 2,
 143         AR5K_RF2413     = 3,
 144         AR5K_RF5413     = 4,
 145 };
 146
 147 /*
 148  * Common silicon revision/version values
 149  */
 150
 151 enum ath5k_srev_type {
 152         AR5K_VERSION_VER,
 153         AR5K_VERSION_RAD,
 154 };
 155
 156 struct ath5k_srev_name {
 157         const char              *sr_name;
 158         enum ath5k_srev_type    sr_type;
 159         u_int                   sr_val;
 160 };
 161
 162 #define AR5K_SREV_UNKNOWN       0xffff
 163
 164 #define AR5K_SREV_VER_AR5210    0x00
 165 #define AR5K_SREV_VER_AR5311    0x10
 166 #define AR5K_SREV_VER_AR5311A   0x20
 167 #define AR5K_SREV_VER_AR5311B   0x30
 168 #define AR5K_SREV_VER_AR5211    0x40
 169 #define AR5K_SREV_VER_AR5212    0x50
 170 #define AR5K_SREV_VER_AR5213    0x55
 171 #define AR5K_SREV_VER_AR5213A   0x59
 172 #define AR5K_SREV_VER_AR2413    0x78
 173 #define AR5K_SREV_VER_AR2414    0x79
 174 #define AR5K_SREV_VER_AR2424    0xa0 /* PCI-E */
 175 #define AR5K_SREV_VER_AR5424    0xa3 /* PCI-E */
 176 #define AR5K_SREV_VER_AR5413    0xa4
 177 #define AR5K_SREV_VER_AR5414    0xa5
 178 #define AR5K_SREV_VER_AR5416    0xc0 /* PCI-E */
 179 #define AR5K_SREV_VER_AR5418    0xca /* PCI-E */
 180 #define AR5K_SREV_VER_AR2425    0xe2 /* PCI-E */
 181
 182 #define AR5K_SREV_RAD_5110      0x00
 183 #define AR5K_SREV_RAD_5111      0x10
 184 #define AR5K_SREV_RAD_5111A     0x15
 185 #define AR5K_SREV_RAD_2111      0x20
 186 #define AR5K_SREV_RAD_5112      0x30
 187 #define AR5K_SREV_RAD_5112A     0x35
 188 #define AR5K_SREV_RAD_2112      0x40
 189 #define AR5K_SREV_RAD_2112A     0x45
 190 #define AR5K_SREV_RAD_SC0       0x56    /* Found on 2413/2414 */
 191 #define AR5K_SREV_RAD_SC1       0x63    /* Found on 5413/5414 */
 192 #define AR5K_SREV_RAD_SC2       0xa2    /* Found on 2424-5/5424 */
 193 #define AR5K_SREV_RAD_5133      0xc0    /* MIMO found on 5418 */
 194
 195 /* IEEE defs */
 196
 197 #define IEEE80211_MAX_LEN       2500
 198
 199 /* TODO add support to mac80211 for vendor-specific rates and modes */
 200
 201 /*
 202  * Some of this information is based on Documentation from:
 203  *
 204  * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
 205  *
 206  * Modulation for Atheros' eXtended Range - range enhancing extension that is
 207  * supposed to double the distance an Atheros client device can keep a
 208  * connection with an Atheros access point. This is achieved by increasing
 209  * the receiver sensitivity up to, -105dBm, which is about 20dB above what
 210  * the 802.11 specifications demand. In addition, new (proprietary) data rates
 211  * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
 212  *
 213  * Please note that can you either use XR or TURBO but you cannot use both,
 214  * they are exclusive.
 215  *
 216  */
 217 #define MODULATION_XR           0x00000200
 218 /*
 219  * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
 220  * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
 221  * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
 222  * channels. To use this feature your Access Point must also suport it.
 223  * There is also a distinction between "static" and "dynamic" turbo modes:
 224  *
 225  * - Static: is the dumb version: devices set to this mode stick to it until
 226  *     the mode is turned off.
 227  * - Dynamic: is the intelligent version, the network decides itself if it
 228  *     is ok to use turbo. As soon as traffic is detected on adjacent channels
 229  *     (which would get used in turbo mode), or when a non-turbo station joins
 230  *     the network, turbo mode won't be used until the situation changes again.
 231  *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
 232  *     monitors the used radio band in order to decide whether turbo mode may
 233  *     be used or not.
 234  *
 235  * This article claims Super G sticks to bonding of channels 5 and 6 for
 236  * USA:
 237  *
 238  * http://www.pcworld.com/article/id,113428-page,1/article.html
 239  *
 240  * The channel bonding seems to be driver specific though. In addition to
 241  * deciding what channels will be used, these "Turbo" modes are accomplished
 242  * by also enabling the following features:
 243  *
 244  * - Bursting: allows multiple frames to be sent at once, rather than pausing
 245  *     after each frame. Bursting is a standards-compliant feature that can be
 246  *     used with any Access Point.
 247  * - Fast frames: increases the amount of information that can be sent per
 248  *     frame, also resulting in a reduction of transmission overhead. It is a
 249  *     proprietary feature that needs to be supported by the Access Point.
 250  * - Compression: data frames are compressed in real time using a Lempel Ziv
 251  *     algorithm. This is done transparently. Once this feature is enabled,
 252  *     compression and decompression takes place inside the chipset, without
 253  *     putting additional load on the host CPU.
 254  *
 255  */
 256 #define MODULATION_TURBO        0x00000080
 257
 258 enum ath5k_driver_mode {
 259         AR5K_MODE_11A           =       0,
 260         AR5K_MODE_11A_TURBO     =       1,
 261         AR5K_MODE_11B           =       2,
 262         AR5K_MODE_11G           =       3,
 263         AR5K_MODE_11G_TURBO     =       4,
 264         AR5K_MODE_XR            =       0,
 265         AR5K_MODE_MAX           =       5
 266 };
 267
 268 /* adding this flag to rate_code enables short preamble, see ar5212_reg.h */
 269 #define AR5K_SET_SHORT_PREAMBLE 0x04
 270
 271 #define HAS_SHPREAMBLE(_ix) \
 272         (rt->rates[_ix].modulation == IEEE80211_RATE_SHORT_PREAMBLE)
 273 #define SHPREAMBLE_FLAG(_ix) \
 274         (HAS_SHPREAMBLE(_ix) ? AR5K_SET_SHORT_PREAMBLE : 0)
 275
 276
 277 /****************\
 278   TX DEFINITIONS
 279 \****************/
 280
 281 /*
 282  * TX Status
 283  */
 284 struct ath5k_tx_status {
 285         u16     ts_seqnum;
 286         u16     ts_tstamp;
 287         u8      ts_status;
 288         u8      ts_rate;
 289         s8      ts_rssi;
 290         u8      ts_shortretry;
 291         u8      ts_longretry;
 292         u8      ts_virtcol;
 293         u8      ts_antenna;
 294 };
 295
 296 #define AR5K_TXSTAT_ALTRATE     0x80
 297 #define AR5K_TXERR_XRETRY       0x01
 298 #define AR5K_TXERR_FILT         0x02
 299 #define AR5K_TXERR_FIFO         0x04
 300
 301 /**
 302  * enum ath5k_tx_queue - Queue types used to classify tx queues.
 303  * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
 304  * @AR5K_TX_QUEUE_DATA: A normal data queue
 305  * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
 306  * @AR5K_TX_QUEUE_BEACON: The beacon queue
 307  * @AR5K_TX_QUEUE_CAB: The after-beacon queue
 308  * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
 309  */
 310 enum ath5k_tx_queue {
 311         AR5K_TX_QUEUE_INACTIVE = 0,
 312         AR5K_TX_QUEUE_DATA,
 313         AR5K_TX_QUEUE_XR_DATA,
 314         AR5K_TX_QUEUE_BEACON,
 315         AR5K_TX_QUEUE_CAB,
 316         AR5K_TX_QUEUE_UAPSD,
 317 };
 318
 319 #define AR5K_NUM_TX_QUEUES              10
 320 #define AR5K_NUM_TX_QUEUES_NOQCU        2
 321
 322 /*
 323  * Queue syb-types to classify normal data queues.
 324  * These are the 4 Access Categories as defined in
 325  * WME spec. 0 is the lowest priority and 4 is the
 326  * highest. Normal data that hasn't been classified
 327  * goes to the Best Effort AC.
 328  */
 329 enum ath5k_tx_queue_subtype {
 330         AR5K_WME_AC_BK = 0,     /*Background traffic*/
 331         AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
 332         AR5K_WME_AC_VI,         /*Video traffic*/
 333         AR5K_WME_AC_VO,         /*Voice traffic*/
 334 };
 335
 336 /*
 337  * Queue ID numbers as returned by the hw functions, each number
 338  * represents a hw queue. If hw does not support hw queues
 339  * (eg 5210) all data goes in one queue. These match
 340  * d80211 definitions (net80211/MadWiFi don't use them).
 341  */
 342 enum ath5k_tx_queue_id {
 343         AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
 344         AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
 345         AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
 346         AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
 347         AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
 348         AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
 349         AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
 350         AR5K_TX_QUEUE_ID_UAPSD          = 8,
 351         AR5K_TX_QUEUE_ID_XR_DATA        = 9,
 352 };
 353
 354
 355 /*
 356  * Flags to set hw queue's parameters...
 357  */
 358 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE            0x0001  /* Enable TXOK interrupt */
 359 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE           0x0002  /* Enable TXERR interrupt */
 360 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE           0x0004  /* Enable TXEOL interrupt -not used- */
 361 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE          0x0008  /* Enable TXDESC interrupt -not used- */
 362 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE           0x0010  /* Enable TXURN interrupt */
 363 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0020  /* Disable random post-backoff */
 364 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040  /* Enable ready time expiry policy (?)*/
 365 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080  /* Enable backoff while bursting */
 366 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x0100  /* Disable backoff while bursting */
 367 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x0200  /* Enable hw compression -not implemented-*/
 368
 369 /*
 370  * A struct to hold tx queue's parameters
 371  */
 372 struct ath5k_txq_info {
 373         enum ath5k_tx_queue tqi_type;
 374         enum ath5k_tx_queue_subtype tqi_subtype;
 375         u16     tqi_flags;      /* Tx queue flags (see above) */
 376         u32     tqi_aifs;       /* Arbitrated Interframe Space */
 377         s32     tqi_cw_min;     /* Minimum Contention Window */
 378         s32     tqi_cw_max;     /* Maximum Contention Window */
 379         u32     tqi_cbr_period; /* Constant bit rate period */
 380         u32     tqi_cbr_overflow_limit;
 381         u32     tqi_burst_time;
 382         u32     tqi_ready_time; /* Not used */
 383 };
 384
 385 /*
 386  * Transmit packet types.
 387  * These are not fully used inside OpenHAL yet
 388  */
 389 enum ath5k_pkt_type {
 390         AR5K_PKT_TYPE_NORMAL            = 0,
 391         AR5K_PKT_TYPE_ATIM              = 1,
 392         AR5K_PKT_TYPE_PSPOLL            = 2,
 393         AR5K_PKT_TYPE_BEACON            = 3,
 394         AR5K_PKT_TYPE_PROBE_RESP        = 4,
 395         AR5K_PKT_TYPE_PIFS              = 5,
 396 };
 397
 398 /*
 399  * TX power and TPC settings
 400  */
 401 #define AR5K_TXPOWER_OFDM(_r, _v)       (                       \
 402         ((0 & 1) << ((_v) + 6)) |                               \
 403         (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v))     \
 404 )
 405
 406 #define AR5K_TXPOWER_CCK(_r, _v)        (                       \
 407         (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
 408 )
 409
 410 /*
 411  * DMA size definitions (2^n+2)
 412  */
 413 enum ath5k_dmasize {
 414         AR5K_DMASIZE_4B = 0,
 415         AR5K_DMASIZE_8B,
 416         AR5K_DMASIZE_16B,
 417         AR5K_DMASIZE_32B,
 418         AR5K_DMASIZE_64B,
 419         AR5K_DMASIZE_128B,
 420         AR5K_DMASIZE_256B,
 421         AR5K_DMASIZE_512B
 422 };
 423
 424
 425 /****************\
 426   RX DEFINITIONS
 427 \****************/
 428
 429 /*
 430  * RX Status
 431  */
 432 struct ath5k_rx_status {
 433         u16     rs_datalen;
 434         u16     rs_tstamp;
 435         u8      rs_status;
 436         u8      rs_phyerr;
 437         s8      rs_rssi;
 438         u8      rs_keyix;
 439         u8      rs_rate;
 440         u8      rs_antenna;
 441         u8      rs_more;
 442 };
 443
 444 #define AR5K_RXERR_CRC          0x01
 445 #define AR5K_RXERR_PHY          0x02
 446 #define AR5K_RXERR_FIFO         0x04
 447 #define AR5K_RXERR_DECRYPT      0x08
 448 #define AR5K_RXERR_MIC          0x10
 449 #define AR5K_RXKEYIX_INVALID    ((u8) - 1)
 450 #define AR5K_TXKEYIX_INVALID    ((u32) - 1)
 451
 452 struct ath5k_mib_stats {
 453         u32     ackrcv_bad;
 454         u32     rts_bad;
 455         u32     rts_good;
 456         u32     fcs_bad;
 457         u32     beacons;
 458 };
 459
 460
 461 /**************************\
 462  BEACON TIMERS DEFINITIONS
 463 \**************************/
 464
 465 #define AR5K_BEACON_PERIOD      0x0000ffff
 466 #define AR5K_BEACON_ENA         0x00800000 /*enable beacon xmit*/
 467 #define AR5K_BEACON_RESET_TSF   0x01000000 /*force a TSF reset*/
 468
 469 #if 0
 470 /**
 471  * struct ath5k_beacon_state - Per-station beacon timer state.
 472  * @bs_interval: in TU's, can also include the above flags
 473  * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
 474  *      Point Coordination Function capable AP
 475  */
 476 struct ath5k_beacon_state {
 477         u32     bs_next_beacon;
 478         u32     bs_next_dtim;
 479         u32     bs_interval;
 480         u8      bs_dtim_period;
 481         u8      bs_cfp_period;
 482         u16     bs_cfp_max_duration;
 483         u16     bs_cfp_du_remain;
 484         u16     bs_tim_offset;
 485         u16     bs_sleep_duration;
 486         u16     bs_bmiss_threshold;
 487         u32     bs_cfp_next;
 488 };
 489 #endif
 490
 491
 492 /*
 493  * TSF to TU conversion:
 494  *
 495  * TSF is a 64bit value in usec (microseconds).
 496  * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
 497  * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
 498  */
 499 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
 500
 501
 502 /********************\
 503   COMMON DEFINITIONS
 504 \********************/
 505
 506 /*
 507  * Atheros hardware descriptor
 508  * This is read and written to by the hardware
 509  */
 510 struct ath5k_desc {
 511         u32     ds_link;        /* physical address of the next descriptor */
 512         u32     ds_data;        /* physical address of data buffer (skb) */
 513
 514         union {
 515                 struct ath5k_hw_5210_tx_desc    ds_tx5210;
 516                 struct ath5k_hw_5212_tx_desc    ds_tx5212;
 517                 struct ath5k_hw_all_rx_desc     ds_rx;
 518         } ud;
 519 } __packed;
 520
 521 #define AR5K_RXDESC_INTREQ      0x0020
 522
 523 #define AR5K_TXDESC_CLRDMASK    0x0001
 524 #define AR5K_TXDESC_NOACK       0x0002  /*[5211+]*/
 525 #define AR5K_TXDESC_RTSENA      0x0004
 526 #define AR5K_TXDESC_CTSENA      0x0008
 527 #define AR5K_TXDESC_INTREQ      0x0010
 528 #define AR5K_TXDESC_VEOL        0x0020  /*[5211+]*/
 529
 530 #define AR5K_SLOT_TIME_9        396
 531 #define AR5K_SLOT_TIME_20       880
 532 #define AR5K_SLOT_TIME_MAX      0xffff
 533
 534 /* channel_flags */
 535 #define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
 536 #define CHANNEL_TURBO   0x0010  /* Turbo Channel */
 537 #define CHANNEL_CCK     0x0020  /* CCK channel */
 538 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
 539 #define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
 540 #define CHANNEL_5GHZ    0x0100  /* 5GHz channel */
 541 #define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed */
 542 #define CHANNEL_DYN     0x0400  /* Dynamic CCK-OFDM channel (for g operation) */
 543 #define CHANNEL_XR      0x0800  /* XR channel */
 544
 545 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
 546 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
 547 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
 548 #define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 549 #define CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 550 #define CHANNEL_108A    CHANNEL_T
 551 #define CHANNEL_108G    CHANNEL_TG
 552 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 553
 554 #define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
 555                 CHANNEL_TURBO)
 556
 557 #define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
 558 #define CHANNEL_MODES           CHANNEL_ALL
 559
 560 /*
 561  * Used internaly in OpenHAL (ar5211.c/ar5212.c
 562  * for reset_tx_queue). Also see struct struct ieee80211_channel.
 563  */
 564 #define IS_CHAN_XR(_c)  ((_c.hw_value & CHANNEL_XR) != 0)
 565 #define IS_CHAN_B(_c)   ((_c.hw_value & CHANNEL_B) != 0)
 566
 567 /*
 568  * The following structure will be used to map 2GHz channels to
 569  * 5GHz Atheros channels.
 570  */
 571 struct ath5k_athchan_2ghz {
 572         u32     a2_flags;
 573         u16     a2_athchan;
 574 };
 575
 576 /*
 577  * Rate definitions
 578  * TODO: Clean them up or move them on mac80211 -most of these infos are
 579  *       used by the rate control algorytm on MadWiFi.
 580  */
 581
 582 /* Max number of rates on the rate table and what it seems
 583  * Atheros hardware supports */
 584 #define AR5K_MAX_RATES 32
 585
 586 /**
 587  * struct ath5k_rate - rate structure
 588  * @valid: is this a valid rate for rate control (remove)
 589  * @modulation: respective mac80211 modulation
 590  * @rate_kbps: rate in kbit/s
 591  * @rate_code: hardware rate value, used in &struct ath5k_desc, on RX on
 592  *     &struct ath5k_rx_status.rs_rate and on TX on
 593  *     &struct ath5k_tx_status.ts_rate. Seems the ar5xxx harware supports
 594  *     up to 32 rates, indexed by 1-32. This means we really only need
 595  *     6 bits for the rate_code.
 596  * @dot11_rate: respective IEEE-802.11 rate value
 597  * @control_rate: index of rate assumed to be used to send control frames.
 598  *     This can be used to set override the value on the rate duration
 599  *     registers. This is only useful if we can override in the harware at
 600  *     what rate we want to send control frames at. Note that IEEE-802.11
 601  *     Ch. 9.6 (after IEEE 802.11g changes) defines the rate at which we
 602  *     should send ACK/CTS, if we change this value we can be breaking
 603  *     the spec.
 604  *
 605  * This structure is used to get the RX rate or set the TX rate on the
 606  * hardware descriptors. It is also used for internal modulation control
 607  * and settings.
 608  *
 609  * On RX after the &struct ath5k_desc is parsed by the appropriate
 610  * ah_proc_rx_desc() the respective hardware rate value is set in
 611  * &struct ath5k_rx_status.rs_rate. On TX the desired rate is set in
 612  * &struct ath5k_tx_status.ts_rate which is later used to setup the
 613  * &struct ath5k_desc correctly. This is the hardware rate map we are
 614  * aware of:
 615  *
 616  * rate_code   1       2       3       4       5       6       7       8
 617  * rate_kbps   3000    1000    ?       ?       ?       2000    500     48000
 618  *
 619  * rate_code   9       10      11      12      13      14      15      16
 620  * rate_kbps   24000   12000   6000    54000   36000   18000   9000    ?
 621  *
 622  * rate_code   17      18      19      20      21      22      23      24
 623  * rate_kbps   ?       ?       ?       ?       ?       ?       ?       11000
 624  *
 625  * rate_code   25      26      27      28      29      30      31      32
 626  * rate_kbps   5500    2000    1000    ?       ?       ?       ?       ?
 627  *
 628  */
 629 struct ath5k_rate {
 630         u8      valid;
 631         u32     modulation;
 632         u16     rate_kbps;
 633         u8      rate_code;
 634         u8      dot11_rate;
 635         u8      control_rate;
 636 };
 637
 638 /* XXX: GRR all this stuff to get leds blinking ??? (check out setcurmode) */
 639 struct ath5k_rate_table {
 640         u16     rate_count;
 641         u8      rate_code_to_index[AR5K_MAX_RATES];     /* Back-mapping */
 642         struct ath5k_rate rates[AR5K_MAX_RATES];
 643 };
 644
 645 /*
 646  * Rate tables...
 647  * TODO: CLEAN THIS !!!
 648  */
 649 #define AR5K_RATES_11A { 8, {                                   \
 650         255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0,     \
 651         7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255,     \
 652         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 653         { 1, 0, 6000, 11, 140, 0 },             \
 654         { 1, 0, 9000, 15, 18, 0 },              \
 655         { 1, 0, 12000, 10, 152, 2 },            \
 656         { 1, 0, 18000, 14, 36, 2 },             \
 657         { 1, 0, 24000, 9, 176, 4 },             \
 658         { 1, 0, 36000, 13, 72, 4 },             \
 659         { 1, 0, 48000, 8, 96, 4 },              \
 660         { 1, 0, 54000, 12, 108, 4 } }           \
 661 }
 662
 663 #define AR5K_RATES_11B { 4, {                                           \
 664         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,     \
 665         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,     \
 666         3, 2, 1, 0, 255, 255, 255, 255 }, {                             \
 667         { 1, 0, 1000, 27, 130, 0 },     \
 668         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 132, 1 }, \
 669         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 139, 1 }, \
 670         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 150, 1 } }       \
 671 }
 672
 673 #define AR5K_RATES_11G { 12, {                                  \
 674         255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4,    \
 675         11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 676         3, 2, 1, 0, 255, 255, 255, 255 }, {                     \
 677         { 1, 0, 1000, 27, 2, 0 },               \
 678         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 4, 1 },           \
 679         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 11, 1 },          \
 680         { 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 22, 1 }, \
 681         { 0, 0, 6000, 11, 12, 4 },      \
 682         { 0, 0, 9000, 15, 18, 4 },      \
 683         { 1, 0, 12000, 10, 24, 6 },     \
 684         { 1, 0, 18000, 14, 36, 6 },     \
 685         { 1, 0, 24000, 9, 48, 8 },      \
 686         { 1, 0, 36000, 13, 72, 8 },     \
 687         { 1, 0, 48000, 8, 96, 8 },      \
 688         { 1, 0, 54000, 12, 108, 8 } }   \
 689 }
 690
 691 #define AR5K_RATES_TURBO { 8, {                                 \
 692         255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0,     \
 693         7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255,     \
 694         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 695         { 1, MODULATION_TURBO, 6000, 11, 140, 0 },      \
 696         { 1, MODULATION_TURBO, 9000, 15, 18, 0 },       \
 697         { 1, MODULATION_TURBO, 12000, 10, 152, 2 },     \
 698         { 1, MODULATION_TURBO, 18000, 14, 36, 2 },      \
 699         { 1, MODULATION_TURBO, 24000, 9, 176, 4 },      \
 700         { 1, MODULATION_TURBO, 36000, 13, 72, 4 },      \
 701         { 1, MODULATION_TURBO, 48000, 8, 96, 4 },       \
 702         { 1, MODULATION_TURBO, 54000, 12, 108, 4 } }    \
 703 }
 704
 705 #define AR5K_RATES_XR { 12, {                                   \
 706         255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4,            \
 707         11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 708         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 709         { 1, MODULATION_XR, 500, 7, 129, 0 },           \
 710         { 1, MODULATION_XR, 1000, 2, 139, 1 },          \
 711         { 1, MODULATION_XR, 2000, 6, 150, 2 },          \
 712         { 1, MODULATION_XR, 3000, 1, 150, 3 },          \
 713         { 1, 0, 6000, 11, 140, 4 },     \
 714         { 1, 0, 9000, 15, 18, 4 },      \
 715         { 1, 0, 12000, 10, 152, 6 },    \
 716         { 1, 0, 18000, 14, 36, 6 },     \
 717         { 1, 0, 24000, 9, 176, 8 },     \
 718         { 1, 0, 36000, 13, 72, 8 },     \
 719         { 1, 0, 48000, 8, 96, 8 },      \
 720         { 1, 0, 54000, 12, 108, 8 } }   \
 721 }
 722
 723 /*
 724  * Crypto definitions
 725  */
 726
 727 #define AR5K_KEYCACHE_SIZE      8
 728
 729 /***********************\
 730  HW RELATED DEFINITIONS
 731 \***********************/
 732
 733 /*
 734  * Misc definitions
 735  */
 736 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
 737
 738 #define AR5K_ASSERT_ENTRY(_e, _s) do {          \
 739         if (_e >= _s)                           \
 740                 return (false);                 \
 741 } while (0)
 742
 743
 744 enum ath5k_ant_setting {
 745         AR5K_ANT_VARIABLE       = 0,    /* variable by programming */
 746         AR5K_ANT_FIXED_A        = 1,    /* fixed to 11a frequencies */
 747         AR5K_ANT_FIXED_B        = 2,    /* fixed to 11b frequencies */
 748         AR5K_ANT_MAX            = 3,
 749 };
 750
 751 /*
 752  * Hardware interrupt abstraction
 753  */
 754
 755 /**
 756  * enum ath5k_int - Hardware interrupt masks helpers
 757  *
 758  * @AR5K_INT_RX: mask to identify received frame interrupts, of type
 759  *      AR5K_ISR_RXOK or AR5K_ISR_RXERR
 760  * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
 761  * @AR5K_INT_RXNOFRM: No frame received (?)
 762  * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
 763  *      Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
 764  *      LinkPtr is NULL. For more details, refer to:
 765  *      http://www.freepatentsonline.com/20030225739.html
 766  * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
 767  *      Note that Rx overrun is not always fatal, on some chips we can continue
 768  *      operation without reseting the card, that's why int_fatal is not
 769  *      common for all chips.
 770  * @AR5K_INT_TX: mask to identify received frame interrupts, of type
 771  *      AR5K_ISR_TXOK or AR5K_ISR_TXERR
 772  * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
 773  * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
 774  *      We currently do increments on interrupt by
 775  *      (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
 776  * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
 777  *      checked. We should do this with ath5k_hw_update_mib_counters() but
 778  *      it seems we should also then do some noise immunity work.
 779  * @AR5K_INT_RXPHY: RX PHY Error
 780  * @AR5K_INT_RXKCM: ??
 781  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
 782  *      beacon that must be handled in software. The alternative is if you
 783  *      have VEOL support, in that case you let the hardware deal with things.
 784  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
 785  *      beacons from the AP have associated with, we should probably try to
 786  *      reassociate. When in IBSS mode this might mean we have not received
 787  *      any beacons from any local stations. Note that every station in an
 788  *      IBSS schedules to send beacons at the Target Beacon Transmission Time
 789  *      (TBTT) with a random backoff.
 790  * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
 791  * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
 792  *      until properly handled
 793  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
 794  *      errors. These types of errors we can enable seem to be of type
 795  *      AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
 796  * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
 797  * @AR5K_INT_NOCARD: signals the card has been removed
 798  * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
 799  *      bit value
 800  *
 801  * These are mapped to take advantage of some common bits
 802  * between the MACs, to be able to set intr properties
 803  * easier. Some of them are not used yet inside hw.c. Most map
 804  * to the respective hw interrupt value as they are common amogst different
 805  * MACs.
 806  */
 807 enum ath5k_int {
 808         AR5K_INT_RX     = 0x00000001, /* Not common */
 809         AR5K_INT_RXDESC = 0x00000002,
 810         AR5K_INT_RXNOFRM = 0x00000008,
 811         AR5K_INT_RXEOL  = 0x00000010,
 812         AR5K_INT_RXORN  = 0x00000020,
 813         AR5K_INT_TX     = 0x00000040, /* Not common */
 814         AR5K_INT_TXDESC = 0x00000080,
 815         AR5K_INT_TXURN  = 0x00000800,
 816         AR5K_INT_MIB    = 0x00001000,
 817         AR5K_INT_RXPHY  = 0x00004000,
 818         AR5K_INT_RXKCM  = 0x00008000,
 819         AR5K_INT_SWBA   = 0x00010000,
 820         AR5K_INT_BMISS  = 0x00040000,
 821         AR5K_INT_BNR    = 0x00100000, /* Not common */
 822         AR5K_INT_GPIO   = 0x01000000,
 823         AR5K_INT_FATAL  = 0x40000000, /* Not common */
 824         AR5K_INT_GLOBAL = 0x80000000,
 825
 826         AR5K_INT_COMMON  = AR5K_INT_RXNOFRM
 827                         | AR5K_INT_RXDESC
 828                         | AR5K_INT_RXEOL
 829                         | AR5K_INT_RXORN
 830                         | AR5K_INT_TXURN
 831                         | AR5K_INT_TXDESC
 832                         | AR5K_INT_MIB
 833                         | AR5K_INT_RXPHY
 834                         | AR5K_INT_RXKCM
 835                         | AR5K_INT_SWBA
 836                         | AR5K_INT_BMISS
 837                         | AR5K_INT_GPIO,
 838         AR5K_INT_NOCARD = 0xffffffff
 839 };
 840
 841 /*
 842  * Power management
 843  */
 844 enum ath5k_power_mode {
 845         AR5K_PM_UNDEFINED = 0,
 846         AR5K_PM_AUTO,
 847         AR5K_PM_AWAKE,
 848         AR5K_PM_FULL_SLEEP,
 849         AR5K_PM_NETWORK_SLEEP,
 850 };
 851
 852 /*
 853  * These match net80211 definitions (not used in
 854  * d80211).
 855  */
 856 #define AR5K_LED_INIT   0 /*IEEE80211_S_INIT*/
 857 #define AR5K_LED_SCAN   1 /*IEEE80211_S_SCAN*/
 858 #define AR5K_LED_AUTH   2 /*IEEE80211_S_AUTH*/
 859 #define AR5K_LED_ASSOC  3 /*IEEE80211_S_ASSOC*/
 860 #define AR5K_LED_RUN    4 /*IEEE80211_S_RUN*/
 861
 862 /* GPIO-controlled software LED */
 863 #define AR5K_SOFTLED_PIN        0
 864 #define AR5K_SOFTLED_ON         0
 865 #define AR5K_SOFTLED_OFF        1
 866
 867 /*
 868  * Chipset capabilities -see ath5k_hw_get_capability-
 869  * get_capability function is not yet fully implemented
 870  * in OpenHAL so most of these don't work yet...
 871  */
 872 enum ath5k_capability_type {
 873         AR5K_CAP_REG_DMN                = 0,    /* Used to get current reg. domain id */
 874         AR5K_CAP_TKIP_MIC               = 2,    /* Can handle TKIP MIC in hardware */
 875         AR5K_CAP_TKIP_SPLIT             = 3,    /* TKIP uses split keys */
 876         AR5K_CAP_PHYCOUNTERS            = 4,    /* PHY error counters */
 877         AR5K_CAP_DIVERSITY              = 5,    /* Supports fast diversity */
 878         AR5K_CAP_NUM_TXQUEUES           = 6,    /* Used to get max number of hw txqueues */
 879         AR5K_CAP_VEOL                   = 7,    /* Supports virtual EOL */
 880         AR5K_CAP_COMPRESSION            = 8,    /* Supports compression */
 881         AR5K_CAP_BURST                  = 9,    /* Supports packet bursting */
 882         AR5K_CAP_FASTFRAME              = 10,   /* Supports fast frames */
 883         AR5K_CAP_TXPOW                  = 11,   /* Used to get global tx power limit */
 884         AR5K_CAP_TPC                    = 12,   /* Can do per-packet tx power control (needed for 802.11a) */
 885         AR5K_CAP_BSSIDMASK              = 13,   /* Supports bssid mask */
 886         AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
 887         AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
 888         AR5K_CAP_XR                     = 16,   /* Supports XR mode */
 889         AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
 890         AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
 891         AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
 892         AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
 893 };
 894
 895
 896 /* XXX: we *may* move cap_range stuff to struct wiphy */
 897 struct ath5k_capabilities {
 898         /*
 899          * Supported PHY modes
 900          * (ie. CHANNEL_A, CHANNEL_B, ...)
 901          */
 902         DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
 903
 904         /*
 905          * Frequency range (without regulation restrictions)
 906          */
 907         struct {
 908                 u16     range_2ghz_min;
 909                 u16     range_2ghz_max;
 910                 u16     range_5ghz_min;
 911                 u16     range_5ghz_max;
 912         } cap_range;
 913
 914         /*
 915          * Values stored in the EEPROM (some of them...)
 916          */
 917         struct ath5k_eeprom_info        cap_eeprom;
 918
 919         /*
 920          * Queue information
 921          */
 922         struct {
 923                 u8      q_tx_num;
 924         } cap_queues;
 925 };
 926
 927
 928 /***************************************\
 929   HARDWARE ABSTRACTION LAYER STRUCTURE
 930 \***************************************/
 931
 932 /*
 933  * Misc defines
 934  */
 935
 936 #define AR5K_MAX_GPIO           10
 937 #define AR5K_MAX_RF_BANKS       8
 938
 939 struct ath5k_hw {
 940         u32                     ah_magic;
 941
 942         struct ath5k_softc      *ah_sc;
 943         void __iomem            *ah_iobase;
 944
 945         enum ath5k_int          ah_imr;
 946
 947         enum ieee80211_if_types ah_op_mode;
 948         enum ath5k_power_mode   ah_power_mode;
 949         struct ieee80211_channel ah_current_channel;
 950         bool                    ah_turbo;
 951         bool                    ah_calibration;
 952         bool                    ah_running;
 953         bool                    ah_single_chip;
 954         enum ath5k_rfgain       ah_rf_gain;
 955
 956         u32                     ah_mac_srev;
 957         u16                     ah_mac_version;
 958         u16                     ah_mac_revision;
 959         u16                     ah_phy_revision;
 960         u16                     ah_radio_5ghz_revision;
 961         u16                     ah_radio_2ghz_revision;
 962         u32                     ah_phy_spending;
 963
 964         enum ath5k_version      ah_version;
 965         enum ath5k_radio        ah_radio;
 966         u32                     ah_phy;
 967
 968         bool                    ah_5ghz;
 969         bool                    ah_2ghz;
 970
 971 #define ah_regdomain            ah_capabilities.cap_regdomain.reg_current
 972 #define ah_regdomain_hw         ah_capabilities.cap_regdomain.reg_hw
 973 #define ah_modes                ah_capabilities.cap_mode
 974 #define ah_ee_version           ah_capabilities.cap_eeprom.ee_version
 975
 976         u32                     ah_atim_window;
 977         u32                     ah_aifs;
 978         u32                     ah_cw_min;
 979         u32                     ah_cw_max;
 980         bool                    ah_software_retry;
 981         u32                     ah_limit_tx_retries;
 982
 983         u32                     ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 984         bool                    ah_ant_diversity;
 985
 986         u8                      ah_sta_id[ETH_ALEN];
 987
 988         /* Current BSSID we are trying to assoc to / creating.
 989          * This is passed by mac80211 on config_interface() and cached here for
 990          * use in resets */
 991         u8                      ah_bssid[ETH_ALEN];
 992
 993         u32                     ah_gpio[AR5K_MAX_GPIO];
 994         int                     ah_gpio_npins;
 995
 996         struct ath5k_capabilities ah_capabilities;
 997
 998         struct ath5k_txq_info   ah_txq[AR5K_NUM_TX_QUEUES];
 999         u32                     ah_txq_status;
1000         u32                     ah_txq_imr_txok;
1001         u32                     ah_txq_imr_txerr;
1002         u32                     ah_txq_imr_txurn;
1003         u32                     ah_txq_imr_txdesc;
1004         u32                     ah_txq_imr_txeol;
1005         u32                     *ah_rf_banks;
1006         size_t                  ah_rf_banks_size;
1007         struct ath5k_gain       ah_gain;
1008         u32                     ah_offset[AR5K_MAX_RF_BANKS];
1009
1010         struct {
1011                 u16             txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1012                 u16             txp_rates[AR5K_MAX_RATES];
1013                 s16             txp_min;
1014                 s16             txp_max;
1015                 bool            txp_tpc;
1016                 s16             txp_ofdm;
1017         } ah_txpower;
1018
1019         struct {
1020                 bool            r_enabled;
1021                 int             r_last_alert;
1022                 struct ieee80211_channel r_last_channel;
1023         } ah_radar;
1024
1025         /* noise floor from last periodic calibration */
1026         s32                     ah_noise_floor;
1027
1028         /*
1029          * Function pointers
1030          */
1031         int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1032                 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1033                 unsigned int, unsigned int, unsigned int, unsigned int,
1034                 unsigned int, unsigned int, unsigned int);
1035         int (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1036                 unsigned int, unsigned int, unsigned int, unsigned int,
1037                 unsigned int, unsigned int);
1038         int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1039                 struct ath5k_tx_status *);
1040         int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1041                 struct ath5k_rx_status *);
1042 };
1043
1044 /*
1045  * Prototypes
1046  */
1047
1048 /* General Functions */
1049 extern int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, bool is_set);
1050 /* Attach/Detach Functions */
1051 extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
1052 extern const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah, unsigned int mode);
1053 extern void ath5k_hw_detach(struct ath5k_hw *ah);
1054 /* Reset Functions */
1055 extern int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel);
1056 /* Power management functions */
1057 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
1058 /* DMA Related Functions */
1059 extern void ath5k_hw_start_rx(struct ath5k_hw *ah);
1060 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1061 extern u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah);
1062 extern void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr);
1063 extern int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue);
1064 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1065 extern u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue);
1066 extern int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr);
1067 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1068 /* Interrupt handling */
1069 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1070 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1071 extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1072 /* EEPROM access functions */
1073 extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain);
1074 /* Protocol Control Unit Functions */
1075 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1076 /* BSSID Functions */
1077 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1078 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1079 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1080 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1081 /* Receive start/stop functions */
1082 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1083 extern void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah);
1084 /* RX Filter functions */
1085 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1086 extern int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index);
1087 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1088 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1089 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1090 /* Beacon related functions */
1091 extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1092 extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1093 extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1094 extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1095 #if 0
1096 extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1097 extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1098 extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1099 #endif
1100 extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ath5k_mib_stats *statistics);
1101 /* ACK bit rate */
1102 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1103 /* ACK/CTS Timeouts */
1104 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1105 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1106 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1107 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1108 /* Key table (WEP) functions */
1109 extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1110 extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1111 extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1112 extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1113 /* Queue Control Unit, DFS Control Unit Functions */
1114 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info);
1115 extern int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue, const struct ath5k_txq_info *queue_info);
1116 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
1117 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1118 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1119 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1120 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1121 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
1122 /* Hardware Descriptor Functions */
1123 extern int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, u32 size, unsigned int flags);
1124 /* GPIO Functions */
1125 extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1126 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1127 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1128 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1129 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1130 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1131 /* Misc functions */
1132 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1133
1134
1135 /* Initial register settings functions */
1136 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1137 /* Initialize RF */
1138 extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
1139 extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
1140 extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
1141 extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
1142
1143
1144 /* PHY/RF channel functions */
1145 extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1146 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1147 /* PHY calibration */
1148 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1149 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1150 /* Misc PHY functions */
1151 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1152 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1153 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1154 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1155 /* TX power setup */
1156 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1157 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1158
1159
1160 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1161 {
1162         return ioread32(ah->ah_iobase + reg);
1163 }
1164
1165 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1166 {
1167         iowrite32(val, ah->ah_iobase + reg);
1168 }
1169
1170 #endif