?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
iwlwifi: introduce host commands callbacks
[linux/fpc-iii.git] / drivers / net / wireless / ath5k / hw.c
blobff579a22362129287c57ee145a9dc5c3c4313b7e
1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 /*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29
30 #include "reg.h"
31 #include "base.h"
32 #include "debug.h"
33
34 /*Rate tables*/
35 static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36 static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37 static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38 static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39 static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
41 /*Prototypes*/
42 static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43 static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
48 static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int);
51 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
52 struct ath5k_tx_status *);
53 static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
54 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
55 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int);
57 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
58 struct ath5k_tx_status *);
59 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *,
60 struct ath5k_rx_status *);
61 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *,
62 struct ath5k_rx_status *);
63 static int ath5k_hw_get_capabilities(struct ath5k_hw *);
64
65 static int ath5k_eeprom_init(struct ath5k_hw *);
66 static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
67
68 static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
69 static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
70
71 /*
72 * Enable to overwrite the country code (use "00" for debug)
73 */
74 #if 0
75 #define COUNTRYCODE "00"
76 #endif
77
78 /*******************\
79 General Functions
80 \*******************/
81
82 /*
83 * Functions used internaly
84 */
85
86 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
87 {
88 return turbo ? (usec * 80) : (usec * 40);
89 }
90
91 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
92 {
93 return turbo ? (clock / 80) : (clock / 40);
94 }
95
96 /*
97 * Check if a register write has been completed
98 */
99 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
100 bool is_set)
101 {
102 int i;
103 u32 data;
104
105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
106 data = ath5k_hw_reg_read(ah, reg);
107 if (is_set && (data & flag))
108 break;
109 else if ((data & flag) == val)
110 break;
111 udelay(15);
112 }
113
114 return (i <= 0) ? -EAGAIN : 0;
115 }
116
117
118 /***************************************\
119 Attach/Detach Functions
120 \***************************************/
121
122 /*
123 * Check if the device is supported and initialize the needed structs
124 */
125 struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
126 {
127 struct ath5k_hw *ah;
128 u8 mac[ETH_ALEN];
129 int ret;
130 u32 srev;
131
132 /*If we passed the test malloc a ath5k_hw struct*/
133 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
134 if (ah == NULL) {
135 ret = -ENOMEM;
136 ATH5K_ERR(sc, "out of memory\n");
137 goto err;
138 }
139
140 ah->ah_sc = sc;
141 ah->ah_iobase = sc->iobase;
142
143 /*
144 * HW information
145 */
146
147 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
148 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
149 ah->ah_turbo = false;
150 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
151 ah->ah_imr = 0;
152 ah->ah_atim_window = 0;
153 ah->ah_aifs = AR5K_TUNE_AIFS;
154 ah->ah_cw_min = AR5K_TUNE_CWMIN;
155 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
156 ah->ah_software_retry = false;
157 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
158
159 /*
160 * Set the mac revision based on the pci id
161 */
162 ah->ah_version = mac_version;
163
164 /*Fill the ath5k_hw struct with the needed functions*/
165 if (ah->ah_version == AR5K_AR5212)
166 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
167 else if (ah->ah_version == AR5K_AR5211)
168 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
169
170 if (ah->ah_version == AR5K_AR5212) {
171 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
172 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
173 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
174 } else {
175 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
176 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
177 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
178 }
179
180 if (ah->ah_version == AR5K_AR5212)
181 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
182 else if (ah->ah_version <= AR5K_AR5211)
183 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
184
185 /* Bring device out of sleep and reset it's units */
186 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
187 if (ret)
188 goto err_free;
189
190 /* Get MAC, PHY and RADIO revisions */
191 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
192 ah->ah_mac_srev = srev;
193 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
194 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
195 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
196 0xffffffff;
197 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
198 CHANNEL_5GHZ);
199
200 if (ah->ah_version == AR5K_AR5210)
201 ah->ah_radio_2ghz_revision = 0;
202 else
203 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
204 CHANNEL_2GHZ);
205
206 /* Return on unsuported chips (unsupported eeprom etc) */
207 if(srev >= AR5K_SREV_VER_AR5416){
208 ATH5K_ERR(sc, "Device not yet supported.\n");
209 ret = -ENODEV;
210 goto err_free;
211 }
212
213 /* Identify single chip solutions */
214 if((srev <= AR5K_SREV_VER_AR5414) &&
215 (srev >= AR5K_SREV_VER_AR2413)) {
216 ah->ah_single_chip = true;
217 } else {
218 ah->ah_single_chip = false;
219 }
220
221 /* Single chip radio */
222 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
223 ah->ah_radio_2ghz_revision = 0;
224
225 /* Identify the radio chip*/
226 if (ah->ah_version == AR5K_AR5210) {
227 ah->ah_radio = AR5K_RF5110;
228 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
229 ah->ah_radio = AR5K_RF5111;
230 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
231 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
232
233 ah->ah_radio = AR5K_RF5112;
234
235 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
236 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
237 } else {
238 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
239 }
240
241 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
242 ah->ah_radio = AR5K_RF2413;
243 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
244 } else {
245
246 ah->ah_radio = AR5K_RF5413;
247
248 if (ah->ah_mac_srev <= AR5K_SREV_VER_AR5424 &&
249 ah->ah_mac_srev >= AR5K_SREV_VER_AR2424)
250 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424;
251 else if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2425)
252 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
253 else
254 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
255
256
257 }
258
259 ah->ah_phy = AR5K_PHY(0);
260
261 /*
262 * Get card capabilities, values, ...
263 */
264
265 ret = ath5k_eeprom_init(ah);
266 if (ret) {
267 ATH5K_ERR(sc, "unable to init EEPROM\n");
268 goto err_free;
269 }
270
271 /* Get misc capabilities */
272 ret = ath5k_hw_get_capabilities(ah);
273 if (ret) {
274 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
275 sc->pdev->device);
276 goto err_free;
277 }
278
279 /* Get MAC address */
280 ret = ath5k_eeprom_read_mac(ah, mac);
281 if (ret) {
282 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
283 sc->pdev->device);
284 goto err_free;
285 }
286
287 ath5k_hw_set_lladdr(ah, mac);
288 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
289 memset(ah->ah_bssid, 0xff, ETH_ALEN);
290 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
291 ath5k_hw_set_opmode(ah);
292
293 ath5k_hw_set_rfgain_opt(ah);
294
295 return ah;
296 err_free:
297 kfree(ah);
298 err:
299 return ERR_PTR(ret);
300 }
301
302 /*
303 * Bring up MAC + PHY Chips
304 */
305 static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
306 {
307 struct pci_dev *pdev = ah->ah_sc->pdev;
308 u32 turbo, mode, clock, bus_flags;
309 int ret;
310
311 turbo = 0;
312 mode = 0;
313 clock = 0;
314
315 ATH5K_TRACE(ah->ah_sc);
316
317 /* Wakeup the device */
318 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
319 if (ret) {
320 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
321 return ret;
322 }
323
324 if (ah->ah_version != AR5K_AR5210) {
325 /*
326 * Get channel mode flags
327 */
328
329 if (ah->ah_radio >= AR5K_RF5112) {
330 mode = AR5K_PHY_MODE_RAD_RF5112;
331 clock = AR5K_PHY_PLL_RF5112;
332 } else {
333 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
334 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
335 }
336
337 if (flags & CHANNEL_2GHZ) {
338 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
339 clock |= AR5K_PHY_PLL_44MHZ;
340
341 if (flags & CHANNEL_CCK) {
342 mode |= AR5K_PHY_MODE_MOD_CCK;
343 } else if (flags & CHANNEL_OFDM) {
344 /* XXX Dynamic OFDM/CCK is not supported by the
345 * AR5211 so we set MOD_OFDM for plain g (no
346 * CCK headers) operation. We need to test
347 * this, 5211 might support ofdm-only g after
348 * all, there are also initial register values
349 * in the code for g mode (see initvals.c). */
350 if (ah->ah_version == AR5K_AR5211)
351 mode |= AR5K_PHY_MODE_MOD_OFDM;
352 else
353 mode |= AR5K_PHY_MODE_MOD_DYN;
354 } else {
355 ATH5K_ERR(ah->ah_sc,
356 "invalid radio modulation mode\n");
357 return -EINVAL;
358 }
359 } else if (flags & CHANNEL_5GHZ) {
360 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
361 clock |= AR5K_PHY_PLL_40MHZ;
362
363 if (flags & CHANNEL_OFDM)
364 mode |= AR5K_PHY_MODE_MOD_OFDM;
365 else {
366 ATH5K_ERR(ah->ah_sc,
367 "invalid radio modulation mode\n");
368 return -EINVAL;
369 }
370 } else {
371 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
372 return -EINVAL;
373 }
374
375 if (flags & CHANNEL_TURBO)
376 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
377 } else { /* Reset the device */
378
379 /* ...enable Atheros turbo mode if requested */
380 if (flags & CHANNEL_TURBO)
381 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
382 AR5K_PHY_TURBO);
383 }
384
385 /* reseting PCI on PCI-E cards results card to hang
386 * and always return 0xffff... so we ingore that flag
387 * for PCI-E cards */
388 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
389
390 /* Reset chipset */
391 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
392 AR5K_RESET_CTL_BASEBAND | bus_flags);
393 if (ret) {
394 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip + PCI\n");
395 return -EIO;
396 }
397
398 if (ah->ah_version == AR5K_AR5210)
399 udelay(2300);
400
401 /* ...wakeup again!*/
402 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
403 if (ret) {
404 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
405 return ret;
406 }
407
408 /* ...final warm reset */
409 if (ath5k_hw_nic_reset(ah, 0)) {
410 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
411 return -EIO;
412 }
413
414 if (ah->ah_version != AR5K_AR5210) {
415 /* ...set the PHY operating mode */
416 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
417 udelay(300);
418
419 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
420 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
421 }
422
423 return 0;
424 }
425
426 /*
427 * Get the rate table for a specific operation mode
428 */
429 const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
430 unsigned int mode)
431 {
432 ATH5K_TRACE(ah->ah_sc);
433
434 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
435 return NULL;
436
437 /* Get rate tables */
438 switch (mode) {
439 case AR5K_MODE_11A:
440 return &ath5k_rt_11a;
441 case AR5K_MODE_11A_TURBO:
442 return &ath5k_rt_turbo;
443 case AR5K_MODE_11B:
444 return &ath5k_rt_11b;
445 case AR5K_MODE_11G:
446 return &ath5k_rt_11g;
447 case AR5K_MODE_11G_TURBO:
448 return &ath5k_rt_xr;
449 }
450
451 return NULL;
452 }
453
454 /*
455 * Free the ath5k_hw struct
456 */
457 void ath5k_hw_detach(struct ath5k_hw *ah)
458 {
459 ATH5K_TRACE(ah->ah_sc);
460
461 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
462
463 if (ah->ah_rf_banks != NULL)
464 kfree(ah->ah_rf_banks);
465
466 /* assume interrupts are down */
467 kfree(ah);
468 }
469
470 /****************************\
471 Reset function and helpers
472 \****************************/
473
474 /**
475 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
476 *
477 * @ah: the &struct ath5k_hw
478 * @channel: the currently set channel upon reset
479 *
480 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
481 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
482 * depending on the bandwidth of the channel.
483 *
484 */
485 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
486 struct ieee80211_channel *channel)
487 {
488 /* Get exponent and mantissa and set it */
489 u32 coef_scaled, coef_exp, coef_man,
490 ds_coef_exp, ds_coef_man, clock;
491
492 if (!(ah->ah_version == AR5K_AR5212) ||
493 !(channel->hw_value & CHANNEL_OFDM))
494 BUG();
495
496 /* Seems there are two PLLs, one for baseband sampling and one
497 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
498 * turbo. */
499 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
500 coef_scaled = ((5 * (clock << 24)) / 2) /
501 channel->center_freq;
502
503 for (coef_exp = 31; coef_exp > 0; coef_exp--)
504 if ((coef_scaled >> coef_exp) & 0x1)
505 break;
506
507 if (!coef_exp)
508 return -EINVAL;
509
510 coef_exp = 14 - (coef_exp - 24);
511 coef_man = coef_scaled +
512 (1 << (24 - coef_exp - 1));
513 ds_coef_man = coef_man >> (24 - coef_exp);
514 ds_coef_exp = coef_exp - 16;
515
516 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
517 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
518 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
519 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
520
521 return 0;
522 }
523
524 /**
525 * ath5k_hw_write_rate_duration - set rate duration during hw resets
526 *
527 * @ah: the &struct ath5k_hw
528 * @mode: one of enum ath5k_driver_mode
529 *
530 * Write the rate duration table for the current mode upon hw reset. This
531 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
532 * an ACK timeout for the hardware for the current mode for each rate. The
533 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
534 * and 11Mbps) have another register for the short preamble ACK timeout
535 * calculation.
536 *
537 */
538 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
539 unsigned int mode)
540 {
541 struct ath5k_softc *sc = ah->ah_sc;
542 const struct ath5k_rate_table *rt;
543 struct ieee80211_rate srate = {};
544 unsigned int i;
545
546 /* Get rate table for the current operating mode */
547 rt = ath5k_hw_get_rate_table(ah, mode);
548
549 /* Write rate duration table */
550 for (i = 0; i < rt->rate_count; i++) {
551 const struct ath5k_rate *rate, *control_rate;
552
553 u32 reg;
554 u16 tx_time;
555
556 rate = &rt->rates[i];
557 control_rate = &rt->rates[rate->control_rate];
558
559 /* Set ACK timeout */
560 reg = AR5K_RATE_DUR(rate->rate_code);
561
562 srate.bitrate = control_rate->rate_kbps/100;
563
564 /* An ACK frame consists of 10 bytes. If you add the FCS,
565 * which ieee80211_generic_frame_duration() adds,
566 * its 14 bytes. Note we use the control rate and not the
567 * actual rate for this rate. See mac80211 tx.c
568 * ieee80211_duration() for a brief description of
569 * what rate we should choose to TX ACKs. */
570 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
571 sc->vif, 10, &srate));
572
573 ath5k_hw_reg_write(ah, tx_time, reg);
574
575 if (!HAS_SHPREAMBLE(i))
576 continue;
577
578 /*
579 * We're not distinguishing short preamble here,
580 * This is true, all we'll get is a longer value here
581 * which is not necessarilly bad. We could use
582 * export ieee80211_frame_duration() but that needs to be
583 * fixed first to be properly used by mac802111 drivers:
584 *
585 * - remove erp stuff and let the routine figure ofdm
586 * erp rates
587 * - remove passing argument ieee80211_local as
588 * drivers don't have access to it
589 * - move drivers using ieee80211_generic_frame_duration()
590 * to this
591 */
592 ath5k_hw_reg_write(ah, tx_time,
593 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
594 }
595 }
596
597 /*
598 * Main reset function
599 */
600 int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
601 struct ieee80211_channel *channel, bool change_channel)
602 {
603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
604 struct pci_dev *pdev = ah->ah_sc->pdev;
605 u32 data, s_seq, s_ant, s_led[3], dma_size;
606 unsigned int i, mode, freq, ee_mode, ant[2];
607 int ret;
608
609 ATH5K_TRACE(ah->ah_sc);
610
611 s_seq = 0;
612 s_ant = 0;
613 ee_mode = 0;
614 freq = 0;
615 mode = 0;
616
617 /*
618 * Save some registers before a reset
619 */
620 /*DCU/Antenna selection not available on 5210*/
621 if (ah->ah_version != AR5K_AR5210) {
622 if (change_channel) {
623 /* Seq number for queue 0 -do this for all queues ? */
624 s_seq = ath5k_hw_reg_read(ah,
625 AR5K_QUEUE_DFS_SEQNUM(0));
626 /*Default antenna*/
627 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
628 }
629 }
630
631 /*GPIOs*/
632 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
633 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
634 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
635
636 if (change_channel && ah->ah_rf_banks != NULL)
637 ath5k_hw_get_rf_gain(ah);
638
639
640 /*Wakeup the device*/
641 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
642 if (ret)
643 return ret;
644
645 /*
646 * Initialize operating mode
647 */
648 ah->ah_op_mode = op_mode;
649
650 /*
651 * 5111/5112 Settings
652 * 5210 only comes with RF5110
653 */
654 if (ah->ah_version != AR5K_AR5210) {
655 if (ah->ah_radio != AR5K_RF5111 &&
656 ah->ah_radio != AR5K_RF5112 &&
657 ah->ah_radio != AR5K_RF5413 &&
658 ah->ah_radio != AR5K_RF2413) {
659 ATH5K_ERR(ah->ah_sc,
660 "invalid phy radio: %u\n", ah->ah_radio);
661 return -EINVAL;
662 }
663
664 switch (channel->hw_value & CHANNEL_MODES) {
665 case CHANNEL_A:
666 mode = AR5K_MODE_11A;
667 freq = AR5K_INI_RFGAIN_5GHZ;
668 ee_mode = AR5K_EEPROM_MODE_11A;
669 break;
670 case CHANNEL_G:
671 mode = AR5K_MODE_11G;
672 freq = AR5K_INI_RFGAIN_2GHZ;
673 ee_mode = AR5K_EEPROM_MODE_11G;
674 break;
675 case CHANNEL_B:
676 mode = AR5K_MODE_11B;
677 freq = AR5K_INI_RFGAIN_2GHZ;
678 ee_mode = AR5K_EEPROM_MODE_11B;
679 break;
680 case CHANNEL_T:
681 mode = AR5K_MODE_11A_TURBO;
682 freq = AR5K_INI_RFGAIN_5GHZ;
683 ee_mode = AR5K_EEPROM_MODE_11A;
684 break;
685 /*Is this ok on 5211 too ?*/
686 case CHANNEL_TG:
687 mode = AR5K_MODE_11G_TURBO;
688 freq = AR5K_INI_RFGAIN_2GHZ;
689 ee_mode = AR5K_EEPROM_MODE_11G;
690 break;
691 case CHANNEL_XR:
692 if (ah->ah_version == AR5K_AR5211) {
693 ATH5K_ERR(ah->ah_sc,
694 "XR mode not available on 5211");
695 return -EINVAL;
696 }
697 mode = AR5K_MODE_XR;
698 freq = AR5K_INI_RFGAIN_5GHZ;
699 ee_mode = AR5K_EEPROM_MODE_11A;
700 break;
701 default:
702 ATH5K_ERR(ah->ah_sc,
703 "invalid channel: %d\n", channel->center_freq);
704 return -EINVAL;
705 }
706
707 /* PHY access enable */
708 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
709
710 }
711
712 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
713 if (ret)
714 return ret;
715
716 /*
717 * 5211/5212 Specific
718 */
719 if (ah->ah_version != AR5K_AR5210) {
720 /*
721 * Write initial RF gain settings
722 * This should work for both 5111/5112
723 */
724 ret = ath5k_hw_rfgain(ah, freq);
725 if (ret)
726 return ret;
727
728 mdelay(1);
729
730 /*
731 * Write some more initial register settings
732 */
733 if (ah->ah_version == AR5K_AR5212) {
734 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
735
736 if (channel->hw_value == CHANNEL_G)
737 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
738 ath5k_hw_reg_write(ah, 0x00f80d80,
739 AR5K_PHY(83));
740 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
741 ath5k_hw_reg_write(ah, 0x00380140,
742 AR5K_PHY(83));
743 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
744 ath5k_hw_reg_write(ah, 0x00fc0ec0,
745 AR5K_PHY(83));
746 else /* 2425 */
747 ath5k_hw_reg_write(ah, 0x00fc0fc0,
748 AR5K_PHY(83));
749 else
750 ath5k_hw_reg_write(ah, 0x00000000,
751 AR5K_PHY(83));
752
753 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
754 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
755 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
756 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
757 }
758
759 /* Fix for first revision of the RF5112 RF chipset */
760 if (ah->ah_radio >= AR5K_RF5112 &&
761 ah->ah_radio_5ghz_revision <
762 AR5K_SREV_RAD_5112A) {
763 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
764 AR5K_PHY_CCKTXCTL);
765 if (channel->hw_value & CHANNEL_5GHZ)
766 data = 0xffb81020;
767 else
768 data = 0xffb80d20;
769 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
770 }
771
772 /*
773 * Set TX power (FIXME)
774 */
775 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
776 if (ret)
777 return ret;
778
779 /* Write rate duration table only on AR5212 and if
780 * virtual interface has already been brought up
781 * XXX: rethink this after new mode changes to
782 * mac80211 are integrated */
783 if (ah->ah_version == AR5K_AR5212 &&
784 ah->ah_sc->vif != NULL)
785 ath5k_hw_write_rate_duration(ah, mode);
786
787 /*
788 * Write RF registers
789 * TODO:Does this work on 5211 (5111) ?
790 */
791 ret = ath5k_hw_rfregs(ah, channel, mode);
792 if (ret)
793 return ret;
794
795 /*
796 * Configure additional registers
797 */
798
799 /* Write OFDM timings on 5212*/
800 if (ah->ah_version == AR5K_AR5212 &&
801 channel->hw_value & CHANNEL_OFDM) {
802 ret = ath5k_hw_write_ofdm_timings(ah, channel);
803 if (ret)
804 return ret;
805 }
806
807 /*Enable/disable 802.11b mode on 5111
808 (enable 2111 frequency converter + CCK)*/
809 if (ah->ah_radio == AR5K_RF5111) {
810 if (mode == AR5K_MODE_11B)
811 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
812 AR5K_TXCFG_B_MODE);
813 else
814 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
815 AR5K_TXCFG_B_MODE);
816 }
817
818 /*
819 * Set channel and calibrate the PHY
820 */
821 ret = ath5k_hw_channel(ah, channel);
822 if (ret)
823 return ret;
824
825 /* Set antenna mode */
826 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
827 ah->ah_antenna[ee_mode][0], 0xfffffc06);
828
829 /*
830 * In case a fixed antenna was set as default
831 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
832 * registers.
833 */
834 if (s_ant != 0){
835 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
836 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
837 else /* 2 - Aux */
838 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
839 } else {
840 ant[0] = AR5K_ANT_FIXED_A;
841 ant[1] = AR5K_ANT_FIXED_B;
842 }
843
844 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
845 AR5K_PHY_ANT_SWITCH_TABLE_0);
846 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
847 AR5K_PHY_ANT_SWITCH_TABLE_1);
848
849 /* Commit values from EEPROM */
850 if (ah->ah_radio == AR5K_RF5111)
851 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
852 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
853
854 ath5k_hw_reg_write(ah,
855 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
856 AR5K_PHY(0x5a));
857
858 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
859 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
860 0xffffc07f);
861 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
862 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
863 0xfffc0fff);
864 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
865 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
866 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
867 0xffff0000);
868
869 ath5k_hw_reg_write(ah,
870 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
871 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
872 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
873 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
874
875 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
876 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
877 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
878 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
879 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
880
881 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
882 AR5K_PHY_IQ_CORR_ENABLE |
883 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
884 ee->ee_q_cal[ee_mode]);
885
886 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
887 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
888 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
889 ee->ee_margin_tx_rx[ee_mode]);
890
891 } else {
892 mdelay(1);
893 /* Disable phy and wait */
894 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
895 mdelay(1);
896 }
897
898 /*
899 * Restore saved values
900 */
901 /*DCU/Antenna selection not available on 5210*/
902 if (ah->ah_version != AR5K_AR5210) {
903 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
904 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
905 }
906 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
907 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
908 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
909
910 /*
911 * Misc
912 */
913 /* XXX: add ah->aid once mac80211 gives this to us */
914 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
915
916 ath5k_hw_set_opmode(ah);
917 /*PISR/SISR Not available on 5210*/
918 if (ah->ah_version != AR5K_AR5210) {
919 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
920 /* If we later allow tuning for this, store into sc structure */
921 data = AR5K_TUNE_RSSI_THRES |
922 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
923 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
924 }
925
926 /*
927 * Set Rx/Tx DMA Configuration
928 *
929 * Set maximum DMA size (512) except for PCI-E cards since
930 * it causes rx overruns and tx errors (tested on 5424 but since
931 * rx overruns also occur on 5416/5418 with madwifi we set 128
932 * for all PCI-E cards to be safe).
933 *
934 * In dumps this is 128 for allchips.
935 *
936 * XXX: need to check 5210 for this
937 * TODO: Check out tx triger level, it's always 64 on dumps but I
938 * guess we can tweak it and see how it goes ;-)
939 */
940 dma_size = (pdev->is_pcie) ? AR5K_DMASIZE_128B : AR5K_DMASIZE_512B;
941 if (ah->ah_version != AR5K_AR5210) {
942 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
943 AR5K_TXCFG_SDMAMR, dma_size);
944 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
945 AR5K_RXCFG_SDMAMW, dma_size);
946 }
947
948 /*
949 * Enable the PHY and wait until completion
950 */
951 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
952
953 /*
954 * 5111/5112 Specific
955 */
956 if (ah->ah_version != AR5K_AR5210) {
957 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
958 AR5K_PHY_RX_DELAY_M;
959 data = (channel->hw_value & CHANNEL_CCK) ?
960 ((data << 2) / 22) : (data / 10);
961
962 udelay(100 + data);
963 } else {
964 mdelay(1);
965 }
966
967 /*
968 * Enable calibration and wait until completion
969 */
970 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
971 AR5K_PHY_AGCCTL_CAL);
972
973 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
974 AR5K_PHY_AGCCTL_CAL, 0, false)) {
975 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
976 channel->center_freq);
977 return -EAGAIN;
978 }
979
980 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
981 if (ret)
982 return ret;
983
984 ah->ah_calibration = false;
985
986 /* A and G modes can use QAM modulation which requires enabling
987 * I and Q calibration. Don't bother in B mode. */
988 if (!(mode == AR5K_MODE_11B)) {
989 ah->ah_calibration = true;
990 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
991 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
992 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
993 AR5K_PHY_IQ_RUN);
994 }
995
996 /*
997 * Reset queues and start beacon timers at the end of the reset routine
998 */
999 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1000 /*No QCU on 5210*/
1001 if (ah->ah_version != AR5K_AR5210)
1002 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
1003
1004 ret = ath5k_hw_reset_tx_queue(ah, i);
1005 if (ret) {
1006 ATH5K_ERR(ah->ah_sc,
1007 "failed to reset TX queue #%d\n", i);
1008 return ret;
1009 }
1010 }
1011
1012 /* Pre-enable interrupts on 5211/5212*/
1013 if (ah->ah_version != AR5K_AR5210)
1014 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
1015 AR5K_INT_FATAL);
1016
1017 /*
1018 * Set RF kill flags if supported by the device (read from the EEPROM)
1019 * Disable gpio_intr for now since it results system hang.
1020 * TODO: Handle this in ath5k_intr
1021 */
1022 #if 0
1023 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1024 ath5k_hw_set_gpio_input(ah, 0);
1025 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1026 if (ah->ah_gpio[0] == 0)
1027 ath5k_hw_set_gpio_intr(ah, 0, 1);
1028 else
1029 ath5k_hw_set_gpio_intr(ah, 0, 0);
1030 }
1031 #endif
1032
1033 /*
1034 * Set the 32MHz reference clock on 5212 phy clock sleep register
1035 *
1036 * TODO: Find out how to switch to external 32Khz clock to save power
1037 */
1038 if (ah->ah_version == AR5K_AR5212) {
1039 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
1040 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
1041 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
1042 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
1043 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
1044 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
1045 }
1046
1047 if (ah->ah_version == AR5K_AR5212) {
1048 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
1049 ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
1050 ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
1051 if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
1052 ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
1053 }
1054
1055 /*
1056 * Disable beacons and reset the register
1057 */
1058 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1059 AR5K_BEACON_RESET_TSF);
1060
1061 return 0;
1062 }
1063
1064 /*
1065 * Reset chipset
1066 */
1067 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1068 {
1069 int ret;
1070 u32 mask = val ? val : ~0U;
1071
1072 ATH5K_TRACE(ah->ah_sc);
1073
1074 /* Read-and-clear RX Descriptor Pointer*/
1075 ath5k_hw_reg_read(ah, AR5K_RXDP);
1076
1077 /*
1078 * Reset the device and wait until success
1079 */
1080 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1081
1082 /* Wait at least 128 PCI clocks */
1083 udelay(15);
1084
1085 if (ah->ah_version == AR5K_AR5210) {
1086 val &= AR5K_RESET_CTL_CHIP;
1087 mask &= AR5K_RESET_CTL_CHIP;
1088 } else {
1089 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1090 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1091 }
1092
1093 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1094
1095 /*
1096 * Reset configuration register (for hw byte-swap). Note that this
1097 * is only set for big endian. We do the necessary magic in
1098 * AR5K_INIT_CFG.
1099 */
1100 if ((val & AR5K_RESET_CTL_PCU) == 0)
1101 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1102
1103 return ret;
1104 }
1105
1106 /*
1107 * Power management functions
1108 */
1109
1110 /*
1111 * Sleep control
1112 */
1113 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1114 bool set_chip, u16 sleep_duration)
1115 {
1116 unsigned int i;
1117 u32 staid;
1118
1119 ATH5K_TRACE(ah->ah_sc);
1120 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1121
1122 switch (mode) {
1123 case AR5K_PM_AUTO:
1124 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1125 /* fallthrough */
1126 case AR5K_PM_NETWORK_SLEEP:
1127 if (set_chip)
1128 ath5k_hw_reg_write(ah,
1129 AR5K_SLEEP_CTL_SLE | sleep_duration,
1130 AR5K_SLEEP_CTL);
1131
1132 staid |= AR5K_STA_ID1_PWR_SV;
1133 break;
1134
1135 case AR5K_PM_FULL_SLEEP:
1136 if (set_chip)
1137 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1138 AR5K_SLEEP_CTL);
1139
1140 staid |= AR5K_STA_ID1_PWR_SV;
1141 break;
1142
1143 case AR5K_PM_AWAKE:
1144 if (!set_chip)
1145 goto commit;
1146
1147 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1148 AR5K_SLEEP_CTL);
1149
1150 for (i = 5000; i > 0; i--) {
1151 /* Check if the chip did wake up */
1152 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1153 AR5K_PCICFG_SPWR_DN) == 0)
1154 break;
1155
1156 /* Wait a bit and retry */
1157 udelay(200);
1158 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1159 AR5K_SLEEP_CTL);
1160 }
1161
1162 /* Fail if the chip didn't wake up */
1163 if (i <= 0)
1164 return -EIO;
1165
1166 staid &= ~AR5K_STA_ID1_PWR_SV;
1167 break;
1168
1169 default:
1170 return -EINVAL;
1171 }
1172
1173 commit:
1174 ah->ah_power_mode = mode;
1175 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1176
1177 return 0;
1178 }
1179
1180 /***********************\
1181 DMA Related Functions
1182 \***********************/
1183
1184 /*
1185 * Receive functions
1186 */
1187
1188 /*
1189 * Start DMA receive
1190 */
1191 void ath5k_hw_start_rx(struct ath5k_hw *ah)
1192 {
1193 ATH5K_TRACE(ah->ah_sc);
1194 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1195 }
1196
1197 /*
1198 * Stop DMA receive
1199 */
1200 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1201 {
1202 unsigned int i;
1203
1204 ATH5K_TRACE(ah->ah_sc);
1205 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1206
1207 /*
1208 * It may take some time to disable the DMA receive unit
1209 */
1210 for (i = 2000; i > 0 &&
1211 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1212 i--)
1213 udelay(10);
1214
1215 return i ? 0 : -EBUSY;
1216 }
1217
1218 /*
1219 * Get the address of the RX Descriptor
1220 */
1221 u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1222 {
1223 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1224 }
1225
1226 /*
1227 * Set the address of the RX Descriptor
1228 */
1229 void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1230 {
1231 ATH5K_TRACE(ah->ah_sc);
1232
1233 /*TODO:Shouldn't we check if RX is enabled first ?*/
1234 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1235 }
1236
1237 /*
1238 * Transmit functions
1239 */
1240
1241 /*
1242 * Start DMA transmit for a specific queue
1243 * (see also QCU/DCU functions)
1244 */
1245 int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1246 {
1247 u32 tx_queue;
1248
1249 ATH5K_TRACE(ah->ah_sc);
1250 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1251
1252 /* Return if queue is declared inactive */
1253 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1254 return -EIO;
1255
1256 if (ah->ah_version == AR5K_AR5210) {
1257 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1258
1259 /*
1260 * Set the queue by type on 5210
1261 */
1262 switch (ah->ah_txq[queue].tqi_type) {
1263 case AR5K_TX_QUEUE_DATA:
1264 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1265 break;
1266 case AR5K_TX_QUEUE_BEACON:
1267 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1268 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1269 AR5K_BSR);
1270 break;
1271 case AR5K_TX_QUEUE_CAB:
1272 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1273 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1274 AR5K_BCR_BDMAE, AR5K_BSR);
1275 break;
1276 default:
1277 return -EINVAL;
1278 }
1279 /* Start queue */
1280 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1281 } else {
1282 /* Return if queue is disabled */
1283 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1284 return -EIO;
1285
1286 /* Start queue */
1287 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1288 }
1289
1290 return 0;
1291 }
1292
1293 /*
1294 * Stop DMA transmit for a specific queue
1295 * (see also QCU/DCU functions)
1296 */
1297 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1298 {
1299 unsigned int i = 100;
1300 u32 tx_queue, pending;
1301
1302 ATH5K_TRACE(ah->ah_sc);
1303 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1304
1305 /* Return if queue is declared inactive */
1306 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1307 return -EIO;
1308
1309 if (ah->ah_version == AR5K_AR5210) {
1310 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1311
1312 /*
1313 * Set by queue type
1314 */
1315 switch (ah->ah_txq[queue].tqi_type) {
1316 case AR5K_TX_QUEUE_DATA:
1317 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1318 break;
1319 case AR5K_TX_QUEUE_BEACON:
1320 case AR5K_TX_QUEUE_CAB:
1321 /* XXX Fix me... */
1322 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1323 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1324 break;
1325 default:
1326 return -EINVAL;
1327 }
1328
1329 /* Stop queue */
1330 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1331 } else {
1332 /*
1333 * Schedule TX disable and wait until queue is empty
1334 */
1335 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1336
1337 /*Check for pending frames*/
1338 do {
1339 pending = ath5k_hw_reg_read(ah,
1340 AR5K_QUEUE_STATUS(queue)) &
1341 AR5K_QCU_STS_FRMPENDCNT;
1342 udelay(100);
1343 } while (--i && pending);
1344
1345 /* Clear register */
1346 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1347 }
1348
1349 /* TODO: Check for success else return error */
1350 return 0;
1351 }
1352
1353 /*
1354 * Get the address of the TX Descriptor for a specific queue
1355 * (see also QCU/DCU functions)
1356 */
1357 u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1358 {
1359 u16 tx_reg;
1360
1361 ATH5K_TRACE(ah->ah_sc);
1362 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1363
1364 /*
1365 * Get the transmit queue descriptor pointer from the selected queue
1366 */
1367 /*5210 doesn't have QCU*/
1368 if (ah->ah_version == AR5K_AR5210) {
1369 switch (ah->ah_txq[queue].tqi_type) {
1370 case AR5K_TX_QUEUE_DATA:
1371 tx_reg = AR5K_NOQCU_TXDP0;
1372 break;
1373 case AR5K_TX_QUEUE_BEACON:
1374 case AR5K_TX_QUEUE_CAB:
1375 tx_reg = AR5K_NOQCU_TXDP1;
1376 break;
1377 default:
1378 return 0xffffffff;
1379 }
1380 } else {
1381 tx_reg = AR5K_QUEUE_TXDP(queue);
1382 }
1383
1384 return ath5k_hw_reg_read(ah, tx_reg);
1385 }
1386
1387 /*
1388 * Set the address of the TX Descriptor for a specific queue
1389 * (see also QCU/DCU functions)
1390 */
1391 int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1392 {
1393 u16 tx_reg;
1394
1395 ATH5K_TRACE(ah->ah_sc);
1396 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1397
1398 /*
1399 * Set the transmit queue descriptor pointer register by type
1400 * on 5210
1401 */
1402 if (ah->ah_version == AR5K_AR5210) {
1403 switch (ah->ah_txq[queue].tqi_type) {
1404 case AR5K_TX_QUEUE_DATA:
1405 tx_reg = AR5K_NOQCU_TXDP0;
1406 break;
1407 case AR5K_TX_QUEUE_BEACON:
1408 case AR5K_TX_QUEUE_CAB:
1409 tx_reg = AR5K_NOQCU_TXDP1;
1410 break;
1411 default:
1412 return -EINVAL;
1413 }
1414 } else {
1415 /*
1416 * Set the transmit queue descriptor pointer for
1417 * the selected queue on QCU for 5211+
1418 * (this won't work if the queue is still active)
1419 */
1420 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1421 return -EIO;
1422
1423 tx_reg = AR5K_QUEUE_TXDP(queue);
1424 }
1425
1426 /* Set descriptor pointer */
1427 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1428
1429 return 0;
1430 }
1431
1432 /*
1433 * Update tx trigger level
1434 */
1435 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1436 {
1437 u32 trigger_level, imr;
1438 int ret = -EIO;
1439
1440 ATH5K_TRACE(ah->ah_sc);
1441
1442 /*
1443 * Disable interrupts by setting the mask
1444 */
1445 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1446
1447 /*TODO: Boundary check on trigger_level*/
1448 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1449 AR5K_TXCFG_TXFULL);
1450
1451 if (!increase) {
1452 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1453 goto done;
1454 } else
1455 trigger_level +=
1456 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1457
1458 /*
1459 * Update trigger level on success
1460 */
1461 if (ah->ah_version == AR5K_AR5210)
1462 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1463 else
1464 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1465 AR5K_TXCFG_TXFULL, trigger_level);
1466
1467 ret = 0;
1468
1469 done:
1470 /*
1471 * Restore interrupt mask
1472 */
1473 ath5k_hw_set_intr(ah, imr);
1474
1475 return ret;
1476 }
1477
1478 /*
1479 * Interrupt handling
1480 */
1481
1482 /*
1483 * Check if we have pending interrupts
1484 */
1485 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1486 {
1487 ATH5K_TRACE(ah->ah_sc);
1488 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1489 }
1490
1491 /*
1492 * Get interrupt mask (ISR)
1493 */
1494 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1495 {
1496 u32 data;
1497
1498 ATH5K_TRACE(ah->ah_sc);
1499
1500 /*
1501 * Read interrupt status from the Interrupt Status register
1502 * on 5210
1503 */
1504 if (ah->ah_version == AR5K_AR5210) {
1505 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1506 if (unlikely(data == AR5K_INT_NOCARD)) {
1507 *interrupt_mask = data;
1508 return -ENODEV;
1509 }
1510 } else {
1511 /*
1512 * Read interrupt status from the Read-And-Clear shadow register
1513 * Note: PISR/SISR Not available on 5210
1514 */
1515 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1516 }
1517
1518 /*
1519 * Get abstract interrupt mask (driver-compatible)
1520 */
1521 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1522
1523 if (unlikely(data == AR5K_INT_NOCARD))
1524 return -ENODEV;
1525
1526 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1527 *interrupt_mask |= AR5K_INT_RX;
1528
1529 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1530 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1531 *interrupt_mask |= AR5K_INT_TX;
1532
1533 if (ah->ah_version != AR5K_AR5210) {
1534 /*HIU = Host Interface Unit (PCI etc)*/
1535 if (unlikely(data & (AR5K_ISR_HIUERR)))
1536 *interrupt_mask |= AR5K_INT_FATAL;
1537
1538 /*Beacon Not Ready*/
1539 if (unlikely(data & (AR5K_ISR_BNR)))
1540 *interrupt_mask |= AR5K_INT_BNR;
1541 }
1542
1543 /*
1544 * XXX: BMISS interrupts may occur after association.
1545 * I found this on 5210 code but it needs testing. If this is
1546 * true we should disable them before assoc and re-enable them
1547 * after a successfull assoc + some jiffies.
1548 */
1549 #if 0
1550 interrupt_mask &= ~AR5K_INT_BMISS;
1551 #endif
1552
1553 /*
1554 * In case we didn't handle anything,
1555 * print the register value.
1556 */
1557 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1558 ATH5K_PRINTF("0x%08x\n", data);
1559
1560 return 0;
1561 }
1562
1563 /*
1564 * Set interrupt mask
1565 */
1566 enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1567 {
1568 enum ath5k_int old_mask, int_mask;
1569
1570 /*
1571 * Disable card interrupts to prevent any race conditions
1572 * (they will be re-enabled afterwards).
1573 */
1574 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1575
1576 old_mask = ah->ah_imr;
1577
1578 /*
1579 * Add additional, chipset-dependent interrupt mask flags
1580 * and write them to the IMR (interrupt mask register).
1581 */
1582 int_mask = new_mask & AR5K_INT_COMMON;
1583
1584 if (new_mask & AR5K_INT_RX)
1585 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1586 AR5K_IMR_RXDESC;
1587
1588 if (new_mask & AR5K_INT_TX)
1589 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1590 AR5K_IMR_TXURN;
1591
1592 if (ah->ah_version != AR5K_AR5210) {
1593 if (new_mask & AR5K_INT_FATAL) {
1594 int_mask |= AR5K_IMR_HIUERR;
1595 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1596 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1597 }
1598 }
1599
1600 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1601
1602 /* Store new interrupt mask */
1603 ah->ah_imr = new_mask;
1604
1605 /* ..re-enable interrupts */
1606 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1607
1608 return old_mask;
1609 }
1610
1611
1612 /*************************\
1613 EEPROM access functions
1614 \*************************/
1615
1616 /*
1617 * Read from eeprom
1618 */
1619 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1620 {
1621 u32 status, timeout;
1622
1623 ATH5K_TRACE(ah->ah_sc);
1624 /*
1625 * Initialize EEPROM access
1626 */
1627 if (ah->ah_version == AR5K_AR5210) {
1628 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1629 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1630 } else {
1631 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1632 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1633 AR5K_EEPROM_CMD_READ);
1634 }
1635
1636 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1637 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1638 if (status & AR5K_EEPROM_STAT_RDDONE) {
1639 if (status & AR5K_EEPROM_STAT_RDERR)
1640 return -EIO;
1641 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1642 0xffff);
1643 return 0;
1644 }
1645 udelay(15);
1646 }
1647
1648 return -ETIMEDOUT;
1649 }
1650
1651 /*
1652 * Write to eeprom - currently disabled, use at your own risk
1653 */
1654 #if 0
1655 static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1656 {
1657
1658 u32 status, timeout;
1659
1660 ATH5K_TRACE(ah->ah_sc);
1661
1662 /*
1663 * Initialize eeprom access
1664 */
1665
1666 if (ah->ah_version == AR5K_AR5210) {
1667 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1668 } else {
1669 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1670 AR5K_EEPROM_CMD_RESET);
1671 }
1672
1673 /*
1674 * Write data to data register
1675 */
1676
1677 if (ah->ah_version == AR5K_AR5210) {
1678 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1679 } else {
1680 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1681 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1682 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1683 AR5K_EEPROM_CMD_WRITE);
1684 }
1685
1686 /*
1687 * Check status
1688 */
1689
1690 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1691 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1692 if (status & AR5K_EEPROM_STAT_WRDONE) {
1693 if (status & AR5K_EEPROM_STAT_WRERR)
1694 return EIO;
1695 return 0;
1696 }
1697 udelay(15);
1698 }
1699
1700 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1701 return -EIO;
1702 }
1703 #endif
1704
1705 /*
1706 * Translate binary channel representation in EEPROM to frequency
1707 */
1708 static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1709 {
1710 u16 val;
1711
1712 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1713 return bin;
1714
1715 if (mode == AR5K_EEPROM_MODE_11A) {
1716 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1717 val = (5 * bin) + 4800;
1718 else
1719 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1720 (bin * 10) + 5100;
1721 } else {
1722 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1723 val = bin + 2300;
1724 else
1725 val = bin + 2400;
1726 }
1727
1728 return val;
1729 }
1730
1731 /*
1732 * Read antenna infos from eeprom
1733 */
1734 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1735 unsigned int mode)
1736 {
1737 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1738 u32 o = *offset;
1739 u16 val;
1740 int ret, i = 0;
1741
1742 AR5K_EEPROM_READ(o++, val);
1743 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1744 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1745 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1746
1747 AR5K_EEPROM_READ(o++, val);
1748 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1749 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1750 ee->ee_ant_control[mode][i++] = val & 0x3f;
1751
1752 AR5K_EEPROM_READ(o++, val);
1753 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1754 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1755 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1756
1757 AR5K_EEPROM_READ(o++, val);
1758 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1759 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1760 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1761 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1762
1763 AR5K_EEPROM_READ(o++, val);
1764 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1765 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1766 ee->ee_ant_control[mode][i++] = val & 0x3f;
1767
1768 /* Get antenna modes */
1769 ah->ah_antenna[mode][0] =
1770 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1771 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1772 ee->ee_ant_control[mode][1] |
1773 (ee->ee_ant_control[mode][2] << 6) |
1774 (ee->ee_ant_control[mode][3] << 12) |
1775 (ee->ee_ant_control[mode][4] << 18) |
1776 (ee->ee_ant_control[mode][5] << 24);
1777 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1778 ee->ee_ant_control[mode][6] |
1779 (ee->ee_ant_control[mode][7] << 6) |
1780 (ee->ee_ant_control[mode][8] << 12) |
1781 (ee->ee_ant_control[mode][9] << 18) |
1782 (ee->ee_ant_control[mode][10] << 24);
1783
1784 /* return new offset */
1785 *offset = o;
1786
1787 return 0;
1788 }
1789
1790 /*
1791 * Read supported modes from eeprom
1792 */
1793 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1794 unsigned int mode)
1795 {
1796 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1797 u32 o = *offset;
1798 u16 val;
1799 int ret;
1800
1801 AR5K_EEPROM_READ(o++, val);
1802 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1803 ee->ee_thr_62[mode] = val & 0xff;
1804
1805 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1806 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1807
1808 AR5K_EEPROM_READ(o++, val);
1809 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1810 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1811
1812 AR5K_EEPROM_READ(o++, val);
1813 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1814
1815 if ((val & 0xff) & 0x80)
1816 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1817 else
1818 ee->ee_noise_floor_thr[mode] = val & 0xff;
1819
1820 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1821 ee->ee_noise_floor_thr[mode] =
1822 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1823
1824 AR5K_EEPROM_READ(o++, val);
1825 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1826 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1827 ee->ee_xpd[mode] = val & 0x1;
1828
1829 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1830 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1831
1832 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1833 AR5K_EEPROM_READ(o++, val);
1834 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1835
1836 if (mode == AR5K_EEPROM_MODE_11A)
1837 ee->ee_xr_power[mode] = val & 0x3f;
1838 else {
1839 ee->ee_ob[mode][0] = val & 0x7;
1840 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1841 }
1842 }
1843
1844 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1845 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1846 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1847 } else {
1848 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1849
1850 AR5K_EEPROM_READ(o++, val);
1851 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1852
1853 if (mode == AR5K_EEPROM_MODE_11G)
1854 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1855 }
1856
1857 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1858 mode == AR5K_EEPROM_MODE_11A) {
1859 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1860 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1861 }
1862
1863 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1864 mode == AR5K_EEPROM_MODE_11G)
1865 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
1866
1867 /* return new offset */
1868 *offset = o;
1869
1870 return 0;
1871 }
1872
1873 /*
1874 * Initialize eeprom & capabilities structs
1875 */
1876 static int ath5k_eeprom_init(struct ath5k_hw *ah)
1877 {
1878 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1879 unsigned int mode, i;
1880 int ret;
1881 u32 offset;
1882 u16 val;
1883
1884 /* Initial TX thermal adjustment values */
1885 ee->ee_tx_clip = 4;
1886 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
1887 ee->ee_gain_select = 1;
1888
1889 /*
1890 * Read values from EEPROM and store them in the capability structure
1891 */
1892 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
1893 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
1894 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
1895 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
1896 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
1897
1898 /* Return if we have an old EEPROM */
1899 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
1900 return 0;
1901
1902 #ifdef notyet
1903 /*
1904 * Validate the checksum of the EEPROM date. There are some
1905 * devices with invalid EEPROMs.
1906 */
1907 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
1908 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
1909 cksum ^= val;
1910 }
1911 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
1912 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
1913 return -EIO;
1914 }
1915 #endif
1916
1917 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
1918 ee_ant_gain);
1919
1920 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1921 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
1922 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
1923 }
1924
1925 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
1926 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
1927 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
1928 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
1929
1930 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
1931 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
1932 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
1933 }
1934
1935 /*
1936 * Get conformance test limit values
1937 */
1938 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
1939 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
1940
1941 for (i = 0; i < ee->ee_ctls; i++) {
1942 AR5K_EEPROM_READ(offset++, val);
1943 ee->ee_ctl[i] = (val >> 8) & 0xff;
1944 ee->ee_ctl[i + 1] = val & 0xff;
1945 }
1946
1947 /*
1948 * Get values for 802.11a (5GHz)
1949 */
1950 mode = AR5K_EEPROM_MODE_11A;
1951
1952 ee->ee_turbo_max_power[mode] =
1953 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
1954
1955 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
1956
1957 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1958 if (ret)
1959 return ret;
1960
1961 AR5K_EEPROM_READ(offset++, val);
1962 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1963 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
1964 ee->ee_db[mode][3] = (val >> 2) & 0x7;
1965 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1966
1967 AR5K_EEPROM_READ(offset++, val);
1968 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
1969 ee->ee_db[mode][2] = (val >> 12) & 0x7;
1970 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
1971 ee->ee_db[mode][1] = (val >> 6) & 0x7;
1972 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
1973 ee->ee_db[mode][0] = val & 0x7;
1974
1975 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1976 if (ret)
1977 return ret;
1978
1979 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
1980 AR5K_EEPROM_READ(offset++, val);
1981 ee->ee_margin_tx_rx[mode] = val & 0x3f;
1982 }
1983
1984 /*
1985 * Get values for 802.11b (2.4GHz)
1986 */
1987 mode = AR5K_EEPROM_MODE_11B;
1988 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
1989
1990 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1991 if (ret)
1992 return ret;
1993
1994 AR5K_EEPROM_READ(offset++, val);
1995 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1996 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1997 ee->ee_db[mode][1] = val & 0x7;
1998
1999 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2000 if (ret)
2001 return ret;
2002
2003 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2004 AR5K_EEPROM_READ(offset++, val);
2005 ee->ee_cal_pier[mode][0] =
2006 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2007 ee->ee_cal_pier[mode][1] =
2008 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2009
2010 AR5K_EEPROM_READ(offset++, val);
2011 ee->ee_cal_pier[mode][2] =
2012 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2013 }
2014
2015 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2016 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2017
2018 /*
2019 * Get values for 802.11g (2.4GHz)
2020 */
2021 mode = AR5K_EEPROM_MODE_11G;
2022 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
2023
2024 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2025 if (ret)
2026 return ret;
2027
2028 AR5K_EEPROM_READ(offset++, val);
2029 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2030 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2031 ee->ee_db[mode][1] = val & 0x7;
2032
2033 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2034 if (ret)
2035 return ret;
2036
2037 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2038 AR5K_EEPROM_READ(offset++, val);
2039 ee->ee_cal_pier[mode][0] =
2040 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2041 ee->ee_cal_pier[mode][1] =
2042 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2043
2044 AR5K_EEPROM_READ(offset++, val);
2045 ee->ee_turbo_max_power[mode] = val & 0x7f;
2046 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
2047
2048 AR5K_EEPROM_READ(offset++, val);
2049 ee->ee_cal_pier[mode][2] =
2050 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2051
2052 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2053 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2054
2055 AR5K_EEPROM_READ(offset++, val);
2056 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
2057 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
2058
2059 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
2060 AR5K_EEPROM_READ(offset++, val);
2061 ee->ee_cck_ofdm_gain_delta = val & 0xff;
2062 }
2063 }
2064
2065 /*
2066 * Read 5GHz EEPROM channels
2067 */
2068
2069 return 0;
2070 }
2071
2072 /*
2073 * Read the MAC address from eeprom
2074 */
2075 static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2076 {
2077 u8 mac_d[ETH_ALEN];
2078 u32 total, offset;
2079 u16 data;
2080 int octet, ret;
2081
2082 memset(mac, 0, ETH_ALEN);
2083 memset(mac_d, 0, ETH_ALEN);
2084
2085 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2086 if (ret)
2087 return ret;
2088
2089 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2090 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2091 if (ret)
2092 return ret;
2093
2094 total += data;
2095 mac_d[octet + 1] = data & 0xff;
2096 mac_d[octet] = data >> 8;
2097 octet += 2;
2098 }
2099
2100 memcpy(mac, mac_d, ETH_ALEN);
2101
2102 if (!total || total == 3 * 0xffff)
2103 return -EINVAL;
2104
2105 return 0;
2106 }
2107
2108 /*
2109 * Fill the capabilities struct
2110 */
2111 static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2112 {
2113 u16 ee_header;
2114
2115 ATH5K_TRACE(ah->ah_sc);
2116 /* Capabilities stored in the EEPROM */
2117 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2118
2119 if (ah->ah_version == AR5K_AR5210) {
2120 /*
2121 * Set radio capabilities
2122 * (The AR5110 only supports the middle 5GHz band)
2123 */
2124 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2125 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2126 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2127 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2128
2129 /* Set supported modes */
2130 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2131 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
2132 } else {
2133 /*
2134 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2135 * XXX and from 2312 to 2732GHz. There are problems with the
2136 * XXX current ieee80211 implementation because the IEEE
2137 * XXX channel mapping does not support negative channel
2138 * XXX numbers (2312MHz is channel -19). Of course, this
2139 * XXX doesn't matter because these channels are out of range
2140 * XXX but some regulation domains like MKK (Japan) will
2141 * XXX support frequencies somewhere around 4.8GHz.
2142 */
2143
2144 /*
2145 * Set radio capabilities
2146 */
2147
2148 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2149 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2150 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2151
2152 /* Set supported modes */
2153 __set_bit(AR5K_MODE_11A,
2154 ah->ah_capabilities.cap_mode);
2155 __set_bit(AR5K_MODE_11A_TURBO,
2156 ah->ah_capabilities.cap_mode);
2157 if (ah->ah_version == AR5K_AR5212)
2158 __set_bit(AR5K_MODE_11G_TURBO,
2159 ah->ah_capabilities.cap_mode);
2160 }
2161
2162 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2163 * connected */
2164 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2165 AR5K_EEPROM_HDR_11G(ee_header)) {
2166 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2167 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2168
2169 if (AR5K_EEPROM_HDR_11B(ee_header))
2170 __set_bit(AR5K_MODE_11B,
2171 ah->ah_capabilities.cap_mode);
2172
2173 if (AR5K_EEPROM_HDR_11G(ee_header))
2174 __set_bit(AR5K_MODE_11G,
2175 ah->ah_capabilities.cap_mode);
2176 }
2177 }
2178
2179 /* GPIO */
2180 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2181
2182 /* Set number of supported TX queues */
2183 if (ah->ah_version == AR5K_AR5210)
2184 ah->ah_capabilities.cap_queues.q_tx_num =
2185 AR5K_NUM_TX_QUEUES_NOQCU;
2186 else
2187 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2188
2189 return 0;
2190 }
2191
2192 /*********************************\
2193 Protocol Control Unit Functions
2194 \*********************************/
2195
2196 /*
2197 * Set Operation mode
2198 */
2199 int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2200 {
2201 u32 pcu_reg, beacon_reg, low_id, high_id;
2202
2203 pcu_reg = 0;
2204 beacon_reg = 0;
2205
2206 ATH5K_TRACE(ah->ah_sc);
2207
2208 switch (ah->ah_op_mode) {
2209 case IEEE80211_IF_TYPE_IBSS:
2210 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2211 (ah->ah_version == AR5K_AR5210 ?
2212 AR5K_STA_ID1_NO_PSPOLL : 0);
2213 beacon_reg |= AR5K_BCR_ADHOC;
2214 break;
2215
2216 case IEEE80211_IF_TYPE_AP:
2217 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2218 (ah->ah_version == AR5K_AR5210 ?
2219 AR5K_STA_ID1_NO_PSPOLL : 0);
2220 beacon_reg |= AR5K_BCR_AP;
2221 break;
2222
2223 case IEEE80211_IF_TYPE_STA:
2224 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2225 (ah->ah_version == AR5K_AR5210 ?
2226 AR5K_STA_ID1_PWR_SV : 0);
2227 case IEEE80211_IF_TYPE_MNTR:
2228 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2229 (ah->ah_version == AR5K_AR5210 ?
2230 AR5K_STA_ID1_NO_PSPOLL : 0);
2231 break;
2232
2233 default:
2234 return -EINVAL;
2235 }
2236
2237 /*
2238 * Set PCU registers
2239 */
2240 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2241 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2242 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2243 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2244
2245 /*
2246 * Set Beacon Control Register on 5210
2247 */
2248 if (ah->ah_version == AR5K_AR5210)
2249 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2250
2251 return 0;
2252 }
2253
2254 /*
2255 * BSSID Functions
2256 */
2257
2258 /*
2259 * Get station id
2260 */
2261 void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2262 {
2263 ATH5K_TRACE(ah->ah_sc);
2264 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2265 }
2266
2267 /*
2268 * Set station id
2269 */
2270 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2271 {
2272 u32 low_id, high_id;
2273
2274 ATH5K_TRACE(ah->ah_sc);
2275 /* Set new station ID */
2276 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2277
2278 low_id = AR5K_LOW_ID(mac);
2279 high_id = AR5K_HIGH_ID(mac);
2280
2281 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2282 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2283
2284 return 0;
2285 }
2286
2287 /*
2288 * Set BSSID
2289 */
2290 void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2291 {
2292 u32 low_id, high_id;
2293 u16 tim_offset = 0;
2294
2295 /*
2296 * Set simple BSSID mask on 5212
2297 */
2298 if (ah->ah_version == AR5K_AR5212) {
2299 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);
2300 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);
2301 }
2302
2303 /*
2304 * Set BSSID which triggers the "SME Join" operation
2305 */
2306 low_id = AR5K_LOW_ID(bssid);
2307 high_id = AR5K_HIGH_ID(bssid);
2308 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2309 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2310 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2311
2312 if (assoc_id == 0) {
2313 ath5k_hw_disable_pspoll(ah);
2314 return;
2315 }
2316
2317 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2318 tim_offset ? tim_offset + 4 : 0);
2319
2320 ath5k_hw_enable_pspoll(ah, NULL, 0);
2321 }
2322 /**
2323 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2324 *
2325 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2326 * which bits of the interface's MAC address should be looked at when trying
2327 * to decide which packets to ACK. In station mode every bit matters. In AP
2328 * mode with a single BSS every bit matters as well. In AP mode with
2329 * multiple BSSes not every bit matters.
2330 *
2331 * @ah: the &struct ath5k_hw
2332 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2333 *
2334 * Note that this is a simple filter and *does* not filter out all
2335 * relevant frames. Some non-relevant frames will get through, probability
2336 * jocks are welcomed to compute.
2337 *
2338 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2339 * computing the set of:
2340 *
2341 * ~ ( MAC XOR BSSID )
2342 *
2343 * When you do this you are essentially computing the common bits. Later it
2344 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2345 * to obtain the relevant bits which should match on the destination frame.
2346 *
2347 * Simple example: on your card you have have two BSSes you have created with
2348 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2349 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2350 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2351 *
2352 * \
2353 * MAC: 0001 |
2354 * BSSID-01: 0100 | --> Belongs to us
2355 * BSSID-02: 1001 |
2356 * /
2357 * -------------------
2358 * BSSID-03: 0110 | --> External
2359 * -------------------
2360 *
2361 * Our bssid_mask would then be:
2362 *
2363 * On loop iteration for BSSID-01:
2364 * ~(0001 ^ 0100) -> ~(0101)
2365 * -> 1010
2366 * bssid_mask = 1010
2367 *
2368 * On loop iteration for BSSID-02:
2369 * bssid_mask &= ~(0001 ^ 1001)
2370 * bssid_mask = (1010) & ~(0001 ^ 1001)
2371 * bssid_mask = (1010) & ~(1001)
2372 * bssid_mask = (1010) & (0110)
2373 * bssid_mask = 0010
2374 *
2375 * A bssid_mask of 0010 means "only pay attention to the second least
2376 * significant bit". This is because its the only bit common
2377 * amongst the MAC and all BSSIDs we support. To findout what the real
2378 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2379 * or our MAC address (we assume the hardware uses the MAC address).
2380 *
2381 * Now, suppose there's an incoming frame for BSSID-03:
2382 *
2383 * IFRAME-01: 0110
2384 *
2385 * An easy eye-inspeciton of this already should tell you that this frame
2386 * will not pass our check. This is beacuse the bssid_mask tells the
2387 * hardware to only look at the second least significant bit and the
2388 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2389 * as 1, which does not match 0.
2390 *
2391 * So with IFRAME-01 we *assume* the hardware will do:
2392 *
2393 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2394 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2395 * --> allow = (0010) == 0000 ? 1 : 0;
2396 * --> allow = 0
2397 *
2398 * Lets now test a frame that should work:
2399 *
2400 * IFRAME-02: 0001 (we should allow)
2401 *
2402 * allow = (0001 & 1010) == 1010
2403 *
2404 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2405 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2406 * --> allow = (0010) == (0010)
2407 * --> allow = 1
2408 *
2409 * Other examples:
2410 *
2411 * IFRAME-03: 0100 --> allowed
2412 * IFRAME-04: 1001 --> allowed
2413 * IFRAME-05: 1101 --> allowed but its not for us!!!
2414 *
2415 */
2416 int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2417 {
2418 u32 low_id, high_id;
2419 ATH5K_TRACE(ah->ah_sc);
2420
2421 if (ah->ah_version == AR5K_AR5212) {
2422 low_id = AR5K_LOW_ID(mask);
2423 high_id = AR5K_HIGH_ID(mask);
2424
2425 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2426 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2427
2428 return 0;
2429 }
2430
2431 return -EIO;
2432 }
2433
2434 /*
2435 * Receive start/stop functions
2436 */
2437
2438 /*
2439 * Start receive on PCU
2440 */
2441 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2442 {
2443 ATH5K_TRACE(ah->ah_sc);
2444 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2445
2446 /* TODO: ANI Support */
2447 }
2448
2449 /*
2450 * Stop receive on PCU
2451 */
2452 void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2453 {
2454 ATH5K_TRACE(ah->ah_sc);
2455 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2456
2457 /* TODO: ANI Support */
2458 }
2459
2460 /*
2461 * RX Filter functions
2462 */
2463
2464 /*
2465 * Set multicast filter
2466 */
2467 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2468 {
2469 ATH5K_TRACE(ah->ah_sc);
2470 /* Set the multicat filter */
2471 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2472 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2473 }
2474
2475 /*
2476 * Set multicast filter by index
2477 */
2478 int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2479 {
2480
2481 ATH5K_TRACE(ah->ah_sc);
2482 if (index >= 64)
2483 return -EINVAL;
2484 else if (index >= 32)
2485 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2486 (1 << (index - 32)));
2487 else
2488 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2489
2490 return 0;
2491 }
2492
2493 /*
2494 * Clear Multicast filter by index
2495 */
2496 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2497 {
2498
2499 ATH5K_TRACE(ah->ah_sc);
2500 if (index >= 64)
2501 return -EINVAL;
2502 else if (index >= 32)
2503 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2504 (1 << (index - 32)));
2505 else
2506 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2507
2508 return 0;
2509 }
2510
2511 /*
2512 * Get current rx filter
2513 */
2514 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2515 {
2516 u32 data, filter = 0;
2517
2518 ATH5K_TRACE(ah->ah_sc);
2519 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2520
2521 /*Radar detection for 5212*/
2522 if (ah->ah_version == AR5K_AR5212) {
2523 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2524
2525 if (data & AR5K_PHY_ERR_FIL_RADAR)
2526 filter |= AR5K_RX_FILTER_RADARERR;
2527 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2528 filter |= AR5K_RX_FILTER_PHYERR;
2529 }
2530
2531 return filter;
2532 }
2533
2534 /*
2535 * Set rx filter
2536 */
2537 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2538 {
2539 u32 data = 0;
2540
2541 ATH5K_TRACE(ah->ah_sc);
2542
2543 /* Set PHY error filter register on 5212*/
2544 if (ah->ah_version == AR5K_AR5212) {
2545 if (filter & AR5K_RX_FILTER_RADARERR)
2546 data |= AR5K_PHY_ERR_FIL_RADAR;
2547 if (filter & AR5K_RX_FILTER_PHYERR)
2548 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2549 }
2550
2551 /*
2552 * The AR5210 uses promiscous mode to detect radar activity
2553 */
2554 if (ah->ah_version == AR5K_AR5210 &&
2555 (filter & AR5K_RX_FILTER_RADARERR)) {
2556 filter &= ~AR5K_RX_FILTER_RADARERR;
2557 filter |= AR5K_RX_FILTER_PROM;
2558 }
2559
2560 /*Zero length DMA*/
2561 if (data)
2562 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2563 else
2564 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2565
2566 /*Write RX Filter register*/
2567 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2568
2569 /*Write PHY error filter register on 5212*/
2570 if (ah->ah_version == AR5K_AR5212)
2571 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2572
2573 }
2574
2575 /*
2576 * Beacon related functions
2577 */
2578
2579 /*
2580 * Get a 32bit TSF
2581 */
2582 u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2583 {
2584 ATH5K_TRACE(ah->ah_sc);
2585 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2586 }
2587
2588 /*
2589 * Get the full 64bit TSF
2590 */
2591 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2592 {
2593 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2594 ATH5K_TRACE(ah->ah_sc);
2595
2596 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2597 }
2598
2599 /*
2600 * Force a TSF reset
2601 */
2602 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2603 {
2604 ATH5K_TRACE(ah->ah_sc);
2605 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2606 }
2607
2608 /*
2609 * Initialize beacon timers
2610 */
2611 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2612 {
2613 u32 timer1, timer2, timer3;
2614
2615 ATH5K_TRACE(ah->ah_sc);
2616 /*
2617 * Set the additional timers by mode
2618 */
2619 switch (ah->ah_op_mode) {
2620 case IEEE80211_IF_TYPE_STA:
2621 if (ah->ah_version == AR5K_AR5210) {
2622 timer1 = 0xffffffff;
2623 timer2 = 0xffffffff;
2624 } else {
2625 timer1 = 0x0000ffff;
2626 timer2 = 0x0007ffff;
2627 }
2628 break;
2629
2630 default:
2631 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2632 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
2633 }
2634
2635 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2636
2637 /*
2638 * Set the beacon register and enable all timers.
2639 * (next beacon, DMA beacon, software beacon, ATIM window time)
2640 */
2641 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2642 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2643 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2644 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2645
2646 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2647 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2648 AR5K_BEACON);
2649 }
2650
2651 #if 0
2652 /*
2653 * Set beacon timers
2654 */
2655 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2656 const struct ath5k_beacon_state *state)
2657 {
2658 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2659
2660 /*
2661 * TODO: should be changed through *state
2662 * review struct ath5k_beacon_state struct
2663 *
2664 * XXX: These are used for cfp period bellow, are they
2665 * ok ? Is it O.K. for tsf here to be 0 or should we use
2666 * get_tsf ?
2667 */
2668 u32 dtim_count = 0; /* XXX */
2669 u32 cfp_count = 0; /* XXX */
2670 u32 tsf = 0; /* XXX */
2671
2672 ATH5K_TRACE(ah->ah_sc);
2673 /* Return on an invalid beacon state */
2674 if (state->bs_interval < 1)
2675 return -EINVAL;
2676
2677 interval = state->bs_interval;
2678 dtim = state->bs_dtim_period;
2679
2680 /*
2681 * PCF support?
2682 */
2683 if (state->bs_cfp_period > 0) {
2684 /*
2685 * Enable PCF mode and set the CFP
2686 * (Contention Free Period) and timer registers
2687 */
2688 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2689 state->bs_interval;
2690 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2691 state->bs_interval;
2692
2693 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2694 AR5K_STA_ID1_DEFAULT_ANTENNA |
2695 AR5K_STA_ID1_PCF);
2696 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2697 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2698 AR5K_CFP_DUR);
2699 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2700 next_cfp)) << 3, AR5K_TIMER2);
2701 } else {
2702 /* Disable PCF mode */
2703 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2704 AR5K_STA_ID1_DEFAULT_ANTENNA |
2705 AR5K_STA_ID1_PCF);
2706 }
2707
2708 /*
2709 * Enable the beacon timer register
2710 */
2711 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2712
2713 /*
2714 * Start the beacon timers
2715 */
2716 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2717 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2718 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2719 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2720 AR5K_BEACON_PERIOD), AR5K_BEACON);
2721
2722 /*
2723 * Write new beacon miss threshold, if it appears to be valid
2724 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2725 * and return if its not in range. We can test this by reading value and
2726 * setting value to a largest value and seeing which values register.
2727 */
2728
2729 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2730 state->bs_bmiss_threshold);
2731
2732 /*
2733 * Set sleep control register
2734 * XXX: Didn't find this in 5210 code but since this register
2735 * exists also in ar5k's 5210 headers i leave it as common code.
2736 */
2737 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2738 (state->bs_sleep_duration - 3) << 3);
2739
2740 /*
2741 * Set enhanced sleep registers on 5212
2742 */
2743 if (ah->ah_version == AR5K_AR5212) {
2744 if (state->bs_sleep_duration > state->bs_interval &&
2745 roundup(state->bs_sleep_duration, interval) ==
2746 state->bs_sleep_duration)
2747 interval = state->bs_sleep_duration;
2748
2749 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2750 roundup(state->bs_sleep_duration, dtim) ==
2751 state->bs_sleep_duration))
2752 dtim = state->bs_sleep_duration;
2753
2754 if (interval > dtim)
2755 return -EINVAL;
2756
2757 next_beacon = interval == dtim ? state->bs_next_dtim :
2758 state->bs_next_beacon;
2759
2760 ath5k_hw_reg_write(ah,
2761 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2762 AR5K_SLEEP0_NEXT_DTIM) |
2763 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2764 AR5K_SLEEP0_ENH_SLEEP_EN |
2765 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2766
2767 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2768 AR5K_SLEEP1_NEXT_TIM) |
2769 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2770
2771 ath5k_hw_reg_write(ah,
2772 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2773 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2774 }
2775
2776 return 0;
2777 }
2778
2779 /*
2780 * Reset beacon timers
2781 */
2782 void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2783 {
2784 ATH5K_TRACE(ah->ah_sc);
2785 /*
2786 * Disable beacon timer
2787 */
2788 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2789
2790 /*
2791 * Disable some beacon register values
2792 */
2793 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2794 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2795 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2796 }
2797
2798 /*
2799 * Wait for beacon queue to finish
2800 */
2801 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2802 {
2803 unsigned int i;
2804 int ret;
2805
2806 ATH5K_TRACE(ah->ah_sc);
2807
2808 /* 5210 doesn't have QCU*/
2809 if (ah->ah_version == AR5K_AR5210) {
2810 /*
2811 * Wait for beaconn queue to finish by checking
2812 * Control Register and Beacon Status Register.
2813 */
2814 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2815 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2816 ||
2817 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2818 break;
2819 udelay(10);
2820 }
2821
2822 /* Timeout... */
2823 if (i <= 0) {
2824 /*
2825 * Re-schedule the beacon queue
2826 */
2827 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2828 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2829 AR5K_BCR);
2830
2831 return -EIO;
2832 }
2833 ret = 0;
2834 } else {
2835 /*5211/5212*/
2836 ret = ath5k_hw_register_timeout(ah,
2837 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2838 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2839
2840 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2841 return -EIO;
2842 }
2843
2844 return ret;
2845 }
2846 #endif
2847
2848 /*
2849 * Update mib counters (statistics)
2850 */
2851 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2852 struct ath5k_mib_stats *statistics)
2853 {
2854 ATH5K_TRACE(ah->ah_sc);
2855 /* Read-And-Clear */
2856 statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2857 statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2858 statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2859 statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2860 statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2861
2862 /* Reset profile count registers on 5212*/
2863 if (ah->ah_version == AR5K_AR5212) {
2864 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
2865 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
2866 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
2867 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
2868 }
2869 }
2870
2871 /** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
2872 *
2873 * @ah: the &struct ath5k_hw
2874 * @high: determines if to use low bit rate or now
2875 */
2876 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
2877 {
2878 if (ah->ah_version != AR5K_AR5212)
2879 return;
2880 else {
2881 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
2882 if (high)
2883 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
2884 else
2885 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
2886 }
2887 }
2888
2889
2890 /*
2891 * ACK/CTS Timeouts
2892 */
2893
2894 /*
2895 * Set ACK timeout on PCU
2896 */
2897 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
2898 {
2899 ATH5K_TRACE(ah->ah_sc);
2900 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
2901 ah->ah_turbo) <= timeout)
2902 return -EINVAL;
2903
2904 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
2905 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2906
2907 return 0;
2908 }
2909
2910 /*
2911 * Read the ACK timeout from PCU
2912 */
2913 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
2914 {
2915 ATH5K_TRACE(ah->ah_sc);
2916
2917 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2918 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
2919 }
2920
2921 /*
2922 * Set CTS timeout on PCU
2923 */
2924 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
2925 {
2926 ATH5K_TRACE(ah->ah_sc);
2927 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
2928 ah->ah_turbo) <= timeout)
2929 return -EINVAL;
2930
2931 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
2932 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2933
2934 return 0;
2935 }
2936
2937 /*
2938 * Read CTS timeout from PCU
2939 */
2940 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
2941 {
2942 ATH5K_TRACE(ah->ah_sc);
2943 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2944 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
2945 }
2946
2947 /*
2948 * Key table (WEP) functions
2949 */
2950
2951 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
2952 {
2953 unsigned int i;
2954
2955 ATH5K_TRACE(ah->ah_sc);
2956 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2957
2958 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
2959 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
2960
2961 /* Set NULL encryption on non-5210*/
2962 if (ah->ah_version != AR5K_AR5210)
2963 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
2964 AR5K_KEYTABLE_TYPE(entry));
2965
2966 return 0;
2967 }
2968
2969 int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
2970 {
2971 ATH5K_TRACE(ah->ah_sc);
2972 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2973
2974 /* Check the validation flag at the end of the entry */
2975 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
2976 AR5K_KEYTABLE_VALID;
2977 }
2978
2979 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
2980 const struct ieee80211_key_conf *key, const u8 *mac)
2981 {
2982 unsigned int i;
2983 __le32 key_v[5] = {};
2984 u32 keytype;
2985
2986 ATH5K_TRACE(ah->ah_sc);
2987
2988 /* key->keylen comes in from mac80211 in bytes */
2989
2990 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
2991 return -EOPNOTSUPP;
2992
2993 switch (key->keylen) {
2994 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
2995 case 40 / 8:
2996 memcpy(&key_v[0], key->key, 5);
2997 keytype = AR5K_KEYTABLE_TYPE_40;
2998 break;
2999
3000 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
3001 case 104 / 8:
3002 memcpy(&key_v[0], &key->key[0], 6);
3003 memcpy(&key_v[2], &key->key[6], 6);
3004 memcpy(&key_v[4], &key->key[12], 1);
3005 keytype = AR5K_KEYTABLE_TYPE_104;
3006 break;
3007 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
3008 case 128 / 8:
3009 memcpy(&key_v[0], &key->key[0], 6);
3010 memcpy(&key_v[2], &key->key[6], 6);
3011 memcpy(&key_v[4], &key->key[12], 4);
3012 keytype = AR5K_KEYTABLE_TYPE_128;
3013 break;
3014
3015 default:
3016 return -EINVAL; /* shouldn't happen */
3017 }
3018
3019 for (i = 0; i < ARRAY_SIZE(key_v); i++)
3020 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
3021 AR5K_KEYTABLE_OFF(entry, i));
3022
3023 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
3024
3025 return ath5k_hw_set_key_lladdr(ah, entry, mac);
3026 }
3027
3028 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
3029 {
3030 u32 low_id, high_id;
3031
3032 ATH5K_TRACE(ah->ah_sc);
3033 /* Invalid entry (key table overflow) */
3034 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3035
3036 /* MAC may be NULL if it's a broadcast key. In this case no need to
3037 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
3038 if (unlikely(mac == NULL)) {
3039 low_id = 0xffffffff;
3040 high_id = 0xffff | AR5K_KEYTABLE_VALID;
3041 } else {
3042 low_id = AR5K_LOW_ID(mac);
3043 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
3044 }
3045
3046 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
3047 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
3048
3049 return 0;
3050 }
3051
3052
3053 /********************************************\
3054 Queue Control Unit, DFS Control Unit Functions
3055 \********************************************/
3056
3057 /*
3058 * Initialize a transmit queue
3059 */
3060 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3061 struct ath5k_txq_info *queue_info)
3062 {
3063 unsigned int queue;
3064 int ret;
3065
3066 ATH5K_TRACE(ah->ah_sc);
3067
3068 /*
3069 * Get queue by type
3070 */
3071 /*5210 only has 2 queues*/
3072 if (ah->ah_version == AR5K_AR5210) {
3073 switch (queue_type) {
3074 case AR5K_TX_QUEUE_DATA:
3075 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3076 break;
3077 case AR5K_TX_QUEUE_BEACON:
3078 case AR5K_TX_QUEUE_CAB:
3079 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3080 break;
3081 default:
3082 return -EINVAL;
3083 }
3084 } else {
3085 switch (queue_type) {
3086 case AR5K_TX_QUEUE_DATA:
3087 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3088 ah->ah_txq[queue].tqi_type !=
3089 AR5K_TX_QUEUE_INACTIVE; queue++) {
3090
3091 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3092 return -EINVAL;
3093 }
3094 break;
3095 case AR5K_TX_QUEUE_UAPSD:
3096 queue = AR5K_TX_QUEUE_ID_UAPSD;
3097 break;
3098 case AR5K_TX_QUEUE_BEACON:
3099 queue = AR5K_TX_QUEUE_ID_BEACON;
3100 break;
3101 case AR5K_TX_QUEUE_CAB:
3102 queue = AR5K_TX_QUEUE_ID_CAB;
3103 break;
3104 case AR5K_TX_QUEUE_XR_DATA:
3105 if (ah->ah_version != AR5K_AR5212)
3106 ATH5K_ERR(ah->ah_sc,
3107 "XR data queues only supported in"
3108 " 5212!\n");
3109 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3110 break;
3111 default:
3112 return -EINVAL;
3113 }
3114 }
3115
3116 /*
3117 * Setup internal queue structure
3118 */
3119 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3120 ah->ah_txq[queue].tqi_type = queue_type;
3121
3122 if (queue_info != NULL) {
3123 queue_info->tqi_type = queue_type;
3124 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3125 if (ret)
3126 return ret;
3127 }
3128 /*
3129 * We use ah_txq_status to hold a temp value for
3130 * the Secondary interrupt mask registers on 5211+
3131 * check out ath5k_hw_reset_tx_queue
3132 */
3133 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3134
3135 return queue;
3136 }
3137
3138 /*
3139 * Setup a transmit queue
3140 */
3141 int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3142 const struct ath5k_txq_info *queue_info)
3143 {
3144 ATH5K_TRACE(ah->ah_sc);
3145 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3146
3147 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3148 return -EIO;
3149
3150 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3151
3152 /*XXX: Is this supported on 5210 ?*/
3153 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3154 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3155 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3156 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3157 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3158
3159 return 0;
3160 }
3161
3162 /*
3163 * Get properties for a specific transmit queue
3164 */
3165 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3166 struct ath5k_txq_info *queue_info)
3167 {
3168 ATH5K_TRACE(ah->ah_sc);
3169 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3170 return 0;
3171 }
3172
3173 /*
3174 * Set a transmit queue inactive
3175 */
3176 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3177 {
3178 ATH5K_TRACE(ah->ah_sc);
3179 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3180 return;
3181
3182 /* This queue will be skipped in further operations */
3183 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3184 /*For SIMR setup*/
3185 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3186 }
3187
3188 /*
3189 * Set DFS params for a transmit queue
3190 */
3191 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3192 {
3193 u32 cw_min, cw_max, retry_lg, retry_sh;
3194 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3195
3196 ATH5K_TRACE(ah->ah_sc);
3197 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3198
3199 tq = &ah->ah_txq[queue];
3200
3201 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3202 return 0;
3203
3204 if (ah->ah_version == AR5K_AR5210) {
3205 /* Only handle data queues, others will be ignored */
3206 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3207 return 0;
3208
3209 /* Set Slot time */
3210 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3211 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3212 AR5K_SLOT_TIME);
3213 /* Set ACK_CTS timeout */
3214 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3215 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3216 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3217 /* Set Transmit Latency */
3218 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3219 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3220 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3221 /* Set IFS0 */
3222 if (ah->ah_turbo)
3223 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3224 (ah->ah_aifs + tq->tqi_aifs) *
3225 AR5K_INIT_SLOT_TIME_TURBO) <<
3226 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3227 AR5K_IFS0);
3228 else
3229 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3230 (ah->ah_aifs + tq->tqi_aifs) *
3231 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3232 AR5K_INIT_SIFS, AR5K_IFS0);
3233
3234 /* Set IFS1 */
3235 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3236 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3237 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3238 /* Set PHY register 0x9844 (??) */
3239 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3240 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3241 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3242 AR5K_PHY(17));
3243 /* Set Frame Control Register */
3244 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3245 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3246 AR5K_PHY_TURBO_SHORT | 0x2020) :
3247 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3248 AR5K_PHY_FRAME_CTL_5210);
3249 }
3250
3251 /*
3252 * Calculate cwmin/max by channel mode
3253 */
3254 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3255 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3256 ah->ah_aifs = AR5K_TUNE_AIFS;
3257 /*XR is only supported on 5212*/
3258 if (IS_CHAN_XR(ah->ah_current_channel) &&
3259 ah->ah_version == AR5K_AR5212) {
3260 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3261 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3262 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3263 /*B mode is not supported on 5210*/
3264 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3265 ah->ah_version != AR5K_AR5210) {
3266 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3267 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3268 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3269 }
3270
3271 cw_min = 1;
3272 while (cw_min < ah->ah_cw_min)
3273 cw_min = (cw_min << 1) | 1;
3274
3275 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3276 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3277 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3278 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3279
3280 /*
3281 * Calculate and set retry limits
3282 */
3283 if (ah->ah_software_retry) {
3284 /* XXX Need to test this */
3285 retry_lg = ah->ah_limit_tx_retries;
3286 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3287 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3288 } else {
3289 retry_lg = AR5K_INIT_LG_RETRY;
3290 retry_sh = AR5K_INIT_SH_RETRY;
3291 }
3292
3293 /*No QCU/DCU [5210]*/
3294 if (ah->ah_version == AR5K_AR5210) {
3295 ath5k_hw_reg_write(ah,
3296 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3297 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3298 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3299 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3300 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3301 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3302 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3303 AR5K_NODCU_RETRY_LMT);
3304 } else {
3305 /*QCU/DCU [5211+]*/
3306 ath5k_hw_reg_write(ah,
3307 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3308 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3309 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3310 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3311 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3312 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3313 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3314
3315 /*===Rest is also for QCU/DCU only [5211+]===*/
3316
3317 /*
3318 * Set initial content window (cw_min/cw_max)
3319 * and arbitrated interframe space (aifs)...
3320 */
3321 ath5k_hw_reg_write(ah,
3322 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3323 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3324 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3325 AR5K_DCU_LCL_IFS_AIFS),
3326 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3327
3328 /*
3329 * Set misc registers
3330 */
3331 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3332 AR5K_QUEUE_MISC(queue));
3333
3334 if (tq->tqi_cbr_period) {
3335 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3336 AR5K_QCU_CBRCFG_INTVAL) |
3337 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3338 AR5K_QCU_CBRCFG_ORN_THRES),
3339 AR5K_QUEUE_CBRCFG(queue));
3340 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3341 AR5K_QCU_MISC_FRSHED_CBR);
3342 if (tq->tqi_cbr_overflow_limit)
3343 AR5K_REG_ENABLE_BITS(ah,
3344 AR5K_QUEUE_MISC(queue),
3345 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3346 }
3347
3348 if (tq->tqi_ready_time)
3349 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3350 AR5K_QCU_RDYTIMECFG_INTVAL) |
3351 AR5K_QCU_RDYTIMECFG_ENABLE,
3352 AR5K_QUEUE_RDYTIMECFG(queue));
3353
3354 if (tq->tqi_burst_time) {
3355 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3356 AR5K_DCU_CHAN_TIME_DUR) |
3357 AR5K_DCU_CHAN_TIME_ENABLE,
3358 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3359
3360 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3361 AR5K_REG_ENABLE_BITS(ah,
3362 AR5K_QUEUE_MISC(queue),
3363 AR5K_QCU_MISC_TXE);
3364 }
3365
3366 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3367 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3368 AR5K_QUEUE_DFS_MISC(queue));
3369
3370 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3371 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3372 AR5K_QUEUE_DFS_MISC(queue));
3373
3374 /*
3375 * Set registers by queue type
3376 */
3377 switch (tq->tqi_type) {
3378 case AR5K_TX_QUEUE_BEACON:
3379 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3380 AR5K_QCU_MISC_FRSHED_DBA_GT |
3381 AR5K_QCU_MISC_CBREXP_BCN |
3382 AR5K_QCU_MISC_BCN_ENABLE);
3383
3384 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3385 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3386 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3387 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3388 AR5K_DCU_MISC_BCN_ENABLE);
3389
3390 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3391 (AR5K_TUNE_SW_BEACON_RESP -
3392 AR5K_TUNE_DMA_BEACON_RESP) -
3393 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3394 AR5K_QCU_RDYTIMECFG_ENABLE,
3395 AR5K_QUEUE_RDYTIMECFG(queue));
3396 break;
3397
3398 case AR5K_TX_QUEUE_CAB:
3399 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3400 AR5K_QCU_MISC_FRSHED_DBA_GT |
3401 AR5K_QCU_MISC_CBREXP |
3402 AR5K_QCU_MISC_CBREXP_BCN);
3403
3404 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3405 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3406 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3407 break;
3408
3409 case AR5K_TX_QUEUE_UAPSD:
3410 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3411 AR5K_QCU_MISC_CBREXP);
3412 break;
3413
3414 case AR5K_TX_QUEUE_DATA:
3415 default:
3416 break;
3417 }
3418
3419 /*
3420 * Enable interrupts for this tx queue
3421 * in the secondary interrupt mask registers
3422 */
3423 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3424 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3425
3426 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3427 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3428
3429 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3430 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3431
3432 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3433 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3434
3435 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3436 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3437
3438
3439 /* Update secondary interrupt mask registers */
3440 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3441 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3442 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3443 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3444 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3445
3446 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3447 AR5K_SIMR0_QCU_TXOK) |
3448 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3449 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3450 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3451 AR5K_SIMR1_QCU_TXERR) |
3452 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3453 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3454 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3455 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3456 }
3457
3458 return 0;
3459 }
3460
3461 /*
3462 * Get number of pending frames
3463 * for a specific queue [5211+]
3464 */
3465 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3466 ATH5K_TRACE(ah->ah_sc);
3467 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3468
3469 /* Return if queue is declared inactive */
3470 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3471 return false;
3472
3473 /* XXX: How about AR5K_CFG_TXCNT ? */
3474 if (ah->ah_version == AR5K_AR5210)
3475 return false;
3476
3477 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3478 }
3479
3480 /*
3481 * Set slot time
3482 */
3483 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3484 {
3485 ATH5K_TRACE(ah->ah_sc);
3486 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3487 return -EINVAL;
3488
3489 if (ah->ah_version == AR5K_AR5210)
3490 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3491 ah->ah_turbo), AR5K_SLOT_TIME);
3492 else
3493 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3494
3495 return 0;
3496 }
3497
3498 /*
3499 * Get slot time
3500 */
3501 unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3502 {
3503 ATH5K_TRACE(ah->ah_sc);
3504 if (ah->ah_version == AR5K_AR5210)
3505 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3506 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3507 else
3508 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3509 }
3510
3511
3512 /******************************\
3513 Hardware Descriptor Functions
3514 \******************************/
3515
3516 /*
3517 * TX Descriptor
3518 */
3519
3520 /*
3521 * Initialize the 2-word tx descriptor on 5210/5211
3522 */
3523 static int
3524 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3525 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3526 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3527 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3528 unsigned int rtscts_rate, unsigned int rtscts_duration)
3529 {
3530 u32 frame_type;
3531 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3532 unsigned int frame_len;
3533
3534 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3535
3536 /*
3537 * Validate input
3538 * - Zero retries don't make sense.
3539 * - A zero rate will put the HW into a mode where it continously sends
3540 * noise on the channel, so it is important to avoid this.
3541 */
3542 if (unlikely(tx_tries0 == 0)) {
3543 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3544 WARN_ON(1);
3545 return -EINVAL;
3546 }
3547 if (unlikely(tx_rate0 == 0)) {
3548 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3549 WARN_ON(1);
3550 return -EINVAL;
3551 }
3552
3553 /* Clear descriptor */
3554 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
3555
3556 /* Setup control descriptor */
3557
3558 /* Verify and set frame length */
3559
3560 /* remove padding we might have added before */
3561 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3562
3563 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3564 return -EINVAL;
3565
3566 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3567
3568 /* Verify and set buffer length */
3569
3570 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3571 if(type == AR5K_PKT_TYPE_BEACON)
3572 pkt_len = roundup(pkt_len, 4);
3573
3574 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3575 return -EINVAL;
3576
3577 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3578
3579 /*
3580 * Verify and set header length
3581 * XXX: I only found that on 5210 code, does it work on 5211 ?
3582 */
3583 if (ah->ah_version == AR5K_AR5210) {
3584 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3585 return -EINVAL;
3586 tx_ctl->tx_control_0 |=
3587 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3588 }
3589
3590 /*Diferences between 5210-5211*/
3591 if (ah->ah_version == AR5K_AR5210) {
3592 switch (type) {
3593 case AR5K_PKT_TYPE_BEACON:
3594 case AR5K_PKT_TYPE_PROBE_RESP:
3595 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3596 case AR5K_PKT_TYPE_PIFS:
3597 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3598 default:
3599 frame_type = type /*<< 2 ?*/;
3600 }
3601
3602 tx_ctl->tx_control_0 |=
3603 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3604 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3605 } else {
3606 tx_ctl->tx_control_0 |=
3607 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3608 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3609 tx_ctl->tx_control_1 |=
3610 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3611 }
3612 #define _TX_FLAGS(_c, _flag) \
3613 if (flags & AR5K_TXDESC_##_flag) \
3614 tx_ctl->tx_control_##_c |= \
3615 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3616
3617 _TX_FLAGS(0, CLRDMASK);
3618 _TX_FLAGS(0, VEOL);
3619 _TX_FLAGS(0, INTREQ);
3620 _TX_FLAGS(0, RTSENA);
3621 _TX_FLAGS(1, NOACK);
3622
3623 #undef _TX_FLAGS
3624
3625 /*
3626 * WEP crap
3627 */
3628 if (key_index != AR5K_TXKEYIX_INVALID) {
3629 tx_ctl->tx_control_0 |=
3630 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3631 tx_ctl->tx_control_1 |=
3632 AR5K_REG_SM(key_index,
3633 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3634 }
3635
3636 /*
3637 * RTS/CTS Duration [5210 ?]
3638 */
3639 if ((ah->ah_version == AR5K_AR5210) &&
3640 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3641 tx_ctl->tx_control_1 |= rtscts_duration &
3642 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3643
3644 return 0;
3645 }
3646
3647 /*
3648 * Initialize the 4-word tx descriptor on 5212
3649 */
3650 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3651 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3652 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3653 unsigned int tx_tries0, unsigned int key_index,
3654 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3655 unsigned int rtscts_duration)
3656 {
3657 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3658 unsigned int frame_len;
3659
3660 ATH5K_TRACE(ah->ah_sc);
3661 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3662
3663 /*
3664 * Validate input
3665 * - Zero retries don't make sense.
3666 * - A zero rate will put the HW into a mode where it continously sends
3667 * noise on the channel, so it is important to avoid this.
3668 */
3669 if (unlikely(tx_tries0 == 0)) {
3670 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3671 WARN_ON(1);
3672 return -EINVAL;
3673 }
3674 if (unlikely(tx_rate0 == 0)) {
3675 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3676 WARN_ON(1);
3677 return -EINVAL;
3678 }
3679
3680 /* Clear descriptor */
3681 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
3682
3683 /* Setup control descriptor */
3684
3685 /* Verify and set frame length */
3686
3687 /* remove padding we might have added before */
3688 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3689
3690 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3691 return -EINVAL;
3692
3693 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3694
3695 /* Verify and set buffer length */
3696
3697 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3698 if(type == AR5K_PKT_TYPE_BEACON)
3699 pkt_len = roundup(pkt_len, 4);
3700
3701 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3702 return -EINVAL;
3703
3704 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3705
3706 tx_ctl->tx_control_0 |=
3707 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3708 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3709 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
3710 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3711 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3712 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3713 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3714
3715 #define _TX_FLAGS(_c, _flag) \
3716 if (flags & AR5K_TXDESC_##_flag) \
3717 tx_ctl->tx_control_##_c |= \
3718 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3719
3720 _TX_FLAGS(0, CLRDMASK);
3721 _TX_FLAGS(0, VEOL);
3722 _TX_FLAGS(0, INTREQ);
3723 _TX_FLAGS(0, RTSENA);
3724 _TX_FLAGS(0, CTSENA);
3725 _TX_FLAGS(1, NOACK);
3726
3727 #undef _TX_FLAGS
3728
3729 /*
3730 * WEP crap
3731 */
3732 if (key_index != AR5K_TXKEYIX_INVALID) {
3733 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3734 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
3735 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3736 }
3737
3738 /*
3739 * RTS/CTS
3740 */
3741 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3742 if ((flags & AR5K_TXDESC_RTSENA) &&
3743 (flags & AR5K_TXDESC_CTSENA))
3744 return -EINVAL;
3745 tx_ctl->tx_control_2 |= rtscts_duration &
3746 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3747 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3748 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3749 }
3750
3751 return 0;
3752 }
3753
3754 /*
3755 * Initialize a 4-word multirate tx descriptor on 5212
3756 */
3757 static int
3758 ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3759 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3760 unsigned int tx_rate3, u_int tx_tries3)
3761 {
3762 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3763
3764 /*
3765 * Rates can be 0 as long as the retry count is 0 too.
3766 * A zero rate and nonzero retry count will put the HW into a mode where
3767 * it continously sends noise on the channel, so it is important to
3768 * avoid this.
3769 */
3770 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3771 (tx_rate2 == 0 && tx_tries2 != 0) ||
3772 (tx_rate3 == 0 && tx_tries3 != 0))) {
3773 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3774 WARN_ON(1);
3775 return -EINVAL;
3776 }
3777
3778 if (ah->ah_version == AR5K_AR5212) {
3779 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3780
3781 #define _XTX_TRIES(_n) \
3782 if (tx_tries##_n) { \
3783 tx_ctl->tx_control_2 |= \
3784 AR5K_REG_SM(tx_tries##_n, \
3785 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3786 tx_ctl->tx_control_3 |= \
3787 AR5K_REG_SM(tx_rate##_n, \
3788 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3789 }
3790
3791 _XTX_TRIES(1);
3792 _XTX_TRIES(2);
3793 _XTX_TRIES(3);
3794
3795 #undef _XTX_TRIES
3796
3797 return 1;
3798 }
3799
3800 return 0;
3801 }
3802
3803 /*
3804 * Proccess the tx status descriptor on 5210/5211
3805 */
3806 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3807 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3808 {
3809 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3810 struct ath5k_hw_tx_status *tx_status;
3811
3812 ATH5K_TRACE(ah->ah_sc);
3813
3814 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3815 tx_status = &desc->ud.ds_tx5210.tx_stat;
3816
3817 /* No frame has been send or error */
3818 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3819 return -EINPROGRESS;
3820
3821 /*
3822 * Get descriptor status
3823 */
3824 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3825 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3826 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3827 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3828 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3829 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3830 /*TODO: ts->ts_virtcol + test*/
3831 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3832 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3833 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3834 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3835 ts->ts_antenna = 1;
3836 ts->ts_status = 0;
3837 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0,
3838 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3839
3840 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3841 if (tx_status->tx_status_0 &
3842 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3843 ts->ts_status |= AR5K_TXERR_XRETRY;
3844
3845 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3846 ts->ts_status |= AR5K_TXERR_FIFO;
3847
3848 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3849 ts->ts_status |= AR5K_TXERR_FILT;
3850 }
3851
3852 return 0;
3853 }
3854
3855 /*
3856 * Proccess a tx descriptor on 5212
3857 */
3858 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3859 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3860 {
3861 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3862 struct ath5k_hw_tx_status *tx_status;
3863
3864 ATH5K_TRACE(ah->ah_sc);
3865
3866 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3867 tx_status = &desc->ud.ds_tx5212.tx_stat;
3868
3869 /* No frame has been send or error */
3870 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3871 return -EINPROGRESS;
3872
3873 /*
3874 * Get descriptor status
3875 */
3876 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3877 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3878 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3879 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3880 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3881 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3882 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3883 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3884 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3885 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3886 ts->ts_antenna = (tx_status->tx_status_1 &
3887 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
3888 ts->ts_status = 0;
3889
3890 switch (AR5K_REG_MS(tx_status->tx_status_1,
3891 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
3892 case 0:
3893 ts->ts_rate = tx_ctl->tx_control_3 &
3894 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3895 break;
3896 case 1:
3897 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
3898 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
3899 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
3900 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
3901 break;
3902 case 2:
3903 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
3904 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
3905 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
3906 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
3907 break;
3908 case 3:
3909 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
3910 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
3911 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
3912 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
3913 break;
3914 }
3915
3916 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3917 if (tx_status->tx_status_0 &
3918 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3919 ts->ts_status |= AR5K_TXERR_XRETRY;
3920
3921 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3922 ts->ts_status |= AR5K_TXERR_FIFO;
3923
3924 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3925 ts->ts_status |= AR5K_TXERR_FILT;
3926 }
3927
3928 return 0;
3929 }
3930
3931 /*
3932 * RX Descriptor
3933 */
3934
3935 /*
3936 * Initialize an rx descriptor
3937 */
3938 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3939 u32 size, unsigned int flags)
3940 {
3941 struct ath5k_hw_rx_ctl *rx_ctl;
3942
3943 ATH5K_TRACE(ah->ah_sc);
3944 rx_ctl = &desc->ud.ds_rx.rx_ctl;
3945
3946 /*
3947 * Clear the descriptor
3948 * If we don't clean the status descriptor,
3949 * while scanning we get too many results,
3950 * most of them virtual, after some secs
3951 * of scanning system hangs. M.F.
3952 */
3953 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
3954
3955 /* Setup descriptor */
3956 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
3957 if (unlikely(rx_ctl->rx_control_1 != size))
3958 return -EINVAL;
3959
3960 if (flags & AR5K_RXDESC_INTREQ)
3961 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
3962
3963 return 0;
3964 }
3965
3966 /*
3967 * Proccess the rx status descriptor on 5210/5211
3968 */
3969 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
3970 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
3971 {
3972 struct ath5k_hw_rx_status *rx_status;
3973
3974 rx_status = &desc->ud.ds_rx.u.rx_stat;
3975
3976 /* No frame received / not ready */
3977 if (unlikely((rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE)
3978 == 0))
3979 return -EINPROGRESS;
3980
3981 /*
3982 * Frame receive status
3983 */
3984 rs->rs_datalen = rx_status->rx_status_0 &
3985 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
3986 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
3987 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
3988 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
3989 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
3990 rs->rs_antenna = rx_status->rx_status_0 &
3991 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA;
3992 rs->rs_more = rx_status->rx_status_0 &
3993 AR5K_5210_RX_DESC_STATUS0_MORE;
3994 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
3995 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
3996 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
3997 rs->rs_status = 0;
3998
3999 /*
4000 * Key table status
4001 */
4002 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
4003 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4004 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
4005 else
4006 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4007
4008 /*
4009 * Receive/descriptor errors
4010 */
4011 if ((rx_status->rx_status_1 &
4012 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4013 if (rx_status->rx_status_1 &
4014 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
4015 rs->rs_status |= AR5K_RXERR_CRC;
4016
4017 if (rx_status->rx_status_1 &
4018 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
4019 rs->rs_status |= AR5K_RXERR_FIFO;
4020
4021 if (rx_status->rx_status_1 &
4022 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
4023 rs->rs_status |= AR5K_RXERR_PHY;
4024 rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
4025 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
4026 }
4027
4028 if (rx_status->rx_status_1 &
4029 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4030 rs->rs_status |= AR5K_RXERR_DECRYPT;
4031 }
4032
4033 return 0;
4034 }
4035
4036 /*
4037 * Proccess the rx status descriptor on 5212
4038 */
4039 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
4040 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4041 {
4042 struct ath5k_hw_rx_status *rx_status;
4043 struct ath5k_hw_rx_error *rx_err;
4044
4045 ATH5K_TRACE(ah->ah_sc);
4046 rx_status = &desc->ud.ds_rx.u.rx_stat;
4047
4048 /* Overlay on error */
4049 rx_err = &desc->ud.ds_rx.u.rx_err;
4050
4051 /* No frame received / not ready */
4052 if (unlikely((rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE)
4053 == 0))
4054 return -EINPROGRESS;
4055
4056 /*
4057 * Frame receive status
4058 */
4059 rs->rs_datalen = rx_status->rx_status_0 &
4060 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
4061 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4062 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4063 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4064 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
4065 rs->rs_antenna = rx_status->rx_status_0 &
4066 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4067 rs->rs_more = rx_status->rx_status_0 &
4068 AR5K_5212_RX_DESC_STATUS0_MORE;
4069 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4070 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4071 rs->rs_status = 0;
4072
4073 /*
4074 * Key table status
4075 */
4076 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
4077 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4078 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
4079 else
4080 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4081
4082 /*
4083 * Receive/descriptor errors
4084 */
4085 if ((rx_status->rx_status_1 &
4086 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4087 if (rx_status->rx_status_1 &
4088 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
4089 rs->rs_status |= AR5K_RXERR_CRC;
4090
4091 if (rx_status->rx_status_1 &
4092 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
4093 rs->rs_status |= AR5K_RXERR_PHY;
4094 rs->rs_phyerr = AR5K_REG_MS(rx_err->rx_error_1,
4095 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4096 }
4097
4098 if (rx_status->rx_status_1 &
4099 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4100 rs->rs_status |= AR5K_RXERR_DECRYPT;
4101
4102 if (rx_status->rx_status_1 &
4103 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
4104 rs->rs_status |= AR5K_RXERR_MIC;
4105 }
4106
4107 return 0;
4108 }
4109
4110
4111 /****************\
4112 GPIO Functions
4113 \****************/
4114
4115 /*
4116 * Set led state
4117 */
4118 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4119 {
4120 u32 led;
4121 /*5210 has different led mode handling*/
4122 u32 led_5210;
4123
4124 ATH5K_TRACE(ah->ah_sc);
4125
4126 /*Reset led status*/
4127 if (ah->ah_version != AR5K_AR5210)
4128 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4129 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4130 else
4131 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4132
4133 /*
4134 * Some blinking values, define at your wish
4135 */
4136 switch (state) {
4137 case AR5K_LED_SCAN:
4138 case AR5K_LED_AUTH:
4139 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4140 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4141 break;
4142
4143 case AR5K_LED_INIT:
4144 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4145 led_5210 = AR5K_PCICFG_LED_PEND;
4146 break;
4147
4148 case AR5K_LED_ASSOC:
4149 case AR5K_LED_RUN:
4150 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4151 led_5210 = AR5K_PCICFG_LED_ASSOC;
4152 break;
4153
4154 default:
4155 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4156 led_5210 = AR5K_PCICFG_LED_PEND;
4157 break;
4158 }
4159
4160 /*Write new status to the register*/
4161 if (ah->ah_version != AR5K_AR5210)
4162 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4163 else
4164 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4165 }
4166
4167 /*
4168 * Set GPIO outputs
4169 */
4170 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4171 {
4172 ATH5K_TRACE(ah->ah_sc);
4173 if (gpio > AR5K_NUM_GPIO)
4174 return -EINVAL;
4175
4176 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4177 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4178
4179 return 0;
4180 }
4181
4182 /*
4183 * Set GPIO inputs
4184 */
4185 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4186 {
4187 ATH5K_TRACE(ah->ah_sc);
4188 if (gpio > AR5K_NUM_GPIO)
4189 return -EINVAL;
4190
4191 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4192 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4193
4194 return 0;
4195 }
4196
4197 /*
4198 * Get GPIO state
4199 */
4200 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4201 {
4202 ATH5K_TRACE(ah->ah_sc);
4203 if (gpio > AR5K_NUM_GPIO)
4204 return 0xffffffff;
4205
4206 /* GPIO input magic */
4207 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4208 0x1;
4209 }
4210
4211 /*
4212 * Set GPIO state
4213 */
4214 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4215 {
4216 u32 data;
4217 ATH5K_TRACE(ah->ah_sc);
4218
4219 if (gpio > AR5K_NUM_GPIO)
4220 return -EINVAL;
4221
4222 /* GPIO output magic */
4223 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4224
4225 data &= ~(1 << gpio);
4226 data |= (val & 1) << gpio;
4227
4228 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4229
4230 return 0;
4231 }
4232
4233 /*
4234 * Initialize the GPIO interrupt (RFKill switch)
4235 */
4236 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4237 u32 interrupt_level)
4238 {
4239 u32 data;
4240
4241 ATH5K_TRACE(ah->ah_sc);
4242 if (gpio > AR5K_NUM_GPIO)
4243 return;
4244
4245 /*
4246 * Set the GPIO interrupt
4247 */
4248 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4249 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4250 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4251 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4252
4253 ath5k_hw_reg_write(ah, interrupt_level ? data :
4254 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4255
4256 ah->ah_imr |= AR5K_IMR_GPIO;
4257
4258 /* Enable GPIO interrupts */
4259 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4260 }
4261
4262
4263
4264
4265 /****************\
4266 Misc functions
4267 \****************/
4268
4269 int ath5k_hw_get_capability(struct ath5k_hw *ah,
4270 enum ath5k_capability_type cap_type,
4271 u32 capability, u32 *result)
4272 {
4273 ATH5K_TRACE(ah->ah_sc);
4274
4275 switch (cap_type) {
4276 case AR5K_CAP_NUM_TXQUEUES:
4277 if (result) {
4278 if (ah->ah_version == AR5K_AR5210)
4279 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4280 else
4281 *result = AR5K_NUM_TX_QUEUES;
4282 goto yes;
4283 }
4284 case AR5K_CAP_VEOL:
4285 goto yes;
4286 case AR5K_CAP_COMPRESSION:
4287 if (ah->ah_version == AR5K_AR5212)
4288 goto yes;
4289 else
4290 goto no;
4291 case AR5K_CAP_BURST:
4292 goto yes;
4293 case AR5K_CAP_TPC:
4294 goto yes;
4295 case AR5K_CAP_BSSIDMASK:
4296 if (ah->ah_version == AR5K_AR5212)
4297 goto yes;
4298 else
4299 goto no;
4300 case AR5K_CAP_XR:
4301 if (ah->ah_version == AR5K_AR5212)
4302 goto yes;
4303 else
4304 goto no;
4305 default:
4306 goto no;
4307 }
4308
4309 no:
4310 return -EINVAL;
4311 yes:
4312 return 0;
4313 }
4314
4315 static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4316 u16 assoc_id)
4317 {
4318 ATH5K_TRACE(ah->ah_sc);
4319
4320 if (ah->ah_version == AR5K_AR5210) {
4321 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4322 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4323 return 0;
4324 }
4325
4326 return -EIO;
4327 }
4328
4329 static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4330 {
4331 ATH5K_TRACE(ah->ah_sc);
4332
4333 if (ah->ah_version == AR5K_AR5210) {
4334 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4335 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4336 return 0;
4337 }
4338
4339 return -EIO;
4340 }
Linux with added FPC-III support