| blob | 06d687425fefa069ea28f0bae2df6d118d437478 |
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt73usb
23 Abstract: Data structures and registers for the rt73usb module.
24 Supported chipsets: rt2571W & rt2671.
25 */
27 #ifndef RT73USB_H
28 #define RT73USB_H
30 /*
31 * RF chip defines.
32 */
33 #define RF5226 0x0001
34 #define RF2528 0x0002
35 #define RF5225 0x0003
36 #define RF2527 0x0004
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define MAX_SIGNAL 100
43 #define MAX_RX_SSI -1
44 #define DEFAULT_RSSI_OFFSET 120
46 /*
47 * Register layout information.
48 */
49 #define CSR_REG_BASE 0x3000
50 #define CSR_REG_SIZE 0x04b0
51 #define EEPROM_BASE 0x0000
52 #define EEPROM_SIZE 0x0100
53 #define BBP_SIZE 0x0080
54 #define RF_SIZE 0x0014
56 /*
57 * USB registers.
58 */
60 /*
61 * MCU_LEDCS: LED control for MCU Mailbox.
62 */
63 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
64 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
65 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
66 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
67 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
68 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
69 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
70 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
71 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
72 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
73 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
74 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
76 /*
77 * 8051 firmware image.
78 */
80 #define FIRMWARE_IMAGE_BASE 0x0800
82 /*
83 * Security key table memory.
84 * 16 entries 32-byte for shared key table
85 * 64 entries 32-byte for pairwise key table
86 * 64 entries 8-byte for pairwise ta key table
87 */
88 #define SHARED_KEY_TABLE_BASE 0x1000
89 #define PAIRWISE_KEY_TABLE_BASE 0x1200
90 #define PAIRWISE_TA_TABLE_BASE 0x1a00
103 /*
104 * Since NULL frame won't be that long (256 byte),
105 * We steal 16 tail bytes to save debugging settings.
106 */
107 #define HW_DEBUG_SETTING_BASE 0x2bf0
109 /*
110 * On-chip BEACON frame space.
111 */
112 #define HW_BEACON_BASE0 0x2400
113 #define HW_BEACON_BASE1 0x2500
114 #define HW_BEACON_BASE2 0x2600
115 #define HW_BEACON_BASE3 0x2700
117 #define HW_BEACON_OFFSET(__index) \
118 ( HW_BEACON_BASE0 + (__index * 0x0100) )
120 /*
121 * MAC Control/Status Registers(CSR).
122 * Some values are set in TU, whereas 1 TU == 1024 us.
123 */
125 /*
126 * MAC_CSR0: ASIC revision number.
127 */
128 #define MAC_CSR0 0x3000
130 /*
131 * MAC_CSR1: System control register.
132 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
133 * BBP_RESET: Hardware reset BBP.
134 * HOST_READY: Host is ready after initialization, 1: ready.
135 */
136 #define MAC_CSR1 0x3004
137 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
138 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
139 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
141 /*
142 * MAC_CSR2: STA MAC register 0.
143 */
144 #define MAC_CSR2 0x3008
145 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
146 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
147 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
148 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
150 /*
151 * MAC_CSR3: STA MAC register 1.
152 * UNICAST_TO_ME_MASK:
153 * Used to mask off bits from byte 5 of the MAC address
154 * to determine the UNICAST_TO_ME bit for RX frames.
155 * The full mask is complemented by BSS_ID_MASK:
156 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
157 */
158 #define MAC_CSR3 0x300c
159 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
160 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
161 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
163 /*
164 * MAC_CSR4: BSSID register 0.
165 */
166 #define MAC_CSR4 0x3010
167 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
168 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
169 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
170 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
172 /*
173 * MAC_CSR5: BSSID register 1.
174 * BSS_ID_MASK:
175 * This mask is used to mask off bits 0 and 1 of byte 5 of the
176 * BSSID. This will make sure that those bits will be ignored
177 * when determining the MY_BSS of RX frames.
178 * 0: 1-BSSID mode (BSS index = 0)
179 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
180 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
181 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
182 */
183 #define MAC_CSR5 0x3014
184 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
185 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
186 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
188 /*
189 * MAC_CSR6: Maximum frame length register.
190 */
191 #define MAC_CSR6 0x3018
192 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
194 /*
195 * MAC_CSR7: Reserved
196 */
197 #define MAC_CSR7 0x301c
199 /*
200 * MAC_CSR8: SIFS/EIFS register.
201 * All units are in US.
202 */
203 #define MAC_CSR8 0x3020
204 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
205 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
206 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
208 /*
209 * MAC_CSR9: Back-Off control register.
210 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
211 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
212 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
213 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
214 */
215 #define MAC_CSR9 0x3024
216 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
217 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
218 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
219 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
221 /*
222 * MAC_CSR10: Power state configuration.
223 */
224 #define MAC_CSR10 0x3028
226 /*
227 * MAC_CSR11: Power saving transition time register.
228 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
229 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
230 * WAKEUP_LATENCY: In unit of TU.
231 */
232 #define MAC_CSR11 0x302c
233 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
234 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
235 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
236 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
238 /*
239 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
240 * CURRENT_STATE: 0:sleep, 1:awake.
241 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
242 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
243 */
244 #define MAC_CSR12 0x3030
245 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
246 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
247 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
248 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
250 /*
251 * MAC_CSR13: GPIO.
252 */
253 #define MAC_CSR13 0x3034
255 /*
256 * MAC_CSR14: LED control register.
257 * ON_PERIOD: On period, default 70ms.
258 * OFF_PERIOD: Off period, default 30ms.
259 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
260 * SW_LED: s/w LED, 1: ON, 0: OFF.
261 * HW_LED_POLARITY: 0: active low, 1: active high.
262 */
263 #define MAC_CSR14 0x3038
264 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
265 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
266 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
267 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
268 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
269 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
271 /*
272 * MAC_CSR15: NAV control.
273 */
274 #define MAC_CSR15 0x303c
276 /*
277 * TXRX control registers.
278 * Some values are set in TU, whereas 1 TU == 1024 us.
279 */
281 /*
282 * TXRX_CSR0: TX/RX configuration register.
283 * TSF_OFFSET: Default is 24.
284 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
285 * DISABLE_RX: Disable Rx engine.
286 * DROP_CRC: Drop CRC error.
287 * DROP_PHYSICAL: Drop physical error.
288 * DROP_CONTROL: Drop control frame.
289 * DROP_NOT_TO_ME: Drop not to me unicast frame.
290 * DROP_TO_DS: Drop fram ToDs bit is true.
291 * DROP_VERSION_ERROR: Drop version error frame.
292 * DROP_MULTICAST: Drop multicast frames.
293 * DROP_BORADCAST: Drop broadcast frames.
294 * ROP_ACK_CTS: Drop received ACK and CTS.
295 */
296 #define TXRX_CSR0 0x3040
297 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
298 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
299 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
300 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
301 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
302 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
303 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
304 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
305 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
306 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
307 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
308 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
309 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
310 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
312 /*
313 * TXRX_CSR1
314 */
315 #define TXRX_CSR1 0x3044
316 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
317 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
318 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
319 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
320 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
321 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
322 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
323 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
325 /*
326 * TXRX_CSR2
327 */
328 #define TXRX_CSR2 0x3048
329 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
330 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
331 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
332 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
333 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
334 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
335 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
336 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
338 /*
339 * TXRX_CSR3
340 */
341 #define TXRX_CSR3 0x304c
342 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
343 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
344 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
345 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
346 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
347 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
348 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
349 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
351 /*
352 * TXRX_CSR4: Auto-Responder/Tx-retry register.
353 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
354 * OFDM_TX_RATE_DOWN: 1:enable.
355 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
356 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
357 */
358 #define TXRX_CSR4 0x3050
359 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
360 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
361 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
362 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
363 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
364 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
365 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
366 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
367 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
368 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
370 /*
371 * TXRX_CSR5
372 */
373 #define TXRX_CSR5 0x3054
375 /*
376 * TXRX_CSR6: ACK/CTS payload consumed time
377 */
378 #define TXRX_CSR6 0x3058
380 /*
381 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
382 */
383 #define TXRX_CSR7 0x305c
384 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
385 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
386 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
387 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
389 /*
390 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
391 */
392 #define TXRX_CSR8 0x3060
393 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
394 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
395 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
396 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
398 /*
399 * TXRX_CSR9: Synchronization control register.
400 * BEACON_INTERVAL: In unit of 1/16 TU.
401 * TSF_TICKING: Enable TSF auto counting.
402 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
403 * BEACON_GEN: Enable beacon generator.
404 */
405 #define TXRX_CSR9 0x3064
406 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
407 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
408 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
409 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
410 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
411 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
413 /*
414 * TXRX_CSR10: BEACON alignment.
415 */
416 #define TXRX_CSR10 0x3068
418 /*
419 * TXRX_CSR11: AES mask.
420 */
421 #define TXRX_CSR11 0x306c
423 /*
424 * TXRX_CSR12: TSF low 32.
425 */
426 #define TXRX_CSR12 0x3070
427 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
429 /*
430 * TXRX_CSR13: TSF high 32.
431 */
432 #define TXRX_CSR13 0x3074
433 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
435 /*
436 * TXRX_CSR14: TBTT timer.
437 */
438 #define TXRX_CSR14 0x3078
440 /*
441 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
442 */
443 #define TXRX_CSR15 0x307c
445 /*
446 * PHY control registers.
447 * Some values are set in TU, whereas 1 TU == 1024 us.
448 */
450 /*
451 * PHY_CSR0: RF/PS control.
452 */
453 #define PHY_CSR0 0x3080
454 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
455 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
457 /*
458 * PHY_CSR1
459 */
460 #define PHY_CSR1 0x3084
461 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
463 /*
464 * PHY_CSR2: Pre-TX BBP control.
465 */
466 #define PHY_CSR2 0x3088
468 /*
469 * PHY_CSR3: BBP serial control register.
470 * VALUE: Register value to program into BBP.
471 * REG_NUM: Selected BBP register.
472 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
473 * BUSY: 1: ASIC is busy execute BBP programming.
474 */
475 #define PHY_CSR3 0x308c
476 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
477 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
478 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
479 #define PHY_CSR3_BUSY FIELD32(0x00010000)
481 /*
482 * PHY_CSR4: RF serial control register
483 * VALUE: Register value (include register id) serial out to RF/IF chip.
484 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
485 * IF_SELECT: 1: select IF to program, 0: select RF to program.
486 * PLL_LD: RF PLL_LD status.
487 * BUSY: 1: ASIC is busy execute RF programming.
488 */
489 #define PHY_CSR4 0x3090
490 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
491 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
492 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
493 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
494 #define PHY_CSR4_BUSY FIELD32(0x80000000)
496 /*
497 * PHY_CSR5: RX to TX signal switch timing control.
498 */
499 #define PHY_CSR5 0x3094
500 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
502 /*
503 * PHY_CSR6: TX to RX signal timing control.
504 */
505 #define PHY_CSR6 0x3098
506 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
508 /*
509 * PHY_CSR7: TX DAC switching timing control.
510 */
511 #define PHY_CSR7 0x309c
513 /*
514 * Security control register.
515 */
517 /*
518 * SEC_CSR0: Shared key table control.
519 */
520 #define SEC_CSR0 0x30a0
521 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
522 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
523 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
524 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
525 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
526 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
527 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
528 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
529 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
530 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
531 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
532 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
533 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
534 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
535 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
536 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
538 /*
539 * SEC_CSR1: Shared key table security mode register.
540 */
541 #define SEC_CSR1 0x30a4
542 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
543 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
544 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
545 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
546 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
547 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
548 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
549 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
551 /*
552 * Pairwise key table valid bitmap registers.
553 * SEC_CSR2: pairwise key table valid bitmap 0.
554 * SEC_CSR3: pairwise key table valid bitmap 1.
555 */
556 #define SEC_CSR2 0x30a8
557 #define SEC_CSR3 0x30ac
559 /*
560 * SEC_CSR4: Pairwise key table lookup control.
561 */
562 #define SEC_CSR4 0x30b0
564 /*
565 * SEC_CSR5: shared key table security mode register.
566 */
567 #define SEC_CSR5 0x30b4
568 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
569 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
570 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
571 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
572 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
573 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
574 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
575 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
577 /*
578 * STA control registers.
579 */
581 /*
582 * STA_CSR0: RX PLCP error count & RX FCS error count.
583 */
584 #define STA_CSR0 0x30c0
585 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
586 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
588 /*
589 * STA_CSR1: RX False CCA count & RX LONG frame count.
590 */
591 #define STA_CSR1 0x30c4
592 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
593 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
595 /*
596 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
597 */
598 #define STA_CSR2 0x30c8
599 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
600 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
602 /*
603 * STA_CSR3: TX Beacon count.
604 */
605 #define STA_CSR3 0x30cc
606 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
608 /*
609 * STA_CSR4: TX Retry count.
610 */
611 #define STA_CSR4 0x30d0
612 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
613 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
615 /*
616 * STA_CSR5: TX Retry count.
617 */
618 #define STA_CSR5 0x30d4
619 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
620 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
622 /*
623 * QOS control registers.
624 */
626 /*
627 * QOS_CSR1: TXOP holder MAC address register.
628 */
629 #define QOS_CSR1 0x30e4
630 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
631 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
633 /*
634 * QOS_CSR2: TXOP holder timeout register.
635 */
636 #define QOS_CSR2 0x30e8
638 /*
639 * RX QOS-CFPOLL MAC address register.
640 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
641 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
642 */
643 #define QOS_CSR3 0x30ec
644 #define QOS_CSR4 0x30f0
646 /*
647 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
648 */
649 #define QOS_CSR5 0x30f4
651 /*
652 * WMM Scheduler Register
653 */
655 /*
656 * AIFSN_CSR: AIFSN for each EDCA AC.
657 * AIFSN0: For AC_BK.
658 * AIFSN1: For AC_BE.
659 * AIFSN2: For AC_VI.
660 * AIFSN3: For AC_VO.
661 */
662 #define AIFSN_CSR 0x0400
663 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
664 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
665 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
666 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
668 /*
669 * CWMIN_CSR: CWmin for each EDCA AC.
670 * CWMIN0: For AC_BK.
671 * CWMIN1: For AC_BE.
672 * CWMIN2: For AC_VI.
673 * CWMIN3: For AC_VO.
674 */
675 #define CWMIN_CSR 0x0404
676 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
677 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
678 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
679 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
681 /*
682 * CWMAX_CSR: CWmax for each EDCA AC.
683 * CWMAX0: For AC_BK.
684 * CWMAX1: For AC_BE.
685 * CWMAX2: For AC_VI.
686 * CWMAX3: For AC_VO.
687 */
688 #define CWMAX_CSR 0x0408
689 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
690 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
691 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
692 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
694 /*
695 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
696 * AC0_TX_OP: For AC_BK, in unit of 32us.
697 * AC1_TX_OP: For AC_BE, in unit of 32us.
698 */
699 #define AC_TXOP_CSR0 0x040c
700 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
701 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
703 /*
704 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
705 * AC2_TX_OP: For AC_VI, in unit of 32us.
706 * AC3_TX_OP: For AC_VO, in unit of 32us.
707 */
708 #define AC_TXOP_CSR1 0x0410
709 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
710 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
712 /*
713 * BBP registers.
714 * The wordsize of the BBP is 8 bits.
715 */
717 /*
718 * R2
719 */
720 #define BBP_R2_BG_MODE FIELD8(0x20)
722 /*
723 * R3
724 */
725 #define BBP_R3_SMART_MODE FIELD8(0x01)
727 /*
728 * R4: RX antenna control
729 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
730 */
732 /*
733 * ANTENNA_CONTROL semantics (guessed):
734 * 0x1: Software controlled antenna switching (fixed or SW diversity)
735 * 0x2: Hardware diversity.
736 */
737 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
738 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
740 /*
741 * R77
742 */
743 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
745 /*
746 * RF registers
747 */
749 /*
750 * RF 3
751 */
752 #define RF3_TXPOWER FIELD32(0x00003e00)
754 /*
755 * RF 4
756 */
757 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
759 /*
760 * EEPROM content.
761 * The wordsize of the EEPROM is 16 bits.
762 */
764 /*
765 * HW MAC address.
766 */
767 #define EEPROM_MAC_ADDR_0 0x0002
768 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
769 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
770 #define EEPROM_MAC_ADDR1 0x0003
771 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
772 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
773 #define EEPROM_MAC_ADDR_2 0x0004
774 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
775 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
777 /*
778 * EEPROM antenna.
779 * ANTENNA_NUM: Number of antenna's.
780 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
781 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
782 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
783 * DYN_TXAGC: Dynamic TX AGC control.
784 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
785 * RF_TYPE: Rf_type of this adapter.
786 */
787 #define EEPROM_ANTENNA 0x0010
788 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
789 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
790 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
791 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
792 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
793 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
794 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
796 /*
797 * EEPROM NIC config.
798 * EXTERNAL_LNA: External LNA.
799 */
800 #define EEPROM_NIC 0x0011
801 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
803 /*
804 * EEPROM geography.
805 * GEO_A: Default geographical setting for 5GHz band
806 * GEO: Default geographical setting.
807 */
808 #define EEPROM_GEOGRAPHY 0x0012
809 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
810 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
812 /*
813 * EEPROM BBP.
814 */
815 #define EEPROM_BBP_START 0x0013
816 #define EEPROM_BBP_SIZE 16
817 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
818 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
820 /*
821 * EEPROM TXPOWER 802.11G
822 */
823 #define EEPROM_TXPOWER_G_START 0x0023
824 #define EEPROM_TXPOWER_G_SIZE 7
825 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
826 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
828 /*
829 * EEPROM Frequency
830 */
831 #define EEPROM_FREQ 0x002f
832 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
833 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
834 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
836 /*
837 * EEPROM LED.
838 * POLARITY_RDY_G: Polarity RDY_G setting.
839 * POLARITY_RDY_A: Polarity RDY_A setting.
840 * POLARITY_ACT: Polarity ACT setting.
841 * POLARITY_GPIO_0: Polarity GPIO0 setting.
842 * POLARITY_GPIO_1: Polarity GPIO1 setting.
843 * POLARITY_GPIO_2: Polarity GPIO2 setting.
844 * POLARITY_GPIO_3: Polarity GPIO3 setting.
845 * POLARITY_GPIO_4: Polarity GPIO4 setting.
846 * LED_MODE: Led mode.
847 */
848 #define EEPROM_LED 0x0030
849 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
850 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
851 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
852 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
853 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
854 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
855 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
856 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
857 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
859 /*
860 * EEPROM TXPOWER 802.11A
861 */
862 #define EEPROM_TXPOWER_A_START 0x0031
863 #define EEPROM_TXPOWER_A_SIZE 12
864 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
865 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
867 /*
868 * EEPROM RSSI offset 802.11BG
869 */
870 #define EEPROM_RSSI_OFFSET_BG 0x004d
871 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
872 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
874 /*
875 * EEPROM RSSI offset 802.11A
876 */
877 #define EEPROM_RSSI_OFFSET_A 0x004e
878 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
879 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
881 /*
882 * DMA descriptor defines.
883 */
884 #define TXD_DESC_SIZE ( 6 * sizeof(__le32) )
885 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
886 #define RXD_DESC_SIZE ( 6 * sizeof(__le32) )
888 /*
889 * TX descriptor format for TX, PRIO and Beacon Ring.
890 */
892 /*
893 * Word0
894 * BURST: Next frame belongs to same "burst" event.
895 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
896 * KEY_TABLE: Use per-client pairwise KEY table.
897 * KEY_INDEX:
898 * Key index (0~31) to the pairwise KEY table.
899 * 0~3 to shared KEY table 0 (BSS0).
900 * 4~7 to shared KEY table 1 (BSS1).
901 * 8~11 to shared KEY table 2 (BSS2).
902 * 12~15 to shared KEY table 3 (BSS3).
903 * BURST2: For backward compatibility, set to same value as BURST.
904 */
905 #define TXD_W0_BURST FIELD32(0x00000001)
906 #define TXD_W0_VALID FIELD32(0x00000002)
907 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
908 #define TXD_W0_ACK FIELD32(0x00000008)
909 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
910 #define TXD_W0_OFDM FIELD32(0x00000020)
911 #define TXD_W0_IFS FIELD32(0x00000040)
912 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
913 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
914 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
915 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
916 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
917 #define TXD_W0_BURST2 FIELD32(0x10000000)
918 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
920 /*
921 * Word1
922 * HOST_Q_ID: EDCA/HCCA queue ID.
923 * HW_SEQUENCE: MAC overwrites the frame sequence number.
924 * BUFFER_COUNT: Number of buffers in this TXD.
925 */
926 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
927 #define TXD_W1_AIFSN FIELD32(0x000000f0)
928 #define TXD_W1_CWMIN FIELD32(0x00000f00)
929 #define TXD_W1_CWMAX FIELD32(0x0000f000)
930 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
931 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
932 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
934 /*
935 * Word2: PLCP information
936 */
937 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
938 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
939 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
940 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
942 /*
943 * Word3
944 */
945 #define TXD_W3_IV FIELD32(0xffffffff)
947 /*
948 * Word4
949 */
950 #define TXD_W4_EIV FIELD32(0xffffffff)
952 /*
953 * Word5
954 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
955 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
956 * WAITING_DMA_DONE_INT: TXD been filled with data
957 * and waiting for TxDoneISR housekeeping.
958 */
959 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
960 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
961 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
962 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
964 /*
965 * RX descriptor format for RX Ring.
966 */
968 /*
969 * Word0
970 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
971 * KEY_INDEX: Decryption key actually used.
972 */
973 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
974 #define RXD_W0_DROP FIELD32(0x00000002)
975 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
976 #define RXD_W0_MULTICAST FIELD32(0x00000008)
977 #define RXD_W0_BROADCAST FIELD32(0x00000010)
978 #define RXD_W0_MY_BSS FIELD32(0x00000020)
979 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
980 #define RXD_W0_OFDM FIELD32(0x00000080)
981 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
982 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
983 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
984 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
986 /*
987 * WORD1
988 * SIGNAL: RX raw data rate reported by BBP.
989 * RSSI: RSSI reported by BBP.
990 */
991 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
992 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
993 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
994 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
996 /*
997 * Word2
998 * IV: Received IV of originally encrypted.
999 */
1000 #define RXD_W2_IV FIELD32(0xffffffff)
1002 /*
1003 * Word3
1004 * EIV: Received EIV of originally encrypted.
1005 */
1006 #define RXD_W3_EIV FIELD32(0xffffffff)
1008 /*
1009 * Word4
1010 */
1011 #define RXD_W4_RESERVED FIELD32(0xffffffff)
1013 /*
1014 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1015 * and passed to the HOST driver.
1016 * The following fields are for DMA block and HOST usage only.
1017 * Can't be touched by ASIC MAC block.
1018 */
1020 /*
1021 * Word5
1022 */
1023 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1025 /*
1026 * Macro's for converting txpower from EEPROM to mac80211 value
1027 * and from mac80211 value to register value.
1028 */
1029 #define MIN_TXPOWER 0
1030 #define MAX_TXPOWER 31
1031 #define DEFAULT_TXPOWER 24
1033 #define TXPOWER_FROM_DEV(__txpower) \
1034 ({ \
1035 ((__txpower) > MAX_TXPOWER) ? \
1036 DEFAULT_TXPOWER : (__txpower); \
1037 })
1039 #define TXPOWER_TO_DEV(__txpower) \
1040 ({ \
1041 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1042 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1043 (__txpower)); \
1044 })