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iwlwifi: introduce host commands callbacks
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_def.h
blob3750319f4968749d99a821fd1294610723c078e3
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <asm/semaphore.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34
35 #define QLA2XXX_DRIVER_NAME "qla2xxx"
36
37 /*
38 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
39 * but that's fine as we don't look at the last 24 ones for
40 * ISP2100 HBAs.
41 */
42 #define MAILBOX_REGISTER_COUNT_2100 8
43 #define MAILBOX_REGISTER_COUNT 32
44
45 #define QLA2200A_RISC_ROM_VER 4
46 #define FPM_2300 6
47 #define FPM_2310 7
48
49 #include "qla_settings.h"
50
51 /*
52 * Data bit definitions
53 */
54 #define BIT_0 0x1
55 #define BIT_1 0x2
56 #define BIT_2 0x4
57 #define BIT_3 0x8
58 #define BIT_4 0x10
59 #define BIT_5 0x20
60 #define BIT_6 0x40
61 #define BIT_7 0x80
62 #define BIT_8 0x100
63 #define BIT_9 0x200
64 #define BIT_10 0x400
65 #define BIT_11 0x800
66 #define BIT_12 0x1000
67 #define BIT_13 0x2000
68 #define BIT_14 0x4000
69 #define BIT_15 0x8000
70 #define BIT_16 0x10000
71 #define BIT_17 0x20000
72 #define BIT_18 0x40000
73 #define BIT_19 0x80000
74 #define BIT_20 0x100000
75 #define BIT_21 0x200000
76 #define BIT_22 0x400000
77 #define BIT_23 0x800000
78 #define BIT_24 0x1000000
79 #define BIT_25 0x2000000
80 #define BIT_26 0x4000000
81 #define BIT_27 0x8000000
82 #define BIT_28 0x10000000
83 #define BIT_29 0x20000000
84 #define BIT_30 0x40000000
85 #define BIT_31 0x80000000
86
87 #define LSB(x) ((uint8_t)(x))
88 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
89
90 #define LSW(x) ((uint16_t)(x))
91 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
92
93 #define LSD(x) ((uint32_t)((uint64_t)(x)))
94 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
95
96
97 /*
98 * I/O register
99 */
100
101 #define RD_REG_BYTE(addr) readb(addr)
102 #define RD_REG_WORD(addr) readw(addr)
103 #define RD_REG_DWORD(addr) readl(addr)
104 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
105 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
106 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
107 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
108 #define WRT_REG_WORD(addr, data) writew(data,addr)
109 #define WRT_REG_DWORD(addr, data) writel(data,addr)
110
111 /*
112 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
113 * 133Mhz slot.
114 */
115 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
116 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
117
118 /*
119 * Fibre Channel device definitions.
120 */
121 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
122 #define MAX_FIBRE_DEVICES 512
123 #define MAX_FIBRE_LUNS 0xFFFF
124 #define MAX_RSCN_COUNT 32
125 #define MAX_HOST_COUNT 16
126
127 /*
128 * Host adapter default definitions.
129 */
130 #define MAX_BUSES 1 /* We only have one bus today */
131 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
132 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
133 #define MIN_LUNS 8
134 #define MAX_LUNS MAX_FIBRE_LUNS
135 #define MAX_CMDS_PER_LUN 255
136
137 /*
138 * Fibre Channel device definitions.
139 */
140 #define SNS_LAST_LOOP_ID_2100 0xfe
141 #define SNS_LAST_LOOP_ID_2300 0x7ff
142
143 #define LAST_LOCAL_LOOP_ID 0x7d
144 #define SNS_FL_PORT 0x7e
145 #define FABRIC_CONTROLLER 0x7f
146 #define SIMPLE_NAME_SERVER 0x80
147 #define SNS_FIRST_LOOP_ID 0x81
148 #define MANAGEMENT_SERVER 0xfe
149 #define BROADCAST 0xff
150
151 /*
152 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
153 * valid range of an N-PORT id is 0 through 0x7ef.
154 */
155 #define NPH_LAST_HANDLE 0x7ef
156 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
157 #define NPH_SNS 0x7fc /* FFFFFC */
158 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
159 #define NPH_F_PORT 0x7fe /* FFFFFE */
160 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
161
162 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
163 #include "qla_fw.h"
164
165 /*
166 * Timeout timer counts in seconds
167 */
168 #define PORT_RETRY_TIME 1
169 #define LOOP_DOWN_TIMEOUT 60
170 #define LOOP_DOWN_TIME 255 /* 240 */
171 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
172
173 /* Maximum outstanding commands in ISP queues (1-65535) */
174 #define MAX_OUTSTANDING_COMMANDS 1024
175
176 /* ISP request and response entry counts (37-65535) */
177 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
178 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
179 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
180 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
181 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
182 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
183
184 /*
185 * SCSI Request Block
186 */
187 typedef struct srb {
188 struct scsi_qla_host *ha; /* HA the SP is queued on */
189 struct fc_port *fcport;
190
191 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
192
193 uint16_t flags;
194
195 /* Single transfer DMA context */
196 dma_addr_t dma_handle;
197
198 uint32_t request_sense_length;
199 uint8_t *request_sense_ptr;
200 } srb_t;
201
202 /*
203 * SRB flag definitions
204 */
205 #define SRB_TIMEOUT BIT_0 /* Command timed out */
206 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
207 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
208 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
209
210 #define SRB_ABORTED BIT_4 /* Command aborted command already */
211 #define SRB_RETRY BIT_5 /* Command needs retrying */
212 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
213 #define SRB_FAILOVER BIT_7 /* Command in failover state */
214
215 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
216 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
217 #define SRB_IOCTL BIT_10 /* IOCTL command. */
218 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
219
220 /*
221 * ISP I/O Register Set structure definitions.
222 */
223 struct device_reg_2xxx {
224 uint16_t flash_address; /* Flash BIOS address */
225 uint16_t flash_data; /* Flash BIOS data */
226 uint16_t unused_1[1]; /* Gap */
227 uint16_t ctrl_status; /* Control/Status */
228 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
229 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
230 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
231
232 uint16_t ictrl; /* Interrupt control */
233 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
234 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
235
236 uint16_t istatus; /* Interrupt status */
237 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
238
239 uint16_t semaphore; /* Semaphore */
240 uint16_t nvram; /* NVRAM register. */
241 #define NVR_DESELECT 0
242 #define NVR_BUSY BIT_15
243 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
244 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
245 #define NVR_DATA_IN BIT_3
246 #define NVR_DATA_OUT BIT_2
247 #define NVR_SELECT BIT_1
248 #define NVR_CLOCK BIT_0
249
250 #define NVR_WAIT_CNT 20000
251
252 union {
253 struct {
254 uint16_t mailbox0;
255 uint16_t mailbox1;
256 uint16_t mailbox2;
257 uint16_t mailbox3;
258 uint16_t mailbox4;
259 uint16_t mailbox5;
260 uint16_t mailbox6;
261 uint16_t mailbox7;
262 uint16_t unused_2[59]; /* Gap */
263 } __attribute__((packed)) isp2100;
264 struct {
265 /* Request Queue */
266 uint16_t req_q_in; /* In-Pointer */
267 uint16_t req_q_out; /* Out-Pointer */
268 /* Response Queue */
269 uint16_t rsp_q_in; /* In-Pointer */
270 uint16_t rsp_q_out; /* Out-Pointer */
271
272 /* RISC to Host Status */
273 uint32_t host_status;
274 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
275 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
276
277 /* Host to Host Semaphore */
278 uint16_t host_semaphore;
279 uint16_t unused_3[17]; /* Gap */
280 uint16_t mailbox0;
281 uint16_t mailbox1;
282 uint16_t mailbox2;
283 uint16_t mailbox3;
284 uint16_t mailbox4;
285 uint16_t mailbox5;
286 uint16_t mailbox6;
287 uint16_t mailbox7;
288 uint16_t mailbox8;
289 uint16_t mailbox9;
290 uint16_t mailbox10;
291 uint16_t mailbox11;
292 uint16_t mailbox12;
293 uint16_t mailbox13;
294 uint16_t mailbox14;
295 uint16_t mailbox15;
296 uint16_t mailbox16;
297 uint16_t mailbox17;
298 uint16_t mailbox18;
299 uint16_t mailbox19;
300 uint16_t mailbox20;
301 uint16_t mailbox21;
302 uint16_t mailbox22;
303 uint16_t mailbox23;
304 uint16_t mailbox24;
305 uint16_t mailbox25;
306 uint16_t mailbox26;
307 uint16_t mailbox27;
308 uint16_t mailbox28;
309 uint16_t mailbox29;
310 uint16_t mailbox30;
311 uint16_t mailbox31;
312 uint16_t fb_cmd;
313 uint16_t unused_4[10]; /* Gap */
314 } __attribute__((packed)) isp2300;
315 } u;
316
317 uint16_t fpm_diag_config;
318 uint16_t unused_5[0x4]; /* Gap */
319 uint16_t risc_hw;
320 uint16_t unused_5_1; /* Gap */
321 uint16_t pcr; /* Processor Control Register. */
322 uint16_t unused_6[0x5]; /* Gap */
323 uint16_t mctr; /* Memory Configuration and Timing. */
324 uint16_t unused_7[0x3]; /* Gap */
325 uint16_t fb_cmd_2100; /* Unused on 23XX */
326 uint16_t unused_8[0x3]; /* Gap */
327 uint16_t hccr; /* Host command & control register. */
328 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
329 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
330 /* HCCR commands */
331 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
332 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
333 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
334 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
335 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
336 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
337 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
338 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
339
340 uint16_t unused_9[5]; /* Gap */
341 uint16_t gpiod; /* GPIO Data register. */
342 uint16_t gpioe; /* GPIO Enable register. */
343 #define GPIO_LED_MASK 0x00C0
344 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
345 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
346 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
347 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
348 #define GPIO_LED_ALL_OFF 0x0000
349 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
350 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
351
352 union {
353 struct {
354 uint16_t unused_10[8]; /* Gap */
355 uint16_t mailbox8;
356 uint16_t mailbox9;
357 uint16_t mailbox10;
358 uint16_t mailbox11;
359 uint16_t mailbox12;
360 uint16_t mailbox13;
361 uint16_t mailbox14;
362 uint16_t mailbox15;
363 uint16_t mailbox16;
364 uint16_t mailbox17;
365 uint16_t mailbox18;
366 uint16_t mailbox19;
367 uint16_t mailbox20;
368 uint16_t mailbox21;
369 uint16_t mailbox22;
370 uint16_t mailbox23; /* Also probe reg. */
371 } __attribute__((packed)) isp2200;
372 } u_end;
373 };
374
375 typedef union {
376 struct device_reg_2xxx isp;
377 struct device_reg_24xx isp24;
378 } device_reg_t;
379
380 #define ISP_REQ_Q_IN(ha, reg) \
381 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
382 &(reg)->u.isp2100.mailbox4 : \
383 &(reg)->u.isp2300.req_q_in)
384 #define ISP_REQ_Q_OUT(ha, reg) \
385 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
386 &(reg)->u.isp2100.mailbox4 : \
387 &(reg)->u.isp2300.req_q_out)
388 #define ISP_RSP_Q_IN(ha, reg) \
389 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
390 &(reg)->u.isp2100.mailbox5 : \
391 &(reg)->u.isp2300.rsp_q_in)
392 #define ISP_RSP_Q_OUT(ha, reg) \
393 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
394 &(reg)->u.isp2100.mailbox5 : \
395 &(reg)->u.isp2300.rsp_q_out)
396
397 #define MAILBOX_REG(ha, reg, num) \
398 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
399 (num < 8 ? \
400 &(reg)->u.isp2100.mailbox0 + (num) : \
401 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
402 &(reg)->u.isp2300.mailbox0 + (num))
403 #define RD_MAILBOX_REG(ha, reg, num) \
404 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
405 #define WRT_MAILBOX_REG(ha, reg, num, data) \
406 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
407
408 #define FB_CMD_REG(ha, reg) \
409 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
410 &(reg)->fb_cmd_2100 : \
411 &(reg)->u.isp2300.fb_cmd)
412 #define RD_FB_CMD_REG(ha, reg) \
413 RD_REG_WORD(FB_CMD_REG(ha, reg))
414 #define WRT_FB_CMD_REG(ha, reg, data) \
415 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
416
417 typedef struct {
418 uint32_t out_mb; /* outbound from driver */
419 uint32_t in_mb; /* Incoming from RISC */
420 uint16_t mb[MAILBOX_REGISTER_COUNT];
421 long buf_size;
422 void *bufp;
423 uint32_t tov;
424 uint8_t flags;
425 #define MBX_DMA_IN BIT_0
426 #define MBX_DMA_OUT BIT_1
427 #define IOCTL_CMD BIT_2
428 } mbx_cmd_t;
429
430 #define MBX_TOV_SECONDS 30
431
432 /*
433 * ISP product identification definitions in mailboxes after reset.
434 */
435 #define PROD_ID_1 0x4953
436 #define PROD_ID_2 0x0000
437 #define PROD_ID_2a 0x5020
438 #define PROD_ID_3 0x2020
439
440 /*
441 * ISP mailbox Self-Test status codes
442 */
443 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
444 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
445 #define MBS_BUSY 4 /* Busy. */
446
447 /*
448 * ISP mailbox command complete status codes
449 */
450 #define MBS_COMMAND_COMPLETE 0x4000
451 #define MBS_INVALID_COMMAND 0x4001
452 #define MBS_HOST_INTERFACE_ERROR 0x4002
453 #define MBS_TEST_FAILED 0x4003
454 #define MBS_COMMAND_ERROR 0x4005
455 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
456 #define MBS_PORT_ID_USED 0x4007
457 #define MBS_LOOP_ID_USED 0x4008
458 #define MBS_ALL_IDS_IN_USE 0x4009
459 #define MBS_NOT_LOGGED_IN 0x400A
460 #define MBS_LINK_DOWN_ERROR 0x400B
461 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
462
463 /*
464 * ISP mailbox asynchronous event status codes
465 */
466 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
467 #define MBA_RESET 0x8001 /* Reset Detected. */
468 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
469 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
470 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
471 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
472 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
473 /* occurred. */
474 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
475 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
476 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
477 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
478 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
479 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
480 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
481 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
482 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
483 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
484 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
485 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
486 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
487 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
488 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
489 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
490 /* used. */
491 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
492 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
493 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
494 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
495 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
496 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
497 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
498 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
499 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
500 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
501 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
502 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
503 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
504 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
505
506 /*
507 * Firmware options 1, 2, 3.
508 */
509 #define FO1_AE_ON_LIPF8 BIT_0
510 #define FO1_AE_ALL_LIP_RESET BIT_1
511 #define FO1_CTIO_RETRY BIT_3
512 #define FO1_DISABLE_LIP_F7_SW BIT_4
513 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
514 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
515 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
516 #define FO1_SET_EMPHASIS_SWING BIT_8
517 #define FO1_AE_AUTO_BYPASS BIT_9
518 #define FO1_ENABLE_PURE_IOCB BIT_10
519 #define FO1_AE_PLOGI_RJT BIT_11
520 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
521 #define FO1_AE_QUEUE_FULL BIT_13
522
523 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
524 #define FO2_REV_LOOPBACK BIT_1
525
526 #define FO3_ENABLE_EMERG_IOCB BIT_0
527 #define FO3_AE_RND_ERROR BIT_1
528
529 /* 24XX additional firmware options */
530 #define ADD_FO_COUNT 3
531 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
532 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
533
534 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
535
536 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
537
538 /*
539 * ISP mailbox commands
540 */
541 #define MBC_LOAD_RAM 1 /* Load RAM. */
542 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
543 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
544 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
545 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
546 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
547 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
548 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
549 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
550 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
551 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
552 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
553 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
554 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
555 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
556 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
557 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
558 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
559 #define MBC_RESET 0x18 /* Reset. */
560 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
561 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
562 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
563 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
564 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
565 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
566 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
567 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
568 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
569 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
570 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
571 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
572 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
573 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
574 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
575 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
576 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
577 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
578 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
579 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
580 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
581 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
582 /* Initialization Procedure */
583 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
584 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
585 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
586 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
587 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
588 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
589 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
590 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
591 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
592 #define MBC_LIP_RESET 0x6c /* LIP reset. */
593 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
594 /* commandd. */
595 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
596 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
597 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
598 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
599 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
600 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
601 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
602 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
603 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
604 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
605 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
606
607 /*
608 * ISP24xx mailbox commands
609 */
610 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
611 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
612 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
613 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
614 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
615 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
616 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
617 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
618 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
619 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
620 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
621 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
622 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
623 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
624 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
625
626 /* Firmware return data sizes */
627 #define FCAL_MAP_SIZE 128
628
629 /* Mailbox bit definitions for out_mb and in_mb */
630 #define MBX_31 BIT_31
631 #define MBX_30 BIT_30
632 #define MBX_29 BIT_29
633 #define MBX_28 BIT_28
634 #define MBX_27 BIT_27
635 #define MBX_26 BIT_26
636 #define MBX_25 BIT_25
637 #define MBX_24 BIT_24
638 #define MBX_23 BIT_23
639 #define MBX_22 BIT_22
640 #define MBX_21 BIT_21
641 #define MBX_20 BIT_20
642 #define MBX_19 BIT_19
643 #define MBX_18 BIT_18
644 #define MBX_17 BIT_17
645 #define MBX_16 BIT_16
646 #define MBX_15 BIT_15
647 #define MBX_14 BIT_14
648 #define MBX_13 BIT_13
649 #define MBX_12 BIT_12
650 #define MBX_11 BIT_11
651 #define MBX_10 BIT_10
652 #define MBX_9 BIT_9
653 #define MBX_8 BIT_8
654 #define MBX_7 BIT_7
655 #define MBX_6 BIT_6
656 #define MBX_5 BIT_5
657 #define MBX_4 BIT_4
658 #define MBX_3 BIT_3
659 #define MBX_2 BIT_2
660 #define MBX_1 BIT_1
661 #define MBX_0 BIT_0
662
663 /*
664 * Firmware state codes from get firmware state mailbox command
665 */
666 #define FSTATE_CONFIG_WAIT 0
667 #define FSTATE_WAIT_AL_PA 1
668 #define FSTATE_WAIT_LOGIN 2
669 #define FSTATE_READY 3
670 #define FSTATE_LOSS_OF_SYNC 4
671 #define FSTATE_ERROR 5
672 #define FSTATE_REINIT 6
673 #define FSTATE_NON_PART 7
674
675 #define FSTATE_CONFIG_CORRECT 0
676 #define FSTATE_P2P_RCV_LIP 1
677 #define FSTATE_P2P_CHOOSE_LOOP 2
678 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
679 #define FSTATE_FATAL_ERROR 4
680 #define FSTATE_LOOP_BACK_CONN 5
681
682 /*
683 * Port Database structure definition
684 * Little endian except where noted.
685 */
686 #define PORT_DATABASE_SIZE 128 /* bytes */
687 typedef struct {
688 uint8_t options;
689 uint8_t control;
690 uint8_t master_state;
691 uint8_t slave_state;
692 uint8_t reserved[2];
693 uint8_t hard_address;
694 uint8_t reserved_1;
695 uint8_t port_id[4];
696 uint8_t node_name[WWN_SIZE];
697 uint8_t port_name[WWN_SIZE];
698 uint16_t execution_throttle;
699 uint16_t execution_count;
700 uint8_t reset_count;
701 uint8_t reserved_2;
702 uint16_t resource_allocation;
703 uint16_t current_allocation;
704 uint16_t queue_head;
705 uint16_t queue_tail;
706 uint16_t transmit_execution_list_next;
707 uint16_t transmit_execution_list_previous;
708 uint16_t common_features;
709 uint16_t total_concurrent_sequences;
710 uint16_t RO_by_information_category;
711 uint8_t recipient;
712 uint8_t initiator;
713 uint16_t receive_data_size;
714 uint16_t concurrent_sequences;
715 uint16_t open_sequences_per_exchange;
716 uint16_t lun_abort_flags;
717 uint16_t lun_stop_flags;
718 uint16_t stop_queue_head;
719 uint16_t stop_queue_tail;
720 uint16_t port_retry_timer;
721 uint16_t next_sequence_id;
722 uint16_t frame_count;
723 uint16_t PRLI_payload_length;
724 uint8_t prli_svc_param_word_0[2]; /* Big endian */
725 /* Bits 15-0 of word 0 */
726 uint8_t prli_svc_param_word_3[2]; /* Big endian */
727 /* Bits 15-0 of word 3 */
728 uint16_t loop_id;
729 uint16_t extended_lun_info_list_pointer;
730 uint16_t extended_lun_stop_list_pointer;
731 } port_database_t;
732
733 /*
734 * Port database slave/master states
735 */
736 #define PD_STATE_DISCOVERY 0
737 #define PD_STATE_WAIT_DISCOVERY_ACK 1
738 #define PD_STATE_PORT_LOGIN 2
739 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
740 #define PD_STATE_PROCESS_LOGIN 4
741 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
742 #define PD_STATE_PORT_LOGGED_IN 6
743 #define PD_STATE_PORT_UNAVAILABLE 7
744 #define PD_STATE_PROCESS_LOGOUT 8
745 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
746 #define PD_STATE_PORT_LOGOUT 10
747 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
748
749
750 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
751 #define QLA_ZIO_DISABLED 0
752 #define QLA_ZIO_DEFAULT_TIMER 2
753
754 /*
755 * ISP Initialization Control Block.
756 * Little endian except where noted.
757 */
758 #define ICB_VERSION 1
759 typedef struct {
760 uint8_t version;
761 uint8_t reserved_1;
762
763 /*
764 * LSB BIT 0 = Enable Hard Loop Id
765 * LSB BIT 1 = Enable Fairness
766 * LSB BIT 2 = Enable Full-Duplex
767 * LSB BIT 3 = Enable Fast Posting
768 * LSB BIT 4 = Enable Target Mode
769 * LSB BIT 5 = Disable Initiator Mode
770 * LSB BIT 6 = Enable ADISC
771 * LSB BIT 7 = Enable Target Inquiry Data
772 *
773 * MSB BIT 0 = Enable PDBC Notify
774 * MSB BIT 1 = Non Participating LIP
775 * MSB BIT 2 = Descending Loop ID Search
776 * MSB BIT 3 = Acquire Loop ID in LIPA
777 * MSB BIT 4 = Stop PortQ on Full Status
778 * MSB BIT 5 = Full Login after LIP
779 * MSB BIT 6 = Node Name Option
780 * MSB BIT 7 = Ext IFWCB enable bit
781 */
782 uint8_t firmware_options[2];
783
784 uint16_t frame_payload_size;
785 uint16_t max_iocb_allocation;
786 uint16_t execution_throttle;
787 uint8_t retry_count;
788 uint8_t retry_delay; /* unused */
789 uint8_t port_name[WWN_SIZE]; /* Big endian. */
790 uint16_t hard_address;
791 uint8_t inquiry_data;
792 uint8_t login_timeout;
793 uint8_t node_name[WWN_SIZE]; /* Big endian. */
794
795 uint16_t request_q_outpointer;
796 uint16_t response_q_inpointer;
797 uint16_t request_q_length;
798 uint16_t response_q_length;
799 uint32_t request_q_address[2];
800 uint32_t response_q_address[2];
801
802 uint16_t lun_enables;
803 uint8_t command_resource_count;
804 uint8_t immediate_notify_resource_count;
805 uint16_t timeout;
806 uint8_t reserved_2[2];
807
808 /*
809 * LSB BIT 0 = Timer Operation mode bit 0
810 * LSB BIT 1 = Timer Operation mode bit 1
811 * LSB BIT 2 = Timer Operation mode bit 2
812 * LSB BIT 3 = Timer Operation mode bit 3
813 * LSB BIT 4 = Init Config Mode bit 0
814 * LSB BIT 5 = Init Config Mode bit 1
815 * LSB BIT 6 = Init Config Mode bit 2
816 * LSB BIT 7 = Enable Non part on LIHA failure
817 *
818 * MSB BIT 0 = Enable class 2
819 * MSB BIT 1 = Enable ACK0
820 * MSB BIT 2 =
821 * MSB BIT 3 =
822 * MSB BIT 4 = FC Tape Enable
823 * MSB BIT 5 = Enable FC Confirm
824 * MSB BIT 6 = Enable command queuing in target mode
825 * MSB BIT 7 = No Logo On Link Down
826 */
827 uint8_t add_firmware_options[2];
828
829 uint8_t response_accumulation_timer;
830 uint8_t interrupt_delay_timer;
831
832 /*
833 * LSB BIT 0 = Enable Read xfr_rdy
834 * LSB BIT 1 = Soft ID only
835 * LSB BIT 2 =
836 * LSB BIT 3 =
837 * LSB BIT 4 = FCP RSP Payload [0]
838 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
839 * LSB BIT 6 = Enable Out-of-Order frame handling
840 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
841 *
842 * MSB BIT 0 = Sbus enable - 2300
843 * MSB BIT 1 =
844 * MSB BIT 2 =
845 * MSB BIT 3 =
846 * MSB BIT 4 = LED mode
847 * MSB BIT 5 = enable 50 ohm termination
848 * MSB BIT 6 = Data Rate (2300 only)
849 * MSB BIT 7 = Data Rate (2300 only)
850 */
851 uint8_t special_options[2];
852
853 uint8_t reserved_3[26];
854 } init_cb_t;
855
856 /*
857 * Get Link Status mailbox command return buffer.
858 */
859 #define GLSO_SEND_RPS BIT_0
860 #define GLSO_USE_DID BIT_3
861
862 struct link_statistics {
863 uint32_t link_fail_cnt;
864 uint32_t loss_sync_cnt;
865 uint32_t loss_sig_cnt;
866 uint32_t prim_seq_err_cnt;
867 uint32_t inval_xmit_word_cnt;
868 uint32_t inval_crc_cnt;
869 uint32_t unused1[0x1b];
870 uint32_t tx_frames;
871 uint32_t rx_frames;
872 uint32_t dumped_frames;
873 uint32_t unused2[2];
874 uint32_t nos_rcvd;
875 };
876
877 /*
878 * NVRAM Command values.
879 */
880 #define NV_START_BIT BIT_2
881 #define NV_WRITE_OP (BIT_26+BIT_24)
882 #define NV_READ_OP (BIT_26+BIT_25)
883 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
884 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
885 #define NV_DELAY_COUNT 10
886
887 /*
888 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
889 */
890 typedef struct {
891 /*
892 * NVRAM header
893 */
894 uint8_t id[4];
895 uint8_t nvram_version;
896 uint8_t reserved_0;
897
898 /*
899 * NVRAM RISC parameter block
900 */
901 uint8_t parameter_block_version;
902 uint8_t reserved_1;
903
904 /*
905 * LSB BIT 0 = Enable Hard Loop Id
906 * LSB BIT 1 = Enable Fairness
907 * LSB BIT 2 = Enable Full-Duplex
908 * LSB BIT 3 = Enable Fast Posting
909 * LSB BIT 4 = Enable Target Mode
910 * LSB BIT 5 = Disable Initiator Mode
911 * LSB BIT 6 = Enable ADISC
912 * LSB BIT 7 = Enable Target Inquiry Data
913 *
914 * MSB BIT 0 = Enable PDBC Notify
915 * MSB BIT 1 = Non Participating LIP
916 * MSB BIT 2 = Descending Loop ID Search
917 * MSB BIT 3 = Acquire Loop ID in LIPA
918 * MSB BIT 4 = Stop PortQ on Full Status
919 * MSB BIT 5 = Full Login after LIP
920 * MSB BIT 6 = Node Name Option
921 * MSB BIT 7 = Ext IFWCB enable bit
922 */
923 uint8_t firmware_options[2];
924
925 uint16_t frame_payload_size;
926 uint16_t max_iocb_allocation;
927 uint16_t execution_throttle;
928 uint8_t retry_count;
929 uint8_t retry_delay; /* unused */
930 uint8_t port_name[WWN_SIZE]; /* Big endian. */
931 uint16_t hard_address;
932 uint8_t inquiry_data;
933 uint8_t login_timeout;
934 uint8_t node_name[WWN_SIZE]; /* Big endian. */
935
936 /*
937 * LSB BIT 0 = Timer Operation mode bit 0
938 * LSB BIT 1 = Timer Operation mode bit 1
939 * LSB BIT 2 = Timer Operation mode bit 2
940 * LSB BIT 3 = Timer Operation mode bit 3
941 * LSB BIT 4 = Init Config Mode bit 0
942 * LSB BIT 5 = Init Config Mode bit 1
943 * LSB BIT 6 = Init Config Mode bit 2
944 * LSB BIT 7 = Enable Non part on LIHA failure
945 *
946 * MSB BIT 0 = Enable class 2
947 * MSB BIT 1 = Enable ACK0
948 * MSB BIT 2 =
949 * MSB BIT 3 =
950 * MSB BIT 4 = FC Tape Enable
951 * MSB BIT 5 = Enable FC Confirm
952 * MSB BIT 6 = Enable command queuing in target mode
953 * MSB BIT 7 = No Logo On Link Down
954 */
955 uint8_t add_firmware_options[2];
956
957 uint8_t response_accumulation_timer;
958 uint8_t interrupt_delay_timer;
959
960 /*
961 * LSB BIT 0 = Enable Read xfr_rdy
962 * LSB BIT 1 = Soft ID only
963 * LSB BIT 2 =
964 * LSB BIT 3 =
965 * LSB BIT 4 = FCP RSP Payload [0]
966 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
967 * LSB BIT 6 = Enable Out-of-Order frame handling
968 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
969 *
970 * MSB BIT 0 = Sbus enable - 2300
971 * MSB BIT 1 =
972 * MSB BIT 2 =
973 * MSB BIT 3 =
974 * MSB BIT 4 = LED mode
975 * MSB BIT 5 = enable 50 ohm termination
976 * MSB BIT 6 = Data Rate (2300 only)
977 * MSB BIT 7 = Data Rate (2300 only)
978 */
979 uint8_t special_options[2];
980
981 /* Reserved for expanded RISC parameter block */
982 uint8_t reserved_2[22];
983
984 /*
985 * LSB BIT 0 = Tx Sensitivity 1G bit 0
986 * LSB BIT 1 = Tx Sensitivity 1G bit 1
987 * LSB BIT 2 = Tx Sensitivity 1G bit 2
988 * LSB BIT 3 = Tx Sensitivity 1G bit 3
989 * LSB BIT 4 = Rx Sensitivity 1G bit 0
990 * LSB BIT 5 = Rx Sensitivity 1G bit 1
991 * LSB BIT 6 = Rx Sensitivity 1G bit 2
992 * LSB BIT 7 = Rx Sensitivity 1G bit 3
993 *
994 * MSB BIT 0 = Tx Sensitivity 2G bit 0
995 * MSB BIT 1 = Tx Sensitivity 2G bit 1
996 * MSB BIT 2 = Tx Sensitivity 2G bit 2
997 * MSB BIT 3 = Tx Sensitivity 2G bit 3
998 * MSB BIT 4 = Rx Sensitivity 2G bit 0
999 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1000 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1001 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1002 *
1003 * LSB BIT 0 = Output Swing 1G bit 0
1004 * LSB BIT 1 = Output Swing 1G bit 1
1005 * LSB BIT 2 = Output Swing 1G bit 2
1006 * LSB BIT 3 = Output Emphasis 1G bit 0
1007 * LSB BIT 4 = Output Emphasis 1G bit 1
1008 * LSB BIT 5 = Output Swing 2G bit 0
1009 * LSB BIT 6 = Output Swing 2G bit 1
1010 * LSB BIT 7 = Output Swing 2G bit 2
1011 *
1012 * MSB BIT 0 = Output Emphasis 2G bit 0
1013 * MSB BIT 1 = Output Emphasis 2G bit 1
1014 * MSB BIT 2 = Output Enable
1015 * MSB BIT 3 =
1016 * MSB BIT 4 =
1017 * MSB BIT 5 =
1018 * MSB BIT 6 =
1019 * MSB BIT 7 =
1020 */
1021 uint8_t seriallink_options[4];
1022
1023 /*
1024 * NVRAM host parameter block
1025 *
1026 * LSB BIT 0 = Enable spinup delay
1027 * LSB BIT 1 = Disable BIOS
1028 * LSB BIT 2 = Enable Memory Map BIOS
1029 * LSB BIT 3 = Enable Selectable Boot
1030 * LSB BIT 4 = Disable RISC code load
1031 * LSB BIT 5 = Set cache line size 1
1032 * LSB BIT 6 = PCI Parity Disable
1033 * LSB BIT 7 = Enable extended logging
1034 *
1035 * MSB BIT 0 = Enable 64bit addressing
1036 * MSB BIT 1 = Enable lip reset
1037 * MSB BIT 2 = Enable lip full login
1038 * MSB BIT 3 = Enable target reset
1039 * MSB BIT 4 = Enable database storage
1040 * MSB BIT 5 = Enable cache flush read
1041 * MSB BIT 6 = Enable database load
1042 * MSB BIT 7 = Enable alternate WWN
1043 */
1044 uint8_t host_p[2];
1045
1046 uint8_t boot_node_name[WWN_SIZE];
1047 uint8_t boot_lun_number;
1048 uint8_t reset_delay;
1049 uint8_t port_down_retry_count;
1050 uint8_t boot_id_number;
1051 uint16_t max_luns_per_target;
1052 uint8_t fcode_boot_port_name[WWN_SIZE];
1053 uint8_t alternate_port_name[WWN_SIZE];
1054 uint8_t alternate_node_name[WWN_SIZE];
1055
1056 /*
1057 * BIT 0 = Selective Login
1058 * BIT 1 = Alt-Boot Enable
1059 * BIT 2 =
1060 * BIT 3 = Boot Order List
1061 * BIT 4 =
1062 * BIT 5 = Selective LUN
1063 * BIT 6 =
1064 * BIT 7 = unused
1065 */
1066 uint8_t efi_parameters;
1067
1068 uint8_t link_down_timeout;
1069
1070 uint8_t adapter_id[16];
1071
1072 uint8_t alt1_boot_node_name[WWN_SIZE];
1073 uint16_t alt1_boot_lun_number;
1074 uint8_t alt2_boot_node_name[WWN_SIZE];
1075 uint16_t alt2_boot_lun_number;
1076 uint8_t alt3_boot_node_name[WWN_SIZE];
1077 uint16_t alt3_boot_lun_number;
1078 uint8_t alt4_boot_node_name[WWN_SIZE];
1079 uint16_t alt4_boot_lun_number;
1080 uint8_t alt5_boot_node_name[WWN_SIZE];
1081 uint16_t alt5_boot_lun_number;
1082 uint8_t alt6_boot_node_name[WWN_SIZE];
1083 uint16_t alt6_boot_lun_number;
1084 uint8_t alt7_boot_node_name[WWN_SIZE];
1085 uint16_t alt7_boot_lun_number;
1086
1087 uint8_t reserved_3[2];
1088
1089 /* Offset 200-215 : Model Number */
1090 uint8_t model_number[16];
1091
1092 /* OEM related items */
1093 uint8_t oem_specific[16];
1094
1095 /*
1096 * NVRAM Adapter Features offset 232-239
1097 *
1098 * LSB BIT 0 = External GBIC
1099 * LSB BIT 1 = Risc RAM parity
1100 * LSB BIT 2 = Buffer Plus Module
1101 * LSB BIT 3 = Multi Chip Adapter
1102 * LSB BIT 4 = Internal connector
1103 * LSB BIT 5 =
1104 * LSB BIT 6 =
1105 * LSB BIT 7 =
1106 *
1107 * MSB BIT 0 =
1108 * MSB BIT 1 =
1109 * MSB BIT 2 =
1110 * MSB BIT 3 =
1111 * MSB BIT 4 =
1112 * MSB BIT 5 =
1113 * MSB BIT 6 =
1114 * MSB BIT 7 =
1115 */
1116 uint8_t adapter_features[2];
1117
1118 uint8_t reserved_4[16];
1119
1120 /* Subsystem vendor ID for ISP2200 */
1121 uint16_t subsystem_vendor_id_2200;
1122
1123 /* Subsystem device ID for ISP2200 */
1124 uint16_t subsystem_device_id_2200;
1125
1126 uint8_t reserved_5;
1127 uint8_t checksum;
1128 } nvram_t;
1129
1130 /*
1131 * ISP queue - response queue entry definition.
1132 */
1133 typedef struct {
1134 uint8_t data[60];
1135 uint32_t signature;
1136 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1137 } response_t;
1138
1139 typedef union {
1140 uint16_t extended;
1141 struct {
1142 uint8_t reserved;
1143 uint8_t standard;
1144 } id;
1145 } target_id_t;
1146
1147 #define SET_TARGET_ID(ha, to, from) \
1148 do { \
1149 if (HAS_EXTENDED_IDS(ha)) \
1150 to.extended = cpu_to_le16(from); \
1151 else \
1152 to.id.standard = (uint8_t)from; \
1153 } while (0)
1154
1155 /*
1156 * ISP queue - command entry structure definition.
1157 */
1158 #define COMMAND_TYPE 0x11 /* Command entry */
1159 typedef struct {
1160 uint8_t entry_type; /* Entry type. */
1161 uint8_t entry_count; /* Entry count. */
1162 uint8_t sys_define; /* System defined. */
1163 uint8_t entry_status; /* Entry Status. */
1164 uint32_t handle; /* System handle. */
1165 target_id_t target; /* SCSI ID */
1166 uint16_t lun; /* SCSI LUN */
1167 uint16_t control_flags; /* Control flags. */
1168 #define CF_WRITE BIT_6
1169 #define CF_READ BIT_5
1170 #define CF_SIMPLE_TAG BIT_3
1171 #define CF_ORDERED_TAG BIT_2
1172 #define CF_HEAD_TAG BIT_1
1173 uint16_t reserved_1;
1174 uint16_t timeout; /* Command timeout. */
1175 uint16_t dseg_count; /* Data segment count. */
1176 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1177 uint32_t byte_count; /* Total byte count. */
1178 uint32_t dseg_0_address; /* Data segment 0 address. */
1179 uint32_t dseg_0_length; /* Data segment 0 length. */
1180 uint32_t dseg_1_address; /* Data segment 1 address. */
1181 uint32_t dseg_1_length; /* Data segment 1 length. */
1182 uint32_t dseg_2_address; /* Data segment 2 address. */
1183 uint32_t dseg_2_length; /* Data segment 2 length. */
1184 } cmd_entry_t;
1185
1186 /*
1187 * ISP queue - 64-Bit addressing, command entry structure definition.
1188 */
1189 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1190 typedef struct {
1191 uint8_t entry_type; /* Entry type. */
1192 uint8_t entry_count; /* Entry count. */
1193 uint8_t sys_define; /* System defined. */
1194 uint8_t entry_status; /* Entry Status. */
1195 uint32_t handle; /* System handle. */
1196 target_id_t target; /* SCSI ID */
1197 uint16_t lun; /* SCSI LUN */
1198 uint16_t control_flags; /* Control flags. */
1199 uint16_t reserved_1;
1200 uint16_t timeout; /* Command timeout. */
1201 uint16_t dseg_count; /* Data segment count. */
1202 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1203 uint32_t byte_count; /* Total byte count. */
1204 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1205 uint32_t dseg_0_length; /* Data segment 0 length. */
1206 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1207 uint32_t dseg_1_length; /* Data segment 1 length. */
1208 } cmd_a64_entry_t, request_t;
1209
1210 /*
1211 * ISP queue - continuation entry structure definition.
1212 */
1213 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1214 typedef struct {
1215 uint8_t entry_type; /* Entry type. */
1216 uint8_t entry_count; /* Entry count. */
1217 uint8_t sys_define; /* System defined. */
1218 uint8_t entry_status; /* Entry Status. */
1219 uint32_t reserved;
1220 uint32_t dseg_0_address; /* Data segment 0 address. */
1221 uint32_t dseg_0_length; /* Data segment 0 length. */
1222 uint32_t dseg_1_address; /* Data segment 1 address. */
1223 uint32_t dseg_1_length; /* Data segment 1 length. */
1224 uint32_t dseg_2_address; /* Data segment 2 address. */
1225 uint32_t dseg_2_length; /* Data segment 2 length. */
1226 uint32_t dseg_3_address; /* Data segment 3 address. */
1227 uint32_t dseg_3_length; /* Data segment 3 length. */
1228 uint32_t dseg_4_address; /* Data segment 4 address. */
1229 uint32_t dseg_4_length; /* Data segment 4 length. */
1230 uint32_t dseg_5_address; /* Data segment 5 address. */
1231 uint32_t dseg_5_length; /* Data segment 5 length. */
1232 uint32_t dseg_6_address; /* Data segment 6 address. */
1233 uint32_t dseg_6_length; /* Data segment 6 length. */
1234 } cont_entry_t;
1235
1236 /*
1237 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1238 */
1239 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1240 typedef struct {
1241 uint8_t entry_type; /* Entry type. */
1242 uint8_t entry_count; /* Entry count. */
1243 uint8_t sys_define; /* System defined. */
1244 uint8_t entry_status; /* Entry Status. */
1245 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1246 uint32_t dseg_0_length; /* Data segment 0 length. */
1247 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1248 uint32_t dseg_1_length; /* Data segment 1 length. */
1249 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1250 uint32_t dseg_2_length; /* Data segment 2 length. */
1251 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1252 uint32_t dseg_3_length; /* Data segment 3 length. */
1253 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1254 uint32_t dseg_4_length; /* Data segment 4 length. */
1255 } cont_a64_entry_t;
1256
1257 /*
1258 * ISP queue - status entry structure definition.
1259 */
1260 #define STATUS_TYPE 0x03 /* Status entry. */
1261 typedef struct {
1262 uint8_t entry_type; /* Entry type. */
1263 uint8_t entry_count; /* Entry count. */
1264 uint8_t sys_define; /* System defined. */
1265 uint8_t entry_status; /* Entry Status. */
1266 uint32_t handle; /* System handle. */
1267 uint16_t scsi_status; /* SCSI status. */
1268 uint16_t comp_status; /* Completion status. */
1269 uint16_t state_flags; /* State flags. */
1270 uint16_t status_flags; /* Status flags. */
1271 uint16_t rsp_info_len; /* Response Info Length. */
1272 uint16_t req_sense_length; /* Request sense data length. */
1273 uint32_t residual_length; /* Residual transfer length. */
1274 uint8_t rsp_info[8]; /* FCP response information. */
1275 uint8_t req_sense_data[32]; /* Request sense data. */
1276 } sts_entry_t;
1277
1278 /*
1279 * Status entry entry status
1280 */
1281 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1282 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1283 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1284 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1285 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1286 #define RF_BUSY BIT_1 /* Busy */
1287 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1288 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1289 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1290 RF_INV_E_TYPE)
1291
1292 /*
1293 * Status entry SCSI status bit definitions.
1294 */
1295 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1296 #define SS_RESIDUAL_UNDER BIT_11
1297 #define SS_RESIDUAL_OVER BIT_10
1298 #define SS_SENSE_LEN_VALID BIT_9
1299 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1300
1301 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1302 #define SS_BUSY_CONDITION BIT_3
1303 #define SS_CONDITION_MET BIT_2
1304 #define SS_CHECK_CONDITION BIT_1
1305
1306 /*
1307 * Status entry completion status
1308 */
1309 #define CS_COMPLETE 0x0 /* No errors */
1310 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1311 #define CS_DMA 0x2 /* A DMA direction error. */
1312 #define CS_TRANSPORT 0x3 /* Transport error. */
1313 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1314 #define CS_ABORTED 0x5 /* System aborted command. */
1315 #define CS_TIMEOUT 0x6 /* Timeout error. */
1316 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1317
1318 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1319 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1320 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1321 /* (selection timeout) */
1322 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1323 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1324 #define CS_PORT_BUSY 0x2B /* Port Busy */
1325 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1326 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1327 #define CS_UNKNOWN 0x81 /* Driver defined */
1328 #define CS_RETRY 0x82 /* Driver defined */
1329 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1330
1331 /*
1332 * Status entry status flags
1333 */
1334 #define SF_ABTS_TERMINATED BIT_10
1335 #define SF_LOGOUT_SENT BIT_13
1336
1337 /*
1338 * ISP queue - status continuation entry structure definition.
1339 */
1340 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1341 typedef struct {
1342 uint8_t entry_type; /* Entry type. */
1343 uint8_t entry_count; /* Entry count. */
1344 uint8_t sys_define; /* System defined. */
1345 uint8_t entry_status; /* Entry Status. */
1346 uint8_t data[60]; /* data */
1347 } sts_cont_entry_t;
1348
1349 /*
1350 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1351 * structure definition.
1352 */
1353 #define STATUS_TYPE_21 0x21 /* Status entry. */
1354 typedef struct {
1355 uint8_t entry_type; /* Entry type. */
1356 uint8_t entry_count; /* Entry count. */
1357 uint8_t handle_count; /* Handle count. */
1358 uint8_t entry_status; /* Entry Status. */
1359 uint32_t handle[15]; /* System handles. */
1360 } sts21_entry_t;
1361
1362 /*
1363 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1364 * structure definition.
1365 */
1366 #define STATUS_TYPE_22 0x22 /* Status entry. */
1367 typedef struct {
1368 uint8_t entry_type; /* Entry type. */
1369 uint8_t entry_count; /* Entry count. */
1370 uint8_t handle_count; /* Handle count. */
1371 uint8_t entry_status; /* Entry Status. */
1372 uint16_t handle[30]; /* System handles. */
1373 } sts22_entry_t;
1374
1375 /*
1376 * ISP queue - marker entry structure definition.
1377 */
1378 #define MARKER_TYPE 0x04 /* Marker entry. */
1379 typedef struct {
1380 uint8_t entry_type; /* Entry type. */
1381 uint8_t entry_count; /* Entry count. */
1382 uint8_t handle_count; /* Handle count. */
1383 uint8_t entry_status; /* Entry Status. */
1384 uint32_t sys_define_2; /* System defined. */
1385 target_id_t target; /* SCSI ID */
1386 uint8_t modifier; /* Modifier (7-0). */
1387 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1388 #define MK_SYNC_ID 1 /* Synchronize ID */
1389 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1390 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1391 /* clear port changed, */
1392 /* use sequence number. */
1393 uint8_t reserved_1;
1394 uint16_t sequence_number; /* Sequence number of event */
1395 uint16_t lun; /* SCSI LUN */
1396 uint8_t reserved_2[48];
1397 } mrk_entry_t;
1398
1399 /*
1400 * ISP queue - Management Server entry structure definition.
1401 */
1402 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1403 typedef struct {
1404 uint8_t entry_type; /* Entry type. */
1405 uint8_t entry_count; /* Entry count. */
1406 uint8_t handle_count; /* Handle count. */
1407 uint8_t entry_status; /* Entry Status. */
1408 uint32_t handle1; /* System handle. */
1409 target_id_t loop_id;
1410 uint16_t status;
1411 uint16_t control_flags; /* Control flags. */
1412 uint16_t reserved2;
1413 uint16_t timeout;
1414 uint16_t cmd_dsd_count;
1415 uint16_t total_dsd_count;
1416 uint8_t type;
1417 uint8_t r_ctl;
1418 uint16_t rx_id;
1419 uint16_t reserved3;
1420 uint32_t handle2;
1421 uint32_t rsp_bytecount;
1422 uint32_t req_bytecount;
1423 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1424 uint32_t dseg_req_length; /* Data segment 0 length. */
1425 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1426 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1427 } ms_iocb_entry_t;
1428
1429
1430 /*
1431 * ISP queue - Mailbox Command entry structure definition.
1432 */
1433 #define MBX_IOCB_TYPE 0x39
1434 struct mbx_entry {
1435 uint8_t entry_type;
1436 uint8_t entry_count;
1437 uint8_t sys_define1;
1438 /* Use sys_define1 for source type */
1439 #define SOURCE_SCSI 0x00
1440 #define SOURCE_IP 0x01
1441 #define SOURCE_VI 0x02
1442 #define SOURCE_SCTP 0x03
1443 #define SOURCE_MP 0x04
1444 #define SOURCE_MPIOCTL 0x05
1445 #define SOURCE_ASYNC_IOCB 0x07
1446
1447 uint8_t entry_status;
1448
1449 uint32_t handle;
1450 target_id_t loop_id;
1451
1452 uint16_t status;
1453 uint16_t state_flags;
1454 uint16_t status_flags;
1455
1456 uint32_t sys_define2[2];
1457
1458 uint16_t mb0;
1459 uint16_t mb1;
1460 uint16_t mb2;
1461 uint16_t mb3;
1462 uint16_t mb6;
1463 uint16_t mb7;
1464 uint16_t mb9;
1465 uint16_t mb10;
1466 uint32_t reserved_2[2];
1467 uint8_t node_name[WWN_SIZE];
1468 uint8_t port_name[WWN_SIZE];
1469 };
1470
1471 /*
1472 * ISP request and response queue entry sizes
1473 */
1474 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1475 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1476
1477
1478 /*
1479 * 24 bit port ID type definition.
1480 */
1481 typedef union {
1482 uint32_t b24 : 24;
1483
1484 struct {
1485 #ifdef __BIG_ENDIAN
1486 uint8_t domain;
1487 uint8_t area;
1488 uint8_t al_pa;
1489 #elif __LITTLE_ENDIAN
1490 uint8_t al_pa;
1491 uint8_t area;
1492 uint8_t domain;
1493 #else
1494 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1495 #endif
1496 uint8_t rsvd_1;
1497 } b;
1498 } port_id_t;
1499 #define INVALID_PORT_ID 0xFFFFFF
1500
1501 /*
1502 * Switch info gathering structure.
1503 */
1504 typedef struct {
1505 port_id_t d_id;
1506 uint8_t node_name[WWN_SIZE];
1507 uint8_t port_name[WWN_SIZE];
1508 uint8_t fabric_port_name[WWN_SIZE];
1509 uint16_t fp_speed;
1510 } sw_info_t;
1511
1512 /*
1513 * Fibre channel port type.
1514 */
1515 typedef enum {
1516 FCT_UNKNOWN,
1517 FCT_RSCN,
1518 FCT_SWITCH,
1519 FCT_BROADCAST,
1520 FCT_INITIATOR,
1521 FCT_TARGET
1522 } fc_port_type_t;
1523
1524 /*
1525 * Fibre channel port structure.
1526 */
1527 typedef struct fc_port {
1528 struct list_head list;
1529 struct scsi_qla_host *ha;
1530
1531 uint8_t node_name[WWN_SIZE];
1532 uint8_t port_name[WWN_SIZE];
1533 port_id_t d_id;
1534 uint16_t loop_id;
1535 uint16_t old_loop_id;
1536
1537 uint8_t fabric_port_name[WWN_SIZE];
1538 uint16_t fp_speed;
1539
1540 fc_port_type_t port_type;
1541
1542 atomic_t state;
1543 uint32_t flags;
1544
1545 unsigned int os_target_id;
1546
1547 int port_login_retry_count;
1548 int login_retry;
1549 atomic_t port_down_timer;
1550
1551 spinlock_t rport_lock;
1552 struct fc_rport *rport, *drport;
1553 u32 supported_classes;
1554
1555 unsigned long last_queue_full;
1556 unsigned long last_ramp_up;
1557
1558 struct list_head vp_fcport;
1559 uint16_t vp_idx;
1560 } fc_port_t;
1561
1562 /*
1563 * Fibre channel port/lun states.
1564 */
1565 #define FCS_UNCONFIGURED 1
1566 #define FCS_DEVICE_DEAD 2
1567 #define FCS_DEVICE_LOST 3
1568 #define FCS_ONLINE 4
1569 #define FCS_NOT_SUPPORTED 5
1570 #define FCS_FAILOVER 6
1571 #define FCS_FAILOVER_FAILED 7
1572
1573 /*
1574 * FC port flags.
1575 */
1576 #define FCF_FABRIC_DEVICE BIT_0
1577 #define FCF_LOGIN_NEEDED BIT_1
1578 #define FCF_FO_MASKED BIT_2
1579 #define FCF_FAILOVER_NEEDED BIT_3
1580 #define FCF_RESET_NEEDED BIT_4
1581 #define FCF_PERSISTENT_BOUND BIT_5
1582 #define FCF_TAPE_PRESENT BIT_6
1583 #define FCF_FARP_DONE BIT_7
1584 #define FCF_FARP_FAILED BIT_8
1585 #define FCF_FARP_REPLY_NEEDED BIT_9
1586 #define FCF_AUTH_REQ BIT_10
1587 #define FCF_SEND_AUTH_REQ BIT_11
1588 #define FCF_RECEIVE_AUTH_REQ BIT_12
1589 #define FCF_AUTH_SUCCESS BIT_13
1590 #define FCF_RLC_SUPPORT BIT_14
1591 #define FCF_CONFIG BIT_15 /* Needed? */
1592 #define FCF_RESCAN_NEEDED BIT_16
1593 #define FCF_XP_DEVICE BIT_17
1594 #define FCF_MSA_DEVICE BIT_18
1595 #define FCF_EVA_DEVICE BIT_19
1596 #define FCF_MSA_PORT_ACTIVE BIT_20
1597 #define FCF_FAILBACK_DISABLE BIT_21
1598 #define FCF_FAILOVER_DISABLE BIT_22
1599 #define FCF_DSXXX_DEVICE BIT_23
1600 #define FCF_AA_EVA_DEVICE BIT_24
1601 #define FCF_AA_MSA_DEVICE BIT_25
1602
1603 /* No loop ID flag. */
1604 #define FC_NO_LOOP_ID 0x1000
1605
1606 /*
1607 * FC-CT interface
1608 *
1609 * NOTE: All structures are big-endian in form.
1610 */
1611
1612 #define CT_REJECT_RESPONSE 0x8001
1613 #define CT_ACCEPT_RESPONSE 0x8002
1614 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1615 #define CT_REASON_CANNOT_PERFORM 0x09
1616 #define CT_EXPL_ALREADY_REGISTERED 0x10
1617
1618 #define NS_N_PORT_TYPE 0x01
1619 #define NS_NL_PORT_TYPE 0x02
1620 #define NS_NX_PORT_TYPE 0x7F
1621
1622 #define GA_NXT_CMD 0x100
1623 #define GA_NXT_REQ_SIZE (16 + 4)
1624 #define GA_NXT_RSP_SIZE (16 + 620)
1625
1626 #define GID_PT_CMD 0x1A1
1627 #define GID_PT_REQ_SIZE (16 + 4)
1628 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1629
1630 #define GPN_ID_CMD 0x112
1631 #define GPN_ID_REQ_SIZE (16 + 4)
1632 #define GPN_ID_RSP_SIZE (16 + 8)
1633
1634 #define GNN_ID_CMD 0x113
1635 #define GNN_ID_REQ_SIZE (16 + 4)
1636 #define GNN_ID_RSP_SIZE (16 + 8)
1637
1638 #define GFT_ID_CMD 0x117
1639 #define GFT_ID_REQ_SIZE (16 + 4)
1640 #define GFT_ID_RSP_SIZE (16 + 32)
1641
1642 #define RFT_ID_CMD 0x217
1643 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1644 #define RFT_ID_RSP_SIZE 16
1645
1646 #define RFF_ID_CMD 0x21F
1647 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1648 #define RFF_ID_RSP_SIZE 16
1649
1650 #define RNN_ID_CMD 0x213
1651 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1652 #define RNN_ID_RSP_SIZE 16
1653
1654 #define RSNN_NN_CMD 0x239
1655 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1656 #define RSNN_NN_RSP_SIZE 16
1657
1658 #define GFPN_ID_CMD 0x11C
1659 #define GFPN_ID_REQ_SIZE (16 + 4)
1660 #define GFPN_ID_RSP_SIZE (16 + 8)
1661
1662 #define GPSC_CMD 0x127
1663 #define GPSC_REQ_SIZE (16 + 8)
1664 #define GPSC_RSP_SIZE (16 + 2 + 2)
1665
1666
1667 /*
1668 * HBA attribute types.
1669 */
1670 #define FDMI_HBA_ATTR_COUNT 9
1671 #define FDMI_HBA_NODE_NAME 1
1672 #define FDMI_HBA_MANUFACTURER 2
1673 #define FDMI_HBA_SERIAL_NUMBER 3
1674 #define FDMI_HBA_MODEL 4
1675 #define FDMI_HBA_MODEL_DESCRIPTION 5
1676 #define FDMI_HBA_HARDWARE_VERSION 6
1677 #define FDMI_HBA_DRIVER_VERSION 7
1678 #define FDMI_HBA_OPTION_ROM_VERSION 8
1679 #define FDMI_HBA_FIRMWARE_VERSION 9
1680 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1681 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1682
1683 struct ct_fdmi_hba_attr {
1684 uint16_t type;
1685 uint16_t len;
1686 union {
1687 uint8_t node_name[WWN_SIZE];
1688 uint8_t manufacturer[32];
1689 uint8_t serial_num[8];
1690 uint8_t model[16];
1691 uint8_t model_desc[80];
1692 uint8_t hw_version[16];
1693 uint8_t driver_version[32];
1694 uint8_t orom_version[16];
1695 uint8_t fw_version[16];
1696 uint8_t os_version[128];
1697 uint8_t max_ct_len[4];
1698 } a;
1699 };
1700
1701 struct ct_fdmi_hba_attributes {
1702 uint32_t count;
1703 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1704 };
1705
1706 /*
1707 * Port attribute types.
1708 */
1709 #define FDMI_PORT_ATTR_COUNT 6
1710 #define FDMI_PORT_FC4_TYPES 1
1711 #define FDMI_PORT_SUPPORT_SPEED 2
1712 #define FDMI_PORT_CURRENT_SPEED 3
1713 #define FDMI_PORT_MAX_FRAME_SIZE 4
1714 #define FDMI_PORT_OS_DEVICE_NAME 5
1715 #define FDMI_PORT_HOST_NAME 6
1716
1717 #define FDMI_PORT_SPEED_1GB 0x1
1718 #define FDMI_PORT_SPEED_2GB 0x2
1719 #define FDMI_PORT_SPEED_10GB 0x4
1720 #define FDMI_PORT_SPEED_4GB 0x8
1721 #define FDMI_PORT_SPEED_8GB 0x10
1722 #define FDMI_PORT_SPEED_16GB 0x20
1723 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1724
1725 struct ct_fdmi_port_attr {
1726 uint16_t type;
1727 uint16_t len;
1728 union {
1729 uint8_t fc4_types[32];
1730 uint32_t sup_speed;
1731 uint32_t cur_speed;
1732 uint32_t max_frame_size;
1733 uint8_t os_dev_name[32];
1734 uint8_t host_name[32];
1735 } a;
1736 };
1737
1738 /*
1739 * Port Attribute Block.
1740 */
1741 struct ct_fdmi_port_attributes {
1742 uint32_t count;
1743 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1744 };
1745
1746 /* FDMI definitions. */
1747 #define GRHL_CMD 0x100
1748 #define GHAT_CMD 0x101
1749 #define GRPL_CMD 0x102
1750 #define GPAT_CMD 0x110
1751
1752 #define RHBA_CMD 0x200
1753 #define RHBA_RSP_SIZE 16
1754
1755 #define RHAT_CMD 0x201
1756 #define RPRT_CMD 0x210
1757
1758 #define RPA_CMD 0x211
1759 #define RPA_RSP_SIZE 16
1760
1761 #define DHBA_CMD 0x300
1762 #define DHBA_REQ_SIZE (16 + 8)
1763 #define DHBA_RSP_SIZE 16
1764
1765 #define DHAT_CMD 0x301
1766 #define DPRT_CMD 0x310
1767 #define DPA_CMD 0x311
1768
1769 /* CT command header -- request/response common fields */
1770 struct ct_cmd_hdr {
1771 uint8_t revision;
1772 uint8_t in_id[3];
1773 uint8_t gs_type;
1774 uint8_t gs_subtype;
1775 uint8_t options;
1776 uint8_t reserved;
1777 };
1778
1779 /* CT command request */
1780 struct ct_sns_req {
1781 struct ct_cmd_hdr header;
1782 uint16_t command;
1783 uint16_t max_rsp_size;
1784 uint8_t fragment_id;
1785 uint8_t reserved[3];
1786
1787 union {
1788 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1789 struct {
1790 uint8_t reserved;
1791 uint8_t port_id[3];
1792 } port_id;
1793
1794 struct {
1795 uint8_t port_type;
1796 uint8_t domain;
1797 uint8_t area;
1798 uint8_t reserved;
1799 } gid_pt;
1800
1801 struct {
1802 uint8_t reserved;
1803 uint8_t port_id[3];
1804 uint8_t fc4_types[32];
1805 } rft_id;
1806
1807 struct {
1808 uint8_t reserved;
1809 uint8_t port_id[3];
1810 uint16_t reserved2;
1811 uint8_t fc4_feature;
1812 uint8_t fc4_type;
1813 } rff_id;
1814
1815 struct {
1816 uint8_t reserved;
1817 uint8_t port_id[3];
1818 uint8_t node_name[8];
1819 } rnn_id;
1820
1821 struct {
1822 uint8_t node_name[8];
1823 uint8_t name_len;
1824 uint8_t sym_node_name[255];
1825 } rsnn_nn;
1826
1827 struct {
1828 uint8_t hba_indentifier[8];
1829 } ghat;
1830
1831 struct {
1832 uint8_t hba_identifier[8];
1833 uint32_t entry_count;
1834 uint8_t port_name[8];
1835 struct ct_fdmi_hba_attributes attrs;
1836 } rhba;
1837
1838 struct {
1839 uint8_t hba_identifier[8];
1840 struct ct_fdmi_hba_attributes attrs;
1841 } rhat;
1842
1843 struct {
1844 uint8_t port_name[8];
1845 struct ct_fdmi_port_attributes attrs;
1846 } rpa;
1847
1848 struct {
1849 uint8_t port_name[8];
1850 } dhba;
1851
1852 struct {
1853 uint8_t port_name[8];
1854 } dhat;
1855
1856 struct {
1857 uint8_t port_name[8];
1858 } dprt;
1859
1860 struct {
1861 uint8_t port_name[8];
1862 } dpa;
1863
1864 struct {
1865 uint8_t port_name[8];
1866 } gpsc;
1867 } req;
1868 };
1869
1870 /* CT command response header */
1871 struct ct_rsp_hdr {
1872 struct ct_cmd_hdr header;
1873 uint16_t response;
1874 uint16_t residual;
1875 uint8_t fragment_id;
1876 uint8_t reason_code;
1877 uint8_t explanation_code;
1878 uint8_t vendor_unique;
1879 };
1880
1881 struct ct_sns_gid_pt_data {
1882 uint8_t control_byte;
1883 uint8_t port_id[3];
1884 };
1885
1886 struct ct_sns_rsp {
1887 struct ct_rsp_hdr header;
1888
1889 union {
1890 struct {
1891 uint8_t port_type;
1892 uint8_t port_id[3];
1893 uint8_t port_name[8];
1894 uint8_t sym_port_name_len;
1895 uint8_t sym_port_name[255];
1896 uint8_t node_name[8];
1897 uint8_t sym_node_name_len;
1898 uint8_t sym_node_name[255];
1899 uint8_t init_proc_assoc[8];
1900 uint8_t node_ip_addr[16];
1901 uint8_t class_of_service[4];
1902 uint8_t fc4_types[32];
1903 uint8_t ip_address[16];
1904 uint8_t fabric_port_name[8];
1905 uint8_t reserved;
1906 uint8_t hard_address[3];
1907 } ga_nxt;
1908
1909 struct {
1910 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1911 } gid_pt;
1912
1913 struct {
1914 uint8_t port_name[8];
1915 } gpn_id;
1916
1917 struct {
1918 uint8_t node_name[8];
1919 } gnn_id;
1920
1921 struct {
1922 uint8_t fc4_types[32];
1923 } gft_id;
1924
1925 struct {
1926 uint32_t entry_count;
1927 uint8_t port_name[8];
1928 struct ct_fdmi_hba_attributes attrs;
1929 } ghat;
1930
1931 struct {
1932 uint8_t port_name[8];
1933 } gfpn_id;
1934
1935 struct {
1936 uint16_t speeds;
1937 uint16_t speed;
1938 } gpsc;
1939 } rsp;
1940 };
1941
1942 struct ct_sns_pkt {
1943 union {
1944 struct ct_sns_req req;
1945 struct ct_sns_rsp rsp;
1946 } p;
1947 };
1948
1949 /*
1950 * SNS command structures -- for 2200 compatability.
1951 */
1952 #define RFT_ID_SNS_SCMD_LEN 22
1953 #define RFT_ID_SNS_CMD_SIZE 60
1954 #define RFT_ID_SNS_DATA_SIZE 16
1955
1956 #define RNN_ID_SNS_SCMD_LEN 10
1957 #define RNN_ID_SNS_CMD_SIZE 36
1958 #define RNN_ID_SNS_DATA_SIZE 16
1959
1960 #define GA_NXT_SNS_SCMD_LEN 6
1961 #define GA_NXT_SNS_CMD_SIZE 28
1962 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1963
1964 #define GID_PT_SNS_SCMD_LEN 6
1965 #define GID_PT_SNS_CMD_SIZE 28
1966 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1967
1968 #define GPN_ID_SNS_SCMD_LEN 6
1969 #define GPN_ID_SNS_CMD_SIZE 28
1970 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1971
1972 #define GNN_ID_SNS_SCMD_LEN 6
1973 #define GNN_ID_SNS_CMD_SIZE 28
1974 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1975
1976 struct sns_cmd_pkt {
1977 union {
1978 struct {
1979 uint16_t buffer_length;
1980 uint16_t reserved_1;
1981 uint32_t buffer_address[2];
1982 uint16_t subcommand_length;
1983 uint16_t reserved_2;
1984 uint16_t subcommand;
1985 uint16_t size;
1986 uint32_t reserved_3;
1987 uint8_t param[36];
1988 } cmd;
1989
1990 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1991 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1992 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1993 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1994 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1995 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1996 } p;
1997 };
1998
1999 struct fw_blob {
2000 char *name;
2001 uint32_t segs[4];
2002 const struct firmware *fw;
2003 };
2004
2005 /* Return data from MBC_GET_ID_LIST call. */
2006 struct gid_list_info {
2007 uint8_t al_pa;
2008 uint8_t area;
2009 uint8_t domain;
2010 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2011 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2012 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2013 };
2014 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2015
2016 /* NPIV */
2017 typedef struct vport_info {
2018 uint8_t port_name[WWN_SIZE];
2019 uint8_t node_name[WWN_SIZE];
2020 int vp_id;
2021 uint16_t loop_id;
2022 unsigned long host_no;
2023 uint8_t port_id[3];
2024 int loop_state;
2025 } vport_info_t;
2026
2027 typedef struct vport_params {
2028 uint8_t port_name[WWN_SIZE];
2029 uint8_t node_name[WWN_SIZE];
2030 uint32_t options;
2031 #define VP_OPTS_RETRY_ENABLE BIT_0
2032 #define VP_OPTS_VP_DISABLE BIT_1
2033 } vport_params_t;
2034
2035 /* NPIV - return codes of VP create and modify */
2036 #define VP_RET_CODE_OK 0
2037 #define VP_RET_CODE_FATAL 1
2038 #define VP_RET_CODE_WRONG_ID 2
2039 #define VP_RET_CODE_WWPN 3
2040 #define VP_RET_CODE_RESOURCES 4
2041 #define VP_RET_CODE_NO_MEM 5
2042 #define VP_RET_CODE_NOT_FOUND 6
2043
2044 /*
2045 * ISP operations
2046 */
2047 struct isp_operations {
2048
2049 int (*pci_config) (struct scsi_qla_host *);
2050 void (*reset_chip) (struct scsi_qla_host *);
2051 int (*chip_diag) (struct scsi_qla_host *);
2052 void (*config_rings) (struct scsi_qla_host *);
2053 void (*reset_adapter) (struct scsi_qla_host *);
2054 int (*nvram_config) (struct scsi_qla_host *);
2055 void (*update_fw_options) (struct scsi_qla_host *);
2056 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2057
2058 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2059 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2060
2061 irq_handler_t intr_handler;
2062 void (*enable_intrs) (struct scsi_qla_host *);
2063 void (*disable_intrs) (struct scsi_qla_host *);
2064
2065 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2066 int (*abort_target) (struct fc_port *);
2067 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2068 uint8_t, uint8_t, uint16_t *, uint8_t);
2069 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2070 uint8_t, uint8_t);
2071
2072 uint16_t (*calc_req_entries) (uint16_t);
2073 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2074 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2075 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2076 uint32_t);
2077
2078 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2079 uint32_t, uint32_t);
2080 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2081 uint32_t);
2082
2083 void (*fw_dump) (struct scsi_qla_host *, int);
2084
2085 int (*beacon_on) (struct scsi_qla_host *);
2086 int (*beacon_off) (struct scsi_qla_host *);
2087 void (*beacon_blink) (struct scsi_qla_host *);
2088
2089 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2090 uint32_t, uint32_t);
2091 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2092 uint32_t);
2093
2094 int (*get_flash_version) (struct scsi_qla_host *, void *);
2095 };
2096
2097 /* MSI-X Support *************************************************************/
2098
2099 #define QLA_MSIX_CHIP_REV_24XX 3
2100 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2101 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2102
2103 #define QLA_MSIX_DEFAULT 0x00
2104 #define QLA_MSIX_RSP_Q 0x01
2105
2106 #define QLA_MSIX_ENTRIES 2
2107 #define QLA_MIDX_DEFAULT 0
2108 #define QLA_MIDX_RSP_Q 1
2109
2110 struct scsi_qla_host;
2111
2112 struct qla_msix_entry {
2113 int have_irq;
2114 uint16_t msix_vector;
2115 uint16_t msix_entry;
2116 };
2117
2118 #define WATCH_INTERVAL 1 /* number of seconds */
2119
2120 /*
2121 * Linux Host Adapter structure
2122 */
2123 typedef struct scsi_qla_host {
2124 struct list_head list;
2125
2126 /* Commonly used flags and state information. */
2127 struct Scsi_Host *host;
2128 struct pci_dev *pdev;
2129
2130 unsigned long host_no;
2131 unsigned long instance;
2132
2133 volatile struct {
2134 uint32_t init_done :1;
2135 uint32_t online :1;
2136 uint32_t mbox_int :1;
2137 uint32_t mbox_busy :1;
2138 uint32_t rscn_queue_overflow :1;
2139 uint32_t reset_active :1;
2140
2141 uint32_t management_server_logged_in :1;
2142 uint32_t process_response_queue :1;
2143
2144 uint32_t disable_risc_code_load :1;
2145 uint32_t enable_64bit_addressing :1;
2146 uint32_t enable_lip_reset :1;
2147 uint32_t enable_lip_full_login :1;
2148 uint32_t enable_target_reset :1;
2149 uint32_t enable_led_scheme :1;
2150 uint32_t inta_enabled :1;
2151 uint32_t msi_enabled :1;
2152 uint32_t msix_enabled :1;
2153 uint32_t disable_serdes :1;
2154 uint32_t gpsc_supported :1;
2155 uint32_t vsan_enabled :1;
2156 uint32_t npiv_supported :1;
2157 uint32_t fce_enabled :1;
2158 } flags;
2159
2160 atomic_t loop_state;
2161 #define LOOP_TIMEOUT 1
2162 #define LOOP_DOWN 2
2163 #define LOOP_UP 3
2164 #define LOOP_UPDATE 4
2165 #define LOOP_READY 5
2166 #define LOOP_DEAD 6
2167
2168 unsigned long dpc_flags;
2169 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2170 #define RESET_ACTIVE 1
2171 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2172 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2173 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2174 #define LOOP_RESYNC_ACTIVE 5
2175 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2176 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2177 #define MAILBOX_RETRY 8
2178 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2179 #define FAILOVER_EVENT_NEEDED 10
2180 #define FAILOVER_EVENT 11
2181 #define FAILOVER_NEEDED 12
2182 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2183 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2184 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2185 #define ABORT_QUEUES_NEEDED 16
2186 #define RELOGIN_NEEDED 17
2187 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2188 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2189 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2190 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2191 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2192 #define IOCTL_ERROR_RECOVERY 23
2193 #define LOOP_RESET_NEEDED 24
2194 #define BEACON_BLINK_NEEDED 25
2195 #define REGISTER_FDMI_NEEDED 26
2196 #define FCPORT_UPDATE_NEEDED 27
2197 #define VP_DPC_NEEDED 28 /* wake up for VP dpc handling */
2198
2199 uint32_t device_flags;
2200 #define DFLG_LOCAL_DEVICES BIT_0
2201 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2202 #define DFLG_FABRIC_DEVICES BIT_2
2203 #define SWITCH_FOUND BIT_3
2204 #define DFLG_NO_CABLE BIT_4
2205
2206 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2207 uint32_t device_type;
2208 #define DT_ISP2100 BIT_0
2209 #define DT_ISP2200 BIT_1
2210 #define DT_ISP2300 BIT_2
2211 #define DT_ISP2312 BIT_3
2212 #define DT_ISP2322 BIT_4
2213 #define DT_ISP6312 BIT_5
2214 #define DT_ISP6322 BIT_6
2215 #define DT_ISP2422 BIT_7
2216 #define DT_ISP2432 BIT_8
2217 #define DT_ISP5422 BIT_9
2218 #define DT_ISP5432 BIT_10
2219 #define DT_ISP2532 BIT_11
2220 #define DT_ISP_LAST (DT_ISP2532 << 1)
2221
2222 #define DT_IIDMA BIT_26
2223 #define DT_FWI2 BIT_27
2224 #define DT_ZIO_SUPPORTED BIT_28
2225 #define DT_OEM_001 BIT_29
2226 #define DT_ISP2200A BIT_30
2227 #define DT_EXTENDED_IDS BIT_31
2228
2229 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2230 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2231 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2232 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2233 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2234 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2235 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2236 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2237 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2238 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2239 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2240 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2241 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2242
2243 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2244 IS_QLA6312(ha) || IS_QLA6322(ha))
2245 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2246 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2247 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2248
2249 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2250 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2251 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2252 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2253 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2254
2255 /* SRB cache. */
2256 #define SRB_MIN_REQ 128
2257 mempool_t *srb_mempool;
2258
2259 /* This spinlock is used to protect "io transactions", you must
2260 * acquire it before doing any IO to the card, eg with RD_REG*() and
2261 * WRT_REG*() for the duration of your entire commandtransaction.
2262 *
2263 * This spinlock is of lower priority than the io request lock.
2264 */
2265
2266 spinlock_t hardware_lock ____cacheline_aligned;
2267
2268 int bars;
2269 int mem_only;
2270 device_reg_t __iomem *iobase; /* Base I/O address */
2271 resource_size_t pio_address;
2272 #define MIN_IOBASE_LEN 0x100
2273
2274 /* ISP ring lock, rings, and indexes */
2275 dma_addr_t request_dma; /* Physical address. */
2276 request_t *request_ring; /* Base virtual address */
2277 request_t *request_ring_ptr; /* Current address. */
2278 uint16_t req_ring_index; /* Current index. */
2279 uint16_t req_q_cnt; /* Number of available entries. */
2280 uint16_t request_q_length;
2281
2282 dma_addr_t response_dma; /* Physical address. */
2283 response_t *response_ring; /* Base virtual address */
2284 response_t *response_ring_ptr; /* Current address. */
2285 uint16_t rsp_ring_index; /* Current index. */
2286 uint16_t response_q_length;
2287
2288 struct isp_operations *isp_ops;
2289
2290 /* Outstandings ISP commands. */
2291 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2292 uint32_t current_outstanding_cmd;
2293 srb_t *status_srb; /* Status continuation entry. */
2294
2295 /* ISP configuration data. */
2296 uint16_t loop_id; /* Host adapter loop id */
2297 uint16_t switch_cap;
2298 #define FLOGI_SEQ_DEL BIT_8
2299 #define FLOGI_MID_SUPPORT BIT_10
2300 #define FLOGI_VSAN_SUPPORT BIT_12
2301 #define FLOGI_SP_SUPPORT BIT_13
2302 uint16_t fb_rev;
2303
2304 port_id_t d_id; /* Host adapter port id */
2305 uint16_t max_public_loop_ids;
2306 uint16_t min_external_loopid; /* First external loop Id */
2307
2308 #define PORT_SPEED_UNKNOWN 0xFFFF
2309 #define PORT_SPEED_1GB 0x00
2310 #define PORT_SPEED_2GB 0x01
2311 #define PORT_SPEED_4GB 0x03
2312 #define PORT_SPEED_8GB 0x04
2313 uint16_t link_data_rate; /* F/W operating speed */
2314
2315 uint8_t current_topology;
2316 uint8_t prev_topology;
2317 #define ISP_CFG_NL 1
2318 #define ISP_CFG_N 2
2319 #define ISP_CFG_FL 4
2320 #define ISP_CFG_F 8
2321
2322 uint8_t operating_mode; /* F/W operating mode */
2323 #define LOOP 0
2324 #define P2P 1
2325 #define LOOP_P2P 2
2326 #define P2P_LOOP 3
2327
2328 uint8_t marker_needed;
2329
2330 uint8_t interrupts_on;
2331
2332 /* HBA serial number */
2333 uint8_t serial0;
2334 uint8_t serial1;
2335 uint8_t serial2;
2336
2337 /* NVRAM configuration data */
2338 #define MAX_NVRAM_SIZE 4096
2339 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2340 uint16_t nvram_size;
2341 uint16_t nvram_base;
2342 void *nvram;
2343 uint16_t vpd_size;
2344 uint16_t vpd_base;
2345 void *vpd;
2346
2347 uint16_t loop_reset_delay;
2348 uint8_t retry_count;
2349 uint8_t login_timeout;
2350 uint16_t r_a_tov;
2351 int port_down_retry_count;
2352 uint8_t mbx_count;
2353 uint16_t last_loop_id;
2354 uint16_t mgmt_svr_loop_id;
2355
2356 uint32_t login_retry_count;
2357 int max_q_depth;
2358
2359 /* Fibre Channel Device List. */
2360 struct list_head fcports;
2361
2362 /* RSCN queue. */
2363 uint32_t rscn_queue[MAX_RSCN_COUNT];
2364 uint8_t rscn_in_ptr;
2365 uint8_t rscn_out_ptr;
2366
2367 /* SNS command interfaces. */
2368 ms_iocb_entry_t *ms_iocb;
2369 dma_addr_t ms_iocb_dma;
2370 struct ct_sns_pkt *ct_sns;
2371 dma_addr_t ct_sns_dma;
2372 /* SNS command interfaces for 2200. */
2373 struct sns_cmd_pkt *sns_cmd;
2374 dma_addr_t sns_cmd_dma;
2375
2376 #define SFP_DEV_SIZE 256
2377 #define SFP_BLOCK_SIZE 64
2378 void *sfp_data;
2379 dma_addr_t sfp_data_dma;
2380
2381 struct task_struct *dpc_thread;
2382 uint8_t dpc_active; /* DPC routine is active */
2383
2384 /* Timeout timers. */
2385 uint8_t loop_down_abort_time; /* port down timer */
2386 atomic_t loop_down_timer; /* loop down timer */
2387 uint8_t link_down_timeout; /* link down timeout */
2388
2389 uint32_t timer_active;
2390 struct timer_list timer;
2391
2392 dma_addr_t gid_list_dma;
2393 struct gid_list_info *gid_list;
2394 int gid_list_info_size;
2395
2396 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2397 #define DMA_POOL_SIZE 256
2398 struct dma_pool *s_dma_pool;
2399
2400 dma_addr_t init_cb_dma;
2401 init_cb_t *init_cb;
2402 int init_cb_size;
2403
2404 /* These are used by mailbox operations. */
2405 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2406
2407 mbx_cmd_t *mcp;
2408 unsigned long mbx_cmd_flags;
2409 #define MBX_INTERRUPT 1
2410 #define MBX_INTR_WAIT 2
2411 #define MBX_UPDATE_FLASH_ACTIVE 3
2412
2413 struct semaphore vport_sem; /* Virtual port synchronization */
2414 struct completion mbx_cmd_comp; /* Serialize mbx access */
2415 struct completion mbx_intr_comp; /* Used for completion notification */
2416
2417 uint32_t mbx_flags;
2418 #define MBX_IN_PROGRESS BIT_0
2419 #define MBX_BUSY BIT_1 /* Got the Access */
2420 #define MBX_SLEEPING_ON_SEM BIT_2
2421 #define MBX_POLLING_FOR_COMP BIT_3
2422 #define MBX_COMPLETED BIT_4
2423 #define MBX_TIMEDOUT BIT_5
2424 #define MBX_ACCESS_TIMEDOUT BIT_6
2425
2426 mbx_cmd_t mc;
2427
2428 /* Basic firmware related information. */
2429 uint16_t fw_major_version;
2430 uint16_t fw_minor_version;
2431 uint16_t fw_subminor_version;
2432 uint16_t fw_attributes;
2433 uint32_t fw_memory_size;
2434 uint32_t fw_transfer_size;
2435 uint32_t fw_srisc_address;
2436 #define RISC_START_ADDRESS_2100 0x1000
2437 #define RISC_START_ADDRESS_2300 0x800
2438 #define RISC_START_ADDRESS_2400 0x100000
2439
2440 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2441 uint8_t fw_seriallink_options[4];
2442 uint16_t fw_seriallink_options24[4];
2443
2444 /* Firmware dump information. */
2445 struct qla2xxx_fw_dump *fw_dump;
2446 uint32_t fw_dump_len;
2447 int fw_dumped;
2448 int fw_dump_reading;
2449 dma_addr_t eft_dma;
2450 void *eft;
2451
2452 struct dentry *dfs_dir;
2453 struct dentry *dfs_fce;
2454 dma_addr_t fce_dma;
2455 void *fce;
2456 uint32_t fce_bufs;
2457 uint16_t fce_mb[8];
2458 uint64_t fce_wr, fce_rd;
2459 struct mutex fce_mutex;
2460
2461 uint8_t host_str[16];
2462 uint32_t pci_attr;
2463 uint16_t chip_revision;
2464
2465 uint16_t product_id[4];
2466
2467 uint8_t model_number[16+1];
2468 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2469 char *model_desc;
2470 uint8_t adapter_id[16+1];
2471
2472 uint8_t *node_name;
2473 uint8_t *port_name;
2474 uint8_t fabric_node_name[WWN_SIZE];
2475 uint32_t isp_abort_cnt;
2476
2477 /* Option ROM information. */
2478 char *optrom_buffer;
2479 uint32_t optrom_size;
2480 int optrom_state;
2481 #define QLA_SWAITING 0
2482 #define QLA_SREADING 1
2483 #define QLA_SWRITING 2
2484 uint32_t optrom_region_start;
2485 uint32_t optrom_region_size;
2486
2487 /* PCI expansion ROM image information. */
2488 #define ROM_CODE_TYPE_BIOS 0
2489 #define ROM_CODE_TYPE_FCODE 1
2490 #define ROM_CODE_TYPE_EFI 3
2491 uint8_t bios_revision[2];
2492 uint8_t efi_revision[2];
2493 uint8_t fcode_revision[16];
2494 uint32_t fw_revision[4];
2495
2496 /* Needed for BEACON */
2497 uint16_t beacon_blink_led;
2498 uint8_t beacon_color_state;
2499 #define QLA_LED_GRN_ON 0x01
2500 #define QLA_LED_YLW_ON 0x02
2501 #define QLA_LED_ABR_ON 0x04
2502 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2503 /* ISP2322: red, green, amber. */
2504
2505 uint16_t zio_mode;
2506 uint16_t zio_timer;
2507 struct fc_host_statistics fc_host_stat;
2508
2509 struct qla_msix_entry msix_entries[QLA_MSIX_ENTRIES];
2510
2511 struct list_head vp_list; /* list of VP */
2512 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2513 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / sizeof(unsigned long)];
2514 uint16_t num_vhosts; /* number of vports created */
2515 uint16_t num_vsans; /* number of vsan created */
2516 uint16_t vp_idx; /* vport ID */
2517
2518 struct scsi_qla_host *parent; /* holds pport */
2519 unsigned long vp_flags;
2520 struct list_head vp_fcports; /* list of fcports */
2521 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2522 #define VP_CREATE_NEEDED 1
2523 #define VP_BIND_NEEDED 2
2524 #define VP_DELETE_NEEDED 3
2525 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2526 atomic_t vp_state;
2527 #define VP_OFFLINE 0
2528 #define VP_ACTIVE 1
2529 #define VP_FAILED 2
2530 // #define VP_DISABLE 3
2531 uint16_t vp_err_state;
2532 uint16_t vp_prev_err_state;
2533 #define VP_ERR_UNKWN 0
2534 #define VP_ERR_PORTDWN 1
2535 #define VP_ERR_FAB_UNSUPPORTED 2
2536 #define VP_ERR_FAB_NORESOURCES 3
2537 #define VP_ERR_FAB_LOGOUT 4
2538 #define VP_ERR_ADAP_NORESOURCES 5
2539 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2540 int cur_vport_count;
2541 } scsi_qla_host_t;
2542
2543
2544 /*
2545 * Macros to help code, maintain, etc.
2546 */
2547 #define LOOP_TRANSITION(ha) \
2548 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2549 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2550 atomic_read(&ha->loop_state) == LOOP_DOWN)
2551
2552 #define qla_printk(level, ha, format, arg...) \
2553 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2554
2555 /*
2556 * qla2x00 local function return status codes
2557 */
2558 #define MBS_MASK 0x3fff
2559
2560 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2561 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2562 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2563 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2564 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2565 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2566 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2567 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2568 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2569 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2570
2571 #define QLA_FUNCTION_TIMEOUT 0x100
2572 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2573 #define QLA_FUNCTION_FAILED 0x102
2574 #define QLA_MEMORY_ALLOC_FAILED 0x103
2575 #define QLA_LOCK_TIMEOUT 0x104
2576 #define QLA_ABORTED 0x105
2577 #define QLA_SUSPENDED 0x106
2578 #define QLA_BUSY 0x107
2579 #define QLA_RSCNS_HANDLED 0x108
2580 #define QLA_ALREADY_REGISTERED 0x109
2581
2582 #define NVRAM_DELAY() udelay(10)
2583
2584 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2585
2586 /*
2587 * Flash support definitions
2588 */
2589 #define OPTROM_SIZE_2300 0x20000
2590 #define OPTROM_SIZE_2322 0x100000
2591 #define OPTROM_SIZE_24XX 0x100000
2592 #define OPTROM_SIZE_25XX 0x200000
2593
2594 #include "qla_gbl.h"
2595 #include "qla_dbg.h"
2596 #include "qla_inline.h"
2597
2598 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2599 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2600 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2601 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2602 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2603 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2604
2605 #endif
Linux with added FPC-III support