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iwlwifi: introduce host commands callbacks
[linux/fpc-iii.git] / drivers / usb / gadget / m66592-udc.c
blob835948f0715a9118f18e90a83fb2e2ff28161895
1 /*
2 * M66592 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <linux/platform_device.h>
28
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31
32 #include "m66592-udc.h"
33
34
35 MODULE_DESCRIPTION("M66592 USB gadget driver");
36 MODULE_LICENSE("GPL");
37 MODULE_AUTHOR("Yoshihiro Shimoda");
38
39 #define DRIVER_VERSION "18 Oct 2007"
40
41 /* module parameters */
42 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
43 static unsigned short endian = M66592_LITTLE;
44 module_param(endian, ushort, 0644);
45 MODULE_PARM_DESC(endian, "data endian: big=0, little=0 (default=0)");
46 #else
47 static unsigned short clock = M66592_XTAL24;
48 module_param(clock, ushort, 0644);
49 MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
50 "(default=16384)");
51
52 static unsigned short vif = M66592_LDRV;
53 module_param(vif, ushort, 0644);
54 MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
55
56 static unsigned short endian;
57 module_param(endian, ushort, 0644);
58 MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
59
60 static unsigned short irq_sense = M66592_INTL;
61 module_param(irq_sense, ushort, 0644);
62 MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
63 "(default=2)");
64 #endif
65
66 static const char udc_name[] = "m66592_udc";
67 static const char *m66592_ep_name[] = {
68 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
69 };
70
71 static void disable_controller(struct m66592 *m66592);
72 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
73 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
74 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
75 gfp_t gfp_flags);
76
77 static void transfer_complete(struct m66592_ep *ep,
78 struct m66592_request *req, int status);
79
80 /*-------------------------------------------------------------------------*/
81 static inline u16 get_usb_speed(struct m66592 *m66592)
82 {
83 return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
84 }
85
86 static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
87 unsigned long reg)
88 {
89 u16 tmp;
90
91 tmp = m66592_read(m66592, M66592_INTENB0);
92 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
93 M66592_INTENB0);
94 m66592_bset(m66592, (1 << pipenum), reg);
95 m66592_write(m66592, tmp, M66592_INTENB0);
96 }
97
98 static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
99 unsigned long reg)
100 {
101 u16 tmp;
102
103 tmp = m66592_read(m66592, M66592_INTENB0);
104 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
105 M66592_INTENB0);
106 m66592_bclr(m66592, (1 << pipenum), reg);
107 m66592_write(m66592, tmp, M66592_INTENB0);
108 }
109
110 static void m66592_usb_connect(struct m66592 *m66592)
111 {
112 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
113 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
114 M66592_INTENB0);
115 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
116
117 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
118 }
119
120 static void m66592_usb_disconnect(struct m66592 *m66592)
121 __releases(m66592->lock)
122 __acquires(m66592->lock)
123 {
124 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
125 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
126 M66592_INTENB0);
127 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
128 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
129
130 m66592->gadget.speed = USB_SPEED_UNKNOWN;
131 spin_unlock(&m66592->lock);
132 m66592->driver->disconnect(&m66592->gadget);
133 spin_lock(&m66592->lock);
134
135 disable_controller(m66592);
136 INIT_LIST_HEAD(&m66592->ep[0].queue);
137 }
138
139 static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
140 {
141 u16 pid = 0;
142 unsigned long offset;
143
144 if (pipenum == 0)
145 pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
146 else if (pipenum < M66592_MAX_NUM_PIPE) {
147 offset = get_pipectr_addr(pipenum);
148 pid = m66592_read(m66592, offset) & M66592_PID;
149 } else
150 pr_err("unexpect pipe num (%d)\n", pipenum);
151
152 return pid;
153 }
154
155 static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
156 u16 pid)
157 {
158 unsigned long offset;
159
160 if (pipenum == 0)
161 m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
162 else if (pipenum < M66592_MAX_NUM_PIPE) {
163 offset = get_pipectr_addr(pipenum);
164 m66592_mdfy(m66592, pid, M66592_PID, offset);
165 } else
166 pr_err("unexpect pipe num (%d)\n", pipenum);
167 }
168
169 static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
170 {
171 control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
172 }
173
174 static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
175 {
176 control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
177 }
178
179 static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
180 {
181 control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
182 }
183
184 static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
185 {
186 u16 ret = 0;
187 unsigned long offset;
188
189 if (pipenum == 0)
190 ret = m66592_read(m66592, M66592_DCPCTR);
191 else if (pipenum < M66592_MAX_NUM_PIPE) {
192 offset = get_pipectr_addr(pipenum);
193 ret = m66592_read(m66592, offset);
194 } else
195 pr_err("unexpect pipe num (%d)\n", pipenum);
196
197 return ret;
198 }
199
200 static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
201 {
202 unsigned long offset;
203
204 pipe_stop(m66592, pipenum);
205
206 if (pipenum == 0)
207 m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
208 else if (pipenum < M66592_MAX_NUM_PIPE) {
209 offset = get_pipectr_addr(pipenum);
210 m66592_bset(m66592, M66592_SQCLR, offset);
211 } else
212 pr_err("unexpect pipe num(%d)\n", pipenum);
213 }
214
215 static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
216 {
217 u16 tmp;
218 int size;
219
220 if (pipenum == 0) {
221 tmp = m66592_read(m66592, M66592_DCPCFG);
222 if ((tmp & M66592_CNTMD) != 0)
223 size = 256;
224 else {
225 tmp = m66592_read(m66592, M66592_DCPMAXP);
226 size = tmp & M66592_MAXP;
227 }
228 } else {
229 m66592_write(m66592, pipenum, M66592_PIPESEL);
230 tmp = m66592_read(m66592, M66592_PIPECFG);
231 if ((tmp & M66592_CNTMD) != 0) {
232 tmp = m66592_read(m66592, M66592_PIPEBUF);
233 size = ((tmp >> 10) + 1) * 64;
234 } else {
235 tmp = m66592_read(m66592, M66592_PIPEMAXP);
236 size = tmp & M66592_MXPS;
237 }
238 }
239
240 return size;
241 }
242
243 static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
244 {
245 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
246
247 if (ep->use_dma)
248 return;
249
250 m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
251
252 ndelay(450);
253
254 m66592_bset(m66592, M66592_MBW, ep->fifosel);
255 }
256
257 static int pipe_buffer_setting(struct m66592 *m66592,
258 struct m66592_pipe_info *info)
259 {
260 u16 bufnum = 0, buf_bsize = 0;
261 u16 pipecfg = 0;
262
263 if (info->pipe == 0)
264 return -EINVAL;
265
266 m66592_write(m66592, info->pipe, M66592_PIPESEL);
267
268 if (info->dir_in)
269 pipecfg |= M66592_DIR;
270 pipecfg |= info->type;
271 pipecfg |= info->epnum;
272 switch (info->type) {
273 case M66592_INT:
274 bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
275 buf_bsize = 0;
276 break;
277 case M66592_BULK:
278 bufnum = m66592->bi_bufnum +
279 (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
280 m66592->bi_bufnum += 16;
281 buf_bsize = 7;
282 pipecfg |= M66592_DBLB;
283 if (!info->dir_in)
284 pipecfg |= M66592_SHTNAK;
285 break;
286 case M66592_ISO:
287 bufnum = m66592->bi_bufnum +
288 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
289 m66592->bi_bufnum += 16;
290 buf_bsize = 7;
291 break;
292 }
293 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
294 pr_err("m66592 pipe memory is insufficient(%d)\n",
295 m66592->bi_bufnum);
296 return -ENOMEM;
297 }
298
299 m66592_write(m66592, pipecfg, M66592_PIPECFG);
300 m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
301 m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
302 if (info->interval)
303 info->interval--;
304 m66592_write(m66592, info->interval, M66592_PIPEPERI);
305
306 return 0;
307 }
308
309 static void pipe_buffer_release(struct m66592 *m66592,
310 struct m66592_pipe_info *info)
311 {
312 if (info->pipe == 0)
313 return;
314
315 switch (info->type) {
316 case M66592_BULK:
317 if (is_bulk_pipe(info->pipe))
318 m66592->bi_bufnum -= 16;
319 break;
320 case M66592_ISO:
321 if (is_isoc_pipe(info->pipe))
322 m66592->bi_bufnum -= 16;
323 break;
324 }
325
326 if (is_bulk_pipe(info->pipe)) {
327 m66592->bulk--;
328 } else if (is_interrupt_pipe(info->pipe))
329 m66592->interrupt--;
330 else if (is_isoc_pipe(info->pipe)) {
331 m66592->isochronous--;
332 if (info->type == M66592_BULK)
333 m66592->bulk--;
334 } else
335 pr_err("ep_release: unexpect pipenum (%d)\n",
336 info->pipe);
337 }
338
339 static void pipe_initialize(struct m66592_ep *ep)
340 {
341 struct m66592 *m66592 = ep->m66592;
342
343 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
344
345 m66592_write(m66592, M66592_ACLRM, ep->pipectr);
346 m66592_write(m66592, 0, ep->pipectr);
347 m66592_write(m66592, M66592_SQCLR, ep->pipectr);
348 if (ep->use_dma) {
349 m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
350
351 ndelay(450);
352
353 m66592_bset(m66592, M66592_MBW, ep->fifosel);
354 }
355 }
356
357 static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
358 const struct usb_endpoint_descriptor *desc,
359 u16 pipenum, int dma)
360 {
361 if ((pipenum != 0) && dma) {
362 if (m66592->num_dma == 0) {
363 m66592->num_dma++;
364 ep->use_dma = 1;
365 ep->fifoaddr = M66592_D0FIFO;
366 ep->fifosel = M66592_D0FIFOSEL;
367 ep->fifoctr = M66592_D0FIFOCTR;
368 ep->fifotrn = M66592_D0FIFOTRN;
369 #if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
370 } else if (m66592->num_dma == 1) {
371 m66592->num_dma++;
372 ep->use_dma = 1;
373 ep->fifoaddr = M66592_D1FIFO;
374 ep->fifosel = M66592_D1FIFOSEL;
375 ep->fifoctr = M66592_D1FIFOCTR;
376 ep->fifotrn = M66592_D1FIFOTRN;
377 #endif
378 } else {
379 ep->use_dma = 0;
380 ep->fifoaddr = M66592_CFIFO;
381 ep->fifosel = M66592_CFIFOSEL;
382 ep->fifoctr = M66592_CFIFOCTR;
383 ep->fifotrn = 0;
384 }
385 } else {
386 ep->use_dma = 0;
387 ep->fifoaddr = M66592_CFIFO;
388 ep->fifosel = M66592_CFIFOSEL;
389 ep->fifoctr = M66592_CFIFOCTR;
390 ep->fifotrn = 0;
391 }
392
393 ep->pipectr = get_pipectr_addr(pipenum);
394 ep->pipenum = pipenum;
395 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
396 m66592->pipenum2ep[pipenum] = ep;
397 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
398 INIT_LIST_HEAD(&ep->queue);
399 }
400
401 static void m66592_ep_release(struct m66592_ep *ep)
402 {
403 struct m66592 *m66592 = ep->m66592;
404 u16 pipenum = ep->pipenum;
405
406 if (pipenum == 0)
407 return;
408
409 if (ep->use_dma)
410 m66592->num_dma--;
411 ep->pipenum = 0;
412 ep->busy = 0;
413 ep->use_dma = 0;
414 }
415
416 static int alloc_pipe_config(struct m66592_ep *ep,
417 const struct usb_endpoint_descriptor *desc)
418 {
419 struct m66592 *m66592 = ep->m66592;
420 struct m66592_pipe_info info;
421 int dma = 0;
422 int *counter;
423 int ret;
424
425 ep->desc = desc;
426
427 BUG_ON(ep->pipenum);
428
429 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
430 case USB_ENDPOINT_XFER_BULK:
431 if (m66592->bulk >= M66592_MAX_NUM_BULK) {
432 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
433 pr_err("bulk pipe is insufficient\n");
434 return -ENODEV;
435 } else {
436 info.pipe = M66592_BASE_PIPENUM_ISOC
437 + m66592->isochronous;
438 counter = &m66592->isochronous;
439 }
440 } else {
441 info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
442 counter = &m66592->bulk;
443 }
444 info.type = M66592_BULK;
445 dma = 1;
446 break;
447 case USB_ENDPOINT_XFER_INT:
448 if (m66592->interrupt >= M66592_MAX_NUM_INT) {
449 pr_err("interrupt pipe is insufficient\n");
450 return -ENODEV;
451 }
452 info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
453 info.type = M66592_INT;
454 counter = &m66592->interrupt;
455 break;
456 case USB_ENDPOINT_XFER_ISOC:
457 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
458 pr_err("isochronous pipe is insufficient\n");
459 return -ENODEV;
460 }
461 info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
462 info.type = M66592_ISO;
463 counter = &m66592->isochronous;
464 break;
465 default:
466 pr_err("unexpect xfer type\n");
467 return -EINVAL;
468 }
469 ep->type = info.type;
470
471 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
472 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
473 info.interval = desc->bInterval;
474 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
475 info.dir_in = 1;
476 else
477 info.dir_in = 0;
478
479 ret = pipe_buffer_setting(m66592, &info);
480 if (ret < 0) {
481 pr_err("pipe_buffer_setting fail\n");
482 return ret;
483 }
484
485 (*counter)++;
486 if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
487 m66592->bulk++;
488
489 m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
490 pipe_initialize(ep);
491
492 return 0;
493 }
494
495 static int free_pipe_config(struct m66592_ep *ep)
496 {
497 struct m66592 *m66592 = ep->m66592;
498 struct m66592_pipe_info info;
499
500 info.pipe = ep->pipenum;
501 info.type = ep->type;
502 pipe_buffer_release(m66592, &info);
503 m66592_ep_release(ep);
504
505 return 0;
506 }
507
508 /*-------------------------------------------------------------------------*/
509 static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
510 {
511 enable_irq_ready(m66592, pipenum);
512 enable_irq_nrdy(m66592, pipenum);
513 }
514
515 static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
516 {
517 disable_irq_ready(m66592, pipenum);
518 disable_irq_nrdy(m66592, pipenum);
519 }
520
521 /* if complete is true, gadget driver complete function is not call */
522 static void control_end(struct m66592 *m66592, unsigned ccpl)
523 {
524 m66592->ep[0].internal_ccpl = ccpl;
525 pipe_start(m66592, 0);
526 m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
527 }
528
529 static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
530 {
531 struct m66592 *m66592 = ep->m66592;
532
533 pipe_change(m66592, ep->pipenum);
534 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
535 (M66592_ISEL | M66592_CURPIPE),
536 M66592_CFIFOSEL);
537 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
538 if (req->req.length == 0) {
539 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
540 pipe_start(m66592, 0);
541 transfer_complete(ep, req, 0);
542 } else {
543 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
544 irq_ep0_write(ep, req);
545 }
546 }
547
548 static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
549 {
550 struct m66592 *m66592 = ep->m66592;
551 u16 tmp;
552
553 pipe_change(m66592, ep->pipenum);
554 disable_irq_empty(m66592, ep->pipenum);
555 pipe_start(m66592, ep->pipenum);
556
557 tmp = m66592_read(m66592, ep->fifoctr);
558 if (unlikely((tmp & M66592_FRDY) == 0))
559 pipe_irq_enable(m66592, ep->pipenum);
560 else
561 irq_packet_write(ep, req);
562 }
563
564 static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
565 {
566 struct m66592 *m66592 = ep->m66592;
567 u16 pipenum = ep->pipenum;
568
569 if (ep->pipenum == 0) {
570 m66592_mdfy(m66592, M66592_PIPE0,
571 (M66592_ISEL | M66592_CURPIPE),
572 M66592_CFIFOSEL);
573 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
574 pipe_start(m66592, pipenum);
575 pipe_irq_enable(m66592, pipenum);
576 } else {
577 if (ep->use_dma) {
578 m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
579 pipe_change(m66592, pipenum);
580 m66592_bset(m66592, M66592_TRENB, ep->fifosel);
581 m66592_write(m66592,
582 (req->req.length + ep->ep.maxpacket - 1)
583 / ep->ep.maxpacket,
584 ep->fifotrn);
585 }
586 pipe_start(m66592, pipenum); /* trigger once */
587 pipe_irq_enable(m66592, pipenum);
588 }
589 }
590
591 static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
592 {
593 if (ep->desc->bEndpointAddress & USB_DIR_IN)
594 start_packet_write(ep, req);
595 else
596 start_packet_read(ep, req);
597 }
598
599 static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
600 {
601 u16 ctsq;
602
603 ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
604
605 switch (ctsq) {
606 case M66592_CS_RDDS:
607 start_ep0_write(ep, req);
608 break;
609 case M66592_CS_WRDS:
610 start_packet_read(ep, req);
611 break;
612
613 case M66592_CS_WRND:
614 control_end(ep->m66592, 0);
615 break;
616 default:
617 pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
618 break;
619 }
620 }
621
622 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
623 static void init_controller(struct m66592 *m66592)
624 {
625 usbf_start_clock();
626 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
627 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
628 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
629 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
630
631 /* This is a workaound for SH7722 2nd cut */
632 m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
633 m66592_bset(m66592, 0x1000, M66592_TESTMODE);
634 m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
635
636 m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
637
638 m66592_write(m66592, 0, M66592_CFBCFG);
639 m66592_write(m66592, 0, M66592_D0FBCFG);
640 m66592_bset(m66592, endian, M66592_CFBCFG);
641 m66592_bset(m66592, endian, M66592_D0FBCFG);
642 }
643 #else /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
644 static void init_controller(struct m66592 *m66592)
645 {
646 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
647 M66592_PINCFG);
648 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
649 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
650
651 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
652 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
653 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
654
655 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
656
657 msleep(3);
658
659 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
660
661 msleep(1);
662
663 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
664
665 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
666 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
667 M66592_DMA0CFG);
668 }
669 #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
670
671 static void disable_controller(struct m66592 *m66592)
672 {
673 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
674 usbf_stop_clock();
675 #else
676 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
677 udelay(1);
678 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
679 udelay(1);
680 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
681 udelay(1);
682 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
683 #endif
684 }
685
686 static void m66592_start_xclock(struct m66592 *m66592)
687 {
688 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
689 usbf_start_clock();
690 #else
691 u16 tmp;
692
693 tmp = m66592_read(m66592, M66592_SYSCFG);
694 if (!(tmp & M66592_XCKE))
695 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
696 #endif
697 }
698
699 /*-------------------------------------------------------------------------*/
700 static void transfer_complete(struct m66592_ep *ep,
701 struct m66592_request *req, int status)
702 __releases(m66592->lock)
703 __acquires(m66592->lock)
704 {
705 int restart = 0;
706
707 if (unlikely(ep->pipenum == 0)) {
708 if (ep->internal_ccpl) {
709 ep->internal_ccpl = 0;
710 return;
711 }
712 }
713
714 list_del_init(&req->queue);
715 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
716 req->req.status = -ESHUTDOWN;
717 else
718 req->req.status = status;
719
720 if (!list_empty(&ep->queue))
721 restart = 1;
722
723 spin_unlock(&ep->m66592->lock);
724 req->req.complete(&ep->ep, &req->req);
725 spin_lock(&ep->m66592->lock);
726
727 if (restart) {
728 req = list_entry(ep->queue.next, struct m66592_request, queue);
729 if (ep->desc)
730 start_packet(ep, req);
731 }
732 }
733
734 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
735 {
736 int i;
737 u16 tmp;
738 unsigned bufsize;
739 size_t size;
740 void *buf;
741 u16 pipenum = ep->pipenum;
742 struct m66592 *m66592 = ep->m66592;
743
744 pipe_change(m66592, pipenum);
745 m66592_bset(m66592, M66592_ISEL, ep->fifosel);
746
747 i = 0;
748 do {
749 tmp = m66592_read(m66592, ep->fifoctr);
750 if (i++ > 100000) {
751 pr_err("pipe0 is busy. maybe cpu i/o bus "
752 "conflict. please power off this controller.");
753 return;
754 }
755 ndelay(1);
756 } while ((tmp & M66592_FRDY) == 0);
757
758 /* prepare parameters */
759 bufsize = get_buffer_size(m66592, pipenum);
760 buf = req->req.buf + req->req.actual;
761 size = min(bufsize, req->req.length - req->req.actual);
762
763 /* write fifo */
764 if (req->req.buf) {
765 if (size > 0)
766 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
767 if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
768 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
769 }
770
771 /* update parameters */
772 req->req.actual += size;
773
774 /* check transfer finish */
775 if ((!req->req.zero && (req->req.actual == req->req.length))
776 || (size % ep->ep.maxpacket)
777 || (size == 0)) {
778 disable_irq_ready(m66592, pipenum);
779 disable_irq_empty(m66592, pipenum);
780 } else {
781 disable_irq_ready(m66592, pipenum);
782 enable_irq_empty(m66592, pipenum);
783 }
784 pipe_start(m66592, pipenum);
785 }
786
787 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
788 {
789 u16 tmp;
790 unsigned bufsize;
791 size_t size;
792 void *buf;
793 u16 pipenum = ep->pipenum;
794 struct m66592 *m66592 = ep->m66592;
795
796 pipe_change(m66592, pipenum);
797 tmp = m66592_read(m66592, ep->fifoctr);
798 if (unlikely((tmp & M66592_FRDY) == 0)) {
799 pipe_stop(m66592, pipenum);
800 pipe_irq_disable(m66592, pipenum);
801 pr_err("write fifo not ready. pipnum=%d\n", pipenum);
802 return;
803 }
804
805 /* prepare parameters */
806 bufsize = get_buffer_size(m66592, pipenum);
807 buf = req->req.buf + req->req.actual;
808 size = min(bufsize, req->req.length - req->req.actual);
809
810 /* write fifo */
811 if (req->req.buf) {
812 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
813 if ((size == 0)
814 || ((size % ep->ep.maxpacket) != 0)
815 || ((bufsize != ep->ep.maxpacket)
816 && (bufsize > size)))
817 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
818 }
819
820 /* update parameters */
821 req->req.actual += size;
822 /* check transfer finish */
823 if ((!req->req.zero && (req->req.actual == req->req.length))
824 || (size % ep->ep.maxpacket)
825 || (size == 0)) {
826 disable_irq_ready(m66592, pipenum);
827 enable_irq_empty(m66592, pipenum);
828 } else {
829 disable_irq_empty(m66592, pipenum);
830 pipe_irq_enable(m66592, pipenum);
831 }
832 }
833
834 static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
835 {
836 u16 tmp;
837 int rcv_len, bufsize, req_len;
838 int size;
839 void *buf;
840 u16 pipenum = ep->pipenum;
841 struct m66592 *m66592 = ep->m66592;
842 int finish = 0;
843
844 pipe_change(m66592, pipenum);
845 tmp = m66592_read(m66592, ep->fifoctr);
846 if (unlikely((tmp & M66592_FRDY) == 0)) {
847 req->req.status = -EPIPE;
848 pipe_stop(m66592, pipenum);
849 pipe_irq_disable(m66592, pipenum);
850 pr_err("read fifo not ready");
851 return;
852 }
853
854 /* prepare parameters */
855 rcv_len = tmp & M66592_DTLN;
856 bufsize = get_buffer_size(m66592, pipenum);
857
858 buf = req->req.buf + req->req.actual;
859 req_len = req->req.length - req->req.actual;
860 if (rcv_len < bufsize)
861 size = min(rcv_len, req_len);
862 else
863 size = min(bufsize, req_len);
864
865 /* update parameters */
866 req->req.actual += size;
867
868 /* check transfer finish */
869 if ((!req->req.zero && (req->req.actual == req->req.length))
870 || (size % ep->ep.maxpacket)
871 || (size == 0)) {
872 pipe_stop(m66592, pipenum);
873 pipe_irq_disable(m66592, pipenum);
874 finish = 1;
875 }
876
877 /* read fifo */
878 if (req->req.buf) {
879 if (size == 0)
880 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
881 else
882 m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
883 }
884
885 if ((ep->pipenum != 0) && finish)
886 transfer_complete(ep, req, 0);
887 }
888
889 static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
890 {
891 u16 check;
892 u16 pipenum;
893 struct m66592_ep *ep;
894 struct m66592_request *req;
895
896 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
897 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
898 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
899 M66592_CFIFOSEL);
900
901 ep = &m66592->ep[0];
902 req = list_entry(ep->queue.next, struct m66592_request, queue);
903 irq_packet_read(ep, req);
904 } else {
905 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
906 check = 1 << pipenum;
907 if ((status & check) && (enb & check)) {
908 m66592_write(m66592, ~check, M66592_BRDYSTS);
909 ep = m66592->pipenum2ep[pipenum];
910 req = list_entry(ep->queue.next,
911 struct m66592_request, queue);
912 if (ep->desc->bEndpointAddress & USB_DIR_IN)
913 irq_packet_write(ep, req);
914 else
915 irq_packet_read(ep, req);
916 }
917 }
918 }
919 }
920
921 static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
922 {
923 u16 tmp;
924 u16 check;
925 u16 pipenum;
926 struct m66592_ep *ep;
927 struct m66592_request *req;
928
929 if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
930 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
931
932 ep = &m66592->ep[0];
933 req = list_entry(ep->queue.next, struct m66592_request, queue);
934 irq_ep0_write(ep, req);
935 } else {
936 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
937 check = 1 << pipenum;
938 if ((status & check) && (enb & check)) {
939 m66592_write(m66592, ~check, M66592_BEMPSTS);
940 tmp = control_reg_get(m66592, pipenum);
941 if ((tmp & M66592_INBUFM) == 0) {
942 disable_irq_empty(m66592, pipenum);
943 pipe_irq_disable(m66592, pipenum);
944 pipe_stop(m66592, pipenum);
945 ep = m66592->pipenum2ep[pipenum];
946 req = list_entry(ep->queue.next,
947 struct m66592_request,
948 queue);
949 if (!list_empty(&ep->queue))
950 transfer_complete(ep, req, 0);
951 }
952 }
953 }
954 }
955 }
956
957 static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
958 __releases(m66592->lock)
959 __acquires(m66592->lock)
960 {
961 struct m66592_ep *ep;
962 u16 pid;
963 u16 status = 0;
964 u16 w_index = le16_to_cpu(ctrl->wIndex);
965
966 switch (ctrl->bRequestType & USB_RECIP_MASK) {
967 case USB_RECIP_DEVICE:
968 status = 1 << USB_DEVICE_SELF_POWERED;
969 break;
970 case USB_RECIP_INTERFACE:
971 status = 0;
972 break;
973 case USB_RECIP_ENDPOINT:
974 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
975 pid = control_reg_get_pid(m66592, ep->pipenum);
976 if (pid == M66592_PID_STALL)
977 status = 1 << USB_ENDPOINT_HALT;
978 else
979 status = 0;
980 break;
981 default:
982 pipe_stall(m66592, 0);
983 return; /* exit */
984 }
985
986 m66592->ep0_data = cpu_to_le16(status);
987 m66592->ep0_req->buf = &m66592->ep0_data;
988 m66592->ep0_req->length = 2;
989 /* AV: what happens if we get called again before that gets through? */
990 spin_unlock(&m66592->lock);
991 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
992 spin_lock(&m66592->lock);
993 }
994
995 static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
996 {
997 switch (ctrl->bRequestType & USB_RECIP_MASK) {
998 case USB_RECIP_DEVICE:
999 control_end(m66592, 1);
1000 break;
1001 case USB_RECIP_INTERFACE:
1002 control_end(m66592, 1);
1003 break;
1004 case USB_RECIP_ENDPOINT: {
1005 struct m66592_ep *ep;
1006 struct m66592_request *req;
1007 u16 w_index = le16_to_cpu(ctrl->wIndex);
1008
1009 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1010 pipe_stop(m66592, ep->pipenum);
1011 control_reg_sqclr(m66592, ep->pipenum);
1012
1013 control_end(m66592, 1);
1014
1015 req = list_entry(ep->queue.next,
1016 struct m66592_request, queue);
1017 if (ep->busy) {
1018 ep->busy = 0;
1019 if (list_empty(&ep->queue))
1020 break;
1021 start_packet(ep, req);
1022 } else if (!list_empty(&ep->queue))
1023 pipe_start(m66592, ep->pipenum);
1024 }
1025 break;
1026 default:
1027 pipe_stall(m66592, 0);
1028 break;
1029 }
1030 }
1031
1032 static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1033 {
1034
1035 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1036 case USB_RECIP_DEVICE:
1037 control_end(m66592, 1);
1038 break;
1039 case USB_RECIP_INTERFACE:
1040 control_end(m66592, 1);
1041 break;
1042 case USB_RECIP_ENDPOINT: {
1043 struct m66592_ep *ep;
1044 u16 w_index = le16_to_cpu(ctrl->wIndex);
1045
1046 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1047 pipe_stall(m66592, ep->pipenum);
1048
1049 control_end(m66592, 1);
1050 }
1051 break;
1052 default:
1053 pipe_stall(m66592, 0);
1054 break;
1055 }
1056 }
1057
1058 /* if return value is true, call class driver's setup() */
1059 static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1060 {
1061 u16 *p = (u16 *)ctrl;
1062 unsigned long offset = M66592_USBREQ;
1063 int i, ret = 0;
1064
1065 /* read fifo */
1066 m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1067
1068 for (i = 0; i < 4; i++)
1069 p[i] = m66592_read(m66592, offset + i*2);
1070
1071 /* check request */
1072 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1073 switch (ctrl->bRequest) {
1074 case USB_REQ_GET_STATUS:
1075 get_status(m66592, ctrl);
1076 break;
1077 case USB_REQ_CLEAR_FEATURE:
1078 clear_feature(m66592, ctrl);
1079 break;
1080 case USB_REQ_SET_FEATURE:
1081 set_feature(m66592, ctrl);
1082 break;
1083 default:
1084 ret = 1;
1085 break;
1086 }
1087 } else
1088 ret = 1;
1089 return ret;
1090 }
1091
1092 static void m66592_update_usb_speed(struct m66592 *m66592)
1093 {
1094 u16 speed = get_usb_speed(m66592);
1095
1096 switch (speed) {
1097 case M66592_HSMODE:
1098 m66592->gadget.speed = USB_SPEED_HIGH;
1099 break;
1100 case M66592_FSMODE:
1101 m66592->gadget.speed = USB_SPEED_FULL;
1102 break;
1103 default:
1104 m66592->gadget.speed = USB_SPEED_UNKNOWN;
1105 pr_err("USB speed unknown\n");
1106 }
1107 }
1108
1109 static void irq_device_state(struct m66592 *m66592)
1110 {
1111 u16 dvsq;
1112
1113 dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1114 m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1115
1116 if (dvsq == M66592_DS_DFLT) { /* bus reset */
1117 m66592->driver->disconnect(&m66592->gadget);
1118 m66592_update_usb_speed(m66592);
1119 }
1120 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1121 m66592_update_usb_speed(m66592);
1122 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1123 && m66592->gadget.speed == USB_SPEED_UNKNOWN)
1124 m66592_update_usb_speed(m66592);
1125
1126 m66592->old_dvsq = dvsq;
1127 }
1128
1129 static void irq_control_stage(struct m66592 *m66592)
1130 __releases(m66592->lock)
1131 __acquires(m66592->lock)
1132 {
1133 struct usb_ctrlrequest ctrl;
1134 u16 ctsq;
1135
1136 ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1137 m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1138
1139 switch (ctsq) {
1140 case M66592_CS_IDST: {
1141 struct m66592_ep *ep;
1142 struct m66592_request *req;
1143 ep = &m66592->ep[0];
1144 req = list_entry(ep->queue.next, struct m66592_request, queue);
1145 transfer_complete(ep, req, 0);
1146 }
1147 break;
1148
1149 case M66592_CS_RDDS:
1150 case M66592_CS_WRDS:
1151 case M66592_CS_WRND:
1152 if (setup_packet(m66592, &ctrl)) {
1153 spin_unlock(&m66592->lock);
1154 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1155 pipe_stall(m66592, 0);
1156 spin_lock(&m66592->lock);
1157 }
1158 break;
1159 case M66592_CS_RDSS:
1160 case M66592_CS_WRSS:
1161 control_end(m66592, 0);
1162 break;
1163 default:
1164 pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1165 break;
1166 }
1167 }
1168
1169 static irqreturn_t m66592_irq(int irq, void *_m66592)
1170 {
1171 struct m66592 *m66592 = _m66592;
1172 u16 intsts0;
1173 u16 intenb0;
1174 u16 brdysts, nrdysts, bempsts;
1175 u16 brdyenb, nrdyenb, bempenb;
1176 u16 savepipe;
1177 u16 mask0;
1178
1179 spin_lock(&m66592->lock);
1180
1181 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1182 intenb0 = m66592_read(m66592, M66592_INTENB0);
1183
1184 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
1185 if (!intsts0 && !intenb0) {
1186 /*
1187 * When USB clock stops, it cannot read register. Even if a
1188 * clock stops, the interrupt occurs. So this driver turn on
1189 * a clock by this timing and do re-reading of register.
1190 */
1191 m66592_start_xclock(m66592);
1192 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1193 intenb0 = m66592_read(m66592, M66592_INTENB0);
1194 }
1195 #endif
1196
1197 savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1198
1199 mask0 = intsts0 & intenb0;
1200 if (mask0) {
1201 brdysts = m66592_read(m66592, M66592_BRDYSTS);
1202 nrdysts = m66592_read(m66592, M66592_NRDYSTS);
1203 bempsts = m66592_read(m66592, M66592_BEMPSTS);
1204 brdyenb = m66592_read(m66592, M66592_BRDYENB);
1205 nrdyenb = m66592_read(m66592, M66592_NRDYENB);
1206 bempenb = m66592_read(m66592, M66592_BEMPENB);
1207
1208 if (mask0 & M66592_VBINT) {
1209 m66592_write(m66592, 0xffff & ~M66592_VBINT,
1210 M66592_INTSTS0);
1211 m66592_start_xclock(m66592);
1212
1213 /* start vbus sampling */
1214 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1215 & M66592_VBSTS;
1216 m66592->scount = M66592_MAX_SAMPLING;
1217
1218 mod_timer(&m66592->timer,
1219 jiffies + msecs_to_jiffies(50));
1220 }
1221 if (intsts0 & M66592_DVSQ)
1222 irq_device_state(m66592);
1223
1224 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1225 && (brdysts & brdyenb)) {
1226 irq_pipe_ready(m66592, brdysts, brdyenb);
1227 }
1228 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1229 && (bempsts & bempenb)) {
1230 irq_pipe_empty(m66592, bempsts, bempenb);
1231 }
1232
1233 if (intsts0 & M66592_CTRT)
1234 irq_control_stage(m66592);
1235 }
1236
1237 m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1238
1239 spin_unlock(&m66592->lock);
1240 return IRQ_HANDLED;
1241 }
1242
1243 static void m66592_timer(unsigned long _m66592)
1244 {
1245 struct m66592 *m66592 = (struct m66592 *)_m66592;
1246 unsigned long flags;
1247 u16 tmp;
1248
1249 spin_lock_irqsave(&m66592->lock, flags);
1250 tmp = m66592_read(m66592, M66592_SYSCFG);
1251 if (!(tmp & M66592_RCKE)) {
1252 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1253 udelay(10);
1254 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1255 }
1256 if (m66592->scount > 0) {
1257 tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1258 if (tmp == m66592->old_vbus) {
1259 m66592->scount--;
1260 if (m66592->scount == 0) {
1261 if (tmp == M66592_VBSTS)
1262 m66592_usb_connect(m66592);
1263 else
1264 m66592_usb_disconnect(m66592);
1265 } else {
1266 mod_timer(&m66592->timer,
1267 jiffies + msecs_to_jiffies(50));
1268 }
1269 } else {
1270 m66592->scount = M66592_MAX_SAMPLING;
1271 m66592->old_vbus = tmp;
1272 mod_timer(&m66592->timer,
1273 jiffies + msecs_to_jiffies(50));
1274 }
1275 }
1276 spin_unlock_irqrestore(&m66592->lock, flags);
1277 }
1278
1279 /*-------------------------------------------------------------------------*/
1280 static int m66592_enable(struct usb_ep *_ep,
1281 const struct usb_endpoint_descriptor *desc)
1282 {
1283 struct m66592_ep *ep;
1284
1285 ep = container_of(_ep, struct m66592_ep, ep);
1286 return alloc_pipe_config(ep, desc);
1287 }
1288
1289 static int m66592_disable(struct usb_ep *_ep)
1290 {
1291 struct m66592_ep *ep;
1292 struct m66592_request *req;
1293 unsigned long flags;
1294
1295 ep = container_of(_ep, struct m66592_ep, ep);
1296 BUG_ON(!ep);
1297
1298 while (!list_empty(&ep->queue)) {
1299 req = list_entry(ep->queue.next, struct m66592_request, queue);
1300 spin_lock_irqsave(&ep->m66592->lock, flags);
1301 transfer_complete(ep, req, -ECONNRESET);
1302 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1303 }
1304
1305 pipe_irq_disable(ep->m66592, ep->pipenum);
1306 return free_pipe_config(ep);
1307 }
1308
1309 static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1310 gfp_t gfp_flags)
1311 {
1312 struct m66592_request *req;
1313
1314 req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1315 if (!req)
1316 return NULL;
1317
1318 INIT_LIST_HEAD(&req->queue);
1319
1320 return &req->req;
1321 }
1322
1323 static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1324 {
1325 struct m66592_request *req;
1326
1327 req = container_of(_req, struct m66592_request, req);
1328 kfree(req);
1329 }
1330
1331 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1332 gfp_t gfp_flags)
1333 {
1334 struct m66592_ep *ep;
1335 struct m66592_request *req;
1336 unsigned long flags;
1337 int request = 0;
1338
1339 ep = container_of(_ep, struct m66592_ep, ep);
1340 req = container_of(_req, struct m66592_request, req);
1341
1342 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1343 return -ESHUTDOWN;
1344
1345 spin_lock_irqsave(&ep->m66592->lock, flags);
1346
1347 if (list_empty(&ep->queue))
1348 request = 1;
1349
1350 list_add_tail(&req->queue, &ep->queue);
1351 req->req.actual = 0;
1352 req->req.status = -EINPROGRESS;
1353
1354 if (ep->desc == NULL) /* control */
1355 start_ep0(ep, req);
1356 else {
1357 if (request && !ep->busy)
1358 start_packet(ep, req);
1359 }
1360
1361 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1362
1363 return 0;
1364 }
1365
1366 static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1367 {
1368 struct m66592_ep *ep;
1369 struct m66592_request *req;
1370 unsigned long flags;
1371
1372 ep = container_of(_ep, struct m66592_ep, ep);
1373 req = container_of(_req, struct m66592_request, req);
1374
1375 spin_lock_irqsave(&ep->m66592->lock, flags);
1376 if (!list_empty(&ep->queue))
1377 transfer_complete(ep, req, -ECONNRESET);
1378 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1379
1380 return 0;
1381 }
1382
1383 static int m66592_set_halt(struct usb_ep *_ep, int value)
1384 {
1385 struct m66592_ep *ep;
1386 struct m66592_request *req;
1387 unsigned long flags;
1388 int ret = 0;
1389
1390 ep = container_of(_ep, struct m66592_ep, ep);
1391 req = list_entry(ep->queue.next, struct m66592_request, queue);
1392
1393 spin_lock_irqsave(&ep->m66592->lock, flags);
1394 if (!list_empty(&ep->queue)) {
1395 ret = -EAGAIN;
1396 goto out;
1397 }
1398 if (value) {
1399 ep->busy = 1;
1400 pipe_stall(ep->m66592, ep->pipenum);
1401 } else {
1402 ep->busy = 0;
1403 pipe_stop(ep->m66592, ep->pipenum);
1404 }
1405
1406 out:
1407 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1408 return ret;
1409 }
1410
1411 static void m66592_fifo_flush(struct usb_ep *_ep)
1412 {
1413 struct m66592_ep *ep;
1414 unsigned long flags;
1415
1416 ep = container_of(_ep, struct m66592_ep, ep);
1417 spin_lock_irqsave(&ep->m66592->lock, flags);
1418 if (list_empty(&ep->queue) && !ep->busy) {
1419 pipe_stop(ep->m66592, ep->pipenum);
1420 m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1421 }
1422 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1423 }
1424
1425 static struct usb_ep_ops m66592_ep_ops = {
1426 .enable = m66592_enable,
1427 .disable = m66592_disable,
1428
1429 .alloc_request = m66592_alloc_request,
1430 .free_request = m66592_free_request,
1431
1432 .queue = m66592_queue,
1433 .dequeue = m66592_dequeue,
1434
1435 .set_halt = m66592_set_halt,
1436 .fifo_flush = m66592_fifo_flush,
1437 };
1438
1439 /*-------------------------------------------------------------------------*/
1440 static struct m66592 *the_controller;
1441
1442 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1443 {
1444 struct m66592 *m66592 = the_controller;
1445 int retval;
1446
1447 if (!driver
1448 || driver->speed != USB_SPEED_HIGH
1449 || !driver->bind
1450 || !driver->setup)
1451 return -EINVAL;
1452 if (!m66592)
1453 return -ENODEV;
1454 if (m66592->driver)
1455 return -EBUSY;
1456
1457 /* hook up the driver */
1458 driver->driver.bus = NULL;
1459 m66592->driver = driver;
1460 m66592->gadget.dev.driver = &driver->driver;
1461
1462 retval = device_add(&m66592->gadget.dev);
1463 if (retval) {
1464 pr_err("device_add error (%d)\n", retval);
1465 goto error;
1466 }
1467
1468 retval = driver->bind (&m66592->gadget);
1469 if (retval) {
1470 pr_err("bind to driver error (%d)\n", retval);
1471 device_del(&m66592->gadget.dev);
1472 goto error;
1473 }
1474
1475 m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1476 if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1477 m66592_start_xclock(m66592);
1478 /* start vbus sampling */
1479 m66592->old_vbus = m66592_read(m66592,
1480 M66592_INTSTS0) & M66592_VBSTS;
1481 m66592->scount = M66592_MAX_SAMPLING;
1482 mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1483 }
1484
1485 return 0;
1486
1487 error:
1488 m66592->driver = NULL;
1489 m66592->gadget.dev.driver = NULL;
1490
1491 return retval;
1492 }
1493 EXPORT_SYMBOL(usb_gadget_register_driver);
1494
1495 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1496 {
1497 struct m66592 *m66592 = the_controller;
1498 unsigned long flags;
1499
1500 if (driver != m66592->driver || !driver->unbind)
1501 return -EINVAL;
1502
1503 spin_lock_irqsave(&m66592->lock, flags);
1504 if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
1505 m66592_usb_disconnect(m66592);
1506 spin_unlock_irqrestore(&m66592->lock, flags);
1507
1508 m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1509
1510 driver->unbind(&m66592->gadget);
1511 m66592->gadget.dev.driver = NULL;
1512
1513 init_controller(m66592);
1514 disable_controller(m66592);
1515
1516 device_del(&m66592->gadget.dev);
1517 m66592->driver = NULL;
1518 return 0;
1519 }
1520 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1521
1522 /*-------------------------------------------------------------------------*/
1523 static int m66592_get_frame(struct usb_gadget *_gadget)
1524 {
1525 struct m66592 *m66592 = gadget_to_m66592(_gadget);
1526 return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1527 }
1528
1529 static struct usb_gadget_ops m66592_gadget_ops = {
1530 .get_frame = m66592_get_frame,
1531 };
1532
1533 static int __exit m66592_remove(struct platform_device *pdev)
1534 {
1535 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
1536
1537 del_timer_sync(&m66592->timer);
1538 iounmap(m66592->reg);
1539 free_irq(platform_get_irq(pdev, 0), m66592);
1540 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1541 usbf_stop_clock();
1542 kfree(m66592);
1543 return 0;
1544 }
1545
1546 static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1547 {
1548 }
1549
1550 #define resource_len(r) (((r)->end - (r)->start) + 1)
1551
1552 static int __init m66592_probe(struct platform_device *pdev)
1553 {
1554 struct resource *res;
1555 int irq;
1556 void __iomem *reg = NULL;
1557 struct m66592 *m66592 = NULL;
1558 int ret = 0;
1559 int i;
1560
1561 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1562 (char *)udc_name);
1563 if (!res) {
1564 ret = -ENODEV;
1565 pr_err("platform_get_resource_byname error.\n");
1566 goto clean_up;
1567 }
1568
1569 irq = platform_get_irq(pdev, 0);
1570 if (irq < 0) {
1571 ret = -ENODEV;
1572 pr_err("platform_get_irq error.\n");
1573 goto clean_up;
1574 }
1575
1576 reg = ioremap(res->start, resource_len(res));
1577 if (reg == NULL) {
1578 ret = -ENOMEM;
1579 pr_err("ioremap error.\n");
1580 goto clean_up;
1581 }
1582
1583 /* initialize ucd */
1584 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1585 if (m66592 == NULL) {
1586 pr_err("kzalloc error\n");
1587 goto clean_up;
1588 }
1589
1590 spin_lock_init(&m66592->lock);
1591 dev_set_drvdata(&pdev->dev, m66592);
1592
1593 m66592->gadget.ops = &m66592_gadget_ops;
1594 device_initialize(&m66592->gadget.dev);
1595 strcpy(m66592->gadget.dev.bus_id, "gadget");
1596 m66592->gadget.is_dualspeed = 1;
1597 m66592->gadget.dev.parent = &pdev->dev;
1598 m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
1599 m66592->gadget.dev.release = pdev->dev.release;
1600 m66592->gadget.name = udc_name;
1601
1602 init_timer(&m66592->timer);
1603 m66592->timer.function = m66592_timer;
1604 m66592->timer.data = (unsigned long)m66592;
1605 m66592->reg = reg;
1606
1607 m66592->bi_bufnum = M66592_BASE_BUFNUM;
1608
1609 ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1610 udc_name, m66592);
1611 if (ret < 0) {
1612 pr_err("request_irq error (%d)\n", ret);
1613 goto clean_up;
1614 }
1615
1616 INIT_LIST_HEAD(&m66592->gadget.ep_list);
1617 m66592->gadget.ep0 = &m66592->ep[0].ep;
1618 INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1619 for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1620 struct m66592_ep *ep = &m66592->ep[i];
1621
1622 if (i != 0) {
1623 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1624 list_add_tail(&m66592->ep[i].ep.ep_list,
1625 &m66592->gadget.ep_list);
1626 }
1627 ep->m66592 = m66592;
1628 INIT_LIST_HEAD(&ep->queue);
1629 ep->ep.name = m66592_ep_name[i];
1630 ep->ep.ops = &m66592_ep_ops;
1631 ep->ep.maxpacket = 512;
1632 }
1633 m66592->ep[0].ep.maxpacket = 64;
1634 m66592->ep[0].pipenum = 0;
1635 m66592->ep[0].fifoaddr = M66592_CFIFO;
1636 m66592->ep[0].fifosel = M66592_CFIFOSEL;
1637 m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1638 m66592->ep[0].fifotrn = 0;
1639 m66592->ep[0].pipectr = get_pipectr_addr(0);
1640 m66592->pipenum2ep[0] = &m66592->ep[0];
1641 m66592->epaddr2ep[0] = &m66592->ep[0];
1642
1643 the_controller = m66592;
1644
1645 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1646 if (m66592->ep0_req == NULL)
1647 goto clean_up2;
1648 m66592->ep0_req->complete = nop_completion;
1649
1650 init_controller(m66592);
1651
1652 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1653 return 0;
1654
1655 clean_up2:
1656 free_irq(irq, m66592);
1657 clean_up:
1658 if (m66592) {
1659 if (m66592->ep0_req)
1660 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1661 kfree(m66592);
1662 }
1663 if (reg)
1664 iounmap(reg);
1665
1666 return ret;
1667 }
1668
1669 /*-------------------------------------------------------------------------*/
1670 static struct platform_driver m66592_driver = {
1671 .remove = __exit_p(m66592_remove),
1672 .driver = {
1673 .name = (char *) udc_name,
1674 },
1675 };
1676
1677 static int __init m66592_udc_init(void)
1678 {
1679 return platform_driver_probe(&m66592_driver, m66592_probe);
1680 }
1681 module_init(m66592_udc_init);
1682
1683 static void __exit m66592_udc_cleanup(void)
1684 {
1685 platform_driver_unregister(&m66592_driver);
1686 }
1687 module_exit(m66592_udc_cleanup);
Linux with added FPC-III support