drivers/clk/qcom/gdsc.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/kernel.h>
  19 #include <linux/pm_domain.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset-controller.h>
  22 #include <linux/slab.h>
  23 #include "gdsc.h"
  24
  25 #define PWR_ON_MASK             BIT(31)
  26 #define EN_REST_WAIT_MASK       GENMASK_ULL(23, 20)
  27 #define EN_FEW_WAIT_MASK        GENMASK_ULL(19, 16)
  28 #define CLK_DIS_WAIT_MASK       GENMASK_ULL(15, 12)
  29 #define SW_OVERRIDE_MASK        BIT(2)
  30 #define HW_CONTROL_MASK         BIT(1)
  31 #define SW_COLLAPSE_MASK        BIT(0)
  32
  33 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
  34 #define EN_REST_WAIT_VAL        (0x2 << 20)
  35 #define EN_FEW_WAIT_VAL         (0x8 << 16)
  36 #define CLK_DIS_WAIT_VAL        (0x2 << 12)
  37
  38 #define RETAIN_MEM              BIT(14)
  39 #define RETAIN_PERIPH           BIT(13)
  40
  41 #define TIMEOUT_US              100
  42
  43 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  44
  45 static int gdsc_is_enabled(struct gdsc *sc)
  46 {
  47         u32 val;
  48         int ret;
  49
  50         ret = regmap_read(sc->regmap, sc->gdscr, &val);
  51         if (ret)
  52                 return ret;
  53
  54         return !!(val & PWR_ON_MASK);
  55 }
  56
  57 static int gdsc_toggle_logic(struct gdsc *sc, bool en)
  58 {
  59         int ret;
  60         u32 val = en ? 0 : SW_COLLAPSE_MASK;
  61         u32 check = en ? PWR_ON_MASK : 0;
  62         unsigned long timeout;
  63
  64         ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
  65         if (ret)
  66                 return ret;
  67
  68         timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
  69         do {
  70                 ret = regmap_read(sc->regmap, sc->gdscr, &val);
  71                 if (ret)
  72                         return ret;
  73
  74                 if ((val & PWR_ON_MASK) == check)
  75                         return 0;
  76         } while (time_before(jiffies, timeout));
  77
  78         ret = regmap_read(sc->regmap, sc->gdscr, &val);
  79         if (ret)
  80                 return ret;
  81
  82         if ((val & PWR_ON_MASK) == check)
  83                 return 0;
  84
  85         return -ETIMEDOUT;
  86 }
  87
  88 static inline int gdsc_deassert_reset(struct gdsc *sc)
  89 {
  90         int i;
  91
  92         for (i = 0; i < sc->reset_count; i++)
  93                 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
  94         return 0;
  95 }
  96
  97 static inline int gdsc_assert_reset(struct gdsc *sc)
  98 {
  99         int i;
 100
 101         for (i = 0; i < sc->reset_count; i++)
 102                 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
 103         return 0;
 104 }
 105
 106 static inline void gdsc_force_mem_on(struct gdsc *sc)
 107 {
 108         int i;
 109         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 110
 111         for (i = 0; i < sc->cxc_count; i++)
 112                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
 113 }
 114
 115 static inline void gdsc_clear_mem_on(struct gdsc *sc)
 116 {
 117         int i;
 118         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 119
 120         for (i = 0; i < sc->cxc_count; i++)
 121                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
 122 }
 123
 124 static int gdsc_enable(struct generic_pm_domain *domain)
 125 {
 126         struct gdsc *sc = domain_to_gdsc(domain);
 127         int ret;
 128
 129         if (sc->pwrsts == PWRSTS_ON)
 130                 return gdsc_deassert_reset(sc);
 131
 132         ret = gdsc_toggle_logic(sc, true);
 133         if (ret)
 134                 return ret;
 135
 136         if (sc->pwrsts & PWRSTS_OFF)
 137                 gdsc_force_mem_on(sc);
 138
 139         /*
 140          * If clocks to this power domain were already on, they will take an
 141          * additional 4 clock cycles to re-enable after the power domain is
 142          * enabled. Delay to account for this. A delay is also needed to ensure
 143          * clocks are not enabled within 400ns of enabling power to the
 144          * memories.
 145          */
 146         udelay(1);
 147
 148         return 0;
 149 }
 150
 151 static int gdsc_disable(struct generic_pm_domain *domain)
 152 {
 153         struct gdsc *sc = domain_to_gdsc(domain);
 154
 155         if (sc->pwrsts == PWRSTS_ON)
 156                 return gdsc_assert_reset(sc);
 157
 158         if (sc->pwrsts & PWRSTS_OFF)
 159                 gdsc_clear_mem_on(sc);
 160
 161         return gdsc_toggle_logic(sc, false);
 162 }
 163
 164 static int gdsc_init(struct gdsc *sc)
 165 {
 166         u32 mask, val;
 167         int on, ret;
 168
 169         /*
 170          * Disable HW trigger: collapse/restore occur based on registers writes.
 171          * Disable SW override: Use hardware state-machine for sequencing.
 172          * Configure wait time between states.
 173          */
 174         mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
 175                EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
 176         val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
 177         ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
 178         if (ret)
 179                 return ret;
 180
 181         /* Force gdsc ON if only ON state is supported */
 182         if (sc->pwrsts == PWRSTS_ON) {
 183                 ret = gdsc_toggle_logic(sc, true);
 184                 if (ret)
 185                         return ret;
 186         }
 187
 188         on = gdsc_is_enabled(sc);
 189         if (on < 0)
 190                 return on;
 191
 192         if (on || (sc->pwrsts & PWRSTS_RET))
 193                 gdsc_force_mem_on(sc);
 194         else
 195                 gdsc_clear_mem_on(sc);
 196
 197         sc->pd.power_off = gdsc_disable;
 198         sc->pd.power_on = gdsc_enable;
 199         pm_genpd_init(&sc->pd, NULL, !on);
 200
 201         return 0;
 202 }
 203
 204 int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
 205                   struct reset_controller_dev *rcdev, struct regmap *regmap)
 206 {
 207         int i, ret;
 208         struct genpd_onecell_data *data;
 209
 210         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 211         if (!data)
 212                 return -ENOMEM;
 213
 214         data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
 215                                      GFP_KERNEL);
 216         if (!data->domains)
 217                 return -ENOMEM;
 218
 219         data->num_domains = num;
 220         for (i = 0; i < num; i++) {
 221                 if (!scs[i])
 222                         continue;
 223                 scs[i]->regmap = regmap;
 224                 scs[i]->rcdev = rcdev;
 225                 ret = gdsc_init(scs[i]);
 226                 if (ret)
 227                         return ret;
 228                 data->domains[i] = &scs[i]->pd;
 229         }
 230
 231         return of_genpd_add_provider_onecell(dev->of_node, data);
 232 }
 233
 234 void gdsc_unregister(struct device *dev)
 235 {
 236         of_genpd_del_provider(dev->of_node);
 237 }