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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / gpu / drm / armada / armada_crtc.c
blobcebcab5606268f76aa1f9161315ef17ba82981d7
1 /*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <drm/drmP.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include "armada_crtc.h"
17 #include "armada_drm.h"
18 #include "armada_fb.h"
19 #include "armada_gem.h"
20 #include "armada_hw.h"
21
22 struct armada_frame_work {
23 struct armada_plane_work work;
24 struct drm_pending_vblank_event *event;
25 struct armada_regs regs[4];
26 struct drm_framebuffer *old_fb;
27 };
28
29 enum csc_mode {
30 CSC_AUTO = 0,
31 CSC_YUV_CCIR601 = 1,
32 CSC_YUV_CCIR709 = 2,
33 CSC_RGB_COMPUTER = 1,
34 CSC_RGB_STUDIO = 2,
35 };
36
37 static const uint32_t armada_primary_formats[] = {
38 DRM_FORMAT_UYVY,
39 DRM_FORMAT_YUYV,
40 DRM_FORMAT_VYUY,
41 DRM_FORMAT_YVYU,
42 DRM_FORMAT_ARGB8888,
43 DRM_FORMAT_ABGR8888,
44 DRM_FORMAT_XRGB8888,
45 DRM_FORMAT_XBGR8888,
46 DRM_FORMAT_RGB888,
47 DRM_FORMAT_BGR888,
48 DRM_FORMAT_ARGB1555,
49 DRM_FORMAT_ABGR1555,
50 DRM_FORMAT_RGB565,
51 DRM_FORMAT_BGR565,
52 };
53
54 /*
55 * A note about interlacing. Let's consider HDMI 1920x1080i.
56 * The timing parameters we have from X are:
57 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
58 * 1920 2448 2492 2640 1080 1084 1094 1125
59 * Which get translated to:
60 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
61 * 1920 2448 2492 2640 540 542 547 562
62 *
63 * This is how it is defined by CEA-861-D - line and pixel numbers are
64 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
65 * line: 2640. The odd frame, the first active line is at line 21, and
66 * the even frame, the first active line is 584.
67 *
68 * LN: 560 561 562 563 567 568 569
69 * DE: ~~~|____________________________//__________________________
70 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
71 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
72 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
73 *
74 * LN: 1123 1124 1125 1 5 6 7
75 * DE: ~~~|____________________________//__________________________
76 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
77 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
78 * 23 blanking lines
79 *
80 * The Armada LCD Controller line and pixel numbers are, like X timings,
81 * referenced to the top left of the active frame.
82 *
83 * So, translating these to our LCD controller:
84 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
85 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
86 * Note: Vsync front porch remains constant!
87 *
88 * if (odd_frame) {
89 * vtotal = mode->crtc_vtotal + 1;
90 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
91 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
92 * } else {
93 * vtotal = mode->crtc_vtotal;
94 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
95 * vhorizpos = mode->crtc_hsync_start;
96 * }
97 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
98 *
99 * So, we need to reprogram these registers on each vsync event:
100 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
101 *
102 * Note: we do not use the frame done interrupts because these appear
103 * to happen too early, and lead to jitter on the display (presumably
104 * they occur at the end of the last active line, before the vsync back
105 * porch, which we're reprogramming.)
106 */
107
108 void
109 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
110 {
111 while (regs->offset != ~0) {
112 void __iomem *reg = dcrtc->base + regs->offset;
113 uint32_t val;
114
115 val = regs->mask;
116 if (val != 0)
117 val &= readl_relaxed(reg);
118 writel_relaxed(val | regs->val, reg);
119 ++regs;
120 }
121 }
122
123 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
124
125 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
126 {
127 uint32_t dumb_ctrl;
128
129 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
130
131 if (!dpms_blanked(dcrtc->dpms))
132 dumb_ctrl |= CFG_DUMB_ENA;
133
134 /*
135 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
136 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
137 * force LCD_D[23:0] to output blank color, overriding the GPIO or
138 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
139 */
140 if (dpms_blanked(dcrtc->dpms) &&
141 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
142 dumb_ctrl &= ~DUMB_MASK;
143 dumb_ctrl |= DUMB_BLANK;
144 }
145
146 /*
147 * The documentation doesn't indicate what the normal state of
148 * the sync signals are. Sebastian Hesselbart kindly probed
149 * these signals on his board to determine their state.
150 *
151 * The non-inverted state of the sync signals is active high.
152 * Setting these bits makes the appropriate signal active low.
153 */
154 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
155 dumb_ctrl |= CFG_INV_CSYNC;
156 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
157 dumb_ctrl |= CFG_INV_HSYNC;
158 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
159 dumb_ctrl |= CFG_INV_VSYNC;
160
161 if (dcrtc->dumb_ctrl != dumb_ctrl) {
162 dcrtc->dumb_ctrl = dumb_ctrl;
163 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
164 }
165 }
166
167 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
168 int x, int y, struct armada_regs *regs, bool interlaced)
169 {
170 struct armada_gem_object *obj = drm_fb_obj(fb);
171 unsigned pitch = fb->pitches[0];
172 unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
173 uint32_t addr_odd, addr_even;
174 unsigned i = 0;
175
176 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
177 pitch, x, y, fb->bits_per_pixel);
178
179 addr_odd = addr_even = obj->dev_addr + offset;
180
181 if (interlaced) {
182 addr_even += pitch;
183 pitch *= 2;
184 }
185
186 /* write offset, base, and pitch */
187 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
188 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
189 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
190
191 return i;
192 }
193
194 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
195 struct armada_plane *plane)
196 {
197 struct armada_plane_work *work = xchg(&plane->work, NULL);
198
199 /* Handle any pending frame work. */
200 if (work) {
201 work->fn(dcrtc, plane, work);
202 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
203 }
204
205 wake_up(&plane->frame_wait);
206 }
207
208 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
209 struct armada_plane *plane, struct armada_plane_work *work)
210 {
211 int ret;
212
213 ret = drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
214 if (ret) {
215 DRM_ERROR("failed to acquire vblank counter\n");
216 return ret;
217 }
218
219 ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
220 if (ret)
221 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
222
223 return ret;
224 }
225
226 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
227 {
228 return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
229 }
230
231 struct armada_plane_work *armada_drm_plane_work_cancel(
232 struct armada_crtc *dcrtc, struct armada_plane *plane)
233 {
234 struct armada_plane_work *work = xchg(&plane->work, NULL);
235
236 if (work)
237 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
238
239 return work;
240 }
241
242 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
243 struct armada_frame_work *work)
244 {
245 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
246
247 return armada_drm_plane_work_queue(dcrtc, plane, &work->work);
248 }
249
250 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
251 struct armada_plane *plane, struct armada_plane_work *work)
252 {
253 struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work);
254 struct drm_device *dev = dcrtc->crtc.dev;
255 unsigned long flags;
256
257 spin_lock_irqsave(&dcrtc->irq_lock, flags);
258 armada_drm_crtc_update_regs(dcrtc, fwork->regs);
259 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
260
261 if (fwork->event) {
262 spin_lock_irqsave(&dev->event_lock, flags);
263 drm_send_vblank_event(dev, dcrtc->num, fwork->event);
264 spin_unlock_irqrestore(&dev->event_lock, flags);
265 }
266
267 /* Finally, queue the process-half of the cleanup. */
268 __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb);
269 kfree(fwork);
270 }
271
272 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
273 struct drm_framebuffer *fb, bool force)
274 {
275 struct armada_frame_work *work;
276
277 if (!fb)
278 return;
279
280 if (force) {
281 /* Display is disabled, so just drop the old fb */
282 drm_framebuffer_unreference(fb);
283 return;
284 }
285
286 work = kmalloc(sizeof(*work), GFP_KERNEL);
287 if (work) {
288 int i = 0;
289 work->work.fn = armada_drm_crtc_complete_frame_work;
290 work->event = NULL;
291 work->old_fb = fb;
292 armada_reg_queue_end(work->regs, i);
293
294 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
295 return;
296
297 kfree(work);
298 }
299
300 /*
301 * Oops - just drop the reference immediately and hope for
302 * the best. The worst that will happen is the buffer gets
303 * reused before it has finished being displayed.
304 */
305 drm_framebuffer_unreference(fb);
306 }
307
308 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
309 {
310 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
311
312 /*
313 * Tell the DRM core that vblank IRQs aren't going to happen for
314 * a while. This cleans up any pending vblank events for us.
315 */
316 drm_crtc_vblank_off(&dcrtc->crtc);
317 armada_drm_plane_work_run(dcrtc, plane);
318 }
319
320 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
321 int idx)
322 {
323 }
324
325 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
326 int idx)
327 {
328 }
329
330 /* The mode_config.mutex will be held for this call */
331 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
332 {
333 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
334
335 if (dcrtc->dpms != dpms) {
336 dcrtc->dpms = dpms;
337 if (!IS_ERR(dcrtc->clk) && !dpms_blanked(dpms))
338 WARN_ON(clk_prepare_enable(dcrtc->clk));
339 armada_drm_crtc_update(dcrtc);
340 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dpms))
341 clk_disable_unprepare(dcrtc->clk);
342 if (dpms_blanked(dpms))
343 armada_drm_vblank_off(dcrtc);
344 else
345 drm_crtc_vblank_on(&dcrtc->crtc);
346 }
347 }
348
349 /*
350 * Prepare for a mode set. Turn off overlay to ensure that we don't end
351 * up with the overlay size being bigger than the active screen size.
352 * We rely upon X refreshing this state after the mode set has completed.
353 *
354 * The mode_config.mutex will be held for this call
355 */
356 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
357 {
358 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
359 struct drm_plane *plane;
360
361 /*
362 * If we have an overlay plane associated with this CRTC, disable
363 * it before the modeset to avoid its coordinates being outside
364 * the new mode parameters.
365 */
366 plane = dcrtc->plane;
367 if (plane)
368 drm_plane_force_disable(plane);
369 }
370
371 /* The mode_config.mutex will be held for this call */
372 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
373 {
374 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
375
376 if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
377 dcrtc->dpms = DRM_MODE_DPMS_ON;
378 armada_drm_crtc_update(dcrtc);
379 }
380 }
381
382 /* The mode_config.mutex will be held for this call */
383 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
384 const struct drm_display_mode *mode, struct drm_display_mode *adj)
385 {
386 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
387 int ret;
388
389 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
390 if (!dcrtc->variant->has_spu_adv_reg &&
391 adj->flags & DRM_MODE_FLAG_INTERLACE)
392 return false;
393
394 /* Check whether the display mode is possible */
395 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
396 if (ret)
397 return false;
398
399 return true;
400 }
401
402 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
403 {
404 void __iomem *base = dcrtc->base;
405 struct drm_plane *ovl_plane;
406
407 if (stat & DMA_FF_UNDERFLOW)
408 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
409 if (stat & GRA_FF_UNDERFLOW)
410 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
411
412 if (stat & VSYNC_IRQ)
413 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
414
415 spin_lock(&dcrtc->irq_lock);
416 ovl_plane = dcrtc->plane;
417 if (ovl_plane) {
418 struct armada_plane *plane = drm_to_armada_plane(ovl_plane);
419 armada_drm_plane_work_run(dcrtc, plane);
420 }
421
422 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
423 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
424 uint32_t val;
425
426 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
427 writel_relaxed(dcrtc->v[i].spu_v_h_total,
428 base + LCD_SPUT_V_H_TOTAL);
429
430 val = readl_relaxed(base + LCD_SPU_ADV_REG);
431 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
432 val |= dcrtc->v[i].spu_adv_reg;
433 writel_relaxed(val, base + LCD_SPU_ADV_REG);
434 }
435
436 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
437 writel_relaxed(dcrtc->cursor_hw_pos,
438 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
439 writel_relaxed(dcrtc->cursor_hw_sz,
440 base + LCD_SPU_HWC_HPXL_VLN);
441 armada_updatel(CFG_HWC_ENA,
442 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
443 base + LCD_SPU_DMA_CTRL0);
444 dcrtc->cursor_update = false;
445 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
446 }
447
448 spin_unlock(&dcrtc->irq_lock);
449
450 if (stat & GRA_FRAME_IRQ) {
451 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
452 armada_drm_plane_work_run(dcrtc, plane);
453 }
454 }
455
456 static irqreturn_t armada_drm_irq(int irq, void *arg)
457 {
458 struct armada_crtc *dcrtc = arg;
459 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
460
461 /*
462 * This is rediculous - rather than writing bits to clear, we
463 * have to set the actual status register value. This is racy.
464 */
465 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
466
467 /* Mask out those interrupts we haven't enabled */
468 v = stat & dcrtc->irq_ena;
469
470 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
471 armada_drm_crtc_irq(dcrtc, stat);
472 return IRQ_HANDLED;
473 }
474 return IRQ_NONE;
475 }
476
477 /* These are locked by dev->vbl_lock */
478 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
479 {
480 if (dcrtc->irq_ena & mask) {
481 dcrtc->irq_ena &= ~mask;
482 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
483 }
484 }
485
486 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
487 {
488 if ((dcrtc->irq_ena & mask) != mask) {
489 dcrtc->irq_ena |= mask;
490 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
491 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
492 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
493 }
494 }
495
496 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
497 {
498 struct drm_display_mode *adj = &dcrtc->crtc.mode;
499 uint32_t val = 0;
500
501 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
502 val |= CFG_CSC_YUV_CCIR709;
503 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
504 val |= CFG_CSC_RGB_STUDIO;
505
506 /*
507 * In auto mode, set the colorimetry, based upon the HDMI spec.
508 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
509 * ITU601. It may be more appropriate to set this depending on
510 * the source - but what if the graphic frame is YUV and the
511 * video frame is RGB?
512 */
513 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
514 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
515 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
516 if (dcrtc->csc_yuv_mode == CSC_AUTO)
517 val |= CFG_CSC_YUV_CCIR709;
518 }
519
520 /*
521 * We assume we're connected to a TV-like device, so the YUV->RGB
522 * conversion should produce a limited range. We should set this
523 * depending on the connectors attached to this CRTC, and what
524 * kind of device they report being connected.
525 */
526 if (dcrtc->csc_rgb_mode == CSC_AUTO)
527 val |= CFG_CSC_RGB_STUDIO;
528
529 return val;
530 }
531
532 /* The mode_config.mutex will be held for this call */
533 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
534 struct drm_display_mode *mode, struct drm_display_mode *adj,
535 int x, int y, struct drm_framebuffer *old_fb)
536 {
537 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
538 struct armada_regs regs[17];
539 uint32_t lm, rm, tm, bm, val, sclk;
540 unsigned long flags;
541 unsigned i;
542 bool interlaced;
543
544 drm_framebuffer_reference(crtc->primary->fb);
545
546 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
547
548 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
549 x, y, regs, interlaced);
550
551 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
552 lm = adj->crtc_htotal - adj->crtc_hsync_end;
553 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
554 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
555
556 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
557 adj->crtc_hdisplay,
558 adj->crtc_hsync_start,
559 adj->crtc_hsync_end,
560 adj->crtc_htotal, lm, rm);
561 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
562 adj->crtc_vdisplay,
563 adj->crtc_vsync_start,
564 adj->crtc_vsync_end,
565 adj->crtc_vtotal, tm, bm);
566
567 /* Wait for pending flips to complete */
568 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
569 MAX_SCHEDULE_TIMEOUT);
570
571 drm_crtc_vblank_off(crtc);
572
573 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
574 if (val != dcrtc->dumb_ctrl) {
575 dcrtc->dumb_ctrl = val;
576 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
577 }
578
579 /*
580 * If we are blanked, we would have disabled the clock. Re-enable
581 * it so that compute_clock() does the right thing.
582 */
583 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
584 WARN_ON(clk_prepare_enable(dcrtc->clk));
585
586 /* Now compute the divider for real */
587 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
588
589 /* Ensure graphic fifo is enabled */
590 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
591 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
592
593 if (interlaced ^ dcrtc->interlaced) {
594 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
595 drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
596 else
597 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
598 dcrtc->interlaced = interlaced;
599 }
600
601 spin_lock_irqsave(&dcrtc->irq_lock, flags);
602
603 /* Even interlaced/progressive frame */
604 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
605 adj->crtc_htotal;
606 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
607 val = adj->crtc_hsync_start;
608 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
609 dcrtc->variant->spu_adv_reg;
610
611 if (interlaced) {
612 /* Odd interlaced frame */
613 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
614 (1 << 16);
615 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
616 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
617 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
618 dcrtc->variant->spu_adv_reg;
619 } else {
620 dcrtc->v[0] = dcrtc->v[1];
621 }
622
623 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
624
625 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
626 armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
627 armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
628 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
629 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
630 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
631 LCD_SPUT_V_H_TOTAL);
632
633 if (dcrtc->variant->has_spu_adv_reg) {
634 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
635 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
636 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
637 }
638
639 val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
640 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
641 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
642
643 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
644 val |= CFG_PALETTE_ENA;
645
646 if (interlaced)
647 val |= CFG_GRA_FTOGGLE;
648
649 armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
650 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
651 CFG_SWAPYU | CFG_YUV2RGB) |
652 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
653 LCD_SPU_DMA_CTRL0);
654
655 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
656 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
657
658 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
659 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
660 armada_reg_queue_end(regs, i);
661
662 armada_drm_crtc_update_regs(dcrtc, regs);
663 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
664
665 armada_drm_crtc_update(dcrtc);
666
667 drm_crtc_vblank_on(crtc);
668 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
669
670 return 0;
671 }
672
673 /* The mode_config.mutex will be held for this call */
674 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
675 struct drm_framebuffer *old_fb)
676 {
677 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
678 struct armada_regs regs[4];
679 unsigned i;
680
681 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
682 dcrtc->interlaced);
683 armada_reg_queue_end(regs, i);
684
685 /* Wait for pending flips to complete */
686 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
687 MAX_SCHEDULE_TIMEOUT);
688
689 /* Take a reference to the new fb as we're using it */
690 drm_framebuffer_reference(crtc->primary->fb);
691
692 /* Update the base in the CRTC */
693 armada_drm_crtc_update_regs(dcrtc, regs);
694
695 /* Drop our previously held reference */
696 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
697
698 return 0;
699 }
700
701 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
702 struct drm_plane *plane)
703 {
704 u32 sram_para1, dma_ctrl0_mask;
705
706 /*
707 * Drop our reference on any framebuffer attached to this plane.
708 * We don't need to NULL this out as drm_plane_force_disable(),
709 * and __setplane_internal() will do so for an overlay plane, and
710 * __drm_helper_disable_unused_functions() will do so for the
711 * primary plane.
712 */
713 if (plane->fb)
714 drm_framebuffer_unreference(plane->fb);
715
716 /* Power down the Y/U/V FIFOs */
717 sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
718
719 /* Power down most RAMs and FIFOs if this is the primary plane */
720 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
721 sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
722 CFG_PDWN32x32 | CFG_PDWN64x66;
723 dma_ctrl0_mask = CFG_GRA_ENA;
724 } else {
725 dma_ctrl0_mask = CFG_DMA_ENA;
726 }
727
728 spin_lock_irq(&dcrtc->irq_lock);
729 armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
730 spin_unlock_irq(&dcrtc->irq_lock);
731
732 armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
733 }
734
735 /* The mode_config.mutex will be held for this call */
736 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
737 {
738 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
739
740 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
741 armada_drm_crtc_plane_disable(dcrtc, crtc->primary);
742 }
743
744 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
745 .dpms = armada_drm_crtc_dpms,
746 .prepare = armada_drm_crtc_prepare,
747 .commit = armada_drm_crtc_commit,
748 .mode_fixup = armada_drm_crtc_mode_fixup,
749 .mode_set = armada_drm_crtc_mode_set,
750 .mode_set_base = armada_drm_crtc_mode_set_base,
751 .disable = armada_drm_crtc_disable,
752 };
753
754 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
755 unsigned stride, unsigned width, unsigned height)
756 {
757 uint32_t addr;
758 unsigned y;
759
760 addr = SRAM_HWC32_RAM1;
761 for (y = 0; y < height; y++) {
762 uint32_t *p = &pix[y * stride];
763 unsigned x;
764
765 for (x = 0; x < width; x++, p++) {
766 uint32_t val = *p;
767
768 val = (val & 0xff00ff00) |
769 (val & 0x000000ff) << 16 |
770 (val & 0x00ff0000) >> 16;
771
772 writel_relaxed(val,
773 base + LCD_SPU_SRAM_WRDAT);
774 writel_relaxed(addr | SRAM_WRITE,
775 base + LCD_SPU_SRAM_CTRL);
776 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
777 addr += 1;
778 if ((addr & 0x00ff) == 0)
779 addr += 0xf00;
780 if ((addr & 0x30ff) == 0)
781 addr = SRAM_HWC32_RAM2;
782 }
783 }
784 }
785
786 static void armada_drm_crtc_cursor_tran(void __iomem *base)
787 {
788 unsigned addr;
789
790 for (addr = 0; addr < 256; addr++) {
791 /* write the default value */
792 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
793 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
794 base + LCD_SPU_SRAM_CTRL);
795 }
796 }
797
798 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
799 {
800 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
801 uint32_t yoff, yscr, h = dcrtc->cursor_h;
802 uint32_t para1;
803
804 /*
805 * Calculate the visible width and height of the cursor,
806 * screen position, and the position in the cursor bitmap.
807 */
808 if (dcrtc->cursor_x < 0) {
809 xoff = -dcrtc->cursor_x;
810 xscr = 0;
811 w -= min(xoff, w);
812 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
813 xoff = 0;
814 xscr = dcrtc->cursor_x;
815 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
816 } else {
817 xoff = 0;
818 xscr = dcrtc->cursor_x;
819 }
820
821 if (dcrtc->cursor_y < 0) {
822 yoff = -dcrtc->cursor_y;
823 yscr = 0;
824 h -= min(yoff, h);
825 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
826 yoff = 0;
827 yscr = dcrtc->cursor_y;
828 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
829 } else {
830 yoff = 0;
831 yscr = dcrtc->cursor_y;
832 }
833
834 /* On interlaced modes, the vertical cursor size must be halved */
835 s = dcrtc->cursor_w;
836 if (dcrtc->interlaced) {
837 s *= 2;
838 yscr /= 2;
839 h /= 2;
840 }
841
842 if (!dcrtc->cursor_obj || !h || !w) {
843 spin_lock_irq(&dcrtc->irq_lock);
844 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
845 dcrtc->cursor_update = false;
846 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
847 spin_unlock_irq(&dcrtc->irq_lock);
848 return 0;
849 }
850
851 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
852 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
853 dcrtc->base + LCD_SPU_SRAM_PARA1);
854
855 /*
856 * Initialize the transparency if the SRAM was powered down.
857 * We must also reload the cursor data as well.
858 */
859 if (!(para1 & CFG_CSB_256x32)) {
860 armada_drm_crtc_cursor_tran(dcrtc->base);
861 reload = true;
862 }
863
864 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
865 spin_lock_irq(&dcrtc->irq_lock);
866 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
867 dcrtc->cursor_update = false;
868 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
869 spin_unlock_irq(&dcrtc->irq_lock);
870 reload = true;
871 }
872 if (reload) {
873 struct armada_gem_object *obj = dcrtc->cursor_obj;
874 uint32_t *pix;
875 /* Set the top-left corner of the cursor image */
876 pix = obj->addr;
877 pix += yoff * s + xoff;
878 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
879 }
880
881 /* Reload the cursor position, size and enable in the IRQ handler */
882 spin_lock_irq(&dcrtc->irq_lock);
883 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
884 dcrtc->cursor_hw_sz = h << 16 | w;
885 dcrtc->cursor_update = true;
886 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
887 spin_unlock_irq(&dcrtc->irq_lock);
888
889 return 0;
890 }
891
892 static void cursor_update(void *data)
893 {
894 armada_drm_crtc_cursor_update(data, true);
895 }
896
897 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
898 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
899 {
900 struct drm_device *dev = crtc->dev;
901 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
902 struct armada_gem_object *obj = NULL;
903 int ret;
904
905 /* If no cursor support, replicate drm's return value */
906 if (!dcrtc->variant->has_spu_adv_reg)
907 return -ENXIO;
908
909 if (handle && w > 0 && h > 0) {
910 /* maximum size is 64x32 or 32x64 */
911 if (w > 64 || h > 64 || (w > 32 && h > 32))
912 return -ENOMEM;
913
914 obj = armada_gem_object_lookup(dev, file, handle);
915 if (!obj)
916 return -ENOENT;
917
918 /* Must be a kernel-mapped object */
919 if (!obj->addr) {
920 drm_gem_object_unreference_unlocked(&obj->obj);
921 return -EINVAL;
922 }
923
924 if (obj->obj.size < w * h * 4) {
925 DRM_ERROR("buffer is too small\n");
926 drm_gem_object_unreference_unlocked(&obj->obj);
927 return -ENOMEM;
928 }
929 }
930
931 mutex_lock(&dev->struct_mutex);
932 if (dcrtc->cursor_obj) {
933 dcrtc->cursor_obj->update = NULL;
934 dcrtc->cursor_obj->update_data = NULL;
935 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
936 }
937 dcrtc->cursor_obj = obj;
938 dcrtc->cursor_w = w;
939 dcrtc->cursor_h = h;
940 ret = armada_drm_crtc_cursor_update(dcrtc, true);
941 if (obj) {
942 obj->update_data = dcrtc;
943 obj->update = cursor_update;
944 }
945 mutex_unlock(&dev->struct_mutex);
946
947 return ret;
948 }
949
950 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
951 {
952 struct drm_device *dev = crtc->dev;
953 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
954 int ret;
955
956 /* If no cursor support, replicate drm's return value */
957 if (!dcrtc->variant->has_spu_adv_reg)
958 return -EFAULT;
959
960 mutex_lock(&dev->struct_mutex);
961 dcrtc->cursor_x = x;
962 dcrtc->cursor_y = y;
963 ret = armada_drm_crtc_cursor_update(dcrtc, false);
964 mutex_unlock(&dev->struct_mutex);
965
966 return ret;
967 }
968
969 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
970 {
971 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
972 struct armada_private *priv = crtc->dev->dev_private;
973
974 if (dcrtc->cursor_obj)
975 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
976
977 priv->dcrtc[dcrtc->num] = NULL;
978 drm_crtc_cleanup(&dcrtc->crtc);
979
980 if (!IS_ERR(dcrtc->clk))
981 clk_disable_unprepare(dcrtc->clk);
982
983 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
984
985 of_node_put(dcrtc->crtc.port);
986
987 kfree(dcrtc);
988 }
989
990 /*
991 * The mode_config lock is held here, to prevent races between this
992 * and a mode_set.
993 */
994 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
995 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
996 {
997 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
998 struct armada_frame_work *work;
999 unsigned i;
1000 int ret;
1001
1002 /* We don't support changing the pixel format */
1003 if (fb->pixel_format != crtc->primary->fb->pixel_format)
1004 return -EINVAL;
1005
1006 work = kmalloc(sizeof(*work), GFP_KERNEL);
1007 if (!work)
1008 return -ENOMEM;
1009
1010 work->work.fn = armada_drm_crtc_complete_frame_work;
1011 work->event = event;
1012 work->old_fb = dcrtc->crtc.primary->fb;
1013
1014 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1015 dcrtc->interlaced);
1016 armada_reg_queue_end(work->regs, i);
1017
1018 /*
1019 * Ensure that we hold a reference on the new framebuffer.
1020 * This has to match the behaviour in mode_set.
1021 */
1022 drm_framebuffer_reference(fb);
1023
1024 ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
1025 if (ret) {
1026 /* Undo our reference above */
1027 drm_framebuffer_unreference(fb);
1028 kfree(work);
1029 return ret;
1030 }
1031
1032 /*
1033 * Don't take a reference on the new framebuffer;
1034 * drm_mode_page_flip_ioctl() has already grabbed a reference and
1035 * will _not_ drop that reference on successful return from this
1036 * function. Simply mark this new framebuffer as the current one.
1037 */
1038 dcrtc->crtc.primary->fb = fb;
1039
1040 /*
1041 * Finally, if the display is blanked, we won't receive an
1042 * interrupt, so complete it now.
1043 */
1044 if (dpms_blanked(dcrtc->dpms))
1045 armada_drm_plane_work_run(dcrtc, drm_to_armada_plane(dcrtc->crtc.primary));
1046
1047 return 0;
1048 }
1049
1050 static int
1051 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1052 struct drm_property *property, uint64_t val)
1053 {
1054 struct armada_private *priv = crtc->dev->dev_private;
1055 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1056 bool update_csc = false;
1057
1058 if (property == priv->csc_yuv_prop) {
1059 dcrtc->csc_yuv_mode = val;
1060 update_csc = true;
1061 } else if (property == priv->csc_rgb_prop) {
1062 dcrtc->csc_rgb_mode = val;
1063 update_csc = true;
1064 }
1065
1066 if (update_csc) {
1067 uint32_t val;
1068
1069 val = dcrtc->spu_iopad_ctrl |
1070 armada_drm_crtc_calculate_csc(dcrtc);
1071 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1072 }
1073
1074 return 0;
1075 }
1076
1077 static struct drm_crtc_funcs armada_crtc_funcs = {
1078 .cursor_set = armada_drm_crtc_cursor_set,
1079 .cursor_move = armada_drm_crtc_cursor_move,
1080 .destroy = armada_drm_crtc_destroy,
1081 .set_config = drm_crtc_helper_set_config,
1082 .page_flip = armada_drm_crtc_page_flip,
1083 .set_property = armada_drm_crtc_set_property,
1084 };
1085
1086 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1087 .update_plane = drm_primary_helper_update,
1088 .disable_plane = drm_primary_helper_disable,
1089 .destroy = drm_primary_helper_destroy,
1090 };
1091
1092 int armada_drm_plane_init(struct armada_plane *plane)
1093 {
1094 init_waitqueue_head(&plane->frame_wait);
1095
1096 return 0;
1097 }
1098
1099 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1100 { CSC_AUTO, "Auto" },
1101 { CSC_YUV_CCIR601, "CCIR601" },
1102 { CSC_YUV_CCIR709, "CCIR709" },
1103 };
1104
1105 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1106 { CSC_AUTO, "Auto" },
1107 { CSC_RGB_COMPUTER, "Computer system" },
1108 { CSC_RGB_STUDIO, "Studio" },
1109 };
1110
1111 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1112 {
1113 struct armada_private *priv = dev->dev_private;
1114
1115 if (priv->csc_yuv_prop)
1116 return 0;
1117
1118 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1119 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1120 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1121 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1122 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1123 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1124
1125 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1126 return -ENOMEM;
1127
1128 return 0;
1129 }
1130
1131 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1132 struct resource *res, int irq, const struct armada_variant *variant,
1133 struct device_node *port)
1134 {
1135 struct armada_private *priv = drm->dev_private;
1136 struct armada_crtc *dcrtc;
1137 struct armada_plane *primary;
1138 void __iomem *base;
1139 int ret;
1140
1141 ret = armada_drm_crtc_create_properties(drm);
1142 if (ret)
1143 return ret;
1144
1145 base = devm_ioremap_resource(dev, res);
1146 if (IS_ERR(base))
1147 return PTR_ERR(base);
1148
1149 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1150 if (!dcrtc) {
1151 DRM_ERROR("failed to allocate Armada crtc\n");
1152 return -ENOMEM;
1153 }
1154
1155 if (dev != drm->dev)
1156 dev_set_drvdata(dev, dcrtc);
1157
1158 dcrtc->variant = variant;
1159 dcrtc->base = base;
1160 dcrtc->num = drm->mode_config.num_crtc;
1161 dcrtc->clk = ERR_PTR(-EINVAL);
1162 dcrtc->csc_yuv_mode = CSC_AUTO;
1163 dcrtc->csc_rgb_mode = CSC_AUTO;
1164 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1165 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1166 spin_lock_init(&dcrtc->irq_lock);
1167 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1168
1169 /* Initialize some registers which we don't otherwise set */
1170 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1171 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1172 writel_relaxed(dcrtc->spu_iopad_ctrl,
1173 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1174 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1175 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1176 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1177 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1178 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1179 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1180 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1181 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1182
1183 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1184 dcrtc);
1185 if (ret < 0) {
1186 kfree(dcrtc);
1187 return ret;
1188 }
1189
1190 if (dcrtc->variant->init) {
1191 ret = dcrtc->variant->init(dcrtc, dev);
1192 if (ret) {
1193 kfree(dcrtc);
1194 return ret;
1195 }
1196 }
1197
1198 /* Ensure AXI pipeline is enabled */
1199 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1200
1201 priv->dcrtc[dcrtc->num] = dcrtc;
1202
1203 dcrtc->crtc.port = port;
1204
1205 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1206 if (!primary)
1207 return -ENOMEM;
1208
1209 ret = armada_drm_plane_init(primary);
1210 if (ret) {
1211 kfree(primary);
1212 return ret;
1213 }
1214
1215 ret = drm_universal_plane_init(drm, &primary->base, 0,
1216 &armada_primary_plane_funcs,
1217 armada_primary_formats,
1218 ARRAY_SIZE(armada_primary_formats),
1219 DRM_PLANE_TYPE_PRIMARY);
1220 if (ret) {
1221 kfree(primary);
1222 return ret;
1223 }
1224
1225 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1226 &armada_crtc_funcs);
1227 if (ret)
1228 goto err_crtc_init;
1229
1230 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1231
1232 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1233 dcrtc->csc_yuv_mode);
1234 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1235 dcrtc->csc_rgb_mode);
1236
1237 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1238
1239 err_crtc_init:
1240 primary->base.funcs->destroy(&primary->base);
1241 return ret;
1242 }
1243
1244 static int
1245 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1246 {
1247 struct platform_device *pdev = to_platform_device(dev);
1248 struct drm_device *drm = data;
1249 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250 int irq = platform_get_irq(pdev, 0);
1251 const struct armada_variant *variant;
1252 struct device_node *port = NULL;
1253
1254 if (irq < 0)
1255 return irq;
1256
1257 if (!dev->of_node) {
1258 const struct platform_device_id *id;
1259
1260 id = platform_get_device_id(pdev);
1261 if (!id)
1262 return -ENXIO;
1263
1264 variant = (const struct armada_variant *)id->driver_data;
1265 } else {
1266 const struct of_device_id *match;
1267 struct device_node *np, *parent = dev->of_node;
1268
1269 match = of_match_device(dev->driver->of_match_table, dev);
1270 if (!match)
1271 return -ENXIO;
1272
1273 np = of_get_child_by_name(parent, "ports");
1274 if (np)
1275 parent = np;
1276 port = of_get_child_by_name(parent, "port");
1277 of_node_put(np);
1278 if (!port) {
1279 dev_err(dev, "no port node found in %s\n",
1280 parent->full_name);
1281 return -ENXIO;
1282 }
1283
1284 variant = match->data;
1285 }
1286
1287 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1288 }
1289
1290 static void
1291 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1292 {
1293 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1294
1295 armada_drm_crtc_destroy(&dcrtc->crtc);
1296 }
1297
1298 static const struct component_ops armada_lcd_ops = {
1299 .bind = armada_lcd_bind,
1300 .unbind = armada_lcd_unbind,
1301 };
1302
1303 static int armada_lcd_probe(struct platform_device *pdev)
1304 {
1305 return component_add(&pdev->dev, &armada_lcd_ops);
1306 }
1307
1308 static int armada_lcd_remove(struct platform_device *pdev)
1309 {
1310 component_del(&pdev->dev, &armada_lcd_ops);
1311 return 0;
1312 }
1313
1314 static struct of_device_id armada_lcd_of_match[] = {
1315 {
1316 .compatible = "marvell,dove-lcd",
1317 .data = &armada510_ops,
1318 },
1319 {}
1320 };
1321 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1322
1323 static const struct platform_device_id armada_lcd_platform_ids[] = {
1324 {
1325 .name = "armada-lcd",
1326 .driver_data = (unsigned long)&armada510_ops,
1327 }, {
1328 .name = "armada-510-lcd",
1329 .driver_data = (unsigned long)&armada510_ops,
1330 },
1331 { },
1332 };
1333 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1334
1335 struct platform_driver armada_lcd_platform_driver = {
1336 .probe = armada_lcd_probe,
1337 .remove = armada_lcd_remove,
1338 .driver = {
1339 .name = "armada-lcd",
1340 .owner = THIS_MODULE,
1341 .of_match_table = armada_lcd_of_match,
1342 },
1343 .id_table = armada_lcd_platform_ids,
1344 };
Linux with added FPC-III support