drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67 #include <linux/interval_tree.h>
  68 #include <linux/hashtable.h>
  69 #include <linux/fence.h>
  70
  71 #include <ttm/ttm_bo_api.h>
  72 #include <ttm/ttm_bo_driver.h>
  73 #include <ttm/ttm_placement.h>
  74 #include <ttm/ttm_module.h>
  75 #include <ttm/ttm_execbuf_util.h>
  76
  77 #include <drm/drm_gem.h>
  78
  79 #include "radeon_family.h"
  80 #include "radeon_mode.h"
  81 #include "radeon_reg.h"
  82
  83 /*
  84  * Modules parameters.
  85  */
  86 extern int radeon_no_wb;
  87 extern int radeon_modeset;
  88 extern int radeon_dynclks;
  89 extern int radeon_r4xx_atom;
  90 extern int radeon_agpmode;
  91 extern int radeon_vram_limit;
  92 extern int radeon_gart_size;
  93 extern int radeon_benchmarking;
  94 extern int radeon_testing;
  95 extern int radeon_connector_table;
  96 extern int radeon_tv;
  97 extern int radeon_audio;
  98 extern int radeon_disp_priority;
  99 extern int radeon_hw_i2c;
 100 extern int radeon_pcie_gen2;
 101 extern int radeon_msi;
 102 extern int radeon_lockup_timeout;
 103 extern int radeon_fastfb;
 104 extern int radeon_dpm;
 105 extern int radeon_aspm;
 106 extern int radeon_runtime_pm;
 107 extern int radeon_hard_reset;
 108 extern int radeon_vm_size;
 109 extern int radeon_vm_block_size;
 110 extern int radeon_deep_color;
 111 extern int radeon_use_pflipirq;
 112 extern int radeon_bapm;
 113 extern int radeon_backlight;
 114 extern int radeon_auxch;
 115 extern int radeon_mst;
 116
 117 /*
 118  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 119  * symbol;
 120  */
 121 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 122 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 123 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 124 #define RADEON_IB_POOL_SIZE                     16
 125 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 126 #define RADEONFB_CONN_LIMIT                     4
 127 #define RADEON_BIOS_NUM_SCRATCH                 8
 128
 129 /* internal ring indices */
 130 /* r1xx+ has gfx CP ring */
 131 #define RADEON_RING_TYPE_GFX_INDEX              0
 132
 133 /* cayman has 2 compute CP rings */
 134 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 135 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 136
 137 /* R600+ has an async dma ring */
 138 #define R600_RING_TYPE_DMA_INDEX                3
 139 /* cayman add a second async dma ring */
 140 #define CAYMAN_RING_TYPE_DMA1_INDEX             4
 141
 142 /* R600+ */
 143 #define R600_RING_TYPE_UVD_INDEX                5
 144
 145 /* TN+ */
 146 #define TN_RING_TYPE_VCE1_INDEX                 6
 147 #define TN_RING_TYPE_VCE2_INDEX                 7
 148
 149 /* max number of rings */
 150 #define RADEON_NUM_RINGS                        8
 151
 152 /* number of hw syncs before falling back on blocking */
 153 #define RADEON_NUM_SYNCS                        4
 154
 155 /* hardcode those limit for now */
 156 #define RADEON_VA_IB_OFFSET                     (1 << 20)
 157 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 158 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 159
 160 /* hard reset data */
 161 #define RADEON_ASIC_RESET_DATA                  0x39d5e86b
 162
 163 /* reset flags */
 164 #define RADEON_RESET_GFX                        (1 << 0)
 165 #define RADEON_RESET_COMPUTE                    (1 << 1)
 166 #define RADEON_RESET_DMA                        (1 << 2)
 167 #define RADEON_RESET_CP                         (1 << 3)
 168 #define RADEON_RESET_GRBM                       (1 << 4)
 169 #define RADEON_RESET_DMA1                       (1 << 5)
 170 #define RADEON_RESET_RLC                        (1 << 6)
 171 #define RADEON_RESET_SEM                        (1 << 7)
 172 #define RADEON_RESET_IH                         (1 << 8)
 173 #define RADEON_RESET_VMC                        (1 << 9)
 174 #define RADEON_RESET_MC                         (1 << 10)
 175 #define RADEON_RESET_DISPLAY                    (1 << 11)
 176
 177 /* CG block flags */
 178 #define RADEON_CG_BLOCK_GFX                     (1 << 0)
 179 #define RADEON_CG_BLOCK_MC                      (1 << 1)
 180 #define RADEON_CG_BLOCK_SDMA                    (1 << 2)
 181 #define RADEON_CG_BLOCK_UVD                     (1 << 3)
 182 #define RADEON_CG_BLOCK_VCE                     (1 << 4)
 183 #define RADEON_CG_BLOCK_HDP                     (1 << 5)
 184 #define RADEON_CG_BLOCK_BIF                     (1 << 6)
 185
 186 /* CG flags */
 187 #define RADEON_CG_SUPPORT_GFX_MGCG              (1 << 0)
 188 #define RADEON_CG_SUPPORT_GFX_MGLS              (1 << 1)
 189 #define RADEON_CG_SUPPORT_GFX_CGCG              (1 << 2)
 190 #define RADEON_CG_SUPPORT_GFX_CGLS              (1 << 3)
 191 #define RADEON_CG_SUPPORT_GFX_CGTS              (1 << 4)
 192 #define RADEON_CG_SUPPORT_GFX_CGTS_LS           (1 << 5)
 193 #define RADEON_CG_SUPPORT_GFX_CP_LS             (1 << 6)
 194 #define RADEON_CG_SUPPORT_GFX_RLC_LS            (1 << 7)
 195 #define RADEON_CG_SUPPORT_MC_LS                 (1 << 8)
 196 #define RADEON_CG_SUPPORT_MC_MGCG               (1 << 9)
 197 #define RADEON_CG_SUPPORT_SDMA_LS               (1 << 10)
 198 #define RADEON_CG_SUPPORT_SDMA_MGCG             (1 << 11)
 199 #define RADEON_CG_SUPPORT_BIF_LS                (1 << 12)
 200 #define RADEON_CG_SUPPORT_UVD_MGCG              (1 << 13)
 201 #define RADEON_CG_SUPPORT_VCE_MGCG              (1 << 14)
 202 #define RADEON_CG_SUPPORT_HDP_LS                (1 << 15)
 203 #define RADEON_CG_SUPPORT_HDP_MGCG              (1 << 16)
 204
 205 /* PG flags */
 206 #define RADEON_PG_SUPPORT_GFX_PG                (1 << 0)
 207 #define RADEON_PG_SUPPORT_GFX_SMG               (1 << 1)
 208 #define RADEON_PG_SUPPORT_GFX_DMG               (1 << 2)
 209 #define RADEON_PG_SUPPORT_UVD                   (1 << 3)
 210 #define RADEON_PG_SUPPORT_VCE                   (1 << 4)
 211 #define RADEON_PG_SUPPORT_CP                    (1 << 5)
 212 #define RADEON_PG_SUPPORT_GDS                   (1 << 6)
 213 #define RADEON_PG_SUPPORT_RLC_SMU_HS            (1 << 7)
 214 #define RADEON_PG_SUPPORT_SDMA                  (1 << 8)
 215 #define RADEON_PG_SUPPORT_ACP                   (1 << 9)
 216 #define RADEON_PG_SUPPORT_SAMU                  (1 << 10)
 217
 218 /* max cursor sizes (in pixels) */
 219 #define CURSOR_WIDTH 64
 220 #define CURSOR_HEIGHT 64
 221
 222 #define CIK_CURSOR_WIDTH 128
 223 #define CIK_CURSOR_HEIGHT 128
 224
 225 /*
 226  * Errata workarounds.
 227  */
 228 enum radeon_pll_errata {
 229         CHIP_ERRATA_R300_CG             = 0x00000001,
 230         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 231         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 232 };
 233
 234
 235 struct radeon_device;
 236
 237
 238 /*
 239  * BIOS.
 240  */
 241 bool radeon_get_bios(struct radeon_device *rdev);
 242
 243 /*
 244  * Dummy page
 245  */
 246 struct radeon_dummy_page {
 247         uint64_t        entry;
 248         struct page     *page;
 249         dma_addr_t      addr;
 250 };
 251 int radeon_dummy_page_init(struct radeon_device *rdev);
 252 void radeon_dummy_page_fini(struct radeon_device *rdev);
 253
 254
 255 /*
 256  * Clocks
 257  */
 258 struct radeon_clock {
 259         struct radeon_pll p1pll;
 260         struct radeon_pll p2pll;
 261         struct radeon_pll dcpll;
 262         struct radeon_pll spll;
 263         struct radeon_pll mpll;
 264         /* 10 Khz units */
 265         uint32_t default_mclk;
 266         uint32_t default_sclk;
 267         uint32_t default_dispclk;
 268         uint32_t current_dispclk;
 269         uint32_t dp_extclk;
 270         uint32_t max_pixel_clock;
 271 };
 272
 273 /*
 274  * Power management
 275  */
 276 int radeon_pm_init(struct radeon_device *rdev);
 277 int radeon_pm_late_init(struct radeon_device *rdev);
 278 void radeon_pm_fini(struct radeon_device *rdev);
 279 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 280 void radeon_pm_suspend(struct radeon_device *rdev);
 281 void radeon_pm_resume(struct radeon_device *rdev);
 282 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 283 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 284 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
 285                                    u8 clock_type,
 286                                    u32 clock,
 287                                    bool strobe_mode,
 288                                    struct atom_clock_dividers *dividers);
 289 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
 290                                         u32 clock,
 291                                         bool strobe_mode,
 292                                         struct atom_mpll_param *mpll_param);
 293 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 294 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
 295                                           u16 voltage_level, u8 voltage_type,
 296                                           u32 *gpio_value, u32 *gpio_mask);
 297 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
 298                                          u32 eng_clock, u32 mem_clock);
 299 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
 300                                  u8 voltage_type, u16 *voltage_step);
 301 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 302                              u16 voltage_id, u16 *voltage);
 303 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
 304                                                       u16 *voltage,
 305                                                       u16 leakage_idx);
 306 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
 307                                           u16 *leakage_id);
 308 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
 309                                                          u16 *vddc, u16 *vddci,
 310                                                          u16 virtual_voltage_id,
 311                                                          u16 vbios_voltage_id);
 312 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
 313                                 u16 virtual_voltage_id,
 314                                 u16 *voltage);
 315 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
 316                                       u8 voltage_type,
 317                                       u16 nominal_voltage,
 318                                       u16 *true_voltage);
 319 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
 320                                 u8 voltage_type, u16 *min_voltage);
 321 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
 322                                 u8 voltage_type, u16 *max_voltage);
 323 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
 324                                   u8 voltage_type, u8 voltage_mode,
 325                                   struct atom_voltage_table *voltage_table);
 326 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
 327                                  u8 voltage_type, u8 voltage_mode);
 328 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
 329                               u8 voltage_type,
 330                               u8 *svd_gpio_id, u8 *svc_gpio_id);
 331 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
 332                                    u32 mem_clock);
 333 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
 334                                u32 mem_clock);
 335 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
 336                                   u8 module_index,
 337                                   struct atom_mc_reg_table *reg_table);
 338 int radeon_atom_get_memory_info(struct radeon_device *rdev,
 339                                 u8 module_index, struct atom_memory_info *mem_info);
 340 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
 341                                      bool gddr5, u8 module_index,
 342                                      struct atom_memory_clock_range_table *mclk_range_table);
 343 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 344                              u16 voltage_id, u16 *voltage);
 345 void rs690_pm_info(struct radeon_device *rdev);
 346 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 347                                     unsigned *bankh, unsigned *mtaspect,
 348                                     unsigned *tile_split);
 349
 350 /*
 351  * Fences.
 352  */
 353 struct radeon_fence_driver {
 354         struct radeon_device            *rdev;
 355         uint32_t                        scratch_reg;
 356         uint64_t                        gpu_addr;
 357         volatile uint32_t               *cpu_addr;
 358         /* sync_seq is protected by ring emission lock */
 359         uint64_t                        sync_seq[RADEON_NUM_RINGS];
 360         atomic64_t                      last_seq;
 361         bool                            initialized, delayed_irq;
 362         struct delayed_work             lockup_work;
 363 };
 364
 365 struct radeon_fence {
 366         struct fence            base;
 367
 368         struct radeon_device    *rdev;
 369         uint64_t                seq;
 370         /* RB, DMA, etc. */
 371         unsigned                ring;
 372         bool                    is_vm_update;
 373
 374         wait_queue_t            fence_wake;
 375 };
 376
 377 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 378 int radeon_fence_driver_init(struct radeon_device *rdev);
 379 void radeon_fence_driver_fini(struct radeon_device *rdev);
 380 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
 381 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 382 void radeon_fence_process(struct radeon_device *rdev, int ring);
 383 bool radeon_fence_signaled(struct radeon_fence *fence);
 384 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 385 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
 386 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
 387 int radeon_fence_wait_any(struct radeon_device *rdev,
 388                           struct radeon_fence **fences,
 389                           bool intr);
 390 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 391 void radeon_fence_unref(struct radeon_fence **fence);
 392 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 393 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
 394 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
 395 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
 396                                                       struct radeon_fence *b)
 397 {
 398         if (!a) {
 399                 return b;
 400         }
 401
 402         if (!b) {
 403                 return a;
 404         }
 405
 406         BUG_ON(a->ring != b->ring);
 407
 408         if (a->seq > b->seq) {
 409                 return a;
 410         } else {
 411                 return b;
 412         }
 413 }
 414
 415 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
 416                                            struct radeon_fence *b)
 417 {
 418         if (!a) {
 419                 return false;
 420         }
 421
 422         if (!b) {
 423                 return true;
 424         }
 425
 426         BUG_ON(a->ring != b->ring);
 427
 428         return a->seq < b->seq;
 429 }
 430
 431 /*
 432  * Tiling registers
 433  */
 434 struct radeon_surface_reg {
 435         struct radeon_bo *bo;
 436 };
 437
 438 #define RADEON_GEM_MAX_SURFACES 8
 439
 440 /*
 441  * TTM.
 442  */
 443 struct radeon_mman {
 444         struct ttm_bo_global_ref        bo_global_ref;
 445         struct drm_global_reference     mem_global_ref;
 446         struct ttm_bo_device            bdev;
 447         bool                            mem_global_referenced;
 448         bool                            initialized;
 449
 450 #if defined(CONFIG_DEBUG_FS)
 451         struct dentry                   *vram;
 452         struct dentry                   *gtt;
 453 #endif
 454 };
 455
 456 struct radeon_bo_list {
 457         struct radeon_bo                *robj;
 458         struct ttm_validate_buffer      tv;
 459         uint64_t                        gpu_offset;
 460         unsigned                        prefered_domains;
 461         unsigned                        allowed_domains;
 462         uint32_t                        tiling_flags;
 463 };
 464
 465 /* bo virtual address in a specific vm */
 466 struct radeon_bo_va {
 467         /* protected by bo being reserved */
 468         struct list_head                bo_list;
 469         uint32_t                        flags;
 470         struct radeon_fence             *last_pt_update;
 471         unsigned                        ref_count;
 472
 473         /* protected by vm mutex */
 474         struct interval_tree_node       it;
 475         struct list_head                vm_status;
 476
 477         /* constant after initialization */
 478         struct radeon_vm                *vm;
 479         struct radeon_bo                *bo;
 480 };
 481
 482 struct radeon_bo {
 483         /* Protected by gem.mutex */
 484         struct list_head                list;
 485         /* Protected by tbo.reserved */
 486         u32                             initial_domain;
 487         struct ttm_place                placements[4];
 488         struct ttm_placement            placement;
 489         struct ttm_buffer_object        tbo;
 490         struct ttm_bo_kmap_obj          kmap;
 491         u32                             flags;
 492         unsigned                        pin_count;
 493         void                            *kptr;
 494         u32                             tiling_flags;
 495         u32                             pitch;
 496         int                             surface_reg;
 497         /* list of all virtual address to which this bo
 498          * is associated to
 499          */
 500         struct list_head                va;
 501         /* Constant after initialization */
 502         struct radeon_device            *rdev;
 503         struct drm_gem_object           gem_base;
 504
 505         struct ttm_bo_kmap_obj          dma_buf_vmap;
 506         pid_t                           pid;
 507
 508         struct radeon_mn                *mn;
 509         struct list_head                mn_list;
 510 };
 511 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 512
 513 int radeon_gem_debugfs_init(struct radeon_device *rdev);
 514
 515 /* sub-allocation manager, it has to be protected by another lock.
 516  * By conception this is an helper for other part of the driver
 517  * like the indirect buffer or semaphore, which both have their
 518  * locking.
 519  *
 520  * Principe is simple, we keep a list of sub allocation in offset
 521  * order (first entry has offset == 0, last entry has the highest
 522  * offset).
 523  *
 524  * When allocating new object we first check if there is room at
 525  * the end total_size - (last_object_offset + last_object_size) >=
 526  * alloc_size. If so we allocate new object there.
 527  *
 528  * When there is not enough room at the end, we start waiting for
 529  * each sub object until we reach object_offset+object_size >=
 530  * alloc_size, this object then become the sub object we return.
 531  *
 532  * Alignment can't be bigger than page size.
 533  *
 534  * Hole are not considered for allocation to keep things simple.
 535  * Assumption is that there won't be hole (all object on same
 536  * alignment).
 537  */
 538 struct radeon_sa_manager {
 539         wait_queue_head_t       wq;
 540         struct radeon_bo        *bo;
 541         struct list_head        *hole;
 542         struct list_head        flist[RADEON_NUM_RINGS];
 543         struct list_head        olist;
 544         unsigned                size;
 545         uint64_t                gpu_addr;
 546         void                    *cpu_ptr;
 547         uint32_t                domain;
 548         uint32_t                align;
 549 };
 550
 551 struct radeon_sa_bo;
 552
 553 /* sub-allocation buffer */
 554 struct radeon_sa_bo {
 555         struct list_head                olist;
 556         struct list_head                flist;
 557         struct radeon_sa_manager        *manager;
 558         unsigned                        soffset;
 559         unsigned                        eoffset;
 560         struct radeon_fence             *fence;
 561 };
 562
 563 /*
 564  * GEM objects.
 565  */
 566 struct radeon_gem {
 567         struct mutex            mutex;
 568         struct list_head        objects;
 569 };
 570
 571 int radeon_gem_init(struct radeon_device *rdev);
 572 void radeon_gem_fini(struct radeon_device *rdev);
 573 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
 574                                 int alignment, int initial_domain,
 575                                 u32 flags, bool kernel,
 576                                 struct drm_gem_object **obj);
 577
 578 int radeon_mode_dumb_create(struct drm_file *file_priv,
 579                             struct drm_device *dev,
 580                             struct drm_mode_create_dumb *args);
 581 int radeon_mode_dumb_mmap(struct drm_file *filp,
 582                           struct drm_device *dev,
 583                           uint32_t handle, uint64_t *offset_p);
 584
 585 /*
 586  * Semaphores.
 587  */
 588 struct radeon_semaphore {
 589         struct radeon_sa_bo     *sa_bo;
 590         signed                  waiters;
 591         uint64_t                gpu_addr;
 592 };
 593
 594 int radeon_semaphore_create(struct radeon_device *rdev,
 595                             struct radeon_semaphore **semaphore);
 596 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 597                                   struct radeon_semaphore *semaphore);
 598 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 599                                 struct radeon_semaphore *semaphore);
 600 void radeon_semaphore_free(struct radeon_device *rdev,
 601                            struct radeon_semaphore **semaphore,
 602                            struct radeon_fence *fence);
 603
 604 /*
 605  * Synchronization
 606  */
 607 struct radeon_sync {
 608         struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
 609         struct radeon_fence     *sync_to[RADEON_NUM_RINGS];
 610         struct radeon_fence     *last_vm_update;
 611 };
 612
 613 void radeon_sync_create(struct radeon_sync *sync);
 614 void radeon_sync_fence(struct radeon_sync *sync,
 615                        struct radeon_fence *fence);
 616 int radeon_sync_resv(struct radeon_device *rdev,
 617                      struct radeon_sync *sync,
 618                      struct reservation_object *resv,
 619                      bool shared);
 620 int radeon_sync_rings(struct radeon_device *rdev,
 621                       struct radeon_sync *sync,
 622                       int waiting_ring);
 623 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
 624                       struct radeon_fence *fence);
 625
 626 /*
 627  * GART structures, functions & helpers
 628  */
 629 struct radeon_mc;
 630
 631 #define RADEON_GPU_PAGE_SIZE 4096
 632 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 633 #define RADEON_GPU_PAGE_SHIFT 12
 634 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 635
 636 #define RADEON_GART_PAGE_DUMMY  0
 637 #define RADEON_GART_PAGE_VALID  (1 << 0)
 638 #define RADEON_GART_PAGE_READ   (1 << 1)
 639 #define RADEON_GART_PAGE_WRITE  (1 << 2)
 640 #define RADEON_GART_PAGE_SNOOP  (1 << 3)
 641
 642 struct radeon_gart {
 643         dma_addr_t                      table_addr;
 644         struct radeon_bo                *robj;
 645         void                            *ptr;
 646         unsigned                        num_gpu_pages;
 647         unsigned                        num_cpu_pages;
 648         unsigned                        table_size;
 649         struct page                     **pages;
 650         uint64_t                        *pages_entry;
 651         bool                            ready;
 652 };
 653
 654 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 655 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 656 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 657 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 658 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 659 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 660 int radeon_gart_init(struct radeon_device *rdev);
 661 void radeon_gart_fini(struct radeon_device *rdev);
 662 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 663                         int pages);
 664 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 665                      int pages, struct page **pagelist,
 666                      dma_addr_t *dma_addr, uint32_t flags);
 667
 668
 669 /*
 670  * GPU MC structures, functions & helpers
 671  */
 672 struct radeon_mc {
 673         resource_size_t         aper_size;
 674         resource_size_t         aper_base;
 675         resource_size_t         agp_base;
 676         /* for some chips with <= 32MB we need to lie
 677          * about vram size near mc fb location */
 678         u64                     mc_vram_size;
 679         u64                     visible_vram_size;
 680         u64                     gtt_size;
 681         u64                     gtt_start;
 682         u64                     gtt_end;
 683         u64                     vram_start;
 684         u64                     vram_end;
 685         unsigned                vram_width;
 686         u64                     real_vram_size;
 687         int                     vram_mtrr;
 688         bool                    vram_is_ddr;
 689         bool                    igp_sideport_enabled;
 690         u64                     gtt_base_align;
 691         u64                     mc_mask;
 692 };
 693
 694 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 695 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 696
 697 /*
 698  * GPU scratch registers structures, functions & helpers
 699  */
 700 struct radeon_scratch {
 701         unsigned                num_reg;
 702         uint32_t                reg_base;
 703         bool                    free[32];
 704         uint32_t                reg[32];
 705 };
 706
 707 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 708 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 709
 710 /*
 711  * GPU doorbell structures, functions & helpers
 712  */
 713 #define RADEON_MAX_DOORBELLS 1024       /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
 714
 715 struct radeon_doorbell {
 716         /* doorbell mmio */
 717         resource_size_t         base;
 718         resource_size_t         size;
 719         u32 __iomem             *ptr;
 720         u32                     num_doorbells;  /* Number of doorbells actually reserved for radeon. */
 721         DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
 722 };
 723
 724 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
 725 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
 726 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
 727                                   phys_addr_t *aperture_base,
 728                                   size_t *aperture_size,
 729                                   size_t *start_offset);
 730
 731 /*
 732  * IRQS.
 733  */
 734
 735 struct radeon_flip_work {
 736         struct work_struct              flip_work;
 737         struct work_struct              unpin_work;
 738         struct radeon_device            *rdev;
 739         int                             crtc_id;
 740         uint64_t                        base;
 741         struct drm_pending_vblank_event *event;
 742         struct radeon_bo                *old_rbo;
 743         struct fence                    *fence;
 744 };
 745
 746 struct r500_irq_stat_regs {
 747         u32 disp_int;
 748         u32 hdmi0_status;
 749 };
 750
 751 struct r600_irq_stat_regs {
 752         u32 disp_int;
 753         u32 disp_int_cont;
 754         u32 disp_int_cont2;
 755         u32 d1grph_int;
 756         u32 d2grph_int;
 757         u32 hdmi0_status;
 758         u32 hdmi1_status;
 759 };
 760
 761 struct evergreen_irq_stat_regs {
 762         u32 disp_int;
 763         u32 disp_int_cont;
 764         u32 disp_int_cont2;
 765         u32 disp_int_cont3;
 766         u32 disp_int_cont4;
 767         u32 disp_int_cont5;
 768         u32 d1grph_int;
 769         u32 d2grph_int;
 770         u32 d3grph_int;
 771         u32 d4grph_int;
 772         u32 d5grph_int;
 773         u32 d6grph_int;
 774         u32 afmt_status1;
 775         u32 afmt_status2;
 776         u32 afmt_status3;
 777         u32 afmt_status4;
 778         u32 afmt_status5;
 779         u32 afmt_status6;
 780 };
 781
 782 struct cik_irq_stat_regs {
 783         u32 disp_int;
 784         u32 disp_int_cont;
 785         u32 disp_int_cont2;
 786         u32 disp_int_cont3;
 787         u32 disp_int_cont4;
 788         u32 disp_int_cont5;
 789         u32 disp_int_cont6;
 790         u32 d1grph_int;
 791         u32 d2grph_int;
 792         u32 d3grph_int;
 793         u32 d4grph_int;
 794         u32 d5grph_int;
 795         u32 d6grph_int;
 796 };
 797
 798 union radeon_irq_stat_regs {
 799         struct r500_irq_stat_regs r500;
 800         struct r600_irq_stat_regs r600;
 801         struct evergreen_irq_stat_regs evergreen;
 802         struct cik_irq_stat_regs cik;
 803 };
 804
 805 struct radeon_irq {
 806         bool                            installed;
 807         spinlock_t                      lock;
 808         atomic_t                        ring_int[RADEON_NUM_RINGS];
 809         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
 810         atomic_t                        pflip[RADEON_MAX_CRTCS];
 811         wait_queue_head_t               vblank_queue;
 812         bool                            hpd[RADEON_MAX_HPD_PINS];
 813         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
 814         union radeon_irq_stat_regs      stat_regs;
 815         bool                            dpm_thermal;
 816 };
 817
 818 int radeon_irq_kms_init(struct radeon_device *rdev);
 819 void radeon_irq_kms_fini(struct radeon_device *rdev);
 820 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 821 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
 822 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 823 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 824 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 825 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
 826 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
 827 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 828 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 829
 830 /*
 831  * CP & rings.
 832  */
 833
 834 struct radeon_ib {
 835         struct radeon_sa_bo             *sa_bo;
 836         uint32_t                        length_dw;
 837         uint64_t                        gpu_addr;
 838         uint32_t                        *ptr;
 839         int                             ring;
 840         struct radeon_fence             *fence;
 841         struct radeon_vm                *vm;
 842         bool                            is_const_ib;
 843         struct radeon_sync              sync;
 844 };
 845
 846 struct radeon_ring {
 847         struct radeon_bo        *ring_obj;
 848         volatile uint32_t       *ring;
 849         unsigned                rptr_offs;
 850         unsigned                rptr_save_reg;
 851         u64                     next_rptr_gpu_addr;
 852         volatile u32            *next_rptr_cpu_addr;
 853         unsigned                wptr;
 854         unsigned                wptr_old;
 855         unsigned                ring_size;
 856         unsigned                ring_free_dw;
 857         int                     count_dw;
 858         atomic_t                last_rptr;
 859         atomic64_t              last_activity;
 860         uint64_t                gpu_addr;
 861         uint32_t                align_mask;
 862         uint32_t                ptr_mask;
 863         bool                    ready;
 864         u32                     nop;
 865         u32                     idx;
 866         u64                     last_semaphore_signal_addr;
 867         u64                     last_semaphore_wait_addr;
 868         /* for CIK queues */
 869         u32 me;
 870         u32 pipe;
 871         u32 queue;
 872         struct radeon_bo        *mqd_obj;
 873         u32 doorbell_index;
 874         unsigned                wptr_offs;
 875 };
 876
 877 struct radeon_mec {
 878         struct radeon_bo        *hpd_eop_obj;
 879         u64                     hpd_eop_gpu_addr;
 880         u32 num_pipe;
 881         u32 num_mec;
 882         u32 num_queue;
 883 };
 884
 885 /*
 886  * VM
 887  */
 888
 889 /* maximum number of VMIDs */
 890 #define RADEON_NUM_VM   16
 891
 892 /* number of entries in page table */
 893 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
 894
 895 /* PTBs (Page Table Blocks) need to be aligned to 32K */
 896 #define RADEON_VM_PTB_ALIGN_SIZE   32768
 897 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
 898 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
 899
 900 #define R600_PTE_VALID          (1 << 0)
 901 #define R600_PTE_SYSTEM         (1 << 1)
 902 #define R600_PTE_SNOOPED        (1 << 2)
 903 #define R600_PTE_READABLE       (1 << 5)
 904 #define R600_PTE_WRITEABLE      (1 << 6)
 905
 906 /* PTE (Page Table Entry) fragment field for different page sizes */
 907 #define R600_PTE_FRAG_4KB       (0 << 7)
 908 #define R600_PTE_FRAG_64KB      (4 << 7)
 909 #define R600_PTE_FRAG_256KB     (6 << 7)
 910
 911 /* flags needed to be set so we can copy directly from the GART table */
 912 #define R600_PTE_GART_MASK      ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
 913                                   R600_PTE_SYSTEM | R600_PTE_VALID )
 914
 915 struct radeon_vm_pt {
 916         struct radeon_bo                *bo;
 917         uint64_t                        addr;
 918 };
 919
 920 struct radeon_vm_id {
 921         unsigned                id;
 922         uint64_t                pd_gpu_addr;
 923         /* last flushed PD/PT update */
 924         struct radeon_fence     *flushed_updates;
 925         /* last use of vmid */
 926         struct radeon_fence     *last_id_use;
 927 };
 928
 929 struct radeon_vm {
 930         struct mutex            mutex;
 931
 932         struct rb_root          va;
 933
 934         /* protecting invalidated and freed */
 935         spinlock_t              status_lock;
 936
 937         /* BOs moved, but not yet updated in the PT */
 938         struct list_head        invalidated;
 939
 940         /* BOs freed, but not yet updated in the PT */
 941         struct list_head        freed;
 942
 943         /* BOs cleared in the PT */
 944         struct list_head        cleared;
 945
 946         /* contains the page directory */
 947         struct radeon_bo        *page_directory;
 948         unsigned                max_pde_used;
 949
 950         /* array of page tables, one for each page directory entry */
 951         struct radeon_vm_pt     *page_tables;
 952
 953         struct radeon_bo_va     *ib_bo_va;
 954
 955         /* for id and flush management per ring */
 956         struct radeon_vm_id     ids[RADEON_NUM_RINGS];
 957 };
 958
 959 struct radeon_vm_manager {
 960         struct radeon_fence             *active[RADEON_NUM_VM];
 961         uint32_t                        max_pfn;
 962         /* number of VMIDs */
 963         unsigned                        nvm;
 964         /* vram base address for page table entry  */
 965         u64                             vram_base_offset;
 966         /* is vm enabled? */
 967         bool                            enabled;
 968         /* for hw to save the PD addr on suspend/resume */
 969         uint32_t                        saved_table_addr[RADEON_NUM_VM];
 970 };
 971
 972 /*
 973  * file private structure
 974  */
 975 struct radeon_fpriv {
 976         struct radeon_vm                vm;
 977 };
 978
 979 /*
 980  * R6xx+ IH ring
 981  */
 982 struct r600_ih {
 983         struct radeon_bo        *ring_obj;
 984         volatile uint32_t       *ring;
 985         unsigned                rptr;
 986         unsigned                ring_size;
 987         uint64_t                gpu_addr;
 988         uint32_t                ptr_mask;
 989         atomic_t                lock;
 990         bool                    enabled;
 991 };
 992
 993 /*
 994  * RLC stuff
 995  */
 996 #include "clearstate_defs.h"
 997
 998 struct radeon_rlc {
 999         /* for power gating */
1000         struct radeon_bo        *save_restore_obj;
1001         uint64_t                save_restore_gpu_addr;
1002         volatile uint32_t       *sr_ptr;
1003         const u32               *reg_list;
1004         u32                     reg_list_size;
1005         /* for clear state */
1006         struct radeon_bo        *clear_state_obj;
1007         uint64_t                clear_state_gpu_addr;
1008         volatile uint32_t       *cs_ptr;
1009         const struct cs_section_def   *cs_data;
1010         u32                     clear_state_size;
1011         /* for cp tables */
1012         struct radeon_bo        *cp_table_obj;
1013         uint64_t                cp_table_gpu_addr;
1014         volatile uint32_t       *cp_table_ptr;
1015         u32                     cp_table_size;
1016 };
1017
1018 int radeon_ib_get(struct radeon_device *rdev, int ring,
1019                   struct radeon_ib *ib, struct radeon_vm *vm,
1020                   unsigned size);
1021 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1022 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1023                        struct radeon_ib *const_ib, bool hdp_flush);
1024 int radeon_ib_pool_init(struct radeon_device *rdev);
1025 void radeon_ib_pool_fini(struct radeon_device *rdev);
1026 int radeon_ib_ring_tests(struct radeon_device *rdev);
1027 /* Ring access between begin & end cannot sleep */
1028 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1029                                       struct radeon_ring *ring);
1030 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1031 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1032 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1033 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1034                         bool hdp_flush);
1035 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1036                                bool hdp_flush);
1037 void radeon_ring_undo(struct radeon_ring *ring);
1038 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1039 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1040 void radeon_ring_lockup_update(struct radeon_device *rdev,
1041                                struct radeon_ring *ring);
1042 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1043 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1044                             uint32_t **data);
1045 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1046                         unsigned size, uint32_t *data);
1047 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1048                      unsigned rptr_offs, u32 nop);
1049 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1050
1051
1052 /* r600 async dma */
1053 void r600_dma_stop(struct radeon_device *rdev);
1054 int r600_dma_resume(struct radeon_device *rdev);
1055 void r600_dma_fini(struct radeon_device *rdev);
1056
1057 void cayman_dma_stop(struct radeon_device *rdev);
1058 int cayman_dma_resume(struct radeon_device *rdev);
1059 void cayman_dma_fini(struct radeon_device *rdev);
1060
1061 /*
1062  * CS.
1063  */
1064 struct radeon_cs_chunk {
1065         uint32_t                length_dw;
1066         uint32_t                *kdata;
1067         void __user             *user_ptr;
1068 };
1069
1070 struct radeon_cs_parser {
1071         struct device           *dev;
1072         struct radeon_device    *rdev;
1073         struct drm_file         *filp;
1074         /* chunks */
1075         unsigned                nchunks;
1076         struct radeon_cs_chunk  *chunks;
1077         uint64_t                *chunks_array;
1078         /* IB */
1079         unsigned                idx;
1080         /* relocations */
1081         unsigned                nrelocs;
1082         struct radeon_bo_list   *relocs;
1083         struct radeon_bo_list   *vm_bos;
1084         struct list_head        validated;
1085         unsigned                dma_reloc_idx;
1086         /* indices of various chunks */
1087         struct radeon_cs_chunk  *chunk_ib;
1088         struct radeon_cs_chunk  *chunk_relocs;
1089         struct radeon_cs_chunk  *chunk_flags;
1090         struct radeon_cs_chunk  *chunk_const_ib;
1091         struct radeon_ib        ib;
1092         struct radeon_ib        const_ib;
1093         void                    *track;
1094         unsigned                family;
1095         int                     parser_error;
1096         u32                     cs_flags;
1097         u32                     ring;
1098         s32                     priority;
1099         struct ww_acquire_ctx   ticket;
1100 };
1101
1102 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1103 {
1104         struct radeon_cs_chunk *ibc = p->chunk_ib;
1105
1106         if (ibc->kdata)
1107                 return ibc->kdata[idx];
1108         return p->ib.ptr[idx];
1109 }
1110
1111
1112 struct radeon_cs_packet {
1113         unsigned        idx;
1114         unsigned        type;
1115         unsigned        reg;
1116         unsigned        opcode;
1117         int             count;
1118         unsigned        one_reg_wr;
1119 };
1120
1121 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1122                                       struct radeon_cs_packet *pkt,
1123                                       unsigned idx, unsigned reg);
1124 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1125                                       struct radeon_cs_packet *pkt);
1126
1127
1128 /*
1129  * AGP
1130  */
1131 int radeon_agp_init(struct radeon_device *rdev);
1132 void radeon_agp_resume(struct radeon_device *rdev);
1133 void radeon_agp_suspend(struct radeon_device *rdev);
1134 void radeon_agp_fini(struct radeon_device *rdev);
1135
1136
1137 /*
1138  * Writeback
1139  */
1140 struct radeon_wb {
1141         struct radeon_bo        *wb_obj;
1142         volatile uint32_t       *wb;
1143         uint64_t                gpu_addr;
1144         bool                    enabled;
1145         bool                    use_event;
1146 };
1147
1148 #define RADEON_WB_SCRATCH_OFFSET 0
1149 #define RADEON_WB_RING0_NEXT_RPTR 256
1150 #define RADEON_WB_CP_RPTR_OFFSET 1024
1151 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1152 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1153 #define R600_WB_DMA_RPTR_OFFSET   1792
1154 #define R600_WB_IH_WPTR_OFFSET   2048
1155 #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
1156 #define R600_WB_EVENT_OFFSET     3072
1157 #define CIK_WB_CP1_WPTR_OFFSET     3328
1158 #define CIK_WB_CP2_WPTR_OFFSET     3584
1159 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1160 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1161
1162 /**
1163  * struct radeon_pm - power management datas
1164  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
1165  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1166  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
1167  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
1168  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
1169  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
1170  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1171  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
1172  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
1173  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
1174  * @needed_bandwidth:   current bandwidth needs
1175  *
1176  * It keeps track of various data needed to take powermanagement decision.
1177  * Bandwidth need is used to determine minimun clock of the GPU and memory.
1178  * Equation between gpu/memory clock and available bandwidth is hw dependent
1179  * (type of memory, bus size, efficiency, ...)
1180  */
1181
1182 enum radeon_pm_method {
1183         PM_METHOD_PROFILE,
1184         PM_METHOD_DYNPM,
1185         PM_METHOD_DPM,
1186 };
1187
1188 enum radeon_dynpm_state {
1189         DYNPM_STATE_DISABLED,
1190         DYNPM_STATE_MINIMUM,
1191         DYNPM_STATE_PAUSED,
1192         DYNPM_STATE_ACTIVE,
1193         DYNPM_STATE_SUSPENDED,
1194 };
1195 enum radeon_dynpm_action {
1196         DYNPM_ACTION_NONE,
1197         DYNPM_ACTION_MINIMUM,
1198         DYNPM_ACTION_DOWNCLOCK,
1199         DYNPM_ACTION_UPCLOCK,
1200         DYNPM_ACTION_DEFAULT
1201 };
1202
1203 enum radeon_voltage_type {
1204         VOLTAGE_NONE = 0,
1205         VOLTAGE_GPIO,
1206         VOLTAGE_VDDC,
1207         VOLTAGE_SW
1208 };
1209
1210 enum radeon_pm_state_type {
1211         /* not used for dpm */
1212         POWER_STATE_TYPE_DEFAULT,
1213         POWER_STATE_TYPE_POWERSAVE,
1214         /* user selectable states */
1215         POWER_STATE_TYPE_BATTERY,
1216         POWER_STATE_TYPE_BALANCED,
1217         POWER_STATE_TYPE_PERFORMANCE,
1218         /* internal states */
1219         POWER_STATE_TYPE_INTERNAL_UVD,
1220         POWER_STATE_TYPE_INTERNAL_UVD_SD,
1221         POWER_STATE_TYPE_INTERNAL_UVD_HD,
1222         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1223         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1224         POWER_STATE_TYPE_INTERNAL_BOOT,
1225         POWER_STATE_TYPE_INTERNAL_THERMAL,
1226         POWER_STATE_TYPE_INTERNAL_ACPI,
1227         POWER_STATE_TYPE_INTERNAL_ULV,
1228         POWER_STATE_TYPE_INTERNAL_3DPERF,
1229 };
1230
1231 enum radeon_pm_profile_type {
1232         PM_PROFILE_DEFAULT,
1233         PM_PROFILE_AUTO,
1234         PM_PROFILE_LOW,
1235         PM_PROFILE_MID,
1236         PM_PROFILE_HIGH,
1237 };
1238
1239 #define PM_PROFILE_DEFAULT_IDX 0
1240 #define PM_PROFILE_LOW_SH_IDX  1
1241 #define PM_PROFILE_MID_SH_IDX  2
1242 #define PM_PROFILE_HIGH_SH_IDX 3
1243 #define PM_PROFILE_LOW_MH_IDX  4
1244 #define PM_PROFILE_MID_MH_IDX  5
1245 #define PM_PROFILE_HIGH_MH_IDX 6
1246 #define PM_PROFILE_MAX         7
1247
1248 struct radeon_pm_profile {
1249         int dpms_off_ps_idx;
1250         int dpms_on_ps_idx;
1251         int dpms_off_cm_idx;
1252         int dpms_on_cm_idx;
1253 };
1254
1255 enum radeon_int_thermal_type {
1256         THERMAL_TYPE_NONE,
1257         THERMAL_TYPE_EXTERNAL,
1258         THERMAL_TYPE_EXTERNAL_GPIO,
1259         THERMAL_TYPE_RV6XX,
1260         THERMAL_TYPE_RV770,
1261         THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1262         THERMAL_TYPE_EVERGREEN,
1263         THERMAL_TYPE_SUMO,
1264         THERMAL_TYPE_NI,
1265         THERMAL_TYPE_SI,
1266         THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1267         THERMAL_TYPE_CI,
1268         THERMAL_TYPE_KV,
1269 };
1270
1271 struct radeon_voltage {
1272         enum radeon_voltage_type type;
1273         /* gpio voltage */
1274         struct radeon_gpio_rec gpio;
1275         u32 delay; /* delay in usec from voltage drop to sclk change */
1276         bool active_high; /* voltage drop is active when bit is high */
1277         /* VDDC voltage */
1278         u8 vddc_id; /* index into vddc voltage table */
1279         u8 vddci_id; /* index into vddci voltage table */
1280         bool vddci_enabled;
1281         /* r6xx+ sw */
1282         u16 voltage;
1283         /* evergreen+ vddci */
1284         u16 vddci;
1285 };
1286
1287 /* clock mode flags */
1288 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1289
1290 struct radeon_pm_clock_info {
1291         /* memory clock */
1292         u32 mclk;
1293         /* engine clock */
1294         u32 sclk;
1295         /* voltage info */
1296         struct radeon_voltage voltage;
1297         /* standardized clock flags */
1298         u32 flags;
1299 };
1300
1301 /* state flags */
1302 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1303
1304 struct radeon_power_state {
1305         enum radeon_pm_state_type type;
1306         struct radeon_pm_clock_info *clock_info;
1307         /* number of valid clock modes in this power state */
1308         int num_clock_modes;
1309         struct radeon_pm_clock_info *default_clock_mode;
1310         /* standardized state flags */
1311         u32 flags;
1312         u32 misc; /* vbios specific flags */
1313         u32 misc2; /* vbios specific flags */
1314         int pcie_lanes; /* pcie lanes */
1315 };
1316
1317 /*
1318  * Some modes are overclocked by very low value, accept them
1319  */
1320 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1321
1322 enum radeon_dpm_auto_throttle_src {
1323         RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1324         RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1325 };
1326
1327 enum radeon_dpm_event_src {
1328         RADEON_DPM_EVENT_SRC_ANALOG = 0,
1329         RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1330         RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1331         RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1332         RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1333 };
1334
1335 #define RADEON_MAX_VCE_LEVELS 6
1336
1337 enum radeon_vce_level {
1338         RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
1339         RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
1340         RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
1341         RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1342         RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
1343         RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1344 };
1345
1346 struct radeon_ps {
1347         u32 caps; /* vbios flags */
1348         u32 class; /* vbios flags */
1349         u32 class2; /* vbios flags */
1350         /* UVD clocks */
1351         u32 vclk;
1352         u32 dclk;
1353         /* VCE clocks */
1354         u32 evclk;
1355         u32 ecclk;
1356         bool vce_active;
1357         enum radeon_vce_level vce_level;
1358         /* asic priv */
1359         void *ps_priv;
1360 };
1361
1362 struct radeon_dpm_thermal {
1363         /* thermal interrupt work */
1364         struct work_struct work;
1365         /* low temperature threshold */
1366         int                min_temp;
1367         /* high temperature threshold */
1368         int                max_temp;
1369         /* was interrupt low to high or high to low */
1370         bool               high_to_low;
1371 };
1372
1373 enum radeon_clk_action
1374 {
1375         RADEON_SCLK_UP = 1,
1376         RADEON_SCLK_DOWN
1377 };
1378
1379 struct radeon_blacklist_clocks
1380 {
1381         u32 sclk;
1382         u32 mclk;
1383         enum radeon_clk_action action;
1384 };
1385
1386 struct radeon_clock_and_voltage_limits {
1387         u32 sclk;
1388         u32 mclk;
1389         u16 vddc;
1390         u16 vddci;
1391 };
1392
1393 struct radeon_clock_array {
1394         u32 count;
1395         u32 *values;
1396 };
1397
1398 struct radeon_clock_voltage_dependency_entry {
1399         u32 clk;
1400         u16 v;
1401 };
1402
1403 struct radeon_clock_voltage_dependency_table {
1404         u32 count;
1405         struct radeon_clock_voltage_dependency_entry *entries;
1406 };
1407
1408 union radeon_cac_leakage_entry {
1409         struct {
1410                 u16 vddc;
1411                 u32 leakage;
1412         };
1413         struct {
1414                 u16 vddc1;
1415                 u16 vddc2;
1416                 u16 vddc3;
1417         };
1418 };
1419
1420 struct radeon_cac_leakage_table {
1421         u32 count;
1422         union radeon_cac_leakage_entry *entries;
1423 };
1424
1425 struct radeon_phase_shedding_limits_entry {
1426         u16 voltage;
1427         u32 sclk;
1428         u32 mclk;
1429 };
1430
1431 struct radeon_phase_shedding_limits_table {
1432         u32 count;
1433         struct radeon_phase_shedding_limits_entry *entries;
1434 };
1435
1436 struct radeon_uvd_clock_voltage_dependency_entry {
1437         u32 vclk;
1438         u32 dclk;
1439         u16 v;
1440 };
1441
1442 struct radeon_uvd_clock_voltage_dependency_table {
1443         u8 count;
1444         struct radeon_uvd_clock_voltage_dependency_entry *entries;
1445 };
1446
1447 struct radeon_vce_clock_voltage_dependency_entry {
1448         u32 ecclk;
1449         u32 evclk;
1450         u16 v;
1451 };
1452
1453 struct radeon_vce_clock_voltage_dependency_table {
1454         u8 count;
1455         struct radeon_vce_clock_voltage_dependency_entry *entries;
1456 };
1457
1458 struct radeon_ppm_table {
1459         u8 ppm_design;
1460         u16 cpu_core_number;
1461         u32 platform_tdp;
1462         u32 small_ac_platform_tdp;
1463         u32 platform_tdc;
1464         u32 small_ac_platform_tdc;
1465         u32 apu_tdp;
1466         u32 dgpu_tdp;
1467         u32 dgpu_ulv_power;
1468         u32 tj_max;
1469 };
1470
1471 struct radeon_cac_tdp_table {
1472         u16 tdp;
1473         u16 configurable_tdp;
1474         u16 tdc;
1475         u16 battery_power_limit;
1476         u16 small_power_limit;
1477         u16 low_cac_leakage;
1478         u16 high_cac_leakage;
1479         u16 maximum_power_delivery_limit;
1480 };
1481
1482 struct radeon_dpm_dynamic_state {
1483         struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1484         struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1485         struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1486         struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1487         struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1488         struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1489         struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1490         struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1491         struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1492         struct radeon_clock_array valid_sclk_values;
1493         struct radeon_clock_array valid_mclk_values;
1494         struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1495         struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1496         u32 mclk_sclk_ratio;
1497         u32 sclk_mclk_delta;
1498         u16 vddc_vddci_delta;
1499         u16 min_vddc_for_pcie_gen2;
1500         struct radeon_cac_leakage_table cac_leakage_table;
1501         struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1502         struct radeon_ppm_table *ppm_table;
1503         struct radeon_cac_tdp_table *cac_tdp_table;
1504 };
1505
1506 struct radeon_dpm_fan {
1507         u16 t_min;
1508         u16 t_med;
1509         u16 t_high;
1510         u16 pwm_min;
1511         u16 pwm_med;
1512         u16 pwm_high;
1513         u8 t_hyst;
1514         u32 cycle_delay;
1515         u16 t_max;
1516         u8 control_mode;
1517         u16 default_max_fan_pwm;
1518         u16 default_fan_output_sensitivity;
1519         u16 fan_output_sensitivity;
1520         bool ucode_fan_control;
1521 };
1522
1523 enum radeon_pcie_gen {
1524         RADEON_PCIE_GEN1 = 0,
1525         RADEON_PCIE_GEN2 = 1,
1526         RADEON_PCIE_GEN3 = 2,
1527         RADEON_PCIE_GEN_INVALID = 0xffff
1528 };
1529
1530 enum radeon_dpm_forced_level {
1531         RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1532         RADEON_DPM_FORCED_LEVEL_LOW = 1,
1533         RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1534 };
1535
1536 struct radeon_vce_state {
1537         /* vce clocks */
1538         u32 evclk;
1539         u32 ecclk;
1540         /* gpu clocks */
1541         u32 sclk;
1542         u32 mclk;
1543         u8 clk_idx;
1544         u8 pstate;
1545 };
1546
1547 struct radeon_dpm {
1548         struct radeon_ps        *ps;
1549         /* number of valid power states */
1550         int                     num_ps;
1551         /* current power state that is active */
1552         struct radeon_ps        *current_ps;
1553         /* requested power state */
1554         struct radeon_ps        *requested_ps;
1555         /* boot up power state */
1556         struct radeon_ps        *boot_ps;
1557         /* default uvd power state */
1558         struct radeon_ps        *uvd_ps;
1559         /* vce requirements */
1560         struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1561         enum radeon_vce_level vce_level;
1562         enum radeon_pm_state_type state;
1563         enum radeon_pm_state_type user_state;
1564         u32                     platform_caps;
1565         u32                     voltage_response_time;
1566         u32                     backbias_response_time;
1567         void                    *priv;
1568         u32                     new_active_crtcs;
1569         int                     new_active_crtc_count;
1570         u32                     current_active_crtcs;
1571         int                     current_active_crtc_count;
1572         bool single_display;
1573         struct radeon_dpm_dynamic_state dyn_state;
1574         struct radeon_dpm_fan fan;
1575         u32 tdp_limit;
1576         u32 near_tdp_limit;
1577         u32 near_tdp_limit_adjusted;
1578         u32 sq_ramping_threshold;
1579         u32 cac_leakage;
1580         u16 tdp_od_limit;
1581         u32 tdp_adjustment;
1582         u16 load_line_slope;
1583         bool power_control;
1584         bool ac_power;
1585         /* special states active */
1586         bool                    thermal_active;
1587         bool                    uvd_active;
1588         bool                    vce_active;
1589         /* thermal handling */
1590         struct radeon_dpm_thermal thermal;
1591         /* forced levels */
1592         enum radeon_dpm_forced_level forced_level;
1593         /* track UVD streams */
1594         unsigned sd;
1595         unsigned hd;
1596 };
1597
1598 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1599 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1600
1601 struct radeon_pm {
1602         struct mutex            mutex;
1603         /* write locked while reprogramming mclk */
1604         struct rw_semaphore     mclk_lock;
1605         u32                     active_crtcs;
1606         int                     active_crtc_count;
1607         int                     req_vblank;
1608         bool                    vblank_sync;
1609         fixed20_12              max_bandwidth;
1610         fixed20_12              igp_sideport_mclk;
1611         fixed20_12              igp_system_mclk;
1612         fixed20_12              igp_ht_link_clk;
1613         fixed20_12              igp_ht_link_width;
1614         fixed20_12              k8_bandwidth;
1615         fixed20_12              sideport_bandwidth;
1616         fixed20_12              ht_bandwidth;
1617         fixed20_12              core_bandwidth;
1618         fixed20_12              sclk;
1619         fixed20_12              mclk;
1620         fixed20_12              needed_bandwidth;
1621         struct radeon_power_state *power_state;
1622         /* number of valid power states */
1623         int                     num_power_states;
1624         int                     current_power_state_index;
1625         int                     current_clock_mode_index;
1626         int                     requested_power_state_index;
1627         int                     requested_clock_mode_index;
1628         int                     default_power_state_index;
1629         u32                     current_sclk;
1630         u32                     current_mclk;
1631         u16                     current_vddc;
1632         u16                     current_vddci;
1633         u32                     default_sclk;
1634         u32                     default_mclk;
1635         u16                     default_vddc;
1636         u16                     default_vddci;
1637         struct radeon_i2c_chan *i2c_bus;
1638         /* selected pm method */
1639         enum radeon_pm_method     pm_method;
1640         /* dynpm power management */
1641         struct delayed_work     dynpm_idle_work;
1642         enum radeon_dynpm_state dynpm_state;
1643         enum radeon_dynpm_action        dynpm_planned_action;
1644         unsigned long           dynpm_action_timeout;
1645         bool                    dynpm_can_upclock;
1646         bool                    dynpm_can_downclock;
1647         /* profile-based power management */
1648         enum radeon_pm_profile_type profile;
1649         int                     profile_index;
1650         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1651         /* internal thermal controller on rv6xx+ */
1652         enum radeon_int_thermal_type int_thermal_type;
1653         struct device           *int_hwmon_dev;
1654         /* fan control parameters */
1655         bool                    no_fan;
1656         u8                      fan_pulses_per_revolution;
1657         u8                      fan_min_rpm;
1658         u8                      fan_max_rpm;
1659         /* dpm */
1660         bool                    dpm_enabled;
1661         bool                    sysfs_initialized;
1662         struct radeon_dpm       dpm;
1663 };
1664
1665 int radeon_pm_get_type_index(struct radeon_device *rdev,
1666                              enum radeon_pm_state_type ps_type,
1667                              int instance);
1668 /*
1669  * UVD
1670  */
1671 #define RADEON_MAX_UVD_HANDLES  10
1672 #define RADEON_UVD_STACK_SIZE   (1024*1024)
1673 #define RADEON_UVD_HEAP_SIZE    (1024*1024)
1674
1675 struct radeon_uvd {
1676         struct radeon_bo        *vcpu_bo;
1677         void                    *cpu_addr;
1678         uint64_t                gpu_addr;
1679         atomic_t                handles[RADEON_MAX_UVD_HANDLES];
1680         struct drm_file         *filp[RADEON_MAX_UVD_HANDLES];
1681         unsigned                img_size[RADEON_MAX_UVD_HANDLES];
1682         struct delayed_work     idle_work;
1683 };
1684
1685 int radeon_uvd_init(struct radeon_device *rdev);
1686 void radeon_uvd_fini(struct radeon_device *rdev);
1687 int radeon_uvd_suspend(struct radeon_device *rdev);
1688 int radeon_uvd_resume(struct radeon_device *rdev);
1689 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1690                               uint32_t handle, struct radeon_fence **fence);
1691 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1692                                uint32_t handle, struct radeon_fence **fence);
1693 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1694                                        uint32_t allowed_domains);
1695 void radeon_uvd_free_handles(struct radeon_device *rdev,
1696                              struct drm_file *filp);
1697 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1698 void radeon_uvd_note_usage(struct radeon_device *rdev);
1699 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1700                                   unsigned vclk, unsigned dclk,
1701                                   unsigned vco_min, unsigned vco_max,
1702                                   unsigned fb_factor, unsigned fb_mask,
1703                                   unsigned pd_min, unsigned pd_max,
1704                                   unsigned pd_even,
1705                                   unsigned *optimal_fb_div,
1706                                   unsigned *optimal_vclk_div,
1707                                   unsigned *optimal_dclk_div);
1708 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1709                                 unsigned cg_upll_func_cntl);
1710
1711 /*
1712  * VCE
1713  */
1714 #define RADEON_MAX_VCE_HANDLES  16
1715
1716 struct radeon_vce {
1717         struct radeon_bo        *vcpu_bo;
1718         uint64_t                gpu_addr;
1719         unsigned                fw_version;
1720         unsigned                fb_version;
1721         atomic_t                handles[RADEON_MAX_VCE_HANDLES];
1722         struct drm_file         *filp[RADEON_MAX_VCE_HANDLES];
1723         unsigned                img_size[RADEON_MAX_VCE_HANDLES];
1724         struct delayed_work     idle_work;
1725         uint32_t                keyselect;
1726 };
1727
1728 int radeon_vce_init(struct radeon_device *rdev);
1729 void radeon_vce_fini(struct radeon_device *rdev);
1730 int radeon_vce_suspend(struct radeon_device *rdev);
1731 int radeon_vce_resume(struct radeon_device *rdev);
1732 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1733                               uint32_t handle, struct radeon_fence **fence);
1734 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1735                                uint32_t handle, struct radeon_fence **fence);
1736 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1737 void radeon_vce_note_usage(struct radeon_device *rdev);
1738 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1739 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1740 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1741                                struct radeon_ring *ring,
1742                                struct radeon_semaphore *semaphore,
1743                                bool emit_wait);
1744 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1745 void radeon_vce_fence_emit(struct radeon_device *rdev,
1746                            struct radeon_fence *fence);
1747 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1748 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1749
1750 struct r600_audio_pin {
1751         int                     channels;
1752         int                     rate;
1753         int                     bits_per_sample;
1754         u8                      status_bits;
1755         u8                      category_code;
1756         u32                     offset;
1757         bool                    connected;
1758         u32                     id;
1759 };
1760
1761 struct r600_audio {
1762         bool enabled;
1763         struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1764         int num_pins;
1765         struct radeon_audio_funcs *hdmi_funcs;
1766         struct radeon_audio_funcs *dp_funcs;
1767         struct radeon_audio_basic_funcs *funcs;
1768 };
1769
1770 /*
1771  * Benchmarking
1772  */
1773 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1774
1775
1776 /*
1777  * Testing
1778  */
1779 void radeon_test_moves(struct radeon_device *rdev);
1780 void radeon_test_ring_sync(struct radeon_device *rdev,
1781                            struct radeon_ring *cpA,
1782                            struct radeon_ring *cpB);
1783 void radeon_test_syncing(struct radeon_device *rdev);
1784
1785 /*
1786  * MMU Notifier
1787  */
1788 #if defined(CONFIG_MMU_NOTIFIER)
1789 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1790 void radeon_mn_unregister(struct radeon_bo *bo);
1791 #else
1792 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1793 {
1794         return -ENODEV;
1795 }
1796 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1797 #endif
1798
1799 /*
1800  * Debugfs
1801  */
1802 struct radeon_debugfs {
1803         struct drm_info_list    *files;
1804         unsigned                num_files;
1805 };
1806
1807 int radeon_debugfs_add_files(struct radeon_device *rdev,
1808                              struct drm_info_list *files,
1809                              unsigned nfiles);
1810 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1811
1812 /*
1813  * ASIC ring specific functions.
1814  */
1815 struct radeon_asic_ring {
1816         /* ring read/write ptr handling */
1817         u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1818         u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1819         void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1820
1821         /* validating and patching of IBs */
1822         int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1823         int (*cs_parse)(struct radeon_cs_parser *p);
1824
1825         /* command emmit functions */
1826         void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1827         void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1828         void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1829         bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1830                                struct radeon_semaphore *semaphore, bool emit_wait);
1831         void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1832                          unsigned vm_id, uint64_t pd_addr);
1833
1834         /* testing functions */
1835         int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1836         int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1837         bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1838
1839         /* deprecated */
1840         void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1841 };
1842
1843 /*
1844  * ASIC specific functions.
1845  */
1846 struct radeon_asic {
1847         int (*init)(struct radeon_device *rdev);
1848         void (*fini)(struct radeon_device *rdev);
1849         int (*resume)(struct radeon_device *rdev);
1850         int (*suspend)(struct radeon_device *rdev);
1851         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1852         int (*asic_reset)(struct radeon_device *rdev);
1853         /* Flush the HDP cache via MMIO */
1854         void (*mmio_hdp_flush)(struct radeon_device *rdev);
1855         /* check if 3D engine is idle */
1856         bool (*gui_idle)(struct radeon_device *rdev);
1857         /* wait for mc_idle */
1858         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1859         /* get the reference clock */
1860         u32 (*get_xclk)(struct radeon_device *rdev);
1861         /* get the gpu clock counter */
1862         uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1863         /* get register for info ioctl */
1864         int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1865         /* gart */
1866         struct {
1867                 void (*tlb_flush)(struct radeon_device *rdev);
1868                 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1869                 void (*set_page)(struct radeon_device *rdev, unsigned i,
1870                                  uint64_t entry);
1871         } gart;
1872         struct {
1873                 int (*init)(struct radeon_device *rdev);
1874                 void (*fini)(struct radeon_device *rdev);
1875                 void (*copy_pages)(struct radeon_device *rdev,
1876                                    struct radeon_ib *ib,
1877                                    uint64_t pe, uint64_t src,
1878                                    unsigned count);
1879                 void (*write_pages)(struct radeon_device *rdev,
1880                                     struct radeon_ib *ib,
1881                                     uint64_t pe,
1882                                     uint64_t addr, unsigned count,
1883                                     uint32_t incr, uint32_t flags);
1884                 void (*set_pages)(struct radeon_device *rdev,
1885                                   struct radeon_ib *ib,
1886                                   uint64_t pe,
1887                                   uint64_t addr, unsigned count,
1888                                   uint32_t incr, uint32_t flags);
1889                 void (*pad_ib)(struct radeon_ib *ib);
1890         } vm;
1891         /* ring specific callbacks */
1892         struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1893         /* irqs */
1894         struct {
1895                 int (*set)(struct radeon_device *rdev);
1896                 int (*process)(struct radeon_device *rdev);
1897         } irq;
1898         /* displays */
1899         struct {
1900                 /* display watermarks */
1901                 void (*bandwidth_update)(struct radeon_device *rdev);
1902                 /* get frame count */
1903                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1904                 /* wait for vblank */
1905                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1906                 /* set backlight level */
1907                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1908                 /* get backlight level */
1909                 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1910                 /* audio callbacks */
1911                 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1912                 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1913         } display;
1914         /* copy functions for bo handling */
1915         struct {
1916                 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1917                                              uint64_t src_offset,
1918                                              uint64_t dst_offset,
1919                                              unsigned num_gpu_pages,
1920                                              struct reservation_object *resv);
1921                 u32 blit_ring_index;
1922                 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1923                                             uint64_t src_offset,
1924                                             uint64_t dst_offset,
1925                                             unsigned num_gpu_pages,
1926                                             struct reservation_object *resv);
1927                 u32 dma_ring_index;
1928                 /* method used for bo copy */
1929                 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1930                                              uint64_t src_offset,
1931                                              uint64_t dst_offset,
1932                                              unsigned num_gpu_pages,
1933                                              struct reservation_object *resv);
1934                 /* ring used for bo copies */
1935                 u32 copy_ring_index;
1936         } copy;
1937         /* surfaces */
1938         struct {
1939                 int (*set_reg)(struct radeon_device *rdev, int reg,
1940                                        uint32_t tiling_flags, uint32_t pitch,
1941                                        uint32_t offset, uint32_t obj_size);
1942                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1943         } surface;
1944         /* hotplug detect */
1945         struct {
1946                 void (*init)(struct radeon_device *rdev);
1947                 void (*fini)(struct radeon_device *rdev);
1948                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1949                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1950         } hpd;
1951         /* static power management */
1952         struct {
1953                 void (*misc)(struct radeon_device *rdev);
1954                 void (*prepare)(struct radeon_device *rdev);
1955                 void (*finish)(struct radeon_device *rdev);
1956                 void (*init_profile)(struct radeon_device *rdev);
1957                 void (*get_dynpm_state)(struct radeon_device *rdev);
1958                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1959                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1960                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1961                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1962                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1963                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1964                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1965                 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1966                 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1967                 int (*get_temperature)(struct radeon_device *rdev);
1968         } pm;
1969         /* dynamic power management */
1970         struct {
1971                 int (*init)(struct radeon_device *rdev);
1972                 void (*setup_asic)(struct radeon_device *rdev);
1973                 int (*enable)(struct radeon_device *rdev);
1974                 int (*late_enable)(struct radeon_device *rdev);
1975                 void (*disable)(struct radeon_device *rdev);
1976                 int (*pre_set_power_state)(struct radeon_device *rdev);
1977                 int (*set_power_state)(struct radeon_device *rdev);
1978                 void (*post_set_power_state)(struct radeon_device *rdev);
1979                 void (*display_configuration_changed)(struct radeon_device *rdev);
1980                 void (*fini)(struct radeon_device *rdev);
1981                 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1982                 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1983                 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1984                 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1985                 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1986                 bool (*vblank_too_short)(struct radeon_device *rdev);
1987                 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1988                 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1989                 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1990                 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1991                 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1992                 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1993                 u32 (*get_current_sclk)(struct radeon_device *rdev);
1994                 u32 (*get_current_mclk)(struct radeon_device *rdev);
1995         } dpm;
1996         /* pageflipping */
1997         struct {
1998                 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1999                 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2000         } pflip;
2001 };
2002
2003 /*
2004  * Asic structures
2005  */
2006 struct r100_asic {
2007         const unsigned          *reg_safe_bm;
2008         unsigned                reg_safe_bm_size;
2009         u32                     hdp_cntl;
2010 };
2011
2012 struct r300_asic {
2013         const unsigned          *reg_safe_bm;
2014         unsigned                reg_safe_bm_size;
2015         u32                     resync_scratch;
2016         u32                     hdp_cntl;
2017 };
2018
2019 struct r600_asic {
2020         unsigned                max_pipes;
2021         unsigned                max_tile_pipes;
2022         unsigned                max_simds;
2023         unsigned                max_backends;
2024         unsigned                max_gprs;
2025         unsigned                max_threads;
2026         unsigned                max_stack_entries;
2027         unsigned                max_hw_contexts;
2028         unsigned                max_gs_threads;
2029         unsigned                sx_max_export_size;
2030         unsigned                sx_max_export_pos_size;
2031         unsigned                sx_max_export_smx_size;
2032         unsigned                sq_num_cf_insts;
2033         unsigned                tiling_nbanks;
2034         unsigned                tiling_npipes;
2035         unsigned                tiling_group_size;
2036         unsigned                tile_config;
2037         unsigned                backend_map;
2038         unsigned                active_simds;
2039 };
2040
2041 struct rv770_asic {
2042         unsigned                max_pipes;
2043         unsigned                max_tile_pipes;
2044         unsigned                max_simds;
2045         unsigned                max_backends;
2046         unsigned                max_gprs;
2047         unsigned                max_threads;
2048         unsigned                max_stack_entries;
2049         unsigned                max_hw_contexts;
2050         unsigned                max_gs_threads;
2051         unsigned                sx_max_export_size;
2052         unsigned                sx_max_export_pos_size;
2053         unsigned                sx_max_export_smx_size;
2054         unsigned                sq_num_cf_insts;
2055         unsigned                sx_num_of_sets;
2056         unsigned                sc_prim_fifo_size;
2057         unsigned                sc_hiz_tile_fifo_size;
2058         unsigned                sc_earlyz_tile_fifo_fize;
2059         unsigned                tiling_nbanks;
2060         unsigned                tiling_npipes;
2061         unsigned                tiling_group_size;
2062         unsigned                tile_config;
2063         unsigned                backend_map;
2064         unsigned                active_simds;
2065 };
2066
2067 struct evergreen_asic {
2068         unsigned num_ses;
2069         unsigned max_pipes;
2070         unsigned max_tile_pipes;
2071         unsigned max_simds;
2072         unsigned max_backends;
2073         unsigned max_gprs;
2074         unsigned max_threads;
2075         unsigned max_stack_entries;
2076         unsigned max_hw_contexts;
2077         unsigned max_gs_threads;
2078         unsigned sx_max_export_size;
2079         unsigned sx_max_export_pos_size;
2080         unsigned sx_max_export_smx_size;
2081         unsigned sq_num_cf_insts;
2082         unsigned sx_num_of_sets;
2083         unsigned sc_prim_fifo_size;
2084         unsigned sc_hiz_tile_fifo_size;
2085         unsigned sc_earlyz_tile_fifo_size;
2086         unsigned tiling_nbanks;
2087         unsigned tiling_npipes;
2088         unsigned tiling_group_size;
2089         unsigned tile_config;
2090         unsigned backend_map;
2091         unsigned active_simds;
2092 };
2093
2094 struct cayman_asic {
2095         unsigned max_shader_engines;
2096         unsigned max_pipes_per_simd;
2097         unsigned max_tile_pipes;
2098         unsigned max_simds_per_se;
2099         unsigned max_backends_per_se;
2100         unsigned max_texture_channel_caches;
2101         unsigned max_gprs;
2102         unsigned max_threads;
2103         unsigned max_gs_threads;
2104         unsigned max_stack_entries;
2105         unsigned sx_num_of_sets;
2106         unsigned sx_max_export_size;
2107         unsigned sx_max_export_pos_size;
2108         unsigned sx_max_export_smx_size;
2109         unsigned max_hw_contexts;
2110         unsigned sq_num_cf_insts;
2111         unsigned sc_prim_fifo_size;
2112         unsigned sc_hiz_tile_fifo_size;
2113         unsigned sc_earlyz_tile_fifo_size;
2114
2115         unsigned num_shader_engines;
2116         unsigned num_shader_pipes_per_simd;
2117         unsigned num_tile_pipes;
2118         unsigned num_simds_per_se;
2119         unsigned num_backends_per_se;
2120         unsigned backend_disable_mask_per_asic;
2121         unsigned backend_map;
2122         unsigned num_texture_channel_caches;
2123         unsigned mem_max_burst_length_bytes;
2124         unsigned mem_row_size_in_kb;
2125         unsigned shader_engine_tile_size;
2126         unsigned num_gpus;
2127         unsigned multi_gpu_tile_size;
2128
2129         unsigned tile_config;
2130         unsigned active_simds;
2131 };
2132
2133 struct si_asic {
2134         unsigned max_shader_engines;
2135         unsigned max_tile_pipes;
2136         unsigned max_cu_per_sh;
2137         unsigned max_sh_per_se;
2138         unsigned max_backends_per_se;
2139         unsigned max_texture_channel_caches;
2140         unsigned max_gprs;
2141         unsigned max_gs_threads;
2142         unsigned max_hw_contexts;
2143         unsigned sc_prim_fifo_size_frontend;
2144         unsigned sc_prim_fifo_size_backend;
2145         unsigned sc_hiz_tile_fifo_size;
2146         unsigned sc_earlyz_tile_fifo_size;
2147
2148         unsigned num_tile_pipes;
2149         unsigned backend_enable_mask;
2150         unsigned backend_disable_mask_per_asic;
2151         unsigned backend_map;
2152         unsigned num_texture_channel_caches;
2153         unsigned mem_max_burst_length_bytes;
2154         unsigned mem_row_size_in_kb;
2155         unsigned shader_engine_tile_size;
2156         unsigned num_gpus;
2157         unsigned multi_gpu_tile_size;
2158
2159         unsigned tile_config;
2160         uint32_t tile_mode_array[32];
2161         uint32_t active_cus;
2162 };
2163
2164 struct cik_asic {
2165         unsigned max_shader_engines;
2166         unsigned max_tile_pipes;
2167         unsigned max_cu_per_sh;
2168         unsigned max_sh_per_se;
2169         unsigned max_backends_per_se;
2170         unsigned max_texture_channel_caches;
2171         unsigned max_gprs;
2172         unsigned max_gs_threads;
2173         unsigned max_hw_contexts;
2174         unsigned sc_prim_fifo_size_frontend;
2175         unsigned sc_prim_fifo_size_backend;
2176         unsigned sc_hiz_tile_fifo_size;
2177         unsigned sc_earlyz_tile_fifo_size;
2178
2179         unsigned num_tile_pipes;
2180         unsigned backend_enable_mask;
2181         unsigned backend_disable_mask_per_asic;
2182         unsigned backend_map;
2183         unsigned num_texture_channel_caches;
2184         unsigned mem_max_burst_length_bytes;
2185         unsigned mem_row_size_in_kb;
2186         unsigned shader_engine_tile_size;
2187         unsigned num_gpus;
2188         unsigned multi_gpu_tile_size;
2189
2190         unsigned tile_config;
2191         uint32_t tile_mode_array[32];
2192         uint32_t macrotile_mode_array[16];
2193         uint32_t active_cus;
2194 };
2195
2196 union radeon_asic_config {
2197         struct r300_asic        r300;
2198         struct r100_asic        r100;
2199         struct r600_asic        r600;
2200         struct rv770_asic       rv770;
2201         struct evergreen_asic   evergreen;
2202         struct cayman_asic      cayman;
2203         struct si_asic          si;
2204         struct cik_asic         cik;
2205 };
2206
2207 /*
2208  * asic initizalization from radeon_asic.c
2209  */
2210 void radeon_agp_disable(struct radeon_device *rdev);
2211 int radeon_asic_init(struct radeon_device *rdev);
2212
2213
2214 /*
2215  * IOCTL.
2216  */
2217 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2218                           struct drm_file *filp);
2219 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2220                             struct drm_file *filp);
2221 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2222                              struct drm_file *filp);
2223 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2224                          struct drm_file *file_priv);
2225 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2226                            struct drm_file *file_priv);
2227 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2228                             struct drm_file *file_priv);
2229 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2230                            struct drm_file *file_priv);
2231 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2232                                 struct drm_file *filp);
2233 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2234                           struct drm_file *filp);
2235 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2236                           struct drm_file *filp);
2237 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2238                               struct drm_file *filp);
2239 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2240                           struct drm_file *filp);
2241 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2242                         struct drm_file *filp);
2243 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2244 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2245                                 struct drm_file *filp);
2246 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2247                                 struct drm_file *filp);
2248
2249 /* VRAM scratch page for HDP bug, default vram page */
2250 struct r600_vram_scratch {
2251         struct radeon_bo                *robj;
2252         volatile uint32_t               *ptr;
2253         u64                             gpu_addr;
2254 };
2255
2256 /*
2257  * ACPI
2258  */
2259 struct radeon_atif_notification_cfg {
2260         bool enabled;
2261         int command_code;
2262 };
2263
2264 struct radeon_atif_notifications {
2265         bool display_switch;
2266         bool expansion_mode_change;
2267         bool thermal_state;
2268         bool forced_power_state;
2269         bool system_power_state;
2270         bool display_conf_change;
2271         bool px_gfx_switch;
2272         bool brightness_change;
2273         bool dgpu_display_event;
2274 };
2275
2276 struct radeon_atif_functions {
2277         bool system_params;
2278         bool sbios_requests;
2279         bool select_active_disp;
2280         bool lid_state;
2281         bool get_tv_standard;
2282         bool set_tv_standard;
2283         bool get_panel_expansion_mode;
2284         bool set_panel_expansion_mode;
2285         bool temperature_change;
2286         bool graphics_device_types;
2287 };
2288
2289 struct radeon_atif {
2290         struct radeon_atif_notifications notifications;
2291         struct radeon_atif_functions functions;
2292         struct radeon_atif_notification_cfg notification_cfg;
2293         struct radeon_encoder *encoder_for_bl;
2294 };
2295
2296 struct radeon_atcs_functions {
2297         bool get_ext_state;
2298         bool pcie_perf_req;
2299         bool pcie_dev_rdy;
2300         bool pcie_bus_width;
2301 };
2302
2303 struct radeon_atcs {
2304         struct radeon_atcs_functions functions;
2305 };
2306
2307 /*
2308  * Core structure, functions and helpers.
2309  */
2310 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2311 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2312
2313 struct radeon_device {
2314         struct device                   *dev;
2315         struct drm_device               *ddev;
2316         struct pci_dev                  *pdev;
2317         struct rw_semaphore             exclusive_lock;
2318         /* ASIC */
2319         union radeon_asic_config        config;
2320         enum radeon_family              family;
2321         unsigned long                   flags;
2322         int                             usec_timeout;
2323         enum radeon_pll_errata          pll_errata;
2324         int                             num_gb_pipes;
2325         int                             num_z_pipes;
2326         int                             disp_priority;
2327         /* BIOS */
2328         uint8_t                         *bios;
2329         bool                            is_atom_bios;
2330         uint16_t                        bios_header_start;
2331         struct radeon_bo                *stollen_vga_memory;
2332         /* Register mmio */
2333         resource_size_t                 rmmio_base;
2334         resource_size_t                 rmmio_size;
2335         /* protects concurrent MM_INDEX/DATA based register access */
2336         spinlock_t mmio_idx_lock;
2337         /* protects concurrent SMC based register access */
2338         spinlock_t smc_idx_lock;
2339         /* protects concurrent PLL register access */
2340         spinlock_t pll_idx_lock;
2341         /* protects concurrent MC register access */
2342         spinlock_t mc_idx_lock;
2343         /* protects concurrent PCIE register access */
2344         spinlock_t pcie_idx_lock;
2345         /* protects concurrent PCIE_PORT register access */
2346         spinlock_t pciep_idx_lock;
2347         /* protects concurrent PIF register access */
2348         spinlock_t pif_idx_lock;
2349         /* protects concurrent CG register access */
2350         spinlock_t cg_idx_lock;
2351         /* protects concurrent UVD register access */
2352         spinlock_t uvd_idx_lock;
2353         /* protects concurrent RCU register access */
2354         spinlock_t rcu_idx_lock;
2355         /* protects concurrent DIDT register access */
2356         spinlock_t didt_idx_lock;
2357         /* protects concurrent ENDPOINT (audio) register access */
2358         spinlock_t end_idx_lock;
2359         void __iomem                    *rmmio;
2360         radeon_rreg_t                   mc_rreg;
2361         radeon_wreg_t                   mc_wreg;
2362         radeon_rreg_t                   pll_rreg;
2363         radeon_wreg_t                   pll_wreg;
2364         uint32_t                        pcie_reg_mask;
2365         radeon_rreg_t                   pciep_rreg;
2366         radeon_wreg_t                   pciep_wreg;
2367         /* io port */
2368         void __iomem                    *rio_mem;
2369         resource_size_t                 rio_mem_size;
2370         struct radeon_clock             clock;
2371         struct radeon_mc                mc;
2372         struct radeon_gart              gart;
2373         struct radeon_mode_info         mode_info;
2374         struct radeon_scratch           scratch;
2375         struct radeon_doorbell          doorbell;
2376         struct radeon_mman              mman;
2377         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
2378         wait_queue_head_t               fence_queue;
2379         unsigned                        fence_context;
2380         struct mutex                    ring_lock;
2381         struct radeon_ring              ring[RADEON_NUM_RINGS];
2382         bool                            ib_pool_ready;
2383         struct radeon_sa_manager        ring_tmp_bo;
2384         struct radeon_irq               irq;
2385         struct radeon_asic              *asic;
2386         struct radeon_gem               gem;
2387         struct radeon_pm                pm;
2388         struct radeon_uvd               uvd;
2389         struct radeon_vce               vce;
2390         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2391         struct radeon_wb                wb;
2392         struct radeon_dummy_page        dummy_page;
2393         bool                            shutdown;
2394         bool                            suspend;
2395         bool                            need_dma32;
2396         bool                            accel_working;
2397         bool                            fastfb_working; /* IGP feature*/
2398         bool                            needs_reset, in_reset;
2399         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2400         const struct firmware *me_fw;   /* all family ME firmware */
2401         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
2402         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
2403         const struct firmware *mc_fw;   /* NI MC firmware */
2404         const struct firmware *ce_fw;   /* SI CE firmware */
2405         const struct firmware *mec_fw;  /* CIK MEC firmware */
2406         const struct firmware *mec2_fw; /* KV MEC2 firmware */
2407         const struct firmware *sdma_fw; /* CIK SDMA firmware */
2408         const struct firmware *smc_fw;  /* SMC firmware */
2409         const struct firmware *uvd_fw;  /* UVD firmware */
2410         const struct firmware *vce_fw;  /* VCE firmware */
2411         bool new_fw;
2412         struct r600_vram_scratch vram_scratch;
2413         int msi_enabled; /* msi enabled */
2414         struct r600_ih ih; /* r6/700 interrupt ring */
2415         struct radeon_rlc rlc;
2416         struct radeon_mec mec;
2417         struct delayed_work hotplug_work;
2418         struct work_struct dp_work;
2419         struct work_struct audio_work;
2420         int num_crtc; /* number of crtcs */
2421         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2422         bool has_uvd;
2423         struct r600_audio audio; /* audio stuff */
2424         struct notifier_block acpi_nb;
2425         /* only one userspace can use Hyperz features or CMASK at a time */
2426         struct drm_file *hyperz_filp;
2427         struct drm_file *cmask_filp;
2428         /* i2c buses */
2429         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2430         /* debugfs */
2431         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2432         unsigned                debugfs_count;
2433         /* virtual memory */
2434         struct radeon_vm_manager        vm_manager;
2435         struct mutex                    gpu_clock_mutex;
2436         /* memory stats */
2437         atomic64_t                      vram_usage;
2438         atomic64_t                      gtt_usage;
2439         atomic64_t                      num_bytes_moved;
2440         atomic_t                        gpu_reset_counter;
2441         /* ACPI interface */
2442         struct radeon_atif              atif;
2443         struct radeon_atcs              atcs;
2444         /* srbm instance registers */
2445         struct mutex                    srbm_mutex;
2446         /* GRBM index mutex. Protects concurrents access to GRBM index */
2447         struct mutex                    grbm_idx_mutex;
2448         /* clock, powergating flags */
2449         u32 cg_flags;
2450         u32 pg_flags;
2451
2452         struct dev_pm_domain vga_pm_domain;
2453         bool have_disp_power_ref;
2454         u32 px_quirk_flags;
2455
2456         /* tracking pinned memory */
2457         u64 vram_pin_size;
2458         u64 gart_pin_size;
2459
2460         /* amdkfd interface */
2461         struct kfd_dev          *kfd;
2462
2463         struct mutex    mn_lock;
2464         DECLARE_HASHTABLE(mn_hash, 7);
2465 };
2466
2467 bool radeon_is_px(struct drm_device *dev);
2468 int radeon_device_init(struct radeon_device *rdev,
2469                        struct drm_device *ddev,
2470                        struct pci_dev *pdev,
2471                        uint32_t flags);
2472 void radeon_device_fini(struct radeon_device *rdev);
2473 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2474
2475 #define RADEON_MIN_MMIO_SIZE 0x10000
2476
2477 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2478 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2479 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2480                                     bool always_indirect)
2481 {
2482         /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2483         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2484                 return readl(((void __iomem *)rdev->rmmio) + reg);
2485         else
2486                 return r100_mm_rreg_slow(rdev, reg);
2487 }
2488 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2489                                 bool always_indirect)
2490 {
2491         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2492                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2493         else
2494                 r100_mm_wreg_slow(rdev, reg, v);
2495 }
2496
2497 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2498 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2499
2500 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2501 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2502
2503 /*
2504  * Cast helper
2505  */
2506 extern const struct fence_ops radeon_fence_ops;
2507
2508 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2509 {
2510         struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2511
2512         if (__f->base.ops == &radeon_fence_ops)
2513                 return __f;
2514
2515         return NULL;
2516 }
2517
2518 /*
2519  * Registers read & write functions.
2520  */
2521 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2522 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2523 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2524 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2525 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2526 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2527 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2528 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2529 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2530 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2531 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2532 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2533 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2534 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2535 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2536 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2537 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2538 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2539 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2540 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2541 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2542 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2543 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2544 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2545 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2546 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2547 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2548 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2549 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2550 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2551 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2552 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2553 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2554 #define WREG32_P(reg, val, mask)                                \
2555         do {                                                    \
2556                 uint32_t tmp_ = RREG32(reg);                    \
2557                 tmp_ &= (mask);                                 \
2558                 tmp_ |= ((val) & ~(mask));                      \
2559                 WREG32(reg, tmp_);                              \
2560         } while (0)
2561 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2562 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2563 #define WREG32_PLL_P(reg, val, mask)                            \
2564         do {                                                    \
2565                 uint32_t tmp_ = RREG32_PLL(reg);                \
2566                 tmp_ &= (mask);                                 \
2567                 tmp_ |= ((val) & ~(mask));                      \
2568                 WREG32_PLL(reg, tmp_);                          \
2569         } while (0)
2570 #define WREG32_SMC_P(reg, val, mask)                            \
2571         do {                                                    \
2572                 uint32_t tmp_ = RREG32_SMC(reg);                \
2573                 tmp_ &= (mask);                                 \
2574                 tmp_ |= ((val) & ~(mask));                      \
2575                 WREG32_SMC(reg, tmp_);                          \
2576         } while (0)
2577 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2578 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2579 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2580
2581 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2582 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2583
2584 /*
2585  * Indirect registers accessors.
2586  * They used to be inlined, but this increases code size by ~65 kbytes.
2587  * Since each performs a pair of MMIO ops
2588  * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2589  * the cost of call+ret is almost negligible. MMIO and locking
2590  * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2591  */
2592 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2593 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2594 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2595 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2596 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2597 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2598 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2599 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2600 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2601 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2602 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2603 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2604 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2605 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2606 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2607 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2608
2609 void r100_pll_errata_after_index(struct radeon_device *rdev);
2610
2611
2612 /*
2613  * ASICs helpers.
2614  */
2615 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2616                             (rdev->pdev->device == 0x5969))
2617 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2618                 (rdev->family == CHIP_RV200) || \
2619                 (rdev->family == CHIP_RS100) || \
2620                 (rdev->family == CHIP_RS200) || \
2621                 (rdev->family == CHIP_RV250) || \
2622                 (rdev->family == CHIP_RV280) || \
2623                 (rdev->family == CHIP_RS300))
2624 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
2625                 (rdev->family == CHIP_RV350) ||                 \
2626                 (rdev->family == CHIP_R350)  ||                 \
2627                 (rdev->family == CHIP_RV380) ||                 \
2628                 (rdev->family == CHIP_R420)  ||                 \
2629                 (rdev->family == CHIP_R423)  ||                 \
2630                 (rdev->family == CHIP_RV410) ||                 \
2631                 (rdev->family == CHIP_RS400) ||                 \
2632                 (rdev->family == CHIP_RS480))
2633 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2634                 (rdev->ddev->pdev->device == 0x9443) || \
2635                 (rdev->ddev->pdev->device == 0x944B) || \
2636                 (rdev->ddev->pdev->device == 0x9506) || \
2637                 (rdev->ddev->pdev->device == 0x9509) || \
2638                 (rdev->ddev->pdev->device == 0x950F) || \
2639                 (rdev->ddev->pdev->device == 0x689C) || \
2640                 (rdev->ddev->pdev->device == 0x689D))
2641 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2642 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
2643                             (rdev->family == CHIP_RS690)  ||    \
2644                             (rdev->family == CHIP_RS740)  ||    \
2645                             (rdev->family >= CHIP_R600))
2646 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2647 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2648 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2649 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2650                              (rdev->flags & RADEON_IS_IGP))
2651 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2652 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2653 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2654                              (rdev->flags & RADEON_IS_IGP))
2655 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2656 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2657 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2658 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2659 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2660 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2661                              (rdev->family == CHIP_MULLINS))
2662
2663 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2664                               (rdev->ddev->pdev->device == 0x6850) || \
2665                               (rdev->ddev->pdev->device == 0x6858) || \
2666                               (rdev->ddev->pdev->device == 0x6859) || \
2667                               (rdev->ddev->pdev->device == 0x6840) || \
2668                               (rdev->ddev->pdev->device == 0x6841) || \
2669                               (rdev->ddev->pdev->device == 0x6842) || \
2670                               (rdev->ddev->pdev->device == 0x6843))
2671
2672 /*
2673  * BIOS helpers.
2674  */
2675 #define RBIOS8(i) (rdev->bios[i])
2676 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2677 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2678
2679 int radeon_combios_init(struct radeon_device *rdev);
2680 void radeon_combios_fini(struct radeon_device *rdev);
2681 int radeon_atombios_init(struct radeon_device *rdev);
2682 void radeon_atombios_fini(struct radeon_device *rdev);
2683
2684
2685 /*
2686  * RING helpers.
2687  */
2688
2689 /**
2690  * radeon_ring_write - write a value to the ring
2691  *
2692  * @ring: radeon_ring structure holding ring information
2693  * @v: dword (dw) value to write
2694  *
2695  * Write a value to the requested ring buffer (all asics).
2696  */
2697 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2698 {
2699         if (ring->count_dw <= 0)
2700                 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2701
2702         ring->ring[ring->wptr++] = v;
2703         ring->wptr &= ring->ptr_mask;
2704         ring->count_dw--;
2705         ring->ring_free_dw--;
2706 }
2707
2708 /*
2709  * ASICs macro.
2710  */
2711 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2712 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2713 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2714 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2715 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2716 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2717 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2718 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2719 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2720 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2721 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2722 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2723 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2724 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2725 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2726 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2727 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2728 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2729 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2730 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2731 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2732 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2733 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2734 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2735 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2736 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2737 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2738 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2739 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2740 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2741 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2742 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2743 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2744 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2745 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2746 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2747 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2748 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2749 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2750 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2751 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2752 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2753 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2754 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2755 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2756 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2757 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2758 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2759 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2760 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2761 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2762 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2763 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2764 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2765 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2766 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2767 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2768 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2769 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2770 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2771 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2772 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2773 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2774 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2775 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2776 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2777 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2778 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2779 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2780 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2781 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2782 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2783 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2784 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2785 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2786 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2787 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2788 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2789 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2790 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2791 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2792 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2793 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2794 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2795 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2796 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2797 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2798 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2799 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2800 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2801 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2802
2803 /* Common functions */
2804 /* AGP */
2805 extern int radeon_gpu_reset(struct radeon_device *rdev);
2806 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2807 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2808 extern void radeon_agp_disable(struct radeon_device *rdev);
2809 extern int radeon_modeset_init(struct radeon_device *rdev);
2810 extern void radeon_modeset_fini(struct radeon_device *rdev);
2811 extern bool radeon_card_posted(struct radeon_device *rdev);
2812 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2813 extern void radeon_update_display_priority(struct radeon_device *rdev);
2814 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2815 extern void radeon_scratch_init(struct radeon_device *rdev);
2816 extern void radeon_wb_fini(struct radeon_device *rdev);
2817 extern int radeon_wb_init(struct radeon_device *rdev);
2818 extern void radeon_wb_disable(struct radeon_device *rdev);
2819 extern void radeon_surface_init(struct radeon_device *rdev);
2820 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2821 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2822 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2823 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2824 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2825 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2826                                      uint32_t flags);
2827 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2828 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2829 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2830 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2831 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2832 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2833 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2834 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2835                                              const u32 *registers,
2836                                              const u32 array_size);
2837
2838 /*
2839  * vm
2840  */
2841 int radeon_vm_manager_init(struct radeon_device *rdev);
2842 void radeon_vm_manager_fini(struct radeon_device *rdev);
2843 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2844 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2845 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2846                                           struct radeon_vm *vm,
2847                                           struct list_head *head);
2848 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2849                                        struct radeon_vm *vm, int ring);
2850 void radeon_vm_flush(struct radeon_device *rdev,
2851                      struct radeon_vm *vm,
2852                      int ring, struct radeon_fence *fence);
2853 void radeon_vm_fence(struct radeon_device *rdev,
2854                      struct radeon_vm *vm,
2855                      struct radeon_fence *fence);
2856 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2857 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2858                                     struct radeon_vm *vm);
2859 int radeon_vm_clear_freed(struct radeon_device *rdev,
2860                           struct radeon_vm *vm);
2861 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2862                              struct radeon_vm *vm);
2863 int radeon_vm_bo_update(struct radeon_device *rdev,
2864                         struct radeon_bo_va *bo_va,
2865                         struct ttm_mem_reg *mem);
2866 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2867                              struct radeon_bo *bo);
2868 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2869                                        struct radeon_bo *bo);
2870 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2871                                       struct radeon_vm *vm,
2872                                       struct radeon_bo *bo);
2873 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2874                           struct radeon_bo_va *bo_va,
2875                           uint64_t offset,
2876                           uint32_t flags);
2877 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2878                       struct radeon_bo_va *bo_va);
2879
2880 /* audio */
2881 void r600_audio_update_hdmi(struct work_struct *work);
2882 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2883 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2884 void r600_audio_enable(struct radeon_device *rdev,
2885                        struct r600_audio_pin *pin,
2886                        u8 enable_mask);
2887 void dce6_audio_enable(struct radeon_device *rdev,
2888                        struct r600_audio_pin *pin,
2889                        u8 enable_mask);
2890
2891 /*
2892  * R600 vram scratch functions
2893  */
2894 int r600_vram_scratch_init(struct radeon_device *rdev);
2895 void r600_vram_scratch_fini(struct radeon_device *rdev);
2896
2897 /*
2898  * r600 cs checking helper
2899  */
2900 unsigned r600_mip_minify(unsigned size, unsigned level);
2901 bool r600_fmt_is_valid_color(u32 format);
2902 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2903 int r600_fmt_get_blocksize(u32 format);
2904 int r600_fmt_get_nblocksx(u32 format, u32 w);
2905 int r600_fmt_get_nblocksy(u32 format, u32 h);
2906
2907 /*
2908  * r600 functions used by radeon_encoder.c
2909  */
2910 struct radeon_hdmi_acr {
2911         u32 clock;
2912
2913         int n_32khz;
2914         int cts_32khz;
2915
2916         int n_44_1khz;
2917         int cts_44_1khz;
2918
2919         int n_48khz;
2920         int cts_48khz;
2921
2922 };
2923
2924 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2925
2926 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2927                                      u32 tiling_pipe_num,
2928                                      u32 max_rb_num,
2929                                      u32 total_max_rb_num,
2930                                      u32 enabled_rb_mask);
2931
2932 /*
2933  * evergreen functions used by radeon_encoder.c
2934  */
2935
2936 extern int ni_init_microcode(struct radeon_device *rdev);
2937 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2938
2939 /* radeon_acpi.c */
2940 #if defined(CONFIG_ACPI)
2941 extern int radeon_acpi_init(struct radeon_device *rdev);
2942 extern void radeon_acpi_fini(struct radeon_device *rdev);
2943 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2944 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2945                                                 u8 perf_req, bool advertise);
2946 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2947 #else
2948 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2949 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2950 #endif
2951
2952 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2953                            struct radeon_cs_packet *pkt,
2954                            unsigned idx);
2955 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2956 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2957                            struct radeon_cs_packet *pkt);
2958 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2959                                 struct radeon_bo_list **cs_reloc,
2960                                 int nomm);
2961 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2962                                uint32_t *vline_start_end,
2963                                uint32_t *vline_status);
2964
2965 #include "radeon_object.h"
2966
2967 #endif