drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_update_memory_usage(struct radeon_bo *bo,
  50                                        unsigned mem_type, int sign)
  51 {
  52         struct radeon_device *rdev = bo->rdev;
  53         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  54
  55         switch (mem_type) {
  56         case TTM_PL_TT:
  57                 if (sign > 0)
  58                         atomic64_add(size, &rdev->gtt_usage);
  59                 else
  60                         atomic64_sub(size, &rdev->gtt_usage);
  61                 break;
  62         case TTM_PL_VRAM:
  63                 if (sign > 0)
  64                         atomic64_add(size, &rdev->vram_usage);
  65                 else
  66                         atomic64_sub(size, &rdev->vram_usage);
  67                 break;
  68         }
  69 }
  70
  71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  72 {
  73         struct radeon_bo *bo;
  74
  75         bo = container_of(tbo, struct radeon_bo, tbo);
  76
  77         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  78
  79         mutex_lock(&bo->rdev->gem.mutex);
  80         list_del_init(&bo->list);
  81         mutex_unlock(&bo->rdev->gem.mutex);
  82         radeon_bo_clear_surface_reg(bo);
  83         WARN_ON(!list_empty(&bo->va));
  84         drm_gem_object_release(&bo->gem_base);
  85         kfree(bo);
  86 }
  87
  88 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  89 {
  90         if (bo->destroy == &radeon_ttm_bo_destroy)
  91                 return true;
  92         return false;
  93 }
  94
  95 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  96 {
  97         u32 c = 0, i;
  98
  99         rbo->placement.placement = rbo->placements;
 100         rbo->placement.busy_placement = rbo->placements;
 101         if (domain & RADEON_GEM_DOMAIN_VRAM) {
 102                 /* Try placing BOs which don't need CPU access outside of the
 103                  * CPU accessible part of VRAM
 104                  */
 105                 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 106                     rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
 107                         rbo->placements[c].fpfn =
 108                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 109                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 110                                                      TTM_PL_FLAG_UNCACHED |
 111                                                      TTM_PL_FLAG_VRAM;
 112                 }
 113
 114                 rbo->placements[c].fpfn = 0;
 115                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 116                                              TTM_PL_FLAG_UNCACHED |
 117                                              TTM_PL_FLAG_VRAM;
 118         }
 119
 120         if (domain & RADEON_GEM_DOMAIN_GTT) {
 121                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 122                         rbo->placements[c].fpfn = 0;
 123                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 124                                 TTM_PL_FLAG_TT;
 125
 126                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 127                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 128                         rbo->placements[c].fpfn = 0;
 129                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 130                                 TTM_PL_FLAG_UNCACHED |
 131                                 TTM_PL_FLAG_TT;
 132                 } else {
 133                         rbo->placements[c].fpfn = 0;
 134                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 135                                                      TTM_PL_FLAG_TT;
 136                 }
 137         }
 138
 139         if (domain & RADEON_GEM_DOMAIN_CPU) {
 140                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 141                         rbo->placements[c].fpfn = 0;
 142                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 143                                 TTM_PL_FLAG_SYSTEM;
 144
 145                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 146                     rbo->rdev->flags & RADEON_IS_AGP) {
 147                         rbo->placements[c].fpfn = 0;
 148                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 149                                 TTM_PL_FLAG_UNCACHED |
 150                                 TTM_PL_FLAG_SYSTEM;
 151                 } else {
 152                         rbo->placements[c].fpfn = 0;
 153                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 154                                                      TTM_PL_FLAG_SYSTEM;
 155                 }
 156         }
 157         if (!c) {
 158                 rbo->placements[c].fpfn = 0;
 159                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 160                                              TTM_PL_FLAG_SYSTEM;
 161         }
 162
 163         rbo->placement.num_placement = c;
 164         rbo->placement.num_busy_placement = c;
 165
 166         for (i = 0; i < c; ++i) {
 167                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 168                     (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 169                     !rbo->placements[i].fpfn)
 170                         rbo->placements[i].lpfn =
 171                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 172                 else
 173                         rbo->placements[i].lpfn = 0;
 174         }
 175 }
 176
 177 int radeon_bo_create(struct radeon_device *rdev,
 178                      unsigned long size, int byte_align, bool kernel,
 179                      u32 domain, u32 flags, struct sg_table *sg,
 180                      struct reservation_object *resv,
 181                      struct radeon_bo **bo_ptr)
 182 {
 183         struct radeon_bo *bo;
 184         enum ttm_bo_type type;
 185         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 186         size_t acc_size;
 187         int r;
 188
 189         size = ALIGN(size, PAGE_SIZE);
 190
 191         if (kernel) {
 192                 type = ttm_bo_type_kernel;
 193         } else if (sg) {
 194                 type = ttm_bo_type_sg;
 195         } else {
 196                 type = ttm_bo_type_device;
 197         }
 198         *bo_ptr = NULL;
 199
 200         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 201                                        sizeof(struct radeon_bo));
 202
 203         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 204         if (bo == NULL)
 205                 return -ENOMEM;
 206         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 207         if (unlikely(r)) {
 208                 kfree(bo);
 209                 return r;
 210         }
 211         bo->rdev = rdev;
 212         bo->surface_reg = -1;
 213         INIT_LIST_HEAD(&bo->list);
 214         INIT_LIST_HEAD(&bo->va);
 215         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 216                                        RADEON_GEM_DOMAIN_GTT |
 217                                        RADEON_GEM_DOMAIN_CPU);
 218
 219         bo->flags = flags;
 220         /* PCI GART is always snooped */
 221         if (!(rdev->flags & RADEON_IS_PCIE))
 222                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 223
 224         /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
 225          * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
 226          */
 227         if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
 228                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 229
 230 #ifdef CONFIG_X86_32
 231         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 232          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 233          */
 234         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 235 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 236         /* Don't try to enable write-combining when it can't work, or things
 237          * may be slow
 238          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 239          */
 240
 241 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 242          thanks to write-combining
 243
 244         if (bo->flags & RADEON_GEM_GTT_WC)
 245                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 246                               "better performance thanks to write-combining\n");
 247         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 248 #endif
 249
 250         radeon_ttm_placement_from_domain(bo, domain);
 251         /* Kernel allocation are uninterruptible */
 252         down_read(&rdev->pm.mclk_lock);
 253         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 254                         &bo->placement, page_align, !kernel, NULL,
 255                         acc_size, sg, resv, &radeon_ttm_bo_destroy);
 256         up_read(&rdev->pm.mclk_lock);
 257         if (unlikely(r != 0)) {
 258                 return r;
 259         }
 260         *bo_ptr = bo;
 261
 262         trace_radeon_bo_create(bo);
 263
 264         return 0;
 265 }
 266
 267 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 268 {
 269         bool is_iomem;
 270         int r;
 271
 272         if (bo->kptr) {
 273                 if (ptr) {
 274                         *ptr = bo->kptr;
 275                 }
 276                 return 0;
 277         }
 278         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 279         if (r) {
 280                 return r;
 281         }
 282         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 283         if (ptr) {
 284                 *ptr = bo->kptr;
 285         }
 286         radeon_bo_check_tiling(bo, 0, 0);
 287         return 0;
 288 }
 289
 290 void radeon_bo_kunmap(struct radeon_bo *bo)
 291 {
 292         if (bo->kptr == NULL)
 293                 return;
 294         bo->kptr = NULL;
 295         radeon_bo_check_tiling(bo, 0, 0);
 296         ttm_bo_kunmap(&bo->kmap);
 297 }
 298
 299 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 300 {
 301         if (bo == NULL)
 302                 return NULL;
 303
 304         ttm_bo_reference(&bo->tbo);
 305         return bo;
 306 }
 307
 308 void radeon_bo_unref(struct radeon_bo **bo)
 309 {
 310         struct ttm_buffer_object *tbo;
 311         struct radeon_device *rdev;
 312
 313         if ((*bo) == NULL)
 314                 return;
 315         rdev = (*bo)->rdev;
 316         tbo = &((*bo)->tbo);
 317         ttm_bo_unref(&tbo);
 318         if (tbo == NULL)
 319                 *bo = NULL;
 320 }
 321
 322 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 323                              u64 *gpu_addr)
 324 {
 325         int r, i;
 326
 327         if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
 328                 return -EPERM;
 329
 330         if (bo->pin_count) {
 331                 bo->pin_count++;
 332                 if (gpu_addr)
 333                         *gpu_addr = radeon_bo_gpu_offset(bo);
 334
 335                 if (max_offset != 0) {
 336                         u64 domain_start;
 337
 338                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 339                                 domain_start = bo->rdev->mc.vram_start;
 340                         else
 341                                 domain_start = bo->rdev->mc.gtt_start;
 342                         WARN_ON_ONCE(max_offset <
 343                                      (radeon_bo_gpu_offset(bo) - domain_start));
 344                 }
 345
 346                 return 0;
 347         }
 348         radeon_ttm_placement_from_domain(bo, domain);
 349         for (i = 0; i < bo->placement.num_placement; i++) {
 350                 /* force to pin into visible video ram */
 351                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 352                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 353                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 354                         bo->placements[i].lpfn =
 355                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 356                 else
 357                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 358
 359                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 360         }
 361
 362         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 363         if (likely(r == 0)) {
 364                 bo->pin_count = 1;
 365                 if (gpu_addr != NULL)
 366                         *gpu_addr = radeon_bo_gpu_offset(bo);
 367                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 368                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 369                 else
 370                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 371         } else {
 372                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 373         }
 374         return r;
 375 }
 376
 377 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 378 {
 379         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 380 }
 381
 382 int radeon_bo_unpin(struct radeon_bo *bo)
 383 {
 384         int r, i;
 385
 386         if (!bo->pin_count) {
 387                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 388                 return 0;
 389         }
 390         bo->pin_count--;
 391         if (bo->pin_count)
 392                 return 0;
 393         for (i = 0; i < bo->placement.num_placement; i++) {
 394                 bo->placements[i].lpfn = 0;
 395                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 396         }
 397         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 398         if (likely(r == 0)) {
 399                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 400                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 401                 else
 402                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 403         } else {
 404                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 405         }
 406         return r;
 407 }
 408
 409 int radeon_bo_evict_vram(struct radeon_device *rdev)
 410 {
 411         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 412         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 413                 if (rdev->mc.igp_sideport_enabled == false)
 414                         /* Useless to evict on IGP chips */
 415                         return 0;
 416         }
 417         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 418 }
 419
 420 void radeon_bo_force_delete(struct radeon_device *rdev)
 421 {
 422         struct radeon_bo *bo, *n;
 423
 424         if (list_empty(&rdev->gem.objects)) {
 425                 return;
 426         }
 427         dev_err(rdev->dev, "Userspace still has active objects !\n");
 428         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 429                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 430                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 431                         *((unsigned long *)&bo->gem_base.refcount));
 432                 mutex_lock(&bo->rdev->gem.mutex);
 433                 list_del_init(&bo->list);
 434                 mutex_unlock(&bo->rdev->gem.mutex);
 435                 /* this should unref the ttm bo */
 436                 drm_gem_object_unreference_unlocked(&bo->gem_base);
 437         }
 438 }
 439
 440 int radeon_bo_init(struct radeon_device *rdev)
 441 {
 442         /* Add an MTRR for the VRAM */
 443         if (!rdev->fastfb_working) {
 444                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 445                                                       rdev->mc.aper_size);
 446         }
 447         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 448                 rdev->mc.mc_vram_size >> 20,
 449                 (unsigned long long)rdev->mc.aper_size >> 20);
 450         DRM_INFO("RAM width %dbits %cDR\n",
 451                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 452         return radeon_ttm_init(rdev);
 453 }
 454
 455 void radeon_bo_fini(struct radeon_device *rdev)
 456 {
 457         radeon_ttm_fini(rdev);
 458         arch_phys_wc_del(rdev->mc.vram_mtrr);
 459 }
 460
 461 /* Returns how many bytes TTM can move per IB.
 462  */
 463 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 464 {
 465         u64 real_vram_size = rdev->mc.real_vram_size;
 466         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 467
 468         /* This function is based on the current VRAM usage.
 469          *
 470          * - If all of VRAM is free, allow relocating the number of bytes that
 471          *   is equal to 1/4 of the size of VRAM for this IB.
 472
 473          * - If more than one half of VRAM is occupied, only allow relocating
 474          *   1 MB of data for this IB.
 475          *
 476          * - From 0 to one half of used VRAM, the threshold decreases
 477          *   linearly.
 478          *         __________________
 479          * 1/4 of -|\               |
 480          * VRAM    | \              |
 481          *         |  \             |
 482          *         |   \            |
 483          *         |    \           |
 484          *         |     \          |
 485          *         |      \         |
 486          *         |       \________|1 MB
 487          *         |----------------|
 488          *    VRAM 0 %             100 %
 489          *         used            used
 490          *
 491          * Note: It's a threshold, not a limit. The threshold must be crossed
 492          * for buffer relocations to stop, so any buffer of an arbitrary size
 493          * can be moved as long as the threshold isn't crossed before
 494          * the relocation takes place. We don't want to disable buffer
 495          * relocations completely.
 496          *
 497          * The idea is that buffers should be placed in VRAM at creation time
 498          * and TTM should only do a minimum number of relocations during
 499          * command submission. In practice, you need to submit at least
 500          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 501          *
 502          * Also, things can get pretty crazy under memory pressure and actual
 503          * VRAM usage can change a lot, so playing safe even at 50% does
 504          * consistently increase performance.
 505          */
 506
 507         u64 half_vram = real_vram_size >> 1;
 508         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 509         u64 bytes_moved_threshold = half_free_vram >> 1;
 510         return max(bytes_moved_threshold, 1024*1024ull);
 511 }
 512
 513 int radeon_bo_list_validate(struct radeon_device *rdev,
 514                             struct ww_acquire_ctx *ticket,
 515                             struct list_head *head, int ring)
 516 {
 517         struct radeon_bo_list *lobj;
 518         struct list_head duplicates;
 519         int r;
 520         u64 bytes_moved = 0, initial_bytes_moved;
 521         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 522
 523         INIT_LIST_HEAD(&duplicates);
 524         r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
 525         if (unlikely(r != 0)) {
 526                 return r;
 527         }
 528
 529         list_for_each_entry(lobj, head, tv.head) {
 530                 struct radeon_bo *bo = lobj->robj;
 531                 if (!bo->pin_count) {
 532                         u32 domain = lobj->prefered_domains;
 533                         u32 allowed = lobj->allowed_domains;
 534                         u32 current_domain =
 535                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 536
 537                         /* Check if this buffer will be moved and don't move it
 538                          * if we have moved too many buffers for this IB already.
 539                          *
 540                          * Note that this allows moving at least one buffer of
 541                          * any size, because it doesn't take the current "bo"
 542                          * into account. We don't want to disallow buffer moves
 543                          * completely.
 544                          */
 545                         if ((allowed & current_domain) != 0 &&
 546                             (domain & current_domain) == 0 && /* will be moved */
 547                             bytes_moved > bytes_moved_threshold) {
 548                                 /* don't move it */
 549                                 domain = current_domain;
 550                         }
 551
 552                 retry:
 553                         radeon_ttm_placement_from_domain(bo, domain);
 554                         if (ring == R600_RING_TYPE_UVD_INDEX)
 555                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 556
 557                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 558                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 559                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 560                                        initial_bytes_moved;
 561
 562                         if (unlikely(r)) {
 563                                 if (r != -ERESTARTSYS &&
 564                                     domain != lobj->allowed_domains) {
 565                                         domain = lobj->allowed_domains;
 566                                         goto retry;
 567                                 }
 568                                 ttm_eu_backoff_reservation(ticket, head);
 569                                 return r;
 570                         }
 571                 }
 572                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 573                 lobj->tiling_flags = bo->tiling_flags;
 574         }
 575
 576         list_for_each_entry(lobj, &duplicates, tv.head) {
 577                 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
 578                 lobj->tiling_flags = lobj->robj->tiling_flags;
 579         }
 580
 581         return 0;
 582 }
 583
 584 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 585 {
 586         struct radeon_device *rdev = bo->rdev;
 587         struct radeon_surface_reg *reg;
 588         struct radeon_bo *old_object;
 589         int steal;
 590         int i;
 591
 592         lockdep_assert_held(&bo->tbo.resv->lock.base);
 593
 594         if (!bo->tiling_flags)
 595                 return 0;
 596
 597         if (bo->surface_reg >= 0) {
 598                 reg = &rdev->surface_regs[bo->surface_reg];
 599                 i = bo->surface_reg;
 600                 goto out;
 601         }
 602
 603         steal = -1;
 604         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 605
 606                 reg = &rdev->surface_regs[i];
 607                 if (!reg->bo)
 608                         break;
 609
 610                 old_object = reg->bo;
 611                 if (old_object->pin_count == 0)
 612                         steal = i;
 613         }
 614
 615         /* if we are all out */
 616         if (i == RADEON_GEM_MAX_SURFACES) {
 617                 if (steal == -1)
 618                         return -ENOMEM;
 619                 /* find someone with a surface reg and nuke their BO */
 620                 reg = &rdev->surface_regs[steal];
 621                 old_object = reg->bo;
 622                 /* blow away the mapping */
 623                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 624                 ttm_bo_unmap_virtual(&old_object->tbo);
 625                 old_object->surface_reg = -1;
 626                 i = steal;
 627         }
 628
 629         bo->surface_reg = i;
 630         reg->bo = bo;
 631
 632 out:
 633         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 634                                bo->tbo.mem.start << PAGE_SHIFT,
 635                                bo->tbo.num_pages << PAGE_SHIFT);
 636         return 0;
 637 }
 638
 639 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 640 {
 641         struct radeon_device *rdev = bo->rdev;
 642         struct radeon_surface_reg *reg;
 643
 644         if (bo->surface_reg == -1)
 645                 return;
 646
 647         reg = &rdev->surface_regs[bo->surface_reg];
 648         radeon_clear_surface_reg(rdev, bo->surface_reg);
 649
 650         reg->bo = NULL;
 651         bo->surface_reg = -1;
 652 }
 653
 654 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 655                                 uint32_t tiling_flags, uint32_t pitch)
 656 {
 657         struct radeon_device *rdev = bo->rdev;
 658         int r;
 659
 660         if (rdev->family >= CHIP_CEDAR) {
 661                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 662
 663                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 664                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 665                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 666                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 667                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 668                 switch (bankw) {
 669                 case 0:
 670                 case 1:
 671                 case 2:
 672                 case 4:
 673                 case 8:
 674                         break;
 675                 default:
 676                         return -EINVAL;
 677                 }
 678                 switch (bankh) {
 679                 case 0:
 680                 case 1:
 681                 case 2:
 682                 case 4:
 683                 case 8:
 684                         break;
 685                 default:
 686                         return -EINVAL;
 687                 }
 688                 switch (mtaspect) {
 689                 case 0:
 690                 case 1:
 691                 case 2:
 692                 case 4:
 693                 case 8:
 694                         break;
 695                 default:
 696                         return -EINVAL;
 697                 }
 698                 if (tilesplit > 6) {
 699                         return -EINVAL;
 700                 }
 701                 if (stilesplit > 6) {
 702                         return -EINVAL;
 703                 }
 704         }
 705         r = radeon_bo_reserve(bo, false);
 706         if (unlikely(r != 0))
 707                 return r;
 708         bo->tiling_flags = tiling_flags;
 709         bo->pitch = pitch;
 710         radeon_bo_unreserve(bo);
 711         return 0;
 712 }
 713
 714 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 715                                 uint32_t *tiling_flags,
 716                                 uint32_t *pitch)
 717 {
 718         lockdep_assert_held(&bo->tbo.resv->lock.base);
 719
 720         if (tiling_flags)
 721                 *tiling_flags = bo->tiling_flags;
 722         if (pitch)
 723                 *pitch = bo->pitch;
 724 }
 725
 726 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 727                                 bool force_drop)
 728 {
 729         if (!force_drop)
 730                 lockdep_assert_held(&bo->tbo.resv->lock.base);
 731
 732         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 733                 return 0;
 734
 735         if (force_drop) {
 736                 radeon_bo_clear_surface_reg(bo);
 737                 return 0;
 738         }
 739
 740         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 741                 if (!has_moved)
 742                         return 0;
 743
 744                 if (bo->surface_reg >= 0)
 745                         radeon_bo_clear_surface_reg(bo);
 746                 return 0;
 747         }
 748
 749         if ((bo->surface_reg >= 0) && !has_moved)
 750                 return 0;
 751
 752         return radeon_bo_get_surface_reg(bo);
 753 }
 754
 755 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 756                            struct ttm_mem_reg *new_mem)
 757 {
 758         struct radeon_bo *rbo;
 759
 760         if (!radeon_ttm_bo_is_radeon_bo(bo))
 761                 return;
 762
 763         rbo = container_of(bo, struct radeon_bo, tbo);
 764         radeon_bo_check_tiling(rbo, 0, 1);
 765         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 766
 767         /* update statistics */
 768         if (!new_mem)
 769                 return;
 770
 771         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 772         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 773 }
 774
 775 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 776 {
 777         struct radeon_device *rdev;
 778         struct radeon_bo *rbo;
 779         unsigned long offset, size, lpfn;
 780         int i, r;
 781
 782         if (!radeon_ttm_bo_is_radeon_bo(bo))
 783                 return 0;
 784         rbo = container_of(bo, struct radeon_bo, tbo);
 785         radeon_bo_check_tiling(rbo, 0, 0);
 786         rdev = rbo->rdev;
 787         if (bo->mem.mem_type != TTM_PL_VRAM)
 788                 return 0;
 789
 790         size = bo->mem.num_pages << PAGE_SHIFT;
 791         offset = bo->mem.start << PAGE_SHIFT;
 792         if ((offset + size) <= rdev->mc.visible_vram_size)
 793                 return 0;
 794
 795         /* hurrah the memory is not visible ! */
 796         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 797         lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
 798         for (i = 0; i < rbo->placement.num_placement; i++) {
 799                 /* Force into visible VRAM */
 800                 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 801                     (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
 802                         rbo->placements[i].lpfn = lpfn;
 803         }
 804         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 805         if (unlikely(r == -ENOMEM)) {
 806                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 807                 return ttm_bo_validate(bo, &rbo->placement, false, false);
 808         } else if (unlikely(r != 0)) {
 809                 return r;
 810         }
 811
 812         offset = bo->mem.start << PAGE_SHIFT;
 813         /* this should never happen */
 814         if ((offset + size) > rdev->mc.visible_vram_size)
 815                 return -EINVAL;
 816
 817         return 0;
 818 }
 819
 820 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 821 {
 822         int r;
 823
 824         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
 825         if (unlikely(r != 0))
 826                 return r;
 827         if (mem_type)
 828                 *mem_type = bo->tbo.mem.mem_type;
 829
 830         r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 831         ttm_bo_unreserve(&bo->tbo);
 832         return r;
 833 }
 834
 835 /**
 836  * radeon_bo_fence - add fence to buffer object
 837  *
 838  * @bo: buffer object in question
 839  * @fence: fence to add
 840  * @shared: true if fence should be added shared
 841  *
 842  */
 843 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
 844                      bool shared)
 845 {
 846         struct reservation_object *resv = bo->tbo.resv;
 847
 848         if (shared)
 849                 reservation_object_add_shared_fence(resv, &fence->base);
 850         else
 851                 reservation_object_add_excl_fence(resv, &fence->base);
 852 }