drivers/gpu/drm/sti/sti_mixer.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
   4  *          Fabien Dessenne <fabien.dessenne@st.com>
   5  *          for STMicroelectronics.
   6  * License terms:  GNU General Public License (GPL), version 2
   7  */
   8
   9 #include "sti_compositor.h"
  10 #include "sti_mixer.h"
  11 #include "sti_vtg.h"
  12
  13 /* Module parameter to set the background color of the mixer */
  14 static unsigned int bkg_color = 0x000000;
  15 MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
  16 module_param_named(bkgcolor, bkg_color, int, 0644);
  17
  18 /* Identity: G=Y , B=Cb , R=Cr */
  19 static const u32 mixerColorSpaceMatIdentity[] = {
  20         0x10000000, 0x00000000, 0x10000000, 0x00001000,
  21         0x00000000, 0x00000000, 0x00000000, 0x00000000
  22 };
  23
  24 /* regs offset */
  25 #define GAM_MIXER_CTL      0x00
  26 #define GAM_MIXER_BKC      0x04
  27 #define GAM_MIXER_BCO      0x0C
  28 #define GAM_MIXER_BCS      0x10
  29 #define GAM_MIXER_AVO      0x28
  30 #define GAM_MIXER_AVS      0x2C
  31 #define GAM_MIXER_CRB      0x34
  32 #define GAM_MIXER_ACT      0x38
  33 #define GAM_MIXER_MBP      0x3C
  34 #define GAM_MIXER_MX0      0x80
  35
  36 /* id for depth of CRB reg */
  37 #define GAM_DEPTH_VID0_ID  1
  38 #define GAM_DEPTH_VID1_ID  2
  39 #define GAM_DEPTH_GDP0_ID  3
  40 #define GAM_DEPTH_GDP1_ID  4
  41 #define GAM_DEPTH_GDP2_ID  5
  42 #define GAM_DEPTH_GDP3_ID  6
  43 #define GAM_DEPTH_MASK_ID  7
  44
  45 /* mask in CTL reg */
  46 #define GAM_CTL_BACK_MASK  BIT(0)
  47 #define GAM_CTL_VID0_MASK  BIT(1)
  48 #define GAM_CTL_VID1_MASK  BIT(2)
  49 #define GAM_CTL_GDP0_MASK  BIT(3)
  50 #define GAM_CTL_GDP1_MASK  BIT(4)
  51 #define GAM_CTL_GDP2_MASK  BIT(5)
  52 #define GAM_CTL_GDP3_MASK  BIT(6)
  53 #define GAM_CTL_CURSOR_MASK BIT(9)
  54
  55 const char *sti_mixer_to_str(struct sti_mixer *mixer)
  56 {
  57         switch (mixer->id) {
  58         case STI_MIXER_MAIN:
  59                 return "MAIN_MIXER";
  60         case STI_MIXER_AUX:
  61                 return "AUX_MIXER";
  62         default:
  63                 return "<UNKNOWN MIXER>";
  64         }
  65 }
  66
  67 static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
  68 {
  69         return readl(mixer->regs + reg_id);
  70 }
  71
  72 static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
  73                                        u32 reg_id, u32 val)
  74 {
  75         writel(val, mixer->regs + reg_id);
  76 }
  77
  78 void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
  79 {
  80         u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
  81
  82         val &= ~GAM_CTL_BACK_MASK;
  83         val |= enable;
  84         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
  85 }
  86
  87 static void sti_mixer_set_background_color(struct sti_mixer *mixer,
  88                                            unsigned int rgb)
  89 {
  90         sti_mixer_reg_write(mixer, GAM_MIXER_BKC, rgb);
  91 }
  92
  93 static void sti_mixer_set_background_area(struct sti_mixer *mixer,
  94                                           struct drm_display_mode *mode)
  95 {
  96         u32 ydo, xdo, yds, xds;
  97
  98         ydo = sti_vtg_get_line_number(*mode, 0);
  99         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 100         xdo = sti_vtg_get_pixel_number(*mode, 0);
 101         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 102
 103         sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
 104         sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
 105 }
 106
 107 int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane)
 108 {
 109         int plane_id, depth = plane->zorder;
 110         unsigned int i;
 111         u32 mask, val;
 112
 113         if ((depth < 1) || (depth > GAM_MIXER_NB_DEPTH_LEVEL))
 114                 return 1;
 115
 116         switch (plane->desc) {
 117         case STI_GDP_0:
 118                 plane_id = GAM_DEPTH_GDP0_ID;
 119                 break;
 120         case STI_GDP_1:
 121                 plane_id = GAM_DEPTH_GDP1_ID;
 122                 break;
 123         case STI_GDP_2:
 124                 plane_id = GAM_DEPTH_GDP2_ID;
 125                 break;
 126         case STI_GDP_3:
 127                 plane_id = GAM_DEPTH_GDP3_ID;
 128                 break;
 129         case STI_HQVDP_0:
 130                 plane_id = GAM_DEPTH_VID0_ID;
 131                 break;
 132         case STI_CURSOR:
 133                 /* no need to set depth for cursor */
 134                 return 0;
 135         default:
 136                 DRM_ERROR("Unknown plane %d\n", plane->desc);
 137                 return 1;
 138         }
 139
 140         /* Search if a previous depth was already assigned to the plane */
 141         val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
 142         for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
 143                 mask = GAM_DEPTH_MASK_ID << (3 * i);
 144                 if ((val & mask) == plane_id << (3 * i))
 145                         break;
 146         }
 147
 148         mask |= GAM_DEPTH_MASK_ID << (3 * (depth - 1));
 149         plane_id = plane_id << (3 * (depth - 1));
 150
 151         DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
 152                          sti_plane_to_str(plane), depth);
 153         dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
 154                 plane_id, mask);
 155
 156         val &= ~mask;
 157         val |= plane_id;
 158         sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
 159
 160         dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
 161                 sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
 162         return 0;
 163 }
 164
 165 int sti_mixer_active_video_area(struct sti_mixer *mixer,
 166                                 struct drm_display_mode *mode)
 167 {
 168         u32 ydo, xdo, yds, xds;
 169
 170         ydo = sti_vtg_get_line_number(*mode, 0);
 171         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 172         xdo = sti_vtg_get_pixel_number(*mode, 0);
 173         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 174
 175         DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
 176                          sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
 177         sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
 178         sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
 179
 180         sti_mixer_set_background_color(mixer, bkg_color);
 181
 182         sti_mixer_set_background_area(mixer, mode);
 183         sti_mixer_set_background_status(mixer, true);
 184         return 0;
 185 }
 186
 187 static u32 sti_mixer_get_plane_mask(struct sti_plane *plane)
 188 {
 189         switch (plane->desc) {
 190         case STI_BACK:
 191                 return GAM_CTL_BACK_MASK;
 192         case STI_GDP_0:
 193                 return GAM_CTL_GDP0_MASK;
 194         case STI_GDP_1:
 195                 return GAM_CTL_GDP1_MASK;
 196         case STI_GDP_2:
 197                 return GAM_CTL_GDP2_MASK;
 198         case STI_GDP_3:
 199                 return GAM_CTL_GDP3_MASK;
 200         case STI_HQVDP_0:
 201                 return GAM_CTL_VID0_MASK;
 202         case STI_CURSOR:
 203                 return GAM_CTL_CURSOR_MASK;
 204         default:
 205                 return 0;
 206         }
 207 }
 208
 209 int sti_mixer_set_plane_status(struct sti_mixer *mixer,
 210                                struct sti_plane *plane, bool status)
 211 {
 212         u32 mask, val;
 213
 214         DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
 215                          sti_mixer_to_str(mixer), sti_plane_to_str(plane));
 216
 217         mask = sti_mixer_get_plane_mask(plane);
 218         if (!mask) {
 219                 DRM_ERROR("Can't find layer mask\n");
 220                 return -EINVAL;
 221         }
 222
 223         val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
 224         val &= ~mask;
 225         val |= status ? mask : 0;
 226         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
 227
 228         return 0;
 229 }
 230
 231 void sti_mixer_set_matrix(struct sti_mixer *mixer)
 232 {
 233         unsigned int i;
 234
 235         for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
 236                 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
 237                                     mixerColorSpaceMatIdentity[i]);
 238 }
 239
 240 struct sti_mixer *sti_mixer_create(struct device *dev, int id,
 241                                    void __iomem *baseaddr)
 242 {
 243         struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
 244         struct device_node *np = dev->of_node;
 245
 246         dev_dbg(dev, "%s\n", __func__);
 247         if (!mixer) {
 248                 DRM_ERROR("Failed to allocated memory for mixer\n");
 249                 return NULL;
 250         }
 251         mixer->regs = baseaddr;
 252         mixer->dev = dev;
 253         mixer->id = id;
 254
 255         if (of_device_is_compatible(np, "st,stih416-compositor"))
 256                 sti_mixer_set_matrix(mixer);
 257
 258         DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
 259                          sti_mixer_to_str(mixer), mixer->regs);
 260
 261         return mixer;
 262 }