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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / net / ethernet / intel / i40e / i40e_dcb.c
blob2691277c0055d2572f2994e24c120066a7bec28b
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_adminq.h"
28 #include "i40e_prototype.h"
29 #include "i40e_dcb.h"
30
31 /**
32 * i40e_get_dcbx_status
33 * @hw: pointer to the hw struct
34 * @status: Embedded DCBX Engine Status
35 *
36 * Get the DCBX status from the Firmware
37 **/
38 i40e_status i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status)
39 {
40 u32 reg;
41
42 if (!status)
43 return I40E_ERR_PARAM;
44
45 reg = rd32(hw, I40E_PRTDCB_GENS);
46 *status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >>
47 I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT);
48
49 return 0;
50 }
51
52 /**
53 * i40e_parse_ieee_etscfg_tlv
54 * @tlv: IEEE 802.1Qaz ETS CFG TLV
55 * @dcbcfg: Local store to update ETS CFG data
56 *
57 * Parses IEEE 802.1Qaz ETS CFG TLV
58 **/
59 static void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv,
60 struct i40e_dcbx_config *dcbcfg)
61 {
62 struct i40e_dcb_ets_config *etscfg;
63 u8 *buf = tlv->tlvinfo;
64 u16 offset = 0;
65 u8 priority;
66 int i;
67
68 /* First Octet post subtype
69 * --------------------------
70 * |will-|CBS | Re- | Max |
71 * |ing | |served| TCs |
72 * --------------------------
73 * |1bit | 1bit|3 bits|3bits|
74 */
75 etscfg = &dcbcfg->etscfg;
76 etscfg->willing = (u8)((buf[offset] & I40E_IEEE_ETS_WILLING_MASK) >>
77 I40E_IEEE_ETS_WILLING_SHIFT);
78 etscfg->cbs = (u8)((buf[offset] & I40E_IEEE_ETS_CBS_MASK) >>
79 I40E_IEEE_ETS_CBS_SHIFT);
80 etscfg->maxtcs = (u8)((buf[offset] & I40E_IEEE_ETS_MAXTC_MASK) >>
81 I40E_IEEE_ETS_MAXTC_SHIFT);
82
83 /* Move offset to Priority Assignment Table */
84 offset++;
85
86 /* Priority Assignment Table (4 octets)
87 * Octets:| 1 | 2 | 3 | 4 |
88 * -----------------------------------------
89 * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
90 * -----------------------------------------
91 * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|
92 * -----------------------------------------
93 */
94 for (i = 0; i < 4; i++) {
95 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>
96 I40E_IEEE_ETS_PRIO_1_SHIFT);
97 etscfg->prioritytable[i * 2] = priority;
98 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>
99 I40E_IEEE_ETS_PRIO_0_SHIFT);
100 etscfg->prioritytable[i * 2 + 1] = priority;
101 offset++;
102 }
103
104 /* TC Bandwidth Table (8 octets)
105 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
106 * ---------------------------------
107 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
108 * ---------------------------------
109 */
110 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
111 etscfg->tcbwtable[i] = buf[offset++];
112
113 /* TSA Assignment Table (8 octets)
114 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
115 * ---------------------------------
116 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
117 * ---------------------------------
118 */
119 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
120 etscfg->tsatable[i] = buf[offset++];
121 }
122
123 /**
124 * i40e_parse_ieee_etsrec_tlv
125 * @tlv: IEEE 802.1Qaz ETS REC TLV
126 * @dcbcfg: Local store to update ETS REC data
127 *
128 * Parses IEEE 802.1Qaz ETS REC TLV
129 **/
130 static void i40e_parse_ieee_etsrec_tlv(struct i40e_lldp_org_tlv *tlv,
131 struct i40e_dcbx_config *dcbcfg)
132 {
133 u8 *buf = tlv->tlvinfo;
134 u16 offset = 0;
135 u8 priority;
136 int i;
137
138 /* Move offset to priority table */
139 offset++;
140
141 /* Priority Assignment Table (4 octets)
142 * Octets:| 1 | 2 | 3 | 4 |
143 * -----------------------------------------
144 * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
145 * -----------------------------------------
146 * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|
147 * -----------------------------------------
148 */
149 for (i = 0; i < 4; i++) {
150 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>
151 I40E_IEEE_ETS_PRIO_1_SHIFT);
152 dcbcfg->etsrec.prioritytable[i*2] = priority;
153 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>
154 I40E_IEEE_ETS_PRIO_0_SHIFT);
155 dcbcfg->etsrec.prioritytable[i*2 + 1] = priority;
156 offset++;
157 }
158
159 /* TC Bandwidth Table (8 octets)
160 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
161 * ---------------------------------
162 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
163 * ---------------------------------
164 */
165 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
166 dcbcfg->etsrec.tcbwtable[i] = buf[offset++];
167
168 /* TSA Assignment Table (8 octets)
169 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
170 * ---------------------------------
171 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|
172 * ---------------------------------
173 */
174 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
175 dcbcfg->etsrec.tsatable[i] = buf[offset++];
176 }
177
178 /**
179 * i40e_parse_ieee_pfccfg_tlv
180 * @tlv: IEEE 802.1Qaz PFC CFG TLV
181 * @dcbcfg: Local store to update PFC CFG data
182 *
183 * Parses IEEE 802.1Qaz PFC CFG TLV
184 **/
185 static void i40e_parse_ieee_pfccfg_tlv(struct i40e_lldp_org_tlv *tlv,
186 struct i40e_dcbx_config *dcbcfg)
187 {
188 u8 *buf = tlv->tlvinfo;
189
190 /* ----------------------------------------
191 * |will-|MBC | Re- | PFC | PFC Enable |
192 * |ing | |served| cap | |
193 * -----------------------------------------
194 * |1bit | 1bit|2 bits|4bits| 1 octet |
195 */
196 dcbcfg->pfc.willing = (u8)((buf[0] & I40E_IEEE_PFC_WILLING_MASK) >>
197 I40E_IEEE_PFC_WILLING_SHIFT);
198 dcbcfg->pfc.mbc = (u8)((buf[0] & I40E_IEEE_PFC_MBC_MASK) >>
199 I40E_IEEE_PFC_MBC_SHIFT);
200 dcbcfg->pfc.pfccap = (u8)((buf[0] & I40E_IEEE_PFC_CAP_MASK) >>
201 I40E_IEEE_PFC_CAP_SHIFT);
202 dcbcfg->pfc.pfcenable = buf[1];
203 }
204
205 /**
206 * i40e_parse_ieee_app_tlv
207 * @tlv: IEEE 802.1Qaz APP TLV
208 * @dcbcfg: Local store to update APP PRIO data
209 *
210 * Parses IEEE 802.1Qaz APP PRIO TLV
211 **/
212 static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv,
213 struct i40e_dcbx_config *dcbcfg)
214 {
215 u16 typelength;
216 u16 offset = 0;
217 u16 length;
218 int i = 0;
219 u8 *buf;
220
221 typelength = ntohs(tlv->typelength);
222 length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
223 I40E_LLDP_TLV_LEN_SHIFT);
224 buf = tlv->tlvinfo;
225
226 /* The App priority table starts 5 octets after TLV header */
227 length -= (sizeof(tlv->ouisubtype) + 1);
228
229 /* Move offset to App Priority Table */
230 offset++;
231
232 /* Application Priority Table (3 octets)
233 * Octets:| 1 | 2 | 3 |
234 * -----------------------------------------
235 * |Priority|Rsrvd| Sel | Protocol ID |
236 * -----------------------------------------
237 * Bits:|23 21|20 19|18 16|15 0|
238 * -----------------------------------------
239 */
240 while (offset < length) {
241 dcbcfg->app[i].priority = (u8)((buf[offset] &
242 I40E_IEEE_APP_PRIO_MASK) >>
243 I40E_IEEE_APP_PRIO_SHIFT);
244 dcbcfg->app[i].selector = (u8)((buf[offset] &
245 I40E_IEEE_APP_SEL_MASK) >>
246 I40E_IEEE_APP_SEL_SHIFT);
247 dcbcfg->app[i].protocolid = (buf[offset + 1] << 0x8) |
248 buf[offset + 2];
249 /* Move to next app */
250 offset += 3;
251 i++;
252 if (i >= I40E_DCBX_MAX_APPS)
253 break;
254 }
255
256 dcbcfg->numapps = i;
257 }
258
259 /**
260 * i40e_parse_ieee_etsrec_tlv
261 * @tlv: IEEE 802.1Qaz TLV
262 * @dcbcfg: Local store to update ETS REC data
263 *
264 * Get the TLV subtype and send it to parsing function
265 * based on the subtype value
266 **/
267 static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,
268 struct i40e_dcbx_config *dcbcfg)
269 {
270 u32 ouisubtype;
271 u8 subtype;
272
273 ouisubtype = ntohl(tlv->ouisubtype);
274 subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>
275 I40E_LLDP_TLV_SUBTYPE_SHIFT);
276 switch (subtype) {
277 case I40E_IEEE_SUBTYPE_ETS_CFG:
278 i40e_parse_ieee_etscfg_tlv(tlv, dcbcfg);
279 break;
280 case I40E_IEEE_SUBTYPE_ETS_REC:
281 i40e_parse_ieee_etsrec_tlv(tlv, dcbcfg);
282 break;
283 case I40E_IEEE_SUBTYPE_PFC_CFG:
284 i40e_parse_ieee_pfccfg_tlv(tlv, dcbcfg);
285 break;
286 case I40E_IEEE_SUBTYPE_APP_PRI:
287 i40e_parse_ieee_app_tlv(tlv, dcbcfg);
288 break;
289 default:
290 break;
291 }
292 }
293
294 /**
295 * i40e_parse_cee_pgcfg_tlv
296 * @tlv: CEE DCBX PG CFG TLV
297 * @dcbcfg: Local store to update ETS CFG data
298 *
299 * Parses CEE DCBX PG CFG TLV
300 **/
301 static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,
302 struct i40e_dcbx_config *dcbcfg)
303 {
304 struct i40e_dcb_ets_config *etscfg;
305 u8 *buf = tlv->tlvinfo;
306 u16 offset = 0;
307 u8 priority;
308 int i;
309
310 etscfg = &dcbcfg->etscfg;
311
312 if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
313 etscfg->willing = 1;
314
315 etscfg->cbs = 0;
316 /* Priority Group Table (4 octets)
317 * Octets:| 1 | 2 | 3 | 4 |
318 * -----------------------------------------
319 * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
320 * -----------------------------------------
321 * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|
322 * -----------------------------------------
323 */
324 for (i = 0; i < 4; i++) {
325 priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >>
326 I40E_CEE_PGID_PRIO_1_SHIFT);
327 etscfg->prioritytable[i * 2] = priority;
328 priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >>
329 I40E_CEE_PGID_PRIO_0_SHIFT);
330 etscfg->prioritytable[i * 2 + 1] = priority;
331 offset++;
332 }
333
334 /* PG Percentage Table (8 octets)
335 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
336 * ---------------------------------
337 * |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|
338 * ---------------------------------
339 */
340 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
341 etscfg->tcbwtable[i] = buf[offset++];
342
343 /* Number of TCs supported (1 octet) */
344 etscfg->maxtcs = buf[offset];
345 }
346
347 /**
348 * i40e_parse_cee_pfccfg_tlv
349 * @tlv: CEE DCBX PFC CFG TLV
350 * @dcbcfg: Local store to update PFC CFG data
351 *
352 * Parses CEE DCBX PFC CFG TLV
353 **/
354 static void i40e_parse_cee_pfccfg_tlv(struct i40e_cee_feat_tlv *tlv,
355 struct i40e_dcbx_config *dcbcfg)
356 {
357 u8 *buf = tlv->tlvinfo;
358
359 if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
360 dcbcfg->pfc.willing = 1;
361
362 /* ------------------------
363 * | PFC Enable | PFC TCs |
364 * ------------------------
365 * | 1 octet | 1 octet |
366 */
367 dcbcfg->pfc.pfcenable = buf[0];
368 dcbcfg->pfc.pfccap = buf[1];
369 }
370
371 /**
372 * i40e_parse_cee_app_tlv
373 * @tlv: CEE DCBX APP TLV
374 * @dcbcfg: Local store to update APP PRIO data
375 *
376 * Parses CEE DCBX APP PRIO TLV
377 **/
378 static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv,
379 struct i40e_dcbx_config *dcbcfg)
380 {
381 u16 length, typelength, offset = 0;
382 struct i40e_cee_app_prio *app;
383 u8 i, up, selector;
384
385 typelength = ntohs(tlv->hdr.typelen);
386 length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
387 I40E_LLDP_TLV_LEN_SHIFT);
388
389 dcbcfg->numapps = length / sizeof(*app);
390 if (!dcbcfg->numapps)
391 return;
392
393 for (i = 0; i < dcbcfg->numapps; i++) {
394 app = (struct i40e_cee_app_prio *)(tlv->tlvinfo + offset);
395 for (up = 0; up < I40E_MAX_USER_PRIORITY; up++) {
396 if (app->prio_map & BIT(up))
397 break;
398 }
399 dcbcfg->app[i].priority = up;
400
401 /* Get Selector from lower 2 bits, and convert to IEEE */
402 selector = (app->upper_oui_sel & I40E_CEE_APP_SELECTOR_MASK);
403 if (selector == I40E_CEE_APP_SEL_ETHTYPE)
404 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
405 else if (selector == I40E_CEE_APP_SEL_TCPIP)
406 dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;
407 else
408 /* Keep selector as it is for unknown types */
409 dcbcfg->app[i].selector = selector;
410
411 dcbcfg->app[i].protocolid = ntohs(app->protocol);
412 /* Move to next app */
413 offset += sizeof(*app);
414 }
415 }
416
417 /**
418 * i40e_parse_cee_tlv
419 * @tlv: CEE DCBX TLV
420 * @dcbcfg: Local store to update DCBX config data
421 *
422 * Get the TLV subtype and send it to parsing function
423 * based on the subtype value
424 **/
425 static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,
426 struct i40e_dcbx_config *dcbcfg)
427 {
428 u16 len, tlvlen, sublen, typelength;
429 struct i40e_cee_feat_tlv *sub_tlv;
430 u8 subtype, feat_tlv_count = 0;
431 u32 ouisubtype;
432
433 ouisubtype = ntohl(tlv->ouisubtype);
434 subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>
435 I40E_LLDP_TLV_SUBTYPE_SHIFT);
436 /* Return if not CEE DCBX */
437 if (subtype != I40E_CEE_DCBX_TYPE)
438 return;
439
440 typelength = ntohs(tlv->typelength);
441 tlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
442 I40E_LLDP_TLV_LEN_SHIFT);
443 len = sizeof(tlv->typelength) + sizeof(ouisubtype) +
444 sizeof(struct i40e_cee_ctrl_tlv);
445 /* Return if no CEE DCBX Feature TLVs */
446 if (tlvlen <= len)
447 return;
448
449 sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);
450 while (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) {
451 typelength = ntohs(sub_tlv->hdr.typelen);
452 sublen = (u16)((typelength &
453 I40E_LLDP_TLV_LEN_MASK) >>
454 I40E_LLDP_TLV_LEN_SHIFT);
455 subtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>
456 I40E_LLDP_TLV_TYPE_SHIFT);
457 switch (subtype) {
458 case I40E_CEE_SUBTYPE_PG_CFG:
459 i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);
460 break;
461 case I40E_CEE_SUBTYPE_PFC_CFG:
462 i40e_parse_cee_pfccfg_tlv(sub_tlv, dcbcfg);
463 break;
464 case I40E_CEE_SUBTYPE_APP_PRI:
465 i40e_parse_cee_app_tlv(sub_tlv, dcbcfg);
466 break;
467 default:
468 return; /* Invalid Sub-type return */
469 }
470 feat_tlv_count++;
471 /* Move to next sub TLV */
472 sub_tlv = (struct i40e_cee_feat_tlv *)((char *)sub_tlv +
473 sizeof(sub_tlv->hdr.typelen) +
474 sublen);
475 }
476 }
477
478 /**
479 * i40e_parse_org_tlv
480 * @tlv: Organization specific TLV
481 * @dcbcfg: Local store to update ETS REC data
482 *
483 * Currently only IEEE 802.1Qaz TLV is supported, all others
484 * will be returned
485 **/
486 static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,
487 struct i40e_dcbx_config *dcbcfg)
488 {
489 u32 ouisubtype;
490 u32 oui;
491
492 ouisubtype = ntohl(tlv->ouisubtype);
493 oui = (u32)((ouisubtype & I40E_LLDP_TLV_OUI_MASK) >>
494 I40E_LLDP_TLV_OUI_SHIFT);
495 switch (oui) {
496 case I40E_IEEE_8021QAZ_OUI:
497 i40e_parse_ieee_tlv(tlv, dcbcfg);
498 break;
499 case I40E_CEE_DCBX_OUI:
500 i40e_parse_cee_tlv(tlv, dcbcfg);
501 break;
502 default:
503 break;
504 }
505 }
506
507 /**
508 * i40e_lldp_to_dcb_config
509 * @lldpmib: LLDPDU to be parsed
510 * @dcbcfg: store for LLDPDU data
511 *
512 * Parse DCB configuration from the LLDPDU
513 **/
514 i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
515 struct i40e_dcbx_config *dcbcfg)
516 {
517 i40e_status ret = 0;
518 struct i40e_lldp_org_tlv *tlv;
519 u16 type;
520 u16 length;
521 u16 typelength;
522 u16 offset = 0;
523
524 if (!lldpmib || !dcbcfg)
525 return I40E_ERR_PARAM;
526
527 /* set to the start of LLDPDU */
528 lldpmib += ETH_HLEN;
529 tlv = (struct i40e_lldp_org_tlv *)lldpmib;
530 while (1) {
531 typelength = ntohs(tlv->typelength);
532 type = (u16)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>
533 I40E_LLDP_TLV_TYPE_SHIFT);
534 length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
535 I40E_LLDP_TLV_LEN_SHIFT);
536 offset += sizeof(typelength) + length;
537
538 /* END TLV or beyond LLDPDU size */
539 if ((type == I40E_TLV_TYPE_END) || (offset > I40E_LLDPDU_SIZE))
540 break;
541
542 switch (type) {
543 case I40E_TLV_TYPE_ORG:
544 i40e_parse_org_tlv(tlv, dcbcfg);
545 break;
546 default:
547 break;
548 }
549
550 /* Move to next TLV */
551 tlv = (struct i40e_lldp_org_tlv *)((char *)tlv +
552 sizeof(tlv->typelength) +
553 length);
554 }
555
556 return ret;
557 }
558
559 /**
560 * i40e_aq_get_dcb_config
561 * @hw: pointer to the hw struct
562 * @mib_type: mib type for the query
563 * @bridgetype: bridge type for the query (remote)
564 * @dcbcfg: store for LLDPDU data
565 *
566 * Query DCB configuration from the Firmware
567 **/
568 i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
569 u8 bridgetype,
570 struct i40e_dcbx_config *dcbcfg)
571 {
572 i40e_status ret = 0;
573 struct i40e_virt_mem mem;
574 u8 *lldpmib;
575
576 /* Allocate the LLDPDU */
577 ret = i40e_allocate_virt_mem(hw, &mem, I40E_LLDPDU_SIZE);
578 if (ret)
579 return ret;
580
581 lldpmib = (u8 *)mem.va;
582 ret = i40e_aq_get_lldp_mib(hw, bridgetype, mib_type,
583 (void *)lldpmib, I40E_LLDPDU_SIZE,
584 NULL, NULL, NULL);
585 if (ret)
586 goto free_mem;
587
588 /* Parse LLDP MIB to get dcb configuration */
589 ret = i40e_lldp_to_dcb_config(lldpmib, dcbcfg);
590
591 free_mem:
592 i40e_free_virt_mem(hw, &mem);
593 return ret;
594 }
595
596 /**
597 * i40e_cee_to_dcb_v1_config
598 * @cee_cfg: pointer to CEE v1 response configuration struct
599 * @dcbcfg: DCB configuration struct
600 *
601 * Convert CEE v1 configuration from firmware to DCB configuration
602 **/
603 static void i40e_cee_to_dcb_v1_config(
604 struct i40e_aqc_get_cee_dcb_cfg_v1_resp *cee_cfg,
605 struct i40e_dcbx_config *dcbcfg)
606 {
607 u16 status, tlv_status = le16_to_cpu(cee_cfg->tlv_status);
608 u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio);
609 u8 i, tc, err;
610
611 /* CEE PG data to ETS config */
612 dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
613
614 for (i = 0; i < 4; i++) {
615 tc = (u8)((cee_cfg->oper_prio_tc[i] &
616 I40E_CEE_PGID_PRIO_1_MASK) >>
617 I40E_CEE_PGID_PRIO_1_SHIFT);
618 dcbcfg->etscfg.prioritytable[i*2] = tc;
619 tc = (u8)((cee_cfg->oper_prio_tc[i] &
620 I40E_CEE_PGID_PRIO_0_MASK) >>
621 I40E_CEE_PGID_PRIO_0_SHIFT);
622 dcbcfg->etscfg.prioritytable[i*2 + 1] = tc;
623 }
624
625 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
626 dcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i];
627
628 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
629 if (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) {
630 /* Map it to next empty TC */
631 dcbcfg->etscfg.prioritytable[i] =
632 cee_cfg->oper_num_tc - 1;
633 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;
634 } else {
635 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
636 }
637 }
638
639 /* CEE PFC data to ETS config */
640 dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en;
641 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
642
643 status = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>
644 I40E_AQC_CEE_APP_STATUS_SHIFT;
645 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
646 /* Add APPs if Error is False */
647 if (!err) {
648 /* CEE operating configuration supports FCoE/iSCSI/FIP only */
649 dcbcfg->numapps = I40E_CEE_OPER_MAX_APPS;
650
651 /* FCoE APP */
652 dcbcfg->app[0].priority =
653 (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>
654 I40E_AQC_CEE_APP_FCOE_SHIFT;
655 dcbcfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
656 dcbcfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
657
658 /* iSCSI APP */
659 dcbcfg->app[1].priority =
660 (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>
661 I40E_AQC_CEE_APP_ISCSI_SHIFT;
662 dcbcfg->app[1].selector = I40E_APP_SEL_TCPIP;
663 dcbcfg->app[1].protocolid = I40E_APP_PROTOID_ISCSI;
664
665 /* FIP APP */
666 dcbcfg->app[2].priority =
667 (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>
668 I40E_AQC_CEE_APP_FIP_SHIFT;
669 dcbcfg->app[2].selector = I40E_APP_SEL_ETHTYPE;
670 dcbcfg->app[2].protocolid = I40E_APP_PROTOID_FIP;
671 }
672 }
673
674 /**
675 * i40e_cee_to_dcb_config
676 * @cee_cfg: pointer to CEE configuration struct
677 * @dcbcfg: DCB configuration struct
678 *
679 * Convert CEE configuration from firmware to DCB configuration
680 **/
681 static void i40e_cee_to_dcb_config(
682 struct i40e_aqc_get_cee_dcb_cfg_resp *cee_cfg,
683 struct i40e_dcbx_config *dcbcfg)
684 {
685 u32 status, tlv_status = le32_to_cpu(cee_cfg->tlv_status);
686 u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio);
687 u8 i, tc, err, sync, oper;
688
689 /* CEE PG data to ETS config */
690 dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
691
692 /* Note that the FW creates the oper_prio_tc nibbles reversed
693 * from those in the CEE Priority Group sub-TLV.
694 */
695 for (i = 0; i < 4; i++) {
696 tc = (u8)((cee_cfg->oper_prio_tc[i] &
697 I40E_CEE_PGID_PRIO_0_MASK) >>
698 I40E_CEE_PGID_PRIO_0_SHIFT);
699 dcbcfg->etscfg.prioritytable[i * 2] = tc;
700 tc = (u8)((cee_cfg->oper_prio_tc[i] &
701 I40E_CEE_PGID_PRIO_1_MASK) >>
702 I40E_CEE_PGID_PRIO_1_SHIFT);
703 dcbcfg->etscfg.prioritytable[i * 2 + 1] = tc;
704 }
705
706 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
707 dcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i];
708
709 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
710 if (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) {
711 /* Map it to next empty TC */
712 dcbcfg->etscfg.prioritytable[i] =
713 cee_cfg->oper_num_tc - 1;
714 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;
715 } else {
716 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
717 }
718 }
719
720 /* CEE PFC data to ETS config */
721 dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en;
722 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
723
724 i = 0;
725 status = (tlv_status & I40E_AQC_CEE_FCOE_STATUS_MASK) >>
726 I40E_AQC_CEE_FCOE_STATUS_SHIFT;
727 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
728 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
729 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
730 /* Add FCoE APP if Error is False and Oper/Sync is True */
731 if (!err && sync && oper) {
732 /* FCoE APP */
733 dcbcfg->app[i].priority =
734 (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>
735 I40E_AQC_CEE_APP_FCOE_SHIFT;
736 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
737 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FCOE;
738 i++;
739 }
740
741 status = (tlv_status & I40E_AQC_CEE_ISCSI_STATUS_MASK) >>
742 I40E_AQC_CEE_ISCSI_STATUS_SHIFT;
743 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
744 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
745 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
746 /* Add iSCSI APP if Error is False and Oper/Sync is True */
747 if (!err && sync && oper) {
748 /* iSCSI APP */
749 dcbcfg->app[i].priority =
750 (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>
751 I40E_AQC_CEE_APP_ISCSI_SHIFT;
752 dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;
753 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_ISCSI;
754 i++;
755 }
756
757 status = (tlv_status & I40E_AQC_CEE_FIP_STATUS_MASK) >>
758 I40E_AQC_CEE_FIP_STATUS_SHIFT;
759 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
760 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
761 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
762 /* Add FIP APP if Error is False and Oper/Sync is True */
763 if (!err && sync && oper) {
764 /* FIP APP */
765 dcbcfg->app[i].priority =
766 (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>
767 I40E_AQC_CEE_APP_FIP_SHIFT;
768 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
769 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FIP;
770 i++;
771 }
772 dcbcfg->numapps = i;
773 }
774
775 /**
776 * i40e_get_ieee_dcb_config
777 * @hw: pointer to the hw struct
778 *
779 * Get IEEE mode DCB configuration from the Firmware
780 **/
781 static i40e_status i40e_get_ieee_dcb_config(struct i40e_hw *hw)
782 {
783 i40e_status ret = 0;
784
785 /* IEEE mode */
786 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
787 /* Get Local DCB Config */
788 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
789 &hw->local_dcbx_config);
790 if (ret)
791 goto out;
792
793 /* Get Remote DCB Config */
794 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
795 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
796 &hw->remote_dcbx_config);
797 /* Don't treat ENOENT as an error for Remote MIBs */
798 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
799 ret = 0;
800
801 out:
802 return ret;
803 }
804
805 /**
806 * i40e_get_dcb_config
807 * @hw: pointer to the hw struct
808 *
809 * Get DCB configuration from the Firmware
810 **/
811 i40e_status i40e_get_dcb_config(struct i40e_hw *hw)
812 {
813 i40e_status ret = 0;
814 struct i40e_aqc_get_cee_dcb_cfg_resp cee_cfg;
815 struct i40e_aqc_get_cee_dcb_cfg_v1_resp cee_v1_cfg;
816
817 /* If Firmware version < v4.33 IEEE only */
818 if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) ||
819 (hw->aq.fw_maj_ver < 4))
820 return i40e_get_ieee_dcb_config(hw);
821
822 /* If Firmware version == v4.33 use old CEE struct */
823 if ((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver == 33)) {
824 ret = i40e_aq_get_cee_dcb_config(hw, &cee_v1_cfg,
825 sizeof(cee_v1_cfg), NULL);
826 if (!ret) {
827 /* CEE mode */
828 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE;
829 hw->local_dcbx_config.tlv_status =
830 le16_to_cpu(cee_v1_cfg.tlv_status);
831 i40e_cee_to_dcb_v1_config(&cee_v1_cfg,
832 &hw->local_dcbx_config);
833 }
834 } else {
835 ret = i40e_aq_get_cee_dcb_config(hw, &cee_cfg,
836 sizeof(cee_cfg), NULL);
837 if (!ret) {
838 /* CEE mode */
839 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE;
840 hw->local_dcbx_config.tlv_status =
841 le32_to_cpu(cee_cfg.tlv_status);
842 i40e_cee_to_dcb_config(&cee_cfg,
843 &hw->local_dcbx_config);
844 }
845 }
846
847 /* CEE mode not enabled try querying IEEE data */
848 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
849 return i40e_get_ieee_dcb_config(hw);
850
851 if (ret)
852 goto out;
853
854 /* Get CEE DCB Desired Config */
855 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
856 &hw->desired_dcbx_config);
857 if (ret)
858 goto out;
859
860 /* Get Remote DCB Config */
861 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
862 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
863 &hw->remote_dcbx_config);
864 /* Don't treat ENOENT as an error for Remote MIBs */
865 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)
866 ret = 0;
867
868 out:
869 return ret;
870 }
871
872 /**
873 * i40e_init_dcb
874 * @hw: pointer to the hw struct
875 *
876 * Update DCB configuration from the Firmware
877 **/
878 i40e_status i40e_init_dcb(struct i40e_hw *hw)
879 {
880 i40e_status ret = 0;
881 struct i40e_lldp_variables lldp_cfg;
882 u8 adminstatus = 0;
883
884 if (!hw->func_caps.dcb)
885 return ret;
886
887 /* Read LLDP NVM area */
888 ret = i40e_read_lldp_cfg(hw, &lldp_cfg);
889 if (ret)
890 return ret;
891
892 /* Get the LLDP AdminStatus for the current port */
893 adminstatus = lldp_cfg.adminstatus >> (hw->port * 4);
894 adminstatus &= 0xF;
895
896 /* LLDP agent disabled */
897 if (!adminstatus) {
898 hw->dcbx_status = I40E_DCBX_STATUS_DISABLED;
899 return ret;
900 }
901
902 /* Get DCBX status */
903 ret = i40e_get_dcbx_status(hw, &hw->dcbx_status);
904 if (ret)
905 return ret;
906
907 /* Check the DCBX Status */
908 switch (hw->dcbx_status) {
909 case I40E_DCBX_STATUS_DONE:
910 case I40E_DCBX_STATUS_IN_PROGRESS:
911 /* Get current DCBX configuration */
912 ret = i40e_get_dcb_config(hw);
913 if (ret)
914 return ret;
915 break;
916 case I40E_DCBX_STATUS_DISABLED:
917 return ret;
918 case I40E_DCBX_STATUS_NOT_STARTED:
919 case I40E_DCBX_STATUS_MULTIPLE_PEERS:
920 default:
921 break;
922 }
923
924 /* Configure the LLDP MIB change event */
925 ret = i40e_aq_cfg_lldp_mib_change_event(hw, true, NULL);
926 if (ret)
927 return ret;
928
929 return ret;
930 }
931
932 /**
933 * i40e_read_lldp_cfg - read LLDP Configuration data from NVM
934 * @hw: pointer to the HW structure
935 * @lldp_cfg: pointer to hold lldp configuration variables
936 *
937 * Reads the LLDP configuration data from NVM
938 **/
939 i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw,
940 struct i40e_lldp_variables *lldp_cfg)
941 {
942 i40e_status ret = 0;
943 u32 offset = (2 * I40E_NVM_LLDP_CFG_PTR);
944
945 if (!lldp_cfg)
946 return I40E_ERR_PARAM;
947
948 ret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
949 if (ret)
950 goto err_lldp_cfg;
951
952 ret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, offset,
953 sizeof(struct i40e_lldp_variables),
954 (u8 *)lldp_cfg,
955 true, NULL);
956 i40e_release_nvm(hw);
957
958 err_lldp_cfg:
959 return ret;
960 }
Linux with added FPC-III support