2 * drivers/net/ethernet/mellanox/mlxsw/trap.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
5 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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40 /* Ethernet EMAD and FDB miss */
41 MLXSW_TRAP_ID_FDB_MC
= 0x01,
42 MLXSW_TRAP_ID_ETHEMAD
= 0x05,
43 /* L2 traps for specific packet types */
44 MLXSW_TRAP_ID_STP
= 0x10,
45 MLXSW_TRAP_ID_LACP
= 0x11,
46 MLXSW_TRAP_ID_EAPOL
= 0x12,
47 MLXSW_TRAP_ID_LLDP
= 0x13,
48 MLXSW_TRAP_ID_MMRP
= 0x14,
49 MLXSW_TRAP_ID_MVRP
= 0x15,
50 MLXSW_TRAP_ID_RPVST
= 0x16,
51 MLXSW_TRAP_ID_DHCP
= 0x19,
52 MLXSW_TRAP_ID_IGMP_QUERY
= 0x30,
53 MLXSW_TRAP_ID_IGMP_V1_REPORT
= 0x31,
54 MLXSW_TRAP_ID_IGMP_V2_REPORT
= 0x32,
55 MLXSW_TRAP_ID_IGMP_V2_LEAVE
= 0x33,
56 MLXSW_TRAP_ID_IGMP_V3_REPORT
= 0x34,
58 MLXSW_TRAP_ID_MAX
= 0x1FF
61 enum mlxsw_event_trap_id
{
62 /* Port Up/Down event generated by hardware */
63 MLXSW_TRAP_ID_PUDE
= 0x8,
66 #endif /* _MLXSW_TRAP_H */