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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / net / ethernet / renesas / sh_eth.c
blob6a8fc0f341ff2528fdda1cb97f8e2934d99c5f14
1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
38 #include <linux/io.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
46
47 #include "sh_eth.h"
48
49 #define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
62
63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155 };
156
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
159
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_ADRH0] = 0x0100,
208
209 [TXNLCR0] = 0x0080,
210 [TXALCR0] = 0x0084,
211 [RXNLCR0] = 0x0088,
212 [RXALCR0] = 0x008C,
213 };
214
215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
216 SH_ETH_OFFSET_DEFAULTS,
217
218 [ECMR] = 0x0300,
219 [RFLR] = 0x0308,
220 [ECSR] = 0x0310,
221 [ECSIPR] = 0x0318,
222 [PIR] = 0x0320,
223 [PSR] = 0x0328,
224 [RDMLR] = 0x0340,
225 [IPGR] = 0x0350,
226 [APR] = 0x0354,
227 [MPR] = 0x0358,
228 [RFCF] = 0x0360,
229 [TPAUSER] = 0x0364,
230 [TPAUSECR] = 0x0368,
231 [MAHR] = 0x03c0,
232 [MALR] = 0x03c8,
233 [TROCR] = 0x03d0,
234 [CDCR] = 0x03d4,
235 [LCCR] = 0x03d8,
236 [CNDCR] = 0x03dc,
237 [CEFCR] = 0x03e4,
238 [FRECR] = 0x03e8,
239 [TSFRCR] = 0x03ec,
240 [TLFRCR] = 0x03f0,
241 [RFCR] = 0x03f4,
242 [MAFCR] = 0x03f8,
243
244 [EDMR] = 0x0200,
245 [EDTRR] = 0x0208,
246 [EDRRR] = 0x0210,
247 [TDLAR] = 0x0218,
248 [RDLAR] = 0x0220,
249 [EESR] = 0x0228,
250 [EESIPR] = 0x0230,
251 [TRSCER] = 0x0238,
252 [RMFCR] = 0x0240,
253 [TFTR] = 0x0248,
254 [FDR] = 0x0250,
255 [RMCR] = 0x0258,
256 [TFUCR] = 0x0264,
257 [RFOCR] = 0x0268,
258 [RMIIMODE] = 0x026c,
259 [FCFTR] = 0x0270,
260 [TRIMD] = 0x027c,
261 };
262
263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
264 SH_ETH_OFFSET_DEFAULTS,
265
266 [ECMR] = 0x0100,
267 [RFLR] = 0x0108,
268 [ECSR] = 0x0110,
269 [ECSIPR] = 0x0118,
270 [PIR] = 0x0120,
271 [PSR] = 0x0128,
272 [RDMLR] = 0x0140,
273 [IPGR] = 0x0150,
274 [APR] = 0x0154,
275 [MPR] = 0x0158,
276 [TPAUSER] = 0x0164,
277 [RFCF] = 0x0160,
278 [TPAUSECR] = 0x0168,
279 [BCFRR] = 0x016c,
280 [MAHR] = 0x01c0,
281 [MALR] = 0x01c8,
282 [TROCR] = 0x01d0,
283 [CDCR] = 0x01d4,
284 [LCCR] = 0x01d8,
285 [CNDCR] = 0x01dc,
286 [CEFCR] = 0x01e4,
287 [FRECR] = 0x01e8,
288 [TSFRCR] = 0x01ec,
289 [TLFRCR] = 0x01f0,
290 [RFCR] = 0x01f4,
291 [MAFCR] = 0x01f8,
292 [RTRATE] = 0x01fc,
293
294 [EDMR] = 0x0000,
295 [EDTRR] = 0x0008,
296 [EDRRR] = 0x0010,
297 [TDLAR] = 0x0018,
298 [RDLAR] = 0x0020,
299 [EESR] = 0x0028,
300 [EESIPR] = 0x0030,
301 [TRSCER] = 0x0038,
302 [RMFCR] = 0x0040,
303 [TFTR] = 0x0048,
304 [FDR] = 0x0050,
305 [RMCR] = 0x0058,
306 [TFUCR] = 0x0064,
307 [RFOCR] = 0x0068,
308 [FCFTR] = 0x0070,
309 [RPADIR] = 0x0078,
310 [TRIMD] = 0x007c,
311 [RBWAR] = 0x00c8,
312 [RDFAR] = 0x00cc,
313 [TBRAR] = 0x00d4,
314 [TDFAR] = 0x00d8,
315 };
316
317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
318 SH_ETH_OFFSET_DEFAULTS,
319
320 [EDMR] = 0x0000,
321 [EDTRR] = 0x0004,
322 [EDRRR] = 0x0008,
323 [TDLAR] = 0x000c,
324 [RDLAR] = 0x0010,
325 [EESR] = 0x0014,
326 [EESIPR] = 0x0018,
327 [TRSCER] = 0x001c,
328 [RMFCR] = 0x0020,
329 [TFTR] = 0x0024,
330 [FDR] = 0x0028,
331 [RMCR] = 0x002c,
332 [EDOCR] = 0x0030,
333 [FCFTR] = 0x0034,
334 [RPADIR] = 0x0038,
335 [TRIMD] = 0x003c,
336 [RBWAR] = 0x0040,
337 [RDFAR] = 0x0044,
338 [TBRAR] = 0x004c,
339 [TDFAR] = 0x0050,
340
341 [ECMR] = 0x0160,
342 [ECSR] = 0x0164,
343 [ECSIPR] = 0x0168,
344 [PIR] = 0x016c,
345 [MAHR] = 0x0170,
346 [MALR] = 0x0174,
347 [RFLR] = 0x0178,
348 [PSR] = 0x017c,
349 [TROCR] = 0x0180,
350 [CDCR] = 0x0184,
351 [LCCR] = 0x0188,
352 [CNDCR] = 0x018c,
353 [CEFCR] = 0x0194,
354 [FRECR] = 0x0198,
355 [TSFRCR] = 0x019c,
356 [TLFRCR] = 0x01a0,
357 [RFCR] = 0x01a4,
358 [MAFCR] = 0x01a8,
359 [IPGR] = 0x01b4,
360 [APR] = 0x01b8,
361 [MPR] = 0x01bc,
362 [TPAUSER] = 0x01c4,
363 [BCFR] = 0x01cc,
364
365 [ARSTR] = 0x0000,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
369 [TSU_FCM] = 0x0018,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
381 [TSU_FWSR] = 0x0050,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
384 [TSU_TEN] = 0x0064,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
389
390 [TXNLCR0] = 0x0080,
391 [TXALCR0] = 0x0084,
392 [RXNLCR0] = 0x0088,
393 [RXALCR0] = 0x008c,
394 [FWNLCR0] = 0x0090,
395 [FWALCR0] = 0x0094,
396 [TXNLCR1] = 0x00a0,
397 [TXALCR1] = 0x00a0,
398 [RXNLCR1] = 0x00a8,
399 [RXALCR1] = 0x00ac,
400 [FWNLCR1] = 0x00b0,
401 [FWALCR1] = 0x00b4,
402
403 [TSU_ADRH0] = 0x0100,
404 };
405
406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408
409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410 {
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
413
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415 return;
416
417 iowrite32(data, mdp->addr + offset);
418 }
419
420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421 {
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
424
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426 return ~0U;
427
428 return ioread32(mdp->addr + offset);
429 }
430
431 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
432 {
433 return mdp->reg_offset == sh_eth_offset_gigabit;
434 }
435
436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
437 {
438 return mdp->reg_offset == sh_eth_offset_fast_rz;
439 }
440
441 static void sh_eth_select_mii(struct net_device *ndev)
442 {
443 u32 value = 0x0;
444 struct sh_eth_private *mdp = netdev_priv(ndev);
445
446 switch (mdp->phy_interface) {
447 case PHY_INTERFACE_MODE_GMII:
448 value = 0x2;
449 break;
450 case PHY_INTERFACE_MODE_MII:
451 value = 0x1;
452 break;
453 case PHY_INTERFACE_MODE_RMII:
454 value = 0x0;
455 break;
456 default:
457 netdev_warn(ndev,
458 "PHY interface mode was not setup. Set to MII.\n");
459 value = 0x1;
460 break;
461 }
462
463 sh_eth_write(ndev, value, RMII_MII);
464 }
465
466 static void sh_eth_set_duplex(struct net_device *ndev)
467 {
468 struct sh_eth_private *mdp = netdev_priv(ndev);
469
470 if (mdp->duplex) /* Full */
471 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
472 else /* Half */
473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
474 }
475
476 /* There is CPU dependent code */
477 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
478 {
479 struct sh_eth_private *mdp = netdev_priv(ndev);
480
481 switch (mdp->speed) {
482 case 10: /* 10BASE */
483 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
484 break;
485 case 100:/* 100BASE */
486 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
487 break;
488 default:
489 break;
490 }
491 }
492
493 /* R8A7778/9 */
494 static struct sh_eth_cpu_data r8a777x_data = {
495 .set_duplex = sh_eth_set_duplex,
496 .set_rate = sh_eth_set_rate_r8a777x,
497
498 .register_type = SH_ETH_REG_FAST_RCAR,
499
500 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
501 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
502 .eesipr_value = 0x01ff009f,
503
504 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
505 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
506 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
507 EESR_ECI,
508 .fdr_value = 0x00000f0f,
509
510 .apr = 1,
511 .mpr = 1,
512 .tpauser = 1,
513 .hw_swap = 1,
514 };
515
516 /* R8A7790/1 */
517 static struct sh_eth_cpu_data r8a779x_data = {
518 .set_duplex = sh_eth_set_duplex,
519 .set_rate = sh_eth_set_rate_r8a777x,
520
521 .register_type = SH_ETH_REG_FAST_RCAR,
522
523 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
524 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
525 .eesipr_value = 0x01ff009f,
526
527 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
528 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
529 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
530 EESR_ECI,
531 .fdr_value = 0x00000f0f,
532
533 .trscer_err_mask = DESC_I_RINT8,
534
535 .apr = 1,
536 .mpr = 1,
537 .tpauser = 1,
538 .hw_swap = 1,
539 .rmiimode = 1,
540 };
541
542 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
543 {
544 struct sh_eth_private *mdp = netdev_priv(ndev);
545
546 switch (mdp->speed) {
547 case 10: /* 10BASE */
548 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
549 break;
550 case 100:/* 100BASE */
551 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
552 break;
553 default:
554 break;
555 }
556 }
557
558 /* SH7724 */
559 static struct sh_eth_cpu_data sh7724_data = {
560 .set_duplex = sh_eth_set_duplex,
561 .set_rate = sh_eth_set_rate_sh7724,
562
563 .register_type = SH_ETH_REG_FAST_SH4,
564
565 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
566 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
567 .eesipr_value = 0x01ff009f,
568
569 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
570 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
571 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
572 EESR_ECI,
573
574 .apr = 1,
575 .mpr = 1,
576 .tpauser = 1,
577 .hw_swap = 1,
578 .rpadir = 1,
579 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
580 };
581
582 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
583 {
584 struct sh_eth_private *mdp = netdev_priv(ndev);
585
586 switch (mdp->speed) {
587 case 10: /* 10BASE */
588 sh_eth_write(ndev, 0, RTRATE);
589 break;
590 case 100:/* 100BASE */
591 sh_eth_write(ndev, 1, RTRATE);
592 break;
593 default:
594 break;
595 }
596 }
597
598 /* SH7757 */
599 static struct sh_eth_cpu_data sh7757_data = {
600 .set_duplex = sh_eth_set_duplex,
601 .set_rate = sh_eth_set_rate_sh7757,
602
603 .register_type = SH_ETH_REG_FAST_SH4,
604
605 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
606
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610 EESR_ECI,
611
612 .irq_flags = IRQF_SHARED,
613 .apr = 1,
614 .mpr = 1,
615 .tpauser = 1,
616 .hw_swap = 1,
617 .no_ade = 1,
618 .rpadir = 1,
619 .rpadir_value = 2 << 16,
620 .rtrate = 1,
621 };
622
623 #define SH_GIGA_ETH_BASE 0xfee00000UL
624 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
625 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
626 static void sh_eth_chip_reset_giga(struct net_device *ndev)
627 {
628 int i;
629 u32 mahr[2], malr[2];
630
631 /* save MAHR and MALR */
632 for (i = 0; i < 2; i++) {
633 malr[i] = ioread32((void *)GIGA_MALR(i));
634 mahr[i] = ioread32((void *)GIGA_MAHR(i));
635 }
636
637 /* reset device */
638 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
639 mdelay(1);
640
641 /* restore MAHR and MALR */
642 for (i = 0; i < 2; i++) {
643 iowrite32(malr[i], (void *)GIGA_MALR(i));
644 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
645 }
646 }
647
648 static void sh_eth_set_rate_giga(struct net_device *ndev)
649 {
650 struct sh_eth_private *mdp = netdev_priv(ndev);
651
652 switch (mdp->speed) {
653 case 10: /* 10BASE */
654 sh_eth_write(ndev, 0x00000000, GECMR);
655 break;
656 case 100:/* 100BASE */
657 sh_eth_write(ndev, 0x00000010, GECMR);
658 break;
659 case 1000: /* 1000BASE */
660 sh_eth_write(ndev, 0x00000020, GECMR);
661 break;
662 default:
663 break;
664 }
665 }
666
667 /* SH7757(GETHERC) */
668 static struct sh_eth_cpu_data sh7757_data_giga = {
669 .chip_reset = sh_eth_chip_reset_giga,
670 .set_duplex = sh_eth_set_duplex,
671 .set_rate = sh_eth_set_rate_giga,
672
673 .register_type = SH_ETH_REG_GIGABIT,
674
675 .ecsr_value = ECSR_ICD | ECSR_MPD,
676 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
677 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
678
679 .tx_check = EESR_TC1 | EESR_FTC,
680 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
681 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
682 EESR_TDE | EESR_ECI,
683 .fdr_value = 0x0000072f,
684
685 .irq_flags = IRQF_SHARED,
686 .apr = 1,
687 .mpr = 1,
688 .tpauser = 1,
689 .bculr = 1,
690 .hw_swap = 1,
691 .rpadir = 1,
692 .rpadir_value = 2 << 16,
693 .no_trimd = 1,
694 .no_ade = 1,
695 .tsu = 1,
696 };
697
698 static void sh_eth_chip_reset(struct net_device *ndev)
699 {
700 struct sh_eth_private *mdp = netdev_priv(ndev);
701
702 /* reset device */
703 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
704 mdelay(1);
705 }
706
707 static void sh_eth_set_rate_gether(struct net_device *ndev)
708 {
709 struct sh_eth_private *mdp = netdev_priv(ndev);
710
711 switch (mdp->speed) {
712 case 10: /* 10BASE */
713 sh_eth_write(ndev, GECMR_10, GECMR);
714 break;
715 case 100:/* 100BASE */
716 sh_eth_write(ndev, GECMR_100, GECMR);
717 break;
718 case 1000: /* 1000BASE */
719 sh_eth_write(ndev, GECMR_1000, GECMR);
720 break;
721 default:
722 break;
723 }
724 }
725
726 /* SH7734 */
727 static struct sh_eth_cpu_data sh7734_data = {
728 .chip_reset = sh_eth_chip_reset,
729 .set_duplex = sh_eth_set_duplex,
730 .set_rate = sh_eth_set_rate_gether,
731
732 .register_type = SH_ETH_REG_GIGABIT,
733
734 .ecsr_value = ECSR_ICD | ECSR_MPD,
735 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
736 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
737
738 .tx_check = EESR_TC1 | EESR_FTC,
739 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
740 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
741 EESR_TDE | EESR_ECI,
742
743 .apr = 1,
744 .mpr = 1,
745 .tpauser = 1,
746 .bculr = 1,
747 .hw_swap = 1,
748 .no_trimd = 1,
749 .no_ade = 1,
750 .tsu = 1,
751 .hw_crc = 1,
752 .select_mii = 1,
753 };
754
755 /* SH7763 */
756 static struct sh_eth_cpu_data sh7763_data = {
757 .chip_reset = sh_eth_chip_reset,
758 .set_duplex = sh_eth_set_duplex,
759 .set_rate = sh_eth_set_rate_gether,
760
761 .register_type = SH_ETH_REG_GIGABIT,
762
763 .ecsr_value = ECSR_ICD | ECSR_MPD,
764 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
765 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
766
767 .tx_check = EESR_TC1 | EESR_FTC,
768 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
769 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
770 EESR_ECI,
771
772 .apr = 1,
773 .mpr = 1,
774 .tpauser = 1,
775 .bculr = 1,
776 .hw_swap = 1,
777 .no_trimd = 1,
778 .no_ade = 1,
779 .tsu = 1,
780 .irq_flags = IRQF_SHARED,
781 };
782
783 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
784 {
785 struct sh_eth_private *mdp = netdev_priv(ndev);
786
787 /* reset device */
788 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
789 mdelay(1);
790
791 sh_eth_select_mii(ndev);
792 }
793
794 /* R8A7740 */
795 static struct sh_eth_cpu_data r8a7740_data = {
796 .chip_reset = sh_eth_chip_reset_r8a7740,
797 .set_duplex = sh_eth_set_duplex,
798 .set_rate = sh_eth_set_rate_gether,
799
800 .register_type = SH_ETH_REG_GIGABIT,
801
802 .ecsr_value = ECSR_ICD | ECSR_MPD,
803 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
804 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
805
806 .tx_check = EESR_TC1 | EESR_FTC,
807 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
808 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
809 EESR_TDE | EESR_ECI,
810 .fdr_value = 0x0000070f,
811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
817 .rpadir = 1,
818 .rpadir_value = 2 << 16,
819 .no_trimd = 1,
820 .no_ade = 1,
821 .tsu = 1,
822 .select_mii = 1,
823 .shift_rd0 = 1,
824 };
825
826 /* R7S72100 */
827 static struct sh_eth_cpu_data r7s72100_data = {
828 .chip_reset = sh_eth_chip_reset,
829 .set_duplex = sh_eth_set_duplex,
830
831 .register_type = SH_ETH_REG_FAST_RZ,
832
833 .ecsr_value = ECSR_ICD,
834 .ecsipr_value = ECSIPR_ICDIP,
835 .eesipr_value = 0xff7f009f,
836
837 .tx_check = EESR_TC1 | EESR_FTC,
838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
840 EESR_TDE | EESR_ECI,
841 .fdr_value = 0x0000070f,
842
843 .no_psr = 1,
844 .apr = 1,
845 .mpr = 1,
846 .tpauser = 1,
847 .hw_swap = 1,
848 .rpadir = 1,
849 .rpadir_value = 2 << 16,
850 .no_trimd = 1,
851 .no_ade = 1,
852 .hw_crc = 1,
853 .tsu = 1,
854 .shift_rd0 = 1,
855 };
856
857 static struct sh_eth_cpu_data sh7619_data = {
858 .register_type = SH_ETH_REG_FAST_SH3_SH2,
859
860 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
861
862 .apr = 1,
863 .mpr = 1,
864 .tpauser = 1,
865 .hw_swap = 1,
866 };
867
868 static struct sh_eth_cpu_data sh771x_data = {
869 .register_type = SH_ETH_REG_FAST_SH3_SH2,
870
871 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
872 .tsu = 1,
873 };
874
875 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
876 {
877 if (!cd->ecsr_value)
878 cd->ecsr_value = DEFAULT_ECSR_INIT;
879
880 if (!cd->ecsipr_value)
881 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
882
883 if (!cd->fcftr_value)
884 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
885 DEFAULT_FIFO_F_D_RFD;
886
887 if (!cd->fdr_value)
888 cd->fdr_value = DEFAULT_FDR_INIT;
889
890 if (!cd->tx_check)
891 cd->tx_check = DEFAULT_TX_CHECK;
892
893 if (!cd->eesr_err_check)
894 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
895
896 if (!cd->trscer_err_mask)
897 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
898 }
899
900 static int sh_eth_check_reset(struct net_device *ndev)
901 {
902 int ret = 0;
903 int cnt = 100;
904
905 while (cnt > 0) {
906 if (!(sh_eth_read(ndev, EDMR) & 0x3))
907 break;
908 mdelay(1);
909 cnt--;
910 }
911 if (cnt <= 0) {
912 netdev_err(ndev, "Device reset failed\n");
913 ret = -ETIMEDOUT;
914 }
915 return ret;
916 }
917
918 static int sh_eth_reset(struct net_device *ndev)
919 {
920 struct sh_eth_private *mdp = netdev_priv(ndev);
921 int ret = 0;
922
923 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
924 sh_eth_write(ndev, EDSR_ENALL, EDSR);
925 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
926 EDMR);
927
928 ret = sh_eth_check_reset(ndev);
929 if (ret)
930 return ret;
931
932 /* Table Init */
933 sh_eth_write(ndev, 0x0, TDLAR);
934 sh_eth_write(ndev, 0x0, TDFAR);
935 sh_eth_write(ndev, 0x0, TDFXR);
936 sh_eth_write(ndev, 0x0, TDFFR);
937 sh_eth_write(ndev, 0x0, RDLAR);
938 sh_eth_write(ndev, 0x0, RDFAR);
939 sh_eth_write(ndev, 0x0, RDFXR);
940 sh_eth_write(ndev, 0x0, RDFFR);
941
942 /* Reset HW CRC register */
943 if (mdp->cd->hw_crc)
944 sh_eth_write(ndev, 0x0, CSMR);
945
946 /* Select MII mode */
947 if (mdp->cd->select_mii)
948 sh_eth_select_mii(ndev);
949 } else {
950 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
951 EDMR);
952 mdelay(3);
953 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
954 EDMR);
955 }
956
957 return ret;
958 }
959
960 static void sh_eth_set_receive_align(struct sk_buff *skb)
961 {
962 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
963
964 if (reserve)
965 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
966 }
967
968
969 /* CPU <-> EDMAC endian convert */
970 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
971 {
972 switch (mdp->edmac_endian) {
973 case EDMAC_LITTLE_ENDIAN:
974 return cpu_to_le32(x);
975 case EDMAC_BIG_ENDIAN:
976 return cpu_to_be32(x);
977 }
978 return x;
979 }
980
981 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
982 {
983 switch (mdp->edmac_endian) {
984 case EDMAC_LITTLE_ENDIAN:
985 return le32_to_cpu(x);
986 case EDMAC_BIG_ENDIAN:
987 return be32_to_cpu(x);
988 }
989 return x;
990 }
991
992 /* Program the hardware MAC address from dev->dev_addr. */
993 static void update_mac_address(struct net_device *ndev)
994 {
995 sh_eth_write(ndev,
996 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
997 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
998 sh_eth_write(ndev,
999 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1000 }
1001
1002 /* Get MAC address from SuperH MAC address register
1003 *
1004 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1005 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1006 * When you want use this device, you must set MAC address in bootloader.
1007 *
1008 */
1009 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1010 {
1011 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1012 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1013 } else {
1014 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
1015 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
1016 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
1017 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
1018 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
1019 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
1020 }
1021 }
1022
1023 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1024 {
1025 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1026 return EDTRR_TRNS_GETHER;
1027 else
1028 return EDTRR_TRNS_ETHER;
1029 }
1030
1031 struct bb_info {
1032 void (*set_gate)(void *addr);
1033 struct mdiobb_ctrl ctrl;
1034 void *addr;
1035 u32 mmd_msk;/* MMD */
1036 u32 mdo_msk;
1037 u32 mdi_msk;
1038 u32 mdc_msk;
1039 };
1040
1041 /* PHY bit set */
1042 static void bb_set(void *addr, u32 msk)
1043 {
1044 iowrite32(ioread32(addr) | msk, addr);
1045 }
1046
1047 /* PHY bit clear */
1048 static void bb_clr(void *addr, u32 msk)
1049 {
1050 iowrite32((ioread32(addr) & ~msk), addr);
1051 }
1052
1053 /* PHY bit read */
1054 static int bb_read(void *addr, u32 msk)
1055 {
1056 return (ioread32(addr) & msk) != 0;
1057 }
1058
1059 /* Data I/O pin control */
1060 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1061 {
1062 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1063
1064 if (bitbang->set_gate)
1065 bitbang->set_gate(bitbang->addr);
1066
1067 if (bit)
1068 bb_set(bitbang->addr, bitbang->mmd_msk);
1069 else
1070 bb_clr(bitbang->addr, bitbang->mmd_msk);
1071 }
1072
1073 /* Set bit data*/
1074 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1075 {
1076 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1077
1078 if (bitbang->set_gate)
1079 bitbang->set_gate(bitbang->addr);
1080
1081 if (bit)
1082 bb_set(bitbang->addr, bitbang->mdo_msk);
1083 else
1084 bb_clr(bitbang->addr, bitbang->mdo_msk);
1085 }
1086
1087 /* Get bit data*/
1088 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1089 {
1090 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1091
1092 if (bitbang->set_gate)
1093 bitbang->set_gate(bitbang->addr);
1094
1095 return bb_read(bitbang->addr, bitbang->mdi_msk);
1096 }
1097
1098 /* MDC pin control */
1099 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1100 {
1101 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1102
1103 if (bitbang->set_gate)
1104 bitbang->set_gate(bitbang->addr);
1105
1106 if (bit)
1107 bb_set(bitbang->addr, bitbang->mdc_msk);
1108 else
1109 bb_clr(bitbang->addr, bitbang->mdc_msk);
1110 }
1111
1112 /* mdio bus control struct */
1113 static struct mdiobb_ops bb_ops = {
1114 .owner = THIS_MODULE,
1115 .set_mdc = sh_mdc_ctrl,
1116 .set_mdio_dir = sh_mmd_ctrl,
1117 .set_mdio_data = sh_set_mdio,
1118 .get_mdio_data = sh_get_mdio,
1119 };
1120
1121 /* free skb and descriptor buffer */
1122 static void sh_eth_ring_free(struct net_device *ndev)
1123 {
1124 struct sh_eth_private *mdp = netdev_priv(ndev);
1125 int ringsize, i;
1126
1127 /* Free Rx skb ringbuffer */
1128 if (mdp->rx_skbuff) {
1129 for (i = 0; i < mdp->num_rx_ring; i++)
1130 dev_kfree_skb(mdp->rx_skbuff[i]);
1131 }
1132 kfree(mdp->rx_skbuff);
1133 mdp->rx_skbuff = NULL;
1134
1135 /* Free Tx skb ringbuffer */
1136 if (mdp->tx_skbuff) {
1137 for (i = 0; i < mdp->num_tx_ring; i++)
1138 dev_kfree_skb(mdp->tx_skbuff[i]);
1139 }
1140 kfree(mdp->tx_skbuff);
1141 mdp->tx_skbuff = NULL;
1142
1143 if (mdp->rx_ring) {
1144 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1145 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1146 mdp->rx_desc_dma);
1147 mdp->rx_ring = NULL;
1148 }
1149
1150 if (mdp->tx_ring) {
1151 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1152 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1153 mdp->tx_desc_dma);
1154 mdp->tx_ring = NULL;
1155 }
1156 }
1157
1158 /* format skb and descriptor buffer */
1159 static void sh_eth_ring_format(struct net_device *ndev)
1160 {
1161 struct sh_eth_private *mdp = netdev_priv(ndev);
1162 int i;
1163 struct sk_buff *skb;
1164 struct sh_eth_rxdesc *rxdesc = NULL;
1165 struct sh_eth_txdesc *txdesc = NULL;
1166 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1167 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1168 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1169 dma_addr_t dma_addr;
1170 u32 buf_len;
1171
1172 mdp->cur_rx = 0;
1173 mdp->cur_tx = 0;
1174 mdp->dirty_rx = 0;
1175 mdp->dirty_tx = 0;
1176
1177 memset(mdp->rx_ring, 0, rx_ringsize);
1178
1179 /* build Rx ring buffer */
1180 for (i = 0; i < mdp->num_rx_ring; i++) {
1181 /* skb */
1182 mdp->rx_skbuff[i] = NULL;
1183 skb = netdev_alloc_skb(ndev, skbuff_size);
1184 if (skb == NULL)
1185 break;
1186 sh_eth_set_receive_align(skb);
1187
1188 /* RX descriptor */
1189 rxdesc = &mdp->rx_ring[i];
1190 /* The size of the buffer is a multiple of 32 bytes. */
1191 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1192 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1193 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1194 DMA_FROM_DEVICE);
1195 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1196 kfree_skb(skb);
1197 break;
1198 }
1199 mdp->rx_skbuff[i] = skb;
1200 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1201 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1202
1203 /* Rx descriptor address set */
1204 if (i == 0) {
1205 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1206 if (sh_eth_is_gether(mdp) ||
1207 sh_eth_is_rz_fast_ether(mdp))
1208 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1209 }
1210 }
1211
1212 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1213
1214 /* Mark the last entry as wrapping the ring. */
1215 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1216
1217 memset(mdp->tx_ring, 0, tx_ringsize);
1218
1219 /* build Tx ring buffer */
1220 for (i = 0; i < mdp->num_tx_ring; i++) {
1221 mdp->tx_skbuff[i] = NULL;
1222 txdesc = &mdp->tx_ring[i];
1223 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1224 txdesc->len = cpu_to_edmac(mdp, 0);
1225 if (i == 0) {
1226 /* Tx descriptor address set */
1227 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1228 if (sh_eth_is_gether(mdp) ||
1229 sh_eth_is_rz_fast_ether(mdp))
1230 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1231 }
1232 }
1233
1234 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1235 }
1236
1237 /* Get skb and descriptor buffer */
1238 static int sh_eth_ring_init(struct net_device *ndev)
1239 {
1240 struct sh_eth_private *mdp = netdev_priv(ndev);
1241 int rx_ringsize, tx_ringsize;
1242
1243 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1244 * card needs room to do 8 byte alignment, +2 so we can reserve
1245 * the first 2 bytes, and +16 gets room for the status word from the
1246 * card.
1247 */
1248 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1249 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1250 if (mdp->cd->rpadir)
1251 mdp->rx_buf_sz += NET_IP_ALIGN;
1252
1253 /* Allocate RX and TX skb rings */
1254 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1255 GFP_KERNEL);
1256 if (!mdp->rx_skbuff)
1257 return -ENOMEM;
1258
1259 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1260 GFP_KERNEL);
1261 if (!mdp->tx_skbuff)
1262 goto ring_free;
1263
1264 /* Allocate all Rx descriptors. */
1265 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1266 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1267 GFP_KERNEL);
1268 if (!mdp->rx_ring)
1269 goto ring_free;
1270
1271 mdp->dirty_rx = 0;
1272
1273 /* Allocate all Tx descriptors. */
1274 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1275 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1276 GFP_KERNEL);
1277 if (!mdp->tx_ring)
1278 goto ring_free;
1279 return 0;
1280
1281 ring_free:
1282 /* Free Rx and Tx skb ring buffer and DMA buffer */
1283 sh_eth_ring_free(ndev);
1284
1285 return -ENOMEM;
1286 }
1287
1288 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1289 {
1290 int ret = 0;
1291 struct sh_eth_private *mdp = netdev_priv(ndev);
1292 u32 val;
1293
1294 /* Soft Reset */
1295 ret = sh_eth_reset(ndev);
1296 if (ret)
1297 return ret;
1298
1299 if (mdp->cd->rmiimode)
1300 sh_eth_write(ndev, 0x1, RMIIMODE);
1301
1302 /* Descriptor format */
1303 sh_eth_ring_format(ndev);
1304 if (mdp->cd->rpadir)
1305 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1306
1307 /* all sh_eth int mask */
1308 sh_eth_write(ndev, 0, EESIPR);
1309
1310 #if defined(__LITTLE_ENDIAN)
1311 if (mdp->cd->hw_swap)
1312 sh_eth_write(ndev, EDMR_EL, EDMR);
1313 else
1314 #endif
1315 sh_eth_write(ndev, 0, EDMR);
1316
1317 /* FIFO size set */
1318 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1319 sh_eth_write(ndev, 0, TFTR);
1320
1321 /* Frame recv control (enable multiple-packets per rx irq) */
1322 sh_eth_write(ndev, RMCR_RNC, RMCR);
1323
1324 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1325
1326 if (mdp->cd->bculr)
1327 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1328
1329 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1330
1331 if (!mdp->cd->no_trimd)
1332 sh_eth_write(ndev, 0, TRIMD);
1333
1334 /* Recv frame limit set register */
1335 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1336 RFLR);
1337
1338 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1339 if (start) {
1340 mdp->irq_enabled = true;
1341 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1342 }
1343
1344 /* PAUSE Prohibition */
1345 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1346 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1347
1348 sh_eth_write(ndev, val, ECMR);
1349
1350 if (mdp->cd->set_rate)
1351 mdp->cd->set_rate(ndev);
1352
1353 /* E-MAC Status Register clear */
1354 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1355
1356 /* E-MAC Interrupt Enable register */
1357 if (start)
1358 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1359
1360 /* Set MAC address */
1361 update_mac_address(ndev);
1362
1363 /* mask reset */
1364 if (mdp->cd->apr)
1365 sh_eth_write(ndev, APR_AP, APR);
1366 if (mdp->cd->mpr)
1367 sh_eth_write(ndev, MPR_MP, MPR);
1368 if (mdp->cd->tpauser)
1369 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1370
1371 if (start) {
1372 /* Setting the Rx mode will start the Rx process. */
1373 sh_eth_write(ndev, EDRRR_R, EDRRR);
1374
1375 netif_start_queue(ndev);
1376 }
1377
1378 return ret;
1379 }
1380
1381 static void sh_eth_dev_exit(struct net_device *ndev)
1382 {
1383 struct sh_eth_private *mdp = netdev_priv(ndev);
1384 int i;
1385
1386 /* Deactivate all TX descriptors, so DMA should stop at next
1387 * packet boundary if it's currently running
1388 */
1389 for (i = 0; i < mdp->num_tx_ring; i++)
1390 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1391
1392 /* Disable TX FIFO egress to MAC */
1393 sh_eth_rcv_snd_disable(ndev);
1394
1395 /* Stop RX DMA at next packet boundary */
1396 sh_eth_write(ndev, 0, EDRRR);
1397
1398 /* Aside from TX DMA, we can't tell when the hardware is
1399 * really stopped, so we need to reset to make sure.
1400 * Before doing that, wait for long enough to *probably*
1401 * finish transmitting the last packet and poll stats.
1402 */
1403 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1404 sh_eth_get_stats(ndev);
1405 sh_eth_reset(ndev);
1406
1407 /* Set MAC address again */
1408 update_mac_address(ndev);
1409 }
1410
1411 /* free Tx skb function */
1412 static int sh_eth_txfree(struct net_device *ndev)
1413 {
1414 struct sh_eth_private *mdp = netdev_priv(ndev);
1415 struct sh_eth_txdesc *txdesc;
1416 int free_num = 0;
1417 int entry = 0;
1418
1419 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1420 entry = mdp->dirty_tx % mdp->num_tx_ring;
1421 txdesc = &mdp->tx_ring[entry];
1422 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1423 break;
1424 /* TACT bit must be checked before all the following reads */
1425 dma_rmb();
1426 netif_info(mdp, tx_done, ndev,
1427 "tx entry %d status 0x%08x\n",
1428 entry, edmac_to_cpu(mdp, txdesc->status));
1429 /* Free the original skb. */
1430 if (mdp->tx_skbuff[entry]) {
1431 dma_unmap_single(&ndev->dev,
1432 edmac_to_cpu(mdp, txdesc->addr),
1433 edmac_to_cpu(mdp, txdesc->len) >> 16,
1434 DMA_TO_DEVICE);
1435 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1436 mdp->tx_skbuff[entry] = NULL;
1437 free_num++;
1438 }
1439 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1440 if (entry >= mdp->num_tx_ring - 1)
1441 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1442
1443 ndev->stats.tx_packets++;
1444 ndev->stats.tx_bytes += edmac_to_cpu(mdp, txdesc->len) >> 16;
1445 }
1446 return free_num;
1447 }
1448
1449 /* Packet receive function */
1450 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1451 {
1452 struct sh_eth_private *mdp = netdev_priv(ndev);
1453 struct sh_eth_rxdesc *rxdesc;
1454
1455 int entry = mdp->cur_rx % mdp->num_rx_ring;
1456 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1457 int limit;
1458 struct sk_buff *skb;
1459 u16 pkt_len = 0;
1460 u32 desc_status;
1461 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1462 dma_addr_t dma_addr;
1463 u32 buf_len;
1464
1465 boguscnt = min(boguscnt, *quota);
1466 limit = boguscnt;
1467 rxdesc = &mdp->rx_ring[entry];
1468 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1469 /* RACT bit must be checked before all the following reads */
1470 dma_rmb();
1471 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1472 pkt_len = edmac_to_cpu(mdp, rxdesc->len) & RD_RFL;
1473
1474 if (--boguscnt < 0)
1475 break;
1476
1477 netif_info(mdp, rx_status, ndev,
1478 "rx entry %d status 0x%08x len %d\n",
1479 entry, desc_status, pkt_len);
1480
1481 if (!(desc_status & RDFEND))
1482 ndev->stats.rx_length_errors++;
1483
1484 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1485 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1486 * bit 0. However, in case of the R8A7740 and R7S72100
1487 * the RFS bits are from bit 25 to bit 16. So, the
1488 * driver needs right shifting by 16.
1489 */
1490 if (mdp->cd->shift_rd0)
1491 desc_status >>= 16;
1492
1493 skb = mdp->rx_skbuff[entry];
1494 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1495 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1496 ndev->stats.rx_errors++;
1497 if (desc_status & RD_RFS1)
1498 ndev->stats.rx_crc_errors++;
1499 if (desc_status & RD_RFS2)
1500 ndev->stats.rx_frame_errors++;
1501 if (desc_status & RD_RFS3)
1502 ndev->stats.rx_length_errors++;
1503 if (desc_status & RD_RFS4)
1504 ndev->stats.rx_length_errors++;
1505 if (desc_status & RD_RFS6)
1506 ndev->stats.rx_missed_errors++;
1507 if (desc_status & RD_RFS10)
1508 ndev->stats.rx_over_errors++;
1509 } else if (skb) {
1510 dma_addr = edmac_to_cpu(mdp, rxdesc->addr);
1511 if (!mdp->cd->hw_swap)
1512 sh_eth_soft_swap(
1513 phys_to_virt(ALIGN(dma_addr, 4)),
1514 pkt_len + 2);
1515 mdp->rx_skbuff[entry] = NULL;
1516 if (mdp->cd->rpadir)
1517 skb_reserve(skb, NET_IP_ALIGN);
1518 dma_unmap_single(&ndev->dev, dma_addr,
1519 ALIGN(mdp->rx_buf_sz, 32),
1520 DMA_FROM_DEVICE);
1521 skb_put(skb, pkt_len);
1522 skb->protocol = eth_type_trans(skb, ndev);
1523 netif_receive_skb(skb);
1524 ndev->stats.rx_packets++;
1525 ndev->stats.rx_bytes += pkt_len;
1526 if (desc_status & RD_RFS8)
1527 ndev->stats.multicast++;
1528 }
1529 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1530 rxdesc = &mdp->rx_ring[entry];
1531 }
1532
1533 /* Refill the Rx ring buffers. */
1534 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1535 entry = mdp->dirty_rx % mdp->num_rx_ring;
1536 rxdesc = &mdp->rx_ring[entry];
1537 /* The size of the buffer is 32 byte boundary. */
1538 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1539 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1540
1541 if (mdp->rx_skbuff[entry] == NULL) {
1542 skb = netdev_alloc_skb(ndev, skbuff_size);
1543 if (skb == NULL)
1544 break; /* Better luck next round. */
1545 sh_eth_set_receive_align(skb);
1546 dma_addr = dma_map_single(&ndev->dev, skb->data,
1547 buf_len, DMA_FROM_DEVICE);
1548 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1549 kfree_skb(skb);
1550 break;
1551 }
1552 mdp->rx_skbuff[entry] = skb;
1553
1554 skb_checksum_none_assert(skb);
1555 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1556 }
1557 dma_wmb(); /* RACT bit must be set after all the above writes */
1558 if (entry >= mdp->num_rx_ring - 1)
1559 rxdesc->status |=
1560 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1561 else
1562 rxdesc->status |=
1563 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1564 }
1565
1566 /* Restart Rx engine if stopped. */
1567 /* If we don't need to check status, don't. -KDU */
1568 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1569 /* fix the values for the next receiving if RDE is set */
1570 if (intr_status & EESR_RDE &&
1571 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1572 u32 count = (sh_eth_read(ndev, RDFAR) -
1573 sh_eth_read(ndev, RDLAR)) >> 4;
1574
1575 mdp->cur_rx = count;
1576 mdp->dirty_rx = count;
1577 }
1578 sh_eth_write(ndev, EDRRR_R, EDRRR);
1579 }
1580
1581 *quota -= limit - boguscnt - 1;
1582
1583 return *quota <= 0;
1584 }
1585
1586 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1587 {
1588 /* disable tx and rx */
1589 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1590 ~(ECMR_RE | ECMR_TE), ECMR);
1591 }
1592
1593 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1594 {
1595 /* enable tx and rx */
1596 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1597 (ECMR_RE | ECMR_TE), ECMR);
1598 }
1599
1600 /* error control function */
1601 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1602 {
1603 struct sh_eth_private *mdp = netdev_priv(ndev);
1604 u32 felic_stat;
1605 u32 link_stat;
1606 u32 mask;
1607
1608 if (intr_status & EESR_ECI) {
1609 felic_stat = sh_eth_read(ndev, ECSR);
1610 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1611 if (felic_stat & ECSR_ICD)
1612 ndev->stats.tx_carrier_errors++;
1613 if (felic_stat & ECSR_LCHNG) {
1614 /* Link Changed */
1615 if (mdp->cd->no_psr || mdp->no_ether_link) {
1616 goto ignore_link;
1617 } else {
1618 link_stat = (sh_eth_read(ndev, PSR));
1619 if (mdp->ether_link_active_low)
1620 link_stat = ~link_stat;
1621 }
1622 if (!(link_stat & PHY_ST_LINK)) {
1623 sh_eth_rcv_snd_disable(ndev);
1624 } else {
1625 /* Link Up */
1626 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1627 ~DMAC_M_ECI, EESIPR);
1628 /* clear int */
1629 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1630 ECSR);
1631 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1632 DMAC_M_ECI, EESIPR);
1633 /* enable tx and rx */
1634 sh_eth_rcv_snd_enable(ndev);
1635 }
1636 }
1637 }
1638
1639 ignore_link:
1640 if (intr_status & EESR_TWB) {
1641 /* Unused write back interrupt */
1642 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1643 ndev->stats.tx_aborted_errors++;
1644 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1645 }
1646 }
1647
1648 if (intr_status & EESR_RABT) {
1649 /* Receive Abort int */
1650 if (intr_status & EESR_RFRMER) {
1651 /* Receive Frame Overflow int */
1652 ndev->stats.rx_frame_errors++;
1653 }
1654 }
1655
1656 if (intr_status & EESR_TDE) {
1657 /* Transmit Descriptor Empty int */
1658 ndev->stats.tx_fifo_errors++;
1659 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1660 }
1661
1662 if (intr_status & EESR_TFE) {
1663 /* FIFO under flow */
1664 ndev->stats.tx_fifo_errors++;
1665 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1666 }
1667
1668 if (intr_status & EESR_RDE) {
1669 /* Receive Descriptor Empty int */
1670 ndev->stats.rx_over_errors++;
1671 }
1672
1673 if (intr_status & EESR_RFE) {
1674 /* Receive FIFO Overflow int */
1675 ndev->stats.rx_fifo_errors++;
1676 }
1677
1678 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1679 /* Address Error */
1680 ndev->stats.tx_fifo_errors++;
1681 netif_err(mdp, tx_err, ndev, "Address Error\n");
1682 }
1683
1684 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1685 if (mdp->cd->no_ade)
1686 mask &= ~EESR_ADE;
1687 if (intr_status & mask) {
1688 /* Tx error */
1689 u32 edtrr = sh_eth_read(ndev, EDTRR);
1690
1691 /* dmesg */
1692 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1693 intr_status, mdp->cur_tx, mdp->dirty_tx,
1694 (u32)ndev->state, edtrr);
1695 /* dirty buffer free */
1696 sh_eth_txfree(ndev);
1697
1698 /* SH7712 BUG */
1699 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1700 /* tx dma start */
1701 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1702 }
1703 /* wakeup */
1704 netif_wake_queue(ndev);
1705 }
1706 }
1707
1708 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1709 {
1710 struct net_device *ndev = netdev;
1711 struct sh_eth_private *mdp = netdev_priv(ndev);
1712 struct sh_eth_cpu_data *cd = mdp->cd;
1713 irqreturn_t ret = IRQ_NONE;
1714 u32 intr_status, intr_enable;
1715
1716 spin_lock(&mdp->lock);
1717
1718 /* Get interrupt status */
1719 intr_status = sh_eth_read(ndev, EESR);
1720 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1721 * enabled since it's the one that comes thru regardless of the mask,
1722 * and we need to fully handle it in sh_eth_error() in order to quench
1723 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1724 */
1725 intr_enable = sh_eth_read(ndev, EESIPR);
1726 intr_status &= intr_enable | DMAC_M_ECI;
1727 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1728 ret = IRQ_HANDLED;
1729 else
1730 goto out;
1731
1732 if (!likely(mdp->irq_enabled)) {
1733 sh_eth_write(ndev, 0, EESIPR);
1734 goto out;
1735 }
1736
1737 if (intr_status & EESR_RX_CHECK) {
1738 if (napi_schedule_prep(&mdp->napi)) {
1739 /* Mask Rx interrupts */
1740 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1741 EESIPR);
1742 __napi_schedule(&mdp->napi);
1743 } else {
1744 netdev_warn(ndev,
1745 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1746 intr_status, intr_enable);
1747 }
1748 }
1749
1750 /* Tx Check */
1751 if (intr_status & cd->tx_check) {
1752 /* Clear Tx interrupts */
1753 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1754
1755 sh_eth_txfree(ndev);
1756 netif_wake_queue(ndev);
1757 }
1758
1759 if (intr_status & cd->eesr_err_check) {
1760 /* Clear error interrupts */
1761 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1762
1763 sh_eth_error(ndev, intr_status);
1764 }
1765
1766 out:
1767 spin_unlock(&mdp->lock);
1768
1769 return ret;
1770 }
1771
1772 static int sh_eth_poll(struct napi_struct *napi, int budget)
1773 {
1774 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1775 napi);
1776 struct net_device *ndev = napi->dev;
1777 int quota = budget;
1778 u32 intr_status;
1779
1780 for (;;) {
1781 intr_status = sh_eth_read(ndev, EESR);
1782 if (!(intr_status & EESR_RX_CHECK))
1783 break;
1784 /* Clear Rx interrupts */
1785 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1786
1787 if (sh_eth_rx(ndev, intr_status, &quota))
1788 goto out;
1789 }
1790
1791 napi_complete(napi);
1792
1793 /* Reenable Rx interrupts */
1794 if (mdp->irq_enabled)
1795 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1796 out:
1797 return budget - quota;
1798 }
1799
1800 /* PHY state control function */
1801 static void sh_eth_adjust_link(struct net_device *ndev)
1802 {
1803 struct sh_eth_private *mdp = netdev_priv(ndev);
1804 struct phy_device *phydev = mdp->phydev;
1805 int new_state = 0;
1806
1807 if (phydev->link) {
1808 if (phydev->duplex != mdp->duplex) {
1809 new_state = 1;
1810 mdp->duplex = phydev->duplex;
1811 if (mdp->cd->set_duplex)
1812 mdp->cd->set_duplex(ndev);
1813 }
1814
1815 if (phydev->speed != mdp->speed) {
1816 new_state = 1;
1817 mdp->speed = phydev->speed;
1818 if (mdp->cd->set_rate)
1819 mdp->cd->set_rate(ndev);
1820 }
1821 if (!mdp->link) {
1822 sh_eth_write(ndev,
1823 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1824 ECMR);
1825 new_state = 1;
1826 mdp->link = phydev->link;
1827 if (mdp->cd->no_psr || mdp->no_ether_link)
1828 sh_eth_rcv_snd_enable(ndev);
1829 }
1830 } else if (mdp->link) {
1831 new_state = 1;
1832 mdp->link = 0;
1833 mdp->speed = 0;
1834 mdp->duplex = -1;
1835 if (mdp->cd->no_psr || mdp->no_ether_link)
1836 sh_eth_rcv_snd_disable(ndev);
1837 }
1838
1839 if (new_state && netif_msg_link(mdp))
1840 phy_print_status(phydev);
1841 }
1842
1843 /* PHY init function */
1844 static int sh_eth_phy_init(struct net_device *ndev)
1845 {
1846 struct device_node *np = ndev->dev.parent->of_node;
1847 struct sh_eth_private *mdp = netdev_priv(ndev);
1848 struct phy_device *phydev = NULL;
1849
1850 mdp->link = 0;
1851 mdp->speed = 0;
1852 mdp->duplex = -1;
1853
1854 /* Try connect to PHY */
1855 if (np) {
1856 struct device_node *pn;
1857
1858 pn = of_parse_phandle(np, "phy-handle", 0);
1859 phydev = of_phy_connect(ndev, pn,
1860 sh_eth_adjust_link, 0,
1861 mdp->phy_interface);
1862
1863 if (!phydev)
1864 phydev = ERR_PTR(-ENOENT);
1865 } else {
1866 char phy_id[MII_BUS_ID_SIZE + 3];
1867
1868 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1869 mdp->mii_bus->id, mdp->phy_id);
1870
1871 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1872 mdp->phy_interface);
1873 }
1874
1875 if (IS_ERR(phydev)) {
1876 netdev_err(ndev, "failed to connect PHY\n");
1877 return PTR_ERR(phydev);
1878 }
1879
1880 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1881 phydev->addr, phydev->irq, phydev->drv->name);
1882
1883 mdp->phydev = phydev;
1884
1885 return 0;
1886 }
1887
1888 /* PHY control start function */
1889 static int sh_eth_phy_start(struct net_device *ndev)
1890 {
1891 struct sh_eth_private *mdp = netdev_priv(ndev);
1892 int ret;
1893
1894 ret = sh_eth_phy_init(ndev);
1895 if (ret)
1896 return ret;
1897
1898 phy_start(mdp->phydev);
1899
1900 return 0;
1901 }
1902
1903 static int sh_eth_get_settings(struct net_device *ndev,
1904 struct ethtool_cmd *ecmd)
1905 {
1906 struct sh_eth_private *mdp = netdev_priv(ndev);
1907 unsigned long flags;
1908 int ret;
1909
1910 if (!mdp->phydev)
1911 return -ENODEV;
1912
1913 spin_lock_irqsave(&mdp->lock, flags);
1914 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1915 spin_unlock_irqrestore(&mdp->lock, flags);
1916
1917 return ret;
1918 }
1919
1920 static int sh_eth_set_settings(struct net_device *ndev,
1921 struct ethtool_cmd *ecmd)
1922 {
1923 struct sh_eth_private *mdp = netdev_priv(ndev);
1924 unsigned long flags;
1925 int ret;
1926
1927 if (!mdp->phydev)
1928 return -ENODEV;
1929
1930 spin_lock_irqsave(&mdp->lock, flags);
1931
1932 /* disable tx and rx */
1933 sh_eth_rcv_snd_disable(ndev);
1934
1935 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1936 if (ret)
1937 goto error_exit;
1938
1939 if (ecmd->duplex == DUPLEX_FULL)
1940 mdp->duplex = 1;
1941 else
1942 mdp->duplex = 0;
1943
1944 if (mdp->cd->set_duplex)
1945 mdp->cd->set_duplex(ndev);
1946
1947 error_exit:
1948 mdelay(1);
1949
1950 /* enable tx and rx */
1951 sh_eth_rcv_snd_enable(ndev);
1952
1953 spin_unlock_irqrestore(&mdp->lock, flags);
1954
1955 return ret;
1956 }
1957
1958 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1959 * version must be bumped as well. Just adding registers up to that
1960 * limit is fine, as long as the existing register indices don't
1961 * change.
1962 */
1963 #define SH_ETH_REG_DUMP_VERSION 1
1964 #define SH_ETH_REG_DUMP_MAX_REGS 256
1965
1966 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1967 {
1968 struct sh_eth_private *mdp = netdev_priv(ndev);
1969 struct sh_eth_cpu_data *cd = mdp->cd;
1970 u32 *valid_map;
1971 size_t len;
1972
1973 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1974
1975 /* Dump starts with a bitmap that tells ethtool which
1976 * registers are defined for this chip.
1977 */
1978 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1979 if (buf) {
1980 valid_map = buf;
1981 buf += len;
1982 } else {
1983 valid_map = NULL;
1984 }
1985
1986 /* Add a register to the dump, if it has a defined offset.
1987 * This automatically skips most undefined registers, but for
1988 * some it is also necessary to check a capability flag in
1989 * struct sh_eth_cpu_data.
1990 */
1991 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1992 #define add_reg_from(reg, read_expr) do { \
1993 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1994 if (buf) { \
1995 mark_reg_valid(reg); \
1996 *buf++ = read_expr; \
1997 } \
1998 ++len; \
1999 } \
2000 } while (0)
2001 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2002 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2003
2004 add_reg(EDSR);
2005 add_reg(EDMR);
2006 add_reg(EDTRR);
2007 add_reg(EDRRR);
2008 add_reg(EESR);
2009 add_reg(EESIPR);
2010 add_reg(TDLAR);
2011 add_reg(TDFAR);
2012 add_reg(TDFXR);
2013 add_reg(TDFFR);
2014 add_reg(RDLAR);
2015 add_reg(RDFAR);
2016 add_reg(RDFXR);
2017 add_reg(RDFFR);
2018 add_reg(TRSCER);
2019 add_reg(RMFCR);
2020 add_reg(TFTR);
2021 add_reg(FDR);
2022 add_reg(RMCR);
2023 add_reg(TFUCR);
2024 add_reg(RFOCR);
2025 if (cd->rmiimode)
2026 add_reg(RMIIMODE);
2027 add_reg(FCFTR);
2028 if (cd->rpadir)
2029 add_reg(RPADIR);
2030 if (!cd->no_trimd)
2031 add_reg(TRIMD);
2032 add_reg(ECMR);
2033 add_reg(ECSR);
2034 add_reg(ECSIPR);
2035 add_reg(PIR);
2036 if (!cd->no_psr)
2037 add_reg(PSR);
2038 add_reg(RDMLR);
2039 add_reg(RFLR);
2040 add_reg(IPGR);
2041 if (cd->apr)
2042 add_reg(APR);
2043 if (cd->mpr)
2044 add_reg(MPR);
2045 add_reg(RFCR);
2046 add_reg(RFCF);
2047 if (cd->tpauser)
2048 add_reg(TPAUSER);
2049 add_reg(TPAUSECR);
2050 add_reg(GECMR);
2051 if (cd->bculr)
2052 add_reg(BCULR);
2053 add_reg(MAHR);
2054 add_reg(MALR);
2055 add_reg(TROCR);
2056 add_reg(CDCR);
2057 add_reg(LCCR);
2058 add_reg(CNDCR);
2059 add_reg(CEFCR);
2060 add_reg(FRECR);
2061 add_reg(TSFRCR);
2062 add_reg(TLFRCR);
2063 add_reg(CERCR);
2064 add_reg(CEECR);
2065 add_reg(MAFCR);
2066 if (cd->rtrate)
2067 add_reg(RTRATE);
2068 if (cd->hw_crc)
2069 add_reg(CSMR);
2070 if (cd->select_mii)
2071 add_reg(RMII_MII);
2072 add_reg(ARSTR);
2073 if (cd->tsu) {
2074 add_tsu_reg(TSU_CTRST);
2075 add_tsu_reg(TSU_FWEN0);
2076 add_tsu_reg(TSU_FWEN1);
2077 add_tsu_reg(TSU_FCM);
2078 add_tsu_reg(TSU_BSYSL0);
2079 add_tsu_reg(TSU_BSYSL1);
2080 add_tsu_reg(TSU_PRISL0);
2081 add_tsu_reg(TSU_PRISL1);
2082 add_tsu_reg(TSU_FWSL0);
2083 add_tsu_reg(TSU_FWSL1);
2084 add_tsu_reg(TSU_FWSLC);
2085 add_tsu_reg(TSU_QTAG0);
2086 add_tsu_reg(TSU_QTAG1);
2087 add_tsu_reg(TSU_QTAGM0);
2088 add_tsu_reg(TSU_QTAGM1);
2089 add_tsu_reg(TSU_FWSR);
2090 add_tsu_reg(TSU_FWINMK);
2091 add_tsu_reg(TSU_ADQT0);
2092 add_tsu_reg(TSU_ADQT1);
2093 add_tsu_reg(TSU_VTAG0);
2094 add_tsu_reg(TSU_VTAG1);
2095 add_tsu_reg(TSU_ADSBSY);
2096 add_tsu_reg(TSU_TEN);
2097 add_tsu_reg(TSU_POST1);
2098 add_tsu_reg(TSU_POST2);
2099 add_tsu_reg(TSU_POST3);
2100 add_tsu_reg(TSU_POST4);
2101 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2102 /* This is the start of a table, not just a single
2103 * register.
2104 */
2105 if (buf) {
2106 unsigned int i;
2107
2108 mark_reg_valid(TSU_ADRH0);
2109 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2110 *buf++ = ioread32(
2111 mdp->tsu_addr +
2112 mdp->reg_offset[TSU_ADRH0] +
2113 i * 4);
2114 }
2115 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2116 }
2117 }
2118
2119 #undef mark_reg_valid
2120 #undef add_reg_from
2121 #undef add_reg
2122 #undef add_tsu_reg
2123
2124 return len * 4;
2125 }
2126
2127 static int sh_eth_get_regs_len(struct net_device *ndev)
2128 {
2129 return __sh_eth_get_regs(ndev, NULL);
2130 }
2131
2132 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2133 void *buf)
2134 {
2135 struct sh_eth_private *mdp = netdev_priv(ndev);
2136
2137 regs->version = SH_ETH_REG_DUMP_VERSION;
2138
2139 pm_runtime_get_sync(&mdp->pdev->dev);
2140 __sh_eth_get_regs(ndev, buf);
2141 pm_runtime_put_sync(&mdp->pdev->dev);
2142 }
2143
2144 static int sh_eth_nway_reset(struct net_device *ndev)
2145 {
2146 struct sh_eth_private *mdp = netdev_priv(ndev);
2147 unsigned long flags;
2148 int ret;
2149
2150 if (!mdp->phydev)
2151 return -ENODEV;
2152
2153 spin_lock_irqsave(&mdp->lock, flags);
2154 ret = phy_start_aneg(mdp->phydev);
2155 spin_unlock_irqrestore(&mdp->lock, flags);
2156
2157 return ret;
2158 }
2159
2160 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2161 {
2162 struct sh_eth_private *mdp = netdev_priv(ndev);
2163 return mdp->msg_enable;
2164 }
2165
2166 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2167 {
2168 struct sh_eth_private *mdp = netdev_priv(ndev);
2169 mdp->msg_enable = value;
2170 }
2171
2172 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2173 "rx_current", "tx_current",
2174 "rx_dirty", "tx_dirty",
2175 };
2176 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2177
2178 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2179 {
2180 switch (sset) {
2181 case ETH_SS_STATS:
2182 return SH_ETH_STATS_LEN;
2183 default:
2184 return -EOPNOTSUPP;
2185 }
2186 }
2187
2188 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2189 struct ethtool_stats *stats, u64 *data)
2190 {
2191 struct sh_eth_private *mdp = netdev_priv(ndev);
2192 int i = 0;
2193
2194 /* device-specific stats */
2195 data[i++] = mdp->cur_rx;
2196 data[i++] = mdp->cur_tx;
2197 data[i++] = mdp->dirty_rx;
2198 data[i++] = mdp->dirty_tx;
2199 }
2200
2201 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2202 {
2203 switch (stringset) {
2204 case ETH_SS_STATS:
2205 memcpy(data, *sh_eth_gstrings_stats,
2206 sizeof(sh_eth_gstrings_stats));
2207 break;
2208 }
2209 }
2210
2211 static void sh_eth_get_ringparam(struct net_device *ndev,
2212 struct ethtool_ringparam *ring)
2213 {
2214 struct sh_eth_private *mdp = netdev_priv(ndev);
2215
2216 ring->rx_max_pending = RX_RING_MAX;
2217 ring->tx_max_pending = TX_RING_MAX;
2218 ring->rx_pending = mdp->num_rx_ring;
2219 ring->tx_pending = mdp->num_tx_ring;
2220 }
2221
2222 static int sh_eth_set_ringparam(struct net_device *ndev,
2223 struct ethtool_ringparam *ring)
2224 {
2225 struct sh_eth_private *mdp = netdev_priv(ndev);
2226 int ret;
2227
2228 if (ring->tx_pending > TX_RING_MAX ||
2229 ring->rx_pending > RX_RING_MAX ||
2230 ring->tx_pending < TX_RING_MIN ||
2231 ring->rx_pending < RX_RING_MIN)
2232 return -EINVAL;
2233 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2234 return -EINVAL;
2235
2236 if (netif_running(ndev)) {
2237 netif_device_detach(ndev);
2238 netif_tx_disable(ndev);
2239
2240 /* Serialise with the interrupt handler and NAPI, then
2241 * disable interrupts. We have to clear the
2242 * irq_enabled flag first to ensure that interrupts
2243 * won't be re-enabled.
2244 */
2245 mdp->irq_enabled = false;
2246 synchronize_irq(ndev->irq);
2247 napi_synchronize(&mdp->napi);
2248 sh_eth_write(ndev, 0x0000, EESIPR);
2249
2250 sh_eth_dev_exit(ndev);
2251
2252 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2253 sh_eth_ring_free(ndev);
2254 }
2255
2256 /* Set new parameters */
2257 mdp->num_rx_ring = ring->rx_pending;
2258 mdp->num_tx_ring = ring->tx_pending;
2259
2260 if (netif_running(ndev)) {
2261 ret = sh_eth_ring_init(ndev);
2262 if (ret < 0) {
2263 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2264 __func__);
2265 return ret;
2266 }
2267 ret = sh_eth_dev_init(ndev, false);
2268 if (ret < 0) {
2269 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2270 __func__);
2271 return ret;
2272 }
2273
2274 mdp->irq_enabled = true;
2275 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2276 /* Setting the Rx mode will start the Rx process. */
2277 sh_eth_write(ndev, EDRRR_R, EDRRR);
2278 netif_device_attach(ndev);
2279 }
2280
2281 return 0;
2282 }
2283
2284 static const struct ethtool_ops sh_eth_ethtool_ops = {
2285 .get_settings = sh_eth_get_settings,
2286 .set_settings = sh_eth_set_settings,
2287 .get_regs_len = sh_eth_get_regs_len,
2288 .get_regs = sh_eth_get_regs,
2289 .nway_reset = sh_eth_nway_reset,
2290 .get_msglevel = sh_eth_get_msglevel,
2291 .set_msglevel = sh_eth_set_msglevel,
2292 .get_link = ethtool_op_get_link,
2293 .get_strings = sh_eth_get_strings,
2294 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2295 .get_sset_count = sh_eth_get_sset_count,
2296 .get_ringparam = sh_eth_get_ringparam,
2297 .set_ringparam = sh_eth_set_ringparam,
2298 };
2299
2300 /* network device open function */
2301 static int sh_eth_open(struct net_device *ndev)
2302 {
2303 int ret = 0;
2304 struct sh_eth_private *mdp = netdev_priv(ndev);
2305
2306 pm_runtime_get_sync(&mdp->pdev->dev);
2307
2308 napi_enable(&mdp->napi);
2309
2310 ret = request_irq(ndev->irq, sh_eth_interrupt,
2311 mdp->cd->irq_flags, ndev->name, ndev);
2312 if (ret) {
2313 netdev_err(ndev, "Can not assign IRQ number\n");
2314 goto out_napi_off;
2315 }
2316
2317 /* Descriptor set */
2318 ret = sh_eth_ring_init(ndev);
2319 if (ret)
2320 goto out_free_irq;
2321
2322 /* device init */
2323 ret = sh_eth_dev_init(ndev, true);
2324 if (ret)
2325 goto out_free_irq;
2326
2327 /* PHY control start*/
2328 ret = sh_eth_phy_start(ndev);
2329 if (ret)
2330 goto out_free_irq;
2331
2332 mdp->is_opened = 1;
2333
2334 return ret;
2335
2336 out_free_irq:
2337 free_irq(ndev->irq, ndev);
2338 out_napi_off:
2339 napi_disable(&mdp->napi);
2340 pm_runtime_put_sync(&mdp->pdev->dev);
2341 return ret;
2342 }
2343
2344 /* Timeout function */
2345 static void sh_eth_tx_timeout(struct net_device *ndev)
2346 {
2347 struct sh_eth_private *mdp = netdev_priv(ndev);
2348 struct sh_eth_rxdesc *rxdesc;
2349 int i;
2350
2351 netif_stop_queue(ndev);
2352
2353 netif_err(mdp, timer, ndev,
2354 "transmit timed out, status %8.8x, resetting...\n",
2355 sh_eth_read(ndev, EESR));
2356
2357 /* tx_errors count up */
2358 ndev->stats.tx_errors++;
2359
2360 /* Free all the skbuffs in the Rx queue. */
2361 for (i = 0; i < mdp->num_rx_ring; i++) {
2362 rxdesc = &mdp->rx_ring[i];
2363 rxdesc->status = cpu_to_edmac(mdp, 0);
2364 rxdesc->addr = cpu_to_edmac(mdp, 0xBADF00D0);
2365 dev_kfree_skb(mdp->rx_skbuff[i]);
2366 mdp->rx_skbuff[i] = NULL;
2367 }
2368 for (i = 0; i < mdp->num_tx_ring; i++) {
2369 dev_kfree_skb(mdp->tx_skbuff[i]);
2370 mdp->tx_skbuff[i] = NULL;
2371 }
2372
2373 /* device init */
2374 sh_eth_dev_init(ndev, true);
2375 }
2376
2377 /* Packet transmit function */
2378 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2379 {
2380 struct sh_eth_private *mdp = netdev_priv(ndev);
2381 struct sh_eth_txdesc *txdesc;
2382 dma_addr_t dma_addr;
2383 u32 entry;
2384 unsigned long flags;
2385
2386 spin_lock_irqsave(&mdp->lock, flags);
2387 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2388 if (!sh_eth_txfree(ndev)) {
2389 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2390 netif_stop_queue(ndev);
2391 spin_unlock_irqrestore(&mdp->lock, flags);
2392 return NETDEV_TX_BUSY;
2393 }
2394 }
2395 spin_unlock_irqrestore(&mdp->lock, flags);
2396
2397 if (skb_put_padto(skb, ETH_ZLEN))
2398 return NETDEV_TX_OK;
2399
2400 entry = mdp->cur_tx % mdp->num_tx_ring;
2401 mdp->tx_skbuff[entry] = skb;
2402 txdesc = &mdp->tx_ring[entry];
2403 /* soft swap. */
2404 if (!mdp->cd->hw_swap)
2405 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2406 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2407 DMA_TO_DEVICE);
2408 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2409 kfree_skb(skb);
2410 return NETDEV_TX_OK;
2411 }
2412 txdesc->addr = cpu_to_edmac(mdp, dma_addr);
2413 txdesc->len = cpu_to_edmac(mdp, skb->len << 16);
2414
2415 dma_wmb(); /* TACT bit must be set after all the above writes */
2416 if (entry >= mdp->num_tx_ring - 1)
2417 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2418 else
2419 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2420
2421 mdp->cur_tx++;
2422
2423 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2424 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2425
2426 return NETDEV_TX_OK;
2427 }
2428
2429 /* The statistics registers have write-clear behaviour, which means we
2430 * will lose any increment between the read and write. We mitigate
2431 * this by only clearing when we read a non-zero value, so we will
2432 * never falsely report a total of zero.
2433 */
2434 static void
2435 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2436 {
2437 u32 delta = sh_eth_read(ndev, reg);
2438
2439 if (delta) {
2440 *stat += delta;
2441 sh_eth_write(ndev, 0, reg);
2442 }
2443 }
2444
2445 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2446 {
2447 struct sh_eth_private *mdp = netdev_priv(ndev);
2448
2449 if (sh_eth_is_rz_fast_ether(mdp))
2450 return &ndev->stats;
2451
2452 if (!mdp->is_opened)
2453 return &ndev->stats;
2454
2455 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2456 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2457 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2458
2459 if (sh_eth_is_gether(mdp)) {
2460 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2461 CERCR);
2462 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2463 CEECR);
2464 } else {
2465 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2466 CNDCR);
2467 }
2468
2469 return &ndev->stats;
2470 }
2471
2472 /* device close function */
2473 static int sh_eth_close(struct net_device *ndev)
2474 {
2475 struct sh_eth_private *mdp = netdev_priv(ndev);
2476
2477 netif_stop_queue(ndev);
2478
2479 /* Serialise with the interrupt handler and NAPI, then disable
2480 * interrupts. We have to clear the irq_enabled flag first to
2481 * ensure that interrupts won't be re-enabled.
2482 */
2483 mdp->irq_enabled = false;
2484 synchronize_irq(ndev->irq);
2485 napi_disable(&mdp->napi);
2486 sh_eth_write(ndev, 0x0000, EESIPR);
2487
2488 sh_eth_dev_exit(ndev);
2489
2490 /* PHY Disconnect */
2491 if (mdp->phydev) {
2492 phy_stop(mdp->phydev);
2493 phy_disconnect(mdp->phydev);
2494 mdp->phydev = NULL;
2495 }
2496
2497 free_irq(ndev->irq, ndev);
2498
2499 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2500 sh_eth_ring_free(ndev);
2501
2502 pm_runtime_put_sync(&mdp->pdev->dev);
2503
2504 mdp->is_opened = 0;
2505
2506 return 0;
2507 }
2508
2509 /* ioctl to device function */
2510 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2511 {
2512 struct sh_eth_private *mdp = netdev_priv(ndev);
2513 struct phy_device *phydev = mdp->phydev;
2514
2515 if (!netif_running(ndev))
2516 return -EINVAL;
2517
2518 if (!phydev)
2519 return -ENODEV;
2520
2521 return phy_mii_ioctl(phydev, rq, cmd);
2522 }
2523
2524 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2525 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2526 int entry)
2527 {
2528 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2529 }
2530
2531 static u32 sh_eth_tsu_get_post_mask(int entry)
2532 {
2533 return 0x0f << (28 - ((entry % 8) * 4));
2534 }
2535
2536 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2537 {
2538 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2539 }
2540
2541 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2542 int entry)
2543 {
2544 struct sh_eth_private *mdp = netdev_priv(ndev);
2545 u32 tmp;
2546 void *reg_offset;
2547
2548 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2549 tmp = ioread32(reg_offset);
2550 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2551 }
2552
2553 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2554 int entry)
2555 {
2556 struct sh_eth_private *mdp = netdev_priv(ndev);
2557 u32 post_mask, ref_mask, tmp;
2558 void *reg_offset;
2559
2560 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2561 post_mask = sh_eth_tsu_get_post_mask(entry);
2562 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2563
2564 tmp = ioread32(reg_offset);
2565 iowrite32(tmp & ~post_mask, reg_offset);
2566
2567 /* If other port enables, the function returns "true" */
2568 return tmp & ref_mask;
2569 }
2570
2571 static int sh_eth_tsu_busy(struct net_device *ndev)
2572 {
2573 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2574 struct sh_eth_private *mdp = netdev_priv(ndev);
2575
2576 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2577 udelay(10);
2578 timeout--;
2579 if (timeout <= 0) {
2580 netdev_err(ndev, "%s: timeout\n", __func__);
2581 return -ETIMEDOUT;
2582 }
2583 }
2584
2585 return 0;
2586 }
2587
2588 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2589 const u8 *addr)
2590 {
2591 u32 val;
2592
2593 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2594 iowrite32(val, reg);
2595 if (sh_eth_tsu_busy(ndev) < 0)
2596 return -EBUSY;
2597
2598 val = addr[4] << 8 | addr[5];
2599 iowrite32(val, reg + 4);
2600 if (sh_eth_tsu_busy(ndev) < 0)
2601 return -EBUSY;
2602
2603 return 0;
2604 }
2605
2606 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2607 {
2608 u32 val;
2609
2610 val = ioread32(reg);
2611 addr[0] = (val >> 24) & 0xff;
2612 addr[1] = (val >> 16) & 0xff;
2613 addr[2] = (val >> 8) & 0xff;
2614 addr[3] = val & 0xff;
2615 val = ioread32(reg + 4);
2616 addr[4] = (val >> 8) & 0xff;
2617 addr[5] = val & 0xff;
2618 }
2619
2620
2621 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2622 {
2623 struct sh_eth_private *mdp = netdev_priv(ndev);
2624 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2625 int i;
2626 u8 c_addr[ETH_ALEN];
2627
2628 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2629 sh_eth_tsu_read_entry(reg_offset, c_addr);
2630 if (ether_addr_equal(addr, c_addr))
2631 return i;
2632 }
2633
2634 return -ENOENT;
2635 }
2636
2637 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2638 {
2639 u8 blank[ETH_ALEN];
2640 int entry;
2641
2642 memset(blank, 0, sizeof(blank));
2643 entry = sh_eth_tsu_find_entry(ndev, blank);
2644 return (entry < 0) ? -ENOMEM : entry;
2645 }
2646
2647 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2648 int entry)
2649 {
2650 struct sh_eth_private *mdp = netdev_priv(ndev);
2651 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2652 int ret;
2653 u8 blank[ETH_ALEN];
2654
2655 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2656 ~(1 << (31 - entry)), TSU_TEN);
2657
2658 memset(blank, 0, sizeof(blank));
2659 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2660 if (ret < 0)
2661 return ret;
2662 return 0;
2663 }
2664
2665 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2666 {
2667 struct sh_eth_private *mdp = netdev_priv(ndev);
2668 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2669 int i, ret;
2670
2671 if (!mdp->cd->tsu)
2672 return 0;
2673
2674 i = sh_eth_tsu_find_entry(ndev, addr);
2675 if (i < 0) {
2676 /* No entry found, create one */
2677 i = sh_eth_tsu_find_empty(ndev);
2678 if (i < 0)
2679 return -ENOMEM;
2680 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2681 if (ret < 0)
2682 return ret;
2683
2684 /* Enable the entry */
2685 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2686 (1 << (31 - i)), TSU_TEN);
2687 }
2688
2689 /* Entry found or created, enable POST */
2690 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2691
2692 return 0;
2693 }
2694
2695 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2696 {
2697 struct sh_eth_private *mdp = netdev_priv(ndev);
2698 int i, ret;
2699
2700 if (!mdp->cd->tsu)
2701 return 0;
2702
2703 i = sh_eth_tsu_find_entry(ndev, addr);
2704 if (i) {
2705 /* Entry found */
2706 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2707 goto done;
2708
2709 /* Disable the entry if both ports was disabled */
2710 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2711 if (ret < 0)
2712 return ret;
2713 }
2714 done:
2715 return 0;
2716 }
2717
2718 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2719 {
2720 struct sh_eth_private *mdp = netdev_priv(ndev);
2721 int i, ret;
2722
2723 if (!mdp->cd->tsu)
2724 return 0;
2725
2726 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2727 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2728 continue;
2729
2730 /* Disable the entry if both ports was disabled */
2731 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2732 if (ret < 0)
2733 return ret;
2734 }
2735
2736 return 0;
2737 }
2738
2739 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2740 {
2741 struct sh_eth_private *mdp = netdev_priv(ndev);
2742 u8 addr[ETH_ALEN];
2743 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2744 int i;
2745
2746 if (!mdp->cd->tsu)
2747 return;
2748
2749 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2750 sh_eth_tsu_read_entry(reg_offset, addr);
2751 if (is_multicast_ether_addr(addr))
2752 sh_eth_tsu_del_entry(ndev, addr);
2753 }
2754 }
2755
2756 /* Update promiscuous flag and multicast filter */
2757 static void sh_eth_set_rx_mode(struct net_device *ndev)
2758 {
2759 struct sh_eth_private *mdp = netdev_priv(ndev);
2760 u32 ecmr_bits;
2761 int mcast_all = 0;
2762 unsigned long flags;
2763
2764 spin_lock_irqsave(&mdp->lock, flags);
2765 /* Initial condition is MCT = 1, PRM = 0.
2766 * Depending on ndev->flags, set PRM or clear MCT
2767 */
2768 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2769 if (mdp->cd->tsu)
2770 ecmr_bits |= ECMR_MCT;
2771
2772 if (!(ndev->flags & IFF_MULTICAST)) {
2773 sh_eth_tsu_purge_mcast(ndev);
2774 mcast_all = 1;
2775 }
2776 if (ndev->flags & IFF_ALLMULTI) {
2777 sh_eth_tsu_purge_mcast(ndev);
2778 ecmr_bits &= ~ECMR_MCT;
2779 mcast_all = 1;
2780 }
2781
2782 if (ndev->flags & IFF_PROMISC) {
2783 sh_eth_tsu_purge_all(ndev);
2784 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2785 } else if (mdp->cd->tsu) {
2786 struct netdev_hw_addr *ha;
2787 netdev_for_each_mc_addr(ha, ndev) {
2788 if (mcast_all && is_multicast_ether_addr(ha->addr))
2789 continue;
2790
2791 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2792 if (!mcast_all) {
2793 sh_eth_tsu_purge_mcast(ndev);
2794 ecmr_bits &= ~ECMR_MCT;
2795 mcast_all = 1;
2796 }
2797 }
2798 }
2799 }
2800
2801 /* update the ethernet mode */
2802 sh_eth_write(ndev, ecmr_bits, ECMR);
2803
2804 spin_unlock_irqrestore(&mdp->lock, flags);
2805 }
2806
2807 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2808 {
2809 if (!mdp->port)
2810 return TSU_VTAG0;
2811 else
2812 return TSU_VTAG1;
2813 }
2814
2815 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2816 __be16 proto, u16 vid)
2817 {
2818 struct sh_eth_private *mdp = netdev_priv(ndev);
2819 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2820
2821 if (unlikely(!mdp->cd->tsu))
2822 return -EPERM;
2823
2824 /* No filtering if vid = 0 */
2825 if (!vid)
2826 return 0;
2827
2828 mdp->vlan_num_ids++;
2829
2830 /* The controller has one VLAN tag HW filter. So, if the filter is
2831 * already enabled, the driver disables it and the filte
2832 */
2833 if (mdp->vlan_num_ids > 1) {
2834 /* disable VLAN filter */
2835 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2836 return 0;
2837 }
2838
2839 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2840 vtag_reg_index);
2841
2842 return 0;
2843 }
2844
2845 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2846 __be16 proto, u16 vid)
2847 {
2848 struct sh_eth_private *mdp = netdev_priv(ndev);
2849 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2850
2851 if (unlikely(!mdp->cd->tsu))
2852 return -EPERM;
2853
2854 /* No filtering if vid = 0 */
2855 if (!vid)
2856 return 0;
2857
2858 mdp->vlan_num_ids--;
2859 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2860
2861 return 0;
2862 }
2863
2864 /* SuperH's TSU register init function */
2865 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2866 {
2867 if (sh_eth_is_rz_fast_ether(mdp)) {
2868 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2869 return;
2870 }
2871
2872 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2873 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2874 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2875 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2876 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2877 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2878 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2879 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2880 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2881 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2882 if (sh_eth_is_gether(mdp)) {
2883 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2884 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2885 } else {
2886 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2887 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2888 }
2889 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2890 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2891 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2892 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2893 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2894 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2895 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2896 }
2897
2898 /* MDIO bus release function */
2899 static int sh_mdio_release(struct sh_eth_private *mdp)
2900 {
2901 /* unregister mdio bus */
2902 mdiobus_unregister(mdp->mii_bus);
2903
2904 /* free bitbang info */
2905 free_mdio_bitbang(mdp->mii_bus);
2906
2907 return 0;
2908 }
2909
2910 /* MDIO bus init function */
2911 static int sh_mdio_init(struct sh_eth_private *mdp,
2912 struct sh_eth_plat_data *pd)
2913 {
2914 int ret, i;
2915 struct bb_info *bitbang;
2916 struct platform_device *pdev = mdp->pdev;
2917 struct device *dev = &mdp->pdev->dev;
2918
2919 /* create bit control struct for PHY */
2920 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2921 if (!bitbang)
2922 return -ENOMEM;
2923
2924 /* bitbang init */
2925 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2926 bitbang->set_gate = pd->set_mdio_gate;
2927 bitbang->mdi_msk = PIR_MDI;
2928 bitbang->mdo_msk = PIR_MDO;
2929 bitbang->mmd_msk = PIR_MMD;
2930 bitbang->mdc_msk = PIR_MDC;
2931 bitbang->ctrl.ops = &bb_ops;
2932
2933 /* MII controller setting */
2934 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2935 if (!mdp->mii_bus)
2936 return -ENOMEM;
2937
2938 /* Hook up MII support for ethtool */
2939 mdp->mii_bus->name = "sh_mii";
2940 mdp->mii_bus->parent = dev;
2941 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2942 pdev->name, pdev->id);
2943
2944 /* PHY IRQ */
2945 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2946 GFP_KERNEL);
2947 if (!mdp->mii_bus->irq) {
2948 ret = -ENOMEM;
2949 goto out_free_bus;
2950 }
2951
2952 /* register MDIO bus */
2953 if (dev->of_node) {
2954 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2955 } else {
2956 for (i = 0; i < PHY_MAX_ADDR; i++)
2957 mdp->mii_bus->irq[i] = PHY_POLL;
2958 if (pd->phy_irq > 0)
2959 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2960
2961 ret = mdiobus_register(mdp->mii_bus);
2962 }
2963
2964 if (ret)
2965 goto out_free_bus;
2966
2967 return 0;
2968
2969 out_free_bus:
2970 free_mdio_bitbang(mdp->mii_bus);
2971 return ret;
2972 }
2973
2974 static const u16 *sh_eth_get_register_offset(int register_type)
2975 {
2976 const u16 *reg_offset = NULL;
2977
2978 switch (register_type) {
2979 case SH_ETH_REG_GIGABIT:
2980 reg_offset = sh_eth_offset_gigabit;
2981 break;
2982 case SH_ETH_REG_FAST_RZ:
2983 reg_offset = sh_eth_offset_fast_rz;
2984 break;
2985 case SH_ETH_REG_FAST_RCAR:
2986 reg_offset = sh_eth_offset_fast_rcar;
2987 break;
2988 case SH_ETH_REG_FAST_SH4:
2989 reg_offset = sh_eth_offset_fast_sh4;
2990 break;
2991 case SH_ETH_REG_FAST_SH3_SH2:
2992 reg_offset = sh_eth_offset_fast_sh3_sh2;
2993 break;
2994 default:
2995 break;
2996 }
2997
2998 return reg_offset;
2999 }
3000
3001 static const struct net_device_ops sh_eth_netdev_ops = {
3002 .ndo_open = sh_eth_open,
3003 .ndo_stop = sh_eth_close,
3004 .ndo_start_xmit = sh_eth_start_xmit,
3005 .ndo_get_stats = sh_eth_get_stats,
3006 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3007 .ndo_tx_timeout = sh_eth_tx_timeout,
3008 .ndo_do_ioctl = sh_eth_do_ioctl,
3009 .ndo_validate_addr = eth_validate_addr,
3010 .ndo_set_mac_address = eth_mac_addr,
3011 .ndo_change_mtu = eth_change_mtu,
3012 };
3013
3014 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3015 .ndo_open = sh_eth_open,
3016 .ndo_stop = sh_eth_close,
3017 .ndo_start_xmit = sh_eth_start_xmit,
3018 .ndo_get_stats = sh_eth_get_stats,
3019 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3020 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3021 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3022 .ndo_tx_timeout = sh_eth_tx_timeout,
3023 .ndo_do_ioctl = sh_eth_do_ioctl,
3024 .ndo_validate_addr = eth_validate_addr,
3025 .ndo_set_mac_address = eth_mac_addr,
3026 .ndo_change_mtu = eth_change_mtu,
3027 };
3028
3029 #ifdef CONFIG_OF
3030 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3031 {
3032 struct device_node *np = dev->of_node;
3033 struct sh_eth_plat_data *pdata;
3034 const char *mac_addr;
3035
3036 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3037 if (!pdata)
3038 return NULL;
3039
3040 pdata->phy_interface = of_get_phy_mode(np);
3041
3042 mac_addr = of_get_mac_address(np);
3043 if (mac_addr)
3044 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3045
3046 pdata->no_ether_link =
3047 of_property_read_bool(np, "renesas,no-ether-link");
3048 pdata->ether_link_active_low =
3049 of_property_read_bool(np, "renesas,ether-link-active-low");
3050
3051 return pdata;
3052 }
3053
3054 static const struct of_device_id sh_eth_match_table[] = {
3055 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3056 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3057 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3058 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3059 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3060 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3061 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3062 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3063 { }
3064 };
3065 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3066 #else
3067 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3068 {
3069 return NULL;
3070 }
3071 #endif
3072
3073 static int sh_eth_drv_probe(struct platform_device *pdev)
3074 {
3075 int ret, devno = 0;
3076 struct resource *res;
3077 struct net_device *ndev = NULL;
3078 struct sh_eth_private *mdp = NULL;
3079 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3080 const struct platform_device_id *id = platform_get_device_id(pdev);
3081
3082 /* get base addr */
3083 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3084
3085 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3086 if (!ndev)
3087 return -ENOMEM;
3088
3089 pm_runtime_enable(&pdev->dev);
3090 pm_runtime_get_sync(&pdev->dev);
3091
3092 devno = pdev->id;
3093 if (devno < 0)
3094 devno = 0;
3095
3096 ndev->dma = -1;
3097 ret = platform_get_irq(pdev, 0);
3098 if (ret < 0)
3099 goto out_release;
3100 ndev->irq = ret;
3101
3102 SET_NETDEV_DEV(ndev, &pdev->dev);
3103
3104 mdp = netdev_priv(ndev);
3105 mdp->num_tx_ring = TX_RING_SIZE;
3106 mdp->num_rx_ring = RX_RING_SIZE;
3107 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3108 if (IS_ERR(mdp->addr)) {
3109 ret = PTR_ERR(mdp->addr);
3110 goto out_release;
3111 }
3112
3113 ndev->base_addr = res->start;
3114
3115 spin_lock_init(&mdp->lock);
3116 mdp->pdev = pdev;
3117
3118 if (pdev->dev.of_node)
3119 pd = sh_eth_parse_dt(&pdev->dev);
3120 if (!pd) {
3121 dev_err(&pdev->dev, "no platform data\n");
3122 ret = -EINVAL;
3123 goto out_release;
3124 }
3125
3126 /* get PHY ID */
3127 mdp->phy_id = pd->phy;
3128 mdp->phy_interface = pd->phy_interface;
3129 /* EDMAC endian */
3130 mdp->edmac_endian = pd->edmac_endian;
3131 mdp->no_ether_link = pd->no_ether_link;
3132 mdp->ether_link_active_low = pd->ether_link_active_low;
3133
3134 /* set cpu data */
3135 if (id) {
3136 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3137 } else {
3138 const struct of_device_id *match;
3139
3140 match = of_match_device(of_match_ptr(sh_eth_match_table),
3141 &pdev->dev);
3142 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3143 }
3144 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3145 if (!mdp->reg_offset) {
3146 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3147 mdp->cd->register_type);
3148 ret = -EINVAL;
3149 goto out_release;
3150 }
3151 sh_eth_set_default_cpu_data(mdp->cd);
3152
3153 /* set function */
3154 if (mdp->cd->tsu)
3155 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3156 else
3157 ndev->netdev_ops = &sh_eth_netdev_ops;
3158 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3159 ndev->watchdog_timeo = TX_TIMEOUT;
3160
3161 /* debug message level */
3162 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3163
3164 /* read and set MAC address */
3165 read_mac_address(ndev, pd->mac_addr);
3166 if (!is_valid_ether_addr(ndev->dev_addr)) {
3167 dev_warn(&pdev->dev,
3168 "no valid MAC address supplied, using a random one.\n");
3169 eth_hw_addr_random(ndev);
3170 }
3171
3172 /* ioremap the TSU registers */
3173 if (mdp->cd->tsu) {
3174 struct resource *rtsu;
3175 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3176 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3177 if (IS_ERR(mdp->tsu_addr)) {
3178 ret = PTR_ERR(mdp->tsu_addr);
3179 goto out_release;
3180 }
3181 mdp->port = devno % 2;
3182 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3183 }
3184
3185 /* initialize first or needed device */
3186 if (!devno || pd->needs_init) {
3187 if (mdp->cd->chip_reset)
3188 mdp->cd->chip_reset(ndev);
3189
3190 if (mdp->cd->tsu) {
3191 /* TSU init (Init only)*/
3192 sh_eth_tsu_init(mdp);
3193 }
3194 }
3195
3196 if (mdp->cd->rmiimode)
3197 sh_eth_write(ndev, 0x1, RMIIMODE);
3198
3199 /* MDIO bus init */
3200 ret = sh_mdio_init(mdp, pd);
3201 if (ret) {
3202 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3203 goto out_release;
3204 }
3205
3206 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3207
3208 /* network device register */
3209 ret = register_netdev(ndev);
3210 if (ret)
3211 goto out_napi_del;
3212
3213 /* print device information */
3214 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3215 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3216
3217 pm_runtime_put(&pdev->dev);
3218 platform_set_drvdata(pdev, ndev);
3219
3220 return ret;
3221
3222 out_napi_del:
3223 netif_napi_del(&mdp->napi);
3224 sh_mdio_release(mdp);
3225
3226 out_release:
3227 /* net_dev free */
3228 if (ndev)
3229 free_netdev(ndev);
3230
3231 pm_runtime_put(&pdev->dev);
3232 pm_runtime_disable(&pdev->dev);
3233 return ret;
3234 }
3235
3236 static int sh_eth_drv_remove(struct platform_device *pdev)
3237 {
3238 struct net_device *ndev = platform_get_drvdata(pdev);
3239 struct sh_eth_private *mdp = netdev_priv(ndev);
3240
3241 unregister_netdev(ndev);
3242 netif_napi_del(&mdp->napi);
3243 sh_mdio_release(mdp);
3244 pm_runtime_disable(&pdev->dev);
3245 free_netdev(ndev);
3246
3247 return 0;
3248 }
3249
3250 #ifdef CONFIG_PM
3251 #ifdef CONFIG_PM_SLEEP
3252 static int sh_eth_suspend(struct device *dev)
3253 {
3254 struct net_device *ndev = dev_get_drvdata(dev);
3255 int ret = 0;
3256
3257 if (netif_running(ndev)) {
3258 netif_device_detach(ndev);
3259 ret = sh_eth_close(ndev);
3260 }
3261
3262 return ret;
3263 }
3264
3265 static int sh_eth_resume(struct device *dev)
3266 {
3267 struct net_device *ndev = dev_get_drvdata(dev);
3268 int ret = 0;
3269
3270 if (netif_running(ndev)) {
3271 ret = sh_eth_open(ndev);
3272 if (ret < 0)
3273 return ret;
3274 netif_device_attach(ndev);
3275 }
3276
3277 return ret;
3278 }
3279 #endif
3280
3281 static int sh_eth_runtime_nop(struct device *dev)
3282 {
3283 /* Runtime PM callback shared between ->runtime_suspend()
3284 * and ->runtime_resume(). Simply returns success.
3285 *
3286 * This driver re-initializes all registers after
3287 * pm_runtime_get_sync() anyway so there is no need
3288 * to save and restore registers here.
3289 */
3290 return 0;
3291 }
3292
3293 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3294 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3295 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3296 };
3297 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3298 #else
3299 #define SH_ETH_PM_OPS NULL
3300 #endif
3301
3302 static struct platform_device_id sh_eth_id_table[] = {
3303 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3304 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3305 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3306 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3307 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3308 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3309 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3310 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3311 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3312 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3313 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3314 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3315 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3316 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3317 { }
3318 };
3319 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3320
3321 static struct platform_driver sh_eth_driver = {
3322 .probe = sh_eth_drv_probe,
3323 .remove = sh_eth_drv_remove,
3324 .id_table = sh_eth_id_table,
3325 .driver = {
3326 .name = CARDNAME,
3327 .pm = SH_ETH_PM_OPS,
3328 .of_match_table = of_match_ptr(sh_eth_match_table),
3329 },
3330 };
3331
3332 module_platform_driver(sh_eth_driver);
3333
3334 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3335 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3336 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support