2 * Driver for Motorola/Freescale IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
39 #include <linux/of_device.h>
41 #include <linux/dma-mapping.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
47 /* Register definitions */
48 #define URXD0 0x0 /* Receiver Register */
49 #define URTX0 0x40 /* Transmitter Register */
50 #define UCR1 0x80 /* Control Register 1 */
51 #define UCR2 0x84 /* Control Register 2 */
52 #define UCR3 0x88 /* Control Register 3 */
53 #define UCR4 0x8c /* Control Register 4 */
54 #define UFCR 0x90 /* FIFO Control Register */
55 #define USR1 0x94 /* Status Register 1 */
56 #define USR2 0x98 /* Status Register 2 */
57 #define UESC 0x9c /* Escape Character Register */
58 #define UTIM 0xa0 /* Escape Timer Register */
59 #define UBIR 0xa4 /* BRM Incremental Register */
60 #define UBMR 0xa8 /* BRM Modulator Register */
61 #define UBRC 0xac /* Baud Rate Count Register */
62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
66 /* UART Control Register Bit Fields.*/
67 #define URXD_DUMMY_READ (1<<16)
68 #define URXD_CHARRDY (1<<15)
69 #define URXD_ERR (1<<14)
70 #define URXD_OVRRUN (1<<13)
71 #define URXD_FRMERR (1<<12)
72 #define URXD_BRK (1<<11)
73 #define URXD_PRERR (1<<10)
74 #define URXD_RX_DATA (0xFF<<0)
75 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
76 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
77 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
78 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
80 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
81 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
82 #define UCR1_IREN (1<<7) /* Infrared interface enable */
83 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
84 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
85 #define UCR1_SNDBRK (1<<4) /* Send break */
86 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
88 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
89 #define UCR1_DOZE (1<<1) /* Doze */
90 #define UCR1_UARTEN (1<<0) /* UART enabled */
91 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
92 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
93 #define UCR2_CTSC (1<<13) /* CTS pin control */
94 #define UCR2_CTS (1<<12) /* Clear to send */
95 #define UCR2_ESCEN (1<<11) /* Escape enable */
96 #define UCR2_PREN (1<<8) /* Parity enable */
97 #define UCR2_PROE (1<<7) /* Parity odd/even */
98 #define UCR2_STPB (1<<6) /* Stop */
99 #define UCR2_WS (1<<5) /* Word size */
100 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
101 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
102 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
103 #define UCR2_RXEN (1<<1) /* Receiver enabled */
104 #define UCR2_SRST (1<<0) /* SW reset */
105 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
106 #define UCR3_PARERREN (1<<12) /* Parity enable */
107 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
108 #define UCR3_DSR (1<<10) /* Data set ready */
109 #define UCR3_DCD (1<<9) /* Data carrier detect */
110 #define UCR3_RI (1<<8) /* Ring indicator */
111 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
112 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
113 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
114 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
115 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
116 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
117 #define UCR3_BPEN (1<<0) /* Preset registers enable */
118 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
119 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
120 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
121 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
122 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
123 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
124 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
125 #define UCR4_IRSC (1<<5) /* IR special case */
126 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
127 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
128 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
129 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
130 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
131 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
132 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
133 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150 #define USR2_IDLE (1<<12) /* Idle condition */
151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152 #define USR2_WAKE (1<<7) /* Wake */
153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154 #define USR2_TXDC (1<<3) /* Transmitter complete */
155 #define USR2_BRCD (1<<2) /* Break condition */
156 #define USR2_ORE (1<<1) /* Overrun error */
157 #define USR2_RDR (1<<0) /* Recv data ready */
158 #define UTS_FRCPERR (1<<13) /* Force parity error */
159 #define UTS_LOOP (1<<12) /* Loop tx and rx */
160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162 #define UTS_TXFULL (1<<4) /* TxFIFO full */
163 #define UTS_RXFULL (1<<3) /* RxFIFO full */
164 #define UTS_SOFTRST (1<<0) /* Software reset */
166 /* We've been assigned a range on the "Low-density serial ports" major */
167 #define SERIAL_IMX_MAJOR 207
168 #define MINOR_START 16
169 #define DEV_NAME "ttymxc"
172 * This determines how often we check the modem status signals
173 * for any change. They generally aren't connected to an IRQ
174 * so we have to poll them. We also check immediately before
175 * filling the TX fifo incase CTS has been dropped.
177 #define MCTRL_TIMEOUT (250*HZ/1000)
179 #define DRIVER_NAME "IMX-uart"
183 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
190 /* device type dependent stuff */
191 struct imx_uart_data
{
193 enum imx_uart_type devtype
;
197 struct uart_port port
;
198 struct timer_list timer
;
199 unsigned int old_status
;
200 unsigned int have_rtscts
:1;
201 unsigned int dte_mode
:1;
202 unsigned int irda_inv_rx
:1;
203 unsigned int irda_inv_tx
:1;
204 unsigned short trcv_delay
; /* transceiver delay */
207 const struct imx_uart_data
*devdata
;
210 unsigned int dma_is_inited
:1;
211 unsigned int dma_is_enabled
:1;
212 unsigned int dma_is_rxing
:1;
213 unsigned int dma_is_txing
:1;
214 struct dma_chan
*dma_chan_rx
, *dma_chan_tx
;
215 struct scatterlist rx_sgl
, tx_sgl
[2];
217 unsigned int tx_bytes
;
218 unsigned int dma_tx_nents
;
219 wait_queue_head_t dma_wait
;
220 unsigned int saved_reg
[10];
224 struct imx_port_ucrs
{
230 static struct imx_uart_data imx_uart_devdata
[] = {
233 .devtype
= IMX1_UART
,
236 .uts_reg
= IMX21_UTS
,
237 .devtype
= IMX21_UART
,
240 .uts_reg
= IMX21_UTS
,
241 .devtype
= IMX6Q_UART
,
245 static const struct platform_device_id imx_uart_devtype
[] = {
248 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX1_UART
],
250 .name
= "imx21-uart",
251 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX21_UART
],
253 .name
= "imx6q-uart",
254 .driver_data
= (kernel_ulong_t
) &imx_uart_devdata
[IMX6Q_UART
],
259 MODULE_DEVICE_TABLE(platform
, imx_uart_devtype
);
261 static const struct of_device_id imx_uart_dt_ids
[] = {
262 { .compatible
= "fsl,imx6q-uart", .data
= &imx_uart_devdata
[IMX6Q_UART
], },
263 { .compatible
= "fsl,imx1-uart", .data
= &imx_uart_devdata
[IMX1_UART
], },
264 { .compatible
= "fsl,imx21-uart", .data
= &imx_uart_devdata
[IMX21_UART
], },
267 MODULE_DEVICE_TABLE(of
, imx_uart_dt_ids
);
269 static inline unsigned uts_reg(struct imx_port
*sport
)
271 return sport
->devdata
->uts_reg
;
274 static inline int is_imx1_uart(struct imx_port
*sport
)
276 return sport
->devdata
->devtype
== IMX1_UART
;
279 static inline int is_imx21_uart(struct imx_port
*sport
)
281 return sport
->devdata
->devtype
== IMX21_UART
;
284 static inline int is_imx6q_uart(struct imx_port
*sport
)
286 return sport
->devdata
->devtype
== IMX6Q_UART
;
289 * Save and restore functions for UCR1, UCR2 and UCR3 registers
291 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
292 static void imx_port_ucrs_save(struct uart_port
*port
,
293 struct imx_port_ucrs
*ucr
)
295 /* save control registers */
296 ucr
->ucr1
= readl(port
->membase
+ UCR1
);
297 ucr
->ucr2
= readl(port
->membase
+ UCR2
);
298 ucr
->ucr3
= readl(port
->membase
+ UCR3
);
301 static void imx_port_ucrs_restore(struct uart_port
*port
,
302 struct imx_port_ucrs
*ucr
)
304 /* restore control registers */
305 writel(ucr
->ucr1
, port
->membase
+ UCR1
);
306 writel(ucr
->ucr2
, port
->membase
+ UCR2
);
307 writel(ucr
->ucr3
, port
->membase
+ UCR3
);
312 * Handle any change of modem status signal since we were last called.
314 static void imx_mctrl_check(struct imx_port
*sport
)
316 unsigned int status
, changed
;
318 status
= sport
->port
.ops
->get_mctrl(&sport
->port
);
319 changed
= status
^ sport
->old_status
;
324 sport
->old_status
= status
;
326 if (changed
& TIOCM_RI
)
327 sport
->port
.icount
.rng
++;
328 if (changed
& TIOCM_DSR
)
329 sport
->port
.icount
.dsr
++;
330 if (changed
& TIOCM_CAR
)
331 uart_handle_dcd_change(&sport
->port
, status
& TIOCM_CAR
);
332 if (changed
& TIOCM_CTS
)
333 uart_handle_cts_change(&sport
->port
, status
& TIOCM_CTS
);
335 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
339 * This is our per-port timeout handler, for checking the
340 * modem status signals.
342 static void imx_timeout(unsigned long data
)
344 struct imx_port
*sport
= (struct imx_port
*)data
;
347 if (sport
->port
.state
) {
348 spin_lock_irqsave(&sport
->port
.lock
, flags
);
349 imx_mctrl_check(sport
);
350 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
352 mod_timer(&sport
->timer
, jiffies
+ MCTRL_TIMEOUT
);
357 * interrupts disabled on entry
359 static void imx_stop_tx(struct uart_port
*port
)
361 struct imx_port
*sport
= (struct imx_port
*)port
;
365 * We are maybe in the SMP context, so if the DMA TX thread is running
366 * on other cpu, we have to wait for it to finish.
368 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
371 temp
= readl(port
->membase
+ UCR1
);
372 writel(temp
& ~UCR1_TXMPTYEN
, port
->membase
+ UCR1
);
374 /* in rs485 mode disable transmitter if shifter is empty */
375 if (port
->rs485
.flags
& SER_RS485_ENABLED
&&
376 readl(port
->membase
+ USR2
) & USR2_TXDC
) {
377 temp
= readl(port
->membase
+ UCR2
);
378 if (port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
382 writel(temp
, port
->membase
+ UCR2
);
384 temp
= readl(port
->membase
+ UCR4
);
386 writel(temp
, port
->membase
+ UCR4
);
391 * interrupts disabled on entry
393 static void imx_stop_rx(struct uart_port
*port
)
395 struct imx_port
*sport
= (struct imx_port
*)port
;
398 if (sport
->dma_is_enabled
&& sport
->dma_is_rxing
) {
399 if (sport
->port
.suspended
) {
400 dmaengine_terminate_all(sport
->dma_chan_rx
);
401 sport
->dma_is_rxing
= 0;
407 temp
= readl(sport
->port
.membase
+ UCR2
);
408 writel(temp
& ~UCR2_RXEN
, sport
->port
.membase
+ UCR2
);
410 /* disable the `Receiver Ready Interrrupt` */
411 temp
= readl(sport
->port
.membase
+ UCR1
);
412 writel(temp
& ~UCR1_RRDYEN
, sport
->port
.membase
+ UCR1
);
416 * Set the modem control timer to fire immediately.
418 static void imx_enable_ms(struct uart_port
*port
)
420 struct imx_port
*sport
= (struct imx_port
*)port
;
422 mod_timer(&sport
->timer
, jiffies
);
425 static void imx_dma_tx(struct imx_port
*sport
);
426 static inline void imx_transmit_buffer(struct imx_port
*sport
)
428 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
431 if (sport
->port
.x_char
) {
433 writel(sport
->port
.x_char
, sport
->port
.membase
+ URTX0
);
434 sport
->port
.icount
.tx
++;
435 sport
->port
.x_char
= 0;
439 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
440 imx_stop_tx(&sport
->port
);
444 if (sport
->dma_is_enabled
) {
446 * We've just sent a X-char Ensure the TX DMA is enabled
447 * and the TX IRQ is disabled.
449 temp
= readl(sport
->port
.membase
+ UCR1
);
450 temp
&= ~UCR1_TXMPTYEN
;
451 if (sport
->dma_is_txing
) {
453 writel(temp
, sport
->port
.membase
+ UCR1
);
455 writel(temp
, sport
->port
.membase
+ UCR1
);
460 while (!uart_circ_empty(xmit
) &&
461 !(readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)) {
462 /* send xmit->buf[xmit->tail]
463 * out the port here */
464 writel(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ URTX0
);
465 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
466 sport
->port
.icount
.tx
++;
469 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
470 uart_write_wakeup(&sport
->port
);
472 if (uart_circ_empty(xmit
))
473 imx_stop_tx(&sport
->port
);
476 static void dma_tx_callback(void *data
)
478 struct imx_port
*sport
= data
;
479 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
480 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
484 spin_lock_irqsave(&sport
->port
.lock
, flags
);
486 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
488 temp
= readl(sport
->port
.membase
+ UCR1
);
489 temp
&= ~UCR1_TDMAEN
;
490 writel(temp
, sport
->port
.membase
+ UCR1
);
492 /* update the stat */
493 xmit
->tail
= (xmit
->tail
+ sport
->tx_bytes
) & (UART_XMIT_SIZE
- 1);
494 sport
->port
.icount
.tx
+= sport
->tx_bytes
;
496 dev_dbg(sport
->port
.dev
, "we finish the TX DMA.\n");
498 sport
->dma_is_txing
= 0;
500 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
502 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
503 uart_write_wakeup(&sport
->port
);
505 if (waitqueue_active(&sport
->dma_wait
)) {
506 wake_up(&sport
->dma_wait
);
507 dev_dbg(sport
->port
.dev
, "exit in %s.\n", __func__
);
511 spin_lock_irqsave(&sport
->port
.lock
, flags
);
512 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&sport
->port
))
514 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
517 static void imx_dma_tx(struct imx_port
*sport
)
519 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
520 struct scatterlist
*sgl
= sport
->tx_sgl
;
521 struct dma_async_tx_descriptor
*desc
;
522 struct dma_chan
*chan
= sport
->dma_chan_tx
;
523 struct device
*dev
= sport
->port
.dev
;
527 if (sport
->dma_is_txing
)
530 sport
->tx_bytes
= uart_circ_chars_pending(xmit
);
532 if (xmit
->tail
< xmit
->head
) {
533 sport
->dma_tx_nents
= 1;
534 sg_init_one(sgl
, xmit
->buf
+ xmit
->tail
, sport
->tx_bytes
);
536 sport
->dma_tx_nents
= 2;
537 sg_init_table(sgl
, 2);
538 sg_set_buf(sgl
, xmit
->buf
+ xmit
->tail
,
539 UART_XMIT_SIZE
- xmit
->tail
);
540 sg_set_buf(sgl
+ 1, xmit
->buf
, xmit
->head
);
543 ret
= dma_map_sg(dev
, sgl
, sport
->dma_tx_nents
, DMA_TO_DEVICE
);
545 dev_err(dev
, "DMA mapping error for TX.\n");
548 desc
= dmaengine_prep_slave_sg(chan
, sgl
, sport
->dma_tx_nents
,
549 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
551 dma_unmap_sg(dev
, sgl
, sport
->dma_tx_nents
,
553 dev_err(dev
, "We cannot prepare for the TX slave dma!\n");
556 desc
->callback
= dma_tx_callback
;
557 desc
->callback_param
= sport
;
559 dev_dbg(dev
, "TX: prepare to send %lu bytes by DMA.\n",
560 uart_circ_chars_pending(xmit
));
562 temp
= readl(sport
->port
.membase
+ UCR1
);
564 writel(temp
, sport
->port
.membase
+ UCR1
);
567 sport
->dma_is_txing
= 1;
568 dmaengine_submit(desc
);
569 dma_async_issue_pending(chan
);
574 * interrupts disabled on entry
576 static void imx_start_tx(struct uart_port
*port
)
578 struct imx_port
*sport
= (struct imx_port
*)port
;
581 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
582 /* enable transmitter and shifter empty irq */
583 temp
= readl(port
->membase
+ UCR2
);
584 if (port
->rs485
.flags
& SER_RS485_RTS_ON_SEND
)
588 writel(temp
, port
->membase
+ UCR2
);
590 temp
= readl(port
->membase
+ UCR4
);
592 writel(temp
, port
->membase
+ UCR4
);
595 if (!sport
->dma_is_enabled
) {
596 temp
= readl(sport
->port
.membase
+ UCR1
);
597 writel(temp
| UCR1_TXMPTYEN
, sport
->port
.membase
+ UCR1
);
600 if (sport
->dma_is_enabled
) {
601 if (sport
->port
.x_char
) {
602 /* We have X-char to send, so enable TX IRQ and
603 * disable TX DMA to let TX interrupt to send X-char */
604 temp
= readl(sport
->port
.membase
+ UCR1
);
605 temp
&= ~UCR1_TDMAEN
;
606 temp
|= UCR1_TXMPTYEN
;
607 writel(temp
, sport
->port
.membase
+ UCR1
);
611 if (!uart_circ_empty(&port
->state
->xmit
) &&
612 !uart_tx_stopped(port
))
618 static irqreturn_t
imx_rtsint(int irq
, void *dev_id
)
620 struct imx_port
*sport
= dev_id
;
624 spin_lock_irqsave(&sport
->port
.lock
, flags
);
626 writel(USR1_RTSD
, sport
->port
.membase
+ USR1
);
627 val
= readl(sport
->port
.membase
+ USR1
) & USR1_RTSS
;
628 uart_handle_cts_change(&sport
->port
, !!val
);
629 wake_up_interruptible(&sport
->port
.state
->port
.delta_msr_wait
);
631 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
635 static irqreturn_t
imx_txint(int irq
, void *dev_id
)
637 struct imx_port
*sport
= dev_id
;
640 spin_lock_irqsave(&sport
->port
.lock
, flags
);
641 imx_transmit_buffer(sport
);
642 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
646 static irqreturn_t
imx_rxint(int irq
, void *dev_id
)
648 struct imx_port
*sport
= dev_id
;
649 unsigned int rx
, flg
, ignored
= 0;
650 struct tty_port
*port
= &sport
->port
.state
->port
;
651 unsigned long flags
, temp
;
653 spin_lock_irqsave(&sport
->port
.lock
, flags
);
655 while (readl(sport
->port
.membase
+ USR2
) & USR2_RDR
) {
657 sport
->port
.icount
.rx
++;
659 rx
= readl(sport
->port
.membase
+ URXD0
);
661 temp
= readl(sport
->port
.membase
+ USR2
);
662 if (temp
& USR2_BRCD
) {
663 writel(USR2_BRCD
, sport
->port
.membase
+ USR2
);
664 if (uart_handle_break(&sport
->port
))
668 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
671 if (unlikely(rx
& URXD_ERR
)) {
673 sport
->port
.icount
.brk
++;
674 else if (rx
& URXD_PRERR
)
675 sport
->port
.icount
.parity
++;
676 else if (rx
& URXD_FRMERR
)
677 sport
->port
.icount
.frame
++;
678 if (rx
& URXD_OVRRUN
)
679 sport
->port
.icount
.overrun
++;
681 if (rx
& sport
->port
.ignore_status_mask
) {
687 rx
&= (sport
->port
.read_status_mask
| 0xFF);
691 else if (rx
& URXD_PRERR
)
693 else if (rx
& URXD_FRMERR
)
695 if (rx
& URXD_OVRRUN
)
699 sport
->port
.sysrq
= 0;
703 if (sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)
706 if (tty_insert_flip_char(port
, rx
, flg
) == 0)
707 sport
->port
.icount
.buf_overrun
++;
711 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
712 tty_flip_buffer_push(port
);
716 static int start_rx_dma(struct imx_port
*sport
);
718 * If the RXFIFO is filled with some data, and then we
719 * arise a DMA operation to receive them.
721 static void imx_dma_rxint(struct imx_port
*sport
)
726 spin_lock_irqsave(&sport
->port
.lock
, flags
);
728 temp
= readl(sport
->port
.membase
+ USR2
);
729 if ((temp
& USR2_RDR
) && !sport
->dma_is_rxing
) {
730 sport
->dma_is_rxing
= 1;
732 /* disable the receiver ready and aging timer interrupts */
733 temp
= readl(sport
->port
.membase
+ UCR1
);
734 temp
&= ~(UCR1_RRDYEN
);
735 writel(temp
, sport
->port
.membase
+ UCR1
);
737 temp
= readl(sport
->port
.membase
+ UCR2
);
738 temp
&= ~(UCR2_ATEN
);
739 writel(temp
, sport
->port
.membase
+ UCR2
);
741 /* tell the DMA to receive the data. */
745 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
748 static irqreturn_t
imx_int(int irq
, void *dev_id
)
750 struct imx_port
*sport
= dev_id
;
754 sts
= readl(sport
->port
.membase
+ USR1
);
755 sts2
= readl(sport
->port
.membase
+ USR2
);
757 if (sts
& (USR1_RRDY
| USR1_AGTIM
)) {
758 if (sport
->dma_is_enabled
)
759 imx_dma_rxint(sport
);
761 imx_rxint(irq
, dev_id
);
764 if ((sts
& USR1_TRDY
&&
765 readl(sport
->port
.membase
+ UCR1
) & UCR1_TXMPTYEN
) ||
767 readl(sport
->port
.membase
+ UCR4
) & UCR4_TCEN
))
768 imx_txint(irq
, dev_id
);
771 imx_rtsint(irq
, dev_id
);
773 if (sts
& USR1_AWAKE
)
774 writel(USR1_AWAKE
, sport
->port
.membase
+ USR1
);
776 if (sts2
& USR2_ORE
) {
777 sport
->port
.icount
.overrun
++;
778 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
785 * Return TIOCSER_TEMT when transmitter is not busy.
787 static unsigned int imx_tx_empty(struct uart_port
*port
)
789 struct imx_port
*sport
= (struct imx_port
*)port
;
792 ret
= (readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
) ? TIOCSER_TEMT
: 0;
794 /* If the TX DMA is working, return 0. */
795 if (sport
->dma_is_enabled
&& sport
->dma_is_txing
)
802 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
804 static unsigned int imx_get_mctrl(struct uart_port
*port
)
806 struct imx_port
*sport
= (struct imx_port
*)port
;
807 unsigned int tmp
= TIOCM_DSR
| TIOCM_CAR
;
809 if (readl(sport
->port
.membase
+ USR1
) & USR1_RTSS
)
812 if (readl(sport
->port
.membase
+ UCR2
) & UCR2_CTS
)
815 if (readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_LOOP
)
821 static void imx_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
823 struct imx_port
*sport
= (struct imx_port
*)port
;
826 if (!(port
->rs485
.flags
& SER_RS485_ENABLED
)) {
827 temp
= readl(sport
->port
.membase
+ UCR2
);
828 temp
&= ~(UCR2_CTS
| UCR2_CTSC
);
829 if (mctrl
& TIOCM_RTS
)
830 temp
|= UCR2_CTS
| UCR2_CTSC
;
831 writel(temp
, sport
->port
.membase
+ UCR2
);
834 temp
= readl(sport
->port
.membase
+ uts_reg(sport
)) & ~UTS_LOOP
;
835 if (mctrl
& TIOCM_LOOP
)
837 writel(temp
, sport
->port
.membase
+ uts_reg(sport
));
841 * Interrupts always disabled.
843 static void imx_break_ctl(struct uart_port
*port
, int break_state
)
845 struct imx_port
*sport
= (struct imx_port
*)port
;
846 unsigned long flags
, temp
;
848 spin_lock_irqsave(&sport
->port
.lock
, flags
);
850 temp
= readl(sport
->port
.membase
+ UCR1
) & ~UCR1_SNDBRK
;
852 if (break_state
!= 0)
855 writel(temp
, sport
->port
.membase
+ UCR1
);
857 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
860 #define RX_BUF_SIZE (PAGE_SIZE)
861 static void imx_rx_dma_done(struct imx_port
*sport
)
866 spin_lock_irqsave(&sport
->port
.lock
, flags
);
868 /* re-enable interrupts to get notified when new symbols are incoming */
869 temp
= readl(sport
->port
.membase
+ UCR1
);
871 writel(temp
, sport
->port
.membase
+ UCR1
);
873 temp
= readl(sport
->port
.membase
+ UCR2
);
875 writel(temp
, sport
->port
.membase
+ UCR2
);
877 sport
->dma_is_rxing
= 0;
879 /* Is the shutdown waiting for us? */
880 if (waitqueue_active(&sport
->dma_wait
))
881 wake_up(&sport
->dma_wait
);
883 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
887 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
888 * [1] the RX DMA buffer is full.
889 * [2] the aging timer expires
891 * Condition [2] is triggered when a character has been sitting in the FIFO
892 * for at least 8 byte durations.
894 static void dma_rx_callback(void *data
)
896 struct imx_port
*sport
= data
;
897 struct dma_chan
*chan
= sport
->dma_chan_rx
;
898 struct scatterlist
*sgl
= &sport
->rx_sgl
;
899 struct tty_port
*port
= &sport
->port
.state
->port
;
900 struct dma_tx_state state
;
901 enum dma_status status
;
905 dma_unmap_sg(sport
->port
.dev
, sgl
, 1, DMA_FROM_DEVICE
);
907 status
= dmaengine_tx_status(chan
, (dma_cookie_t
)0, &state
);
908 count
= RX_BUF_SIZE
- state
.residue
;
910 dev_dbg(sport
->port
.dev
, "We get %d bytes.\n", count
);
913 if (!(sport
->port
.ignore_status_mask
& URXD_DUMMY_READ
)) {
914 int bytes
= tty_insert_flip_string(port
, sport
->rx_buf
,
918 sport
->port
.icount
.buf_overrun
++;
920 tty_flip_buffer_push(port
);
921 sport
->port
.icount
.rx
+= count
;
925 * Restart RX DMA directly if more data is available in order to skip
926 * the roundtrip through the IRQ handler. If there is some data already
927 * in the FIFO, DMA needs to be restarted soon anyways.
929 * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once
930 * data starts to arrive again.
932 if (readl(sport
->port
.membase
+ USR2
) & USR2_RDR
)
935 imx_rx_dma_done(sport
);
938 static int start_rx_dma(struct imx_port
*sport
)
940 struct scatterlist
*sgl
= &sport
->rx_sgl
;
941 struct dma_chan
*chan
= sport
->dma_chan_rx
;
942 struct device
*dev
= sport
->port
.dev
;
943 struct dma_async_tx_descriptor
*desc
;
946 sg_init_one(sgl
, sport
->rx_buf
, RX_BUF_SIZE
);
947 ret
= dma_map_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
949 dev_err(dev
, "DMA mapping error for RX.\n");
952 desc
= dmaengine_prep_slave_sg(chan
, sgl
, 1, DMA_DEV_TO_MEM
,
955 dma_unmap_sg(dev
, sgl
, 1, DMA_FROM_DEVICE
);
956 dev_err(dev
, "We cannot prepare for the RX slave dma!\n");
959 desc
->callback
= dma_rx_callback
;
960 desc
->callback_param
= sport
;
962 dev_dbg(dev
, "RX: prepare for the DMA.\n");
963 dmaengine_submit(desc
);
964 dma_async_issue_pending(chan
);
968 #define TXTL_DEFAULT 2 /* reset default */
969 #define RXTL_DEFAULT 1 /* reset default */
970 #define TXTL_DMA 8 /* DMA burst setting */
971 #define RXTL_DMA 9 /* DMA burst setting */
973 static void imx_setup_ufcr(struct imx_port
*sport
,
974 unsigned char txwl
, unsigned char rxwl
)
978 /* set receiver / transmitter trigger level */
979 val
= readl(sport
->port
.membase
+ UFCR
) & (UFCR_RFDIV
| UFCR_DCEDTE
);
980 val
|= txwl
<< UFCR_TXTL_SHF
| rxwl
;
981 writel(val
, sport
->port
.membase
+ UFCR
);
984 static void imx_uart_dma_exit(struct imx_port
*sport
)
986 if (sport
->dma_chan_rx
) {
987 dma_release_channel(sport
->dma_chan_rx
);
988 sport
->dma_chan_rx
= NULL
;
990 kfree(sport
->rx_buf
);
991 sport
->rx_buf
= NULL
;
994 if (sport
->dma_chan_tx
) {
995 dma_release_channel(sport
->dma_chan_tx
);
996 sport
->dma_chan_tx
= NULL
;
999 sport
->dma_is_inited
= 0;
1002 static int imx_uart_dma_init(struct imx_port
*sport
)
1004 struct dma_slave_config slave_config
= {};
1005 struct device
*dev
= sport
->port
.dev
;
1008 /* Prepare for RX : */
1009 sport
->dma_chan_rx
= dma_request_slave_channel(dev
, "rx");
1010 if (!sport
->dma_chan_rx
) {
1011 dev_dbg(dev
, "cannot get the DMA channel.\n");
1016 slave_config
.direction
= DMA_DEV_TO_MEM
;
1017 slave_config
.src_addr
= sport
->port
.mapbase
+ URXD0
;
1018 slave_config
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1019 /* one byte less than the watermark level to enable the aging timer */
1020 slave_config
.src_maxburst
= RXTL_DMA
- 1;
1021 ret
= dmaengine_slave_config(sport
->dma_chan_rx
, &slave_config
);
1023 dev_err(dev
, "error in RX dma configuration.\n");
1027 sport
->rx_buf
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
1028 if (!sport
->rx_buf
) {
1033 /* Prepare for TX : */
1034 sport
->dma_chan_tx
= dma_request_slave_channel(dev
, "tx");
1035 if (!sport
->dma_chan_tx
) {
1036 dev_err(dev
, "cannot get the TX DMA channel!\n");
1041 slave_config
.direction
= DMA_MEM_TO_DEV
;
1042 slave_config
.dst_addr
= sport
->port
.mapbase
+ URTX0
;
1043 slave_config
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1044 slave_config
.dst_maxburst
= TXTL_DMA
;
1045 ret
= dmaengine_slave_config(sport
->dma_chan_tx
, &slave_config
);
1047 dev_err(dev
, "error in TX dma configuration.");
1051 sport
->dma_is_inited
= 1;
1055 imx_uart_dma_exit(sport
);
1059 static void imx_enable_dma(struct imx_port
*sport
)
1063 init_waitqueue_head(&sport
->dma_wait
);
1066 temp
= readl(sport
->port
.membase
+ UCR1
);
1067 temp
|= UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
;
1068 writel(temp
, sport
->port
.membase
+ UCR1
);
1070 temp
= readl(sport
->port
.membase
+ UCR2
);
1072 writel(temp
, sport
->port
.membase
+ UCR2
);
1074 imx_setup_ufcr(sport
, TXTL_DMA
, RXTL_DMA
);
1076 sport
->dma_is_enabled
= 1;
1079 static void imx_disable_dma(struct imx_port
*sport
)
1084 temp
= readl(sport
->port
.membase
+ UCR1
);
1085 temp
&= ~(UCR1_RDMAEN
| UCR1_TDMAEN
| UCR1_ATDMAEN
);
1086 writel(temp
, sport
->port
.membase
+ UCR1
);
1089 temp
= readl(sport
->port
.membase
+ UCR2
);
1090 temp
&= ~(UCR2_CTSC
| UCR2_CTS
| UCR2_ATEN
);
1091 writel(temp
, sport
->port
.membase
+ UCR2
);
1093 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1095 sport
->dma_is_enabled
= 0;
1098 /* half the RX buffer size */
1101 static int imx_startup(struct uart_port
*port
)
1103 struct imx_port
*sport
= (struct imx_port
*)port
;
1105 unsigned long flags
, temp
;
1107 retval
= clk_prepare_enable(sport
->clk_per
);
1110 retval
= clk_prepare_enable(sport
->clk_ipg
);
1112 clk_disable_unprepare(sport
->clk_per
);
1116 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1118 /* disable the DREN bit (Data Ready interrupt enable) before
1121 temp
= readl(sport
->port
.membase
+ UCR4
);
1123 /* set the trigger level for CTS */
1124 temp
&= ~(UCR4_CTSTL_MASK
<< UCR4_CTSTL_SHF
);
1125 temp
|= CTSTL
<< UCR4_CTSTL_SHF
;
1127 writel(temp
& ~UCR4_DREN
, sport
->port
.membase
+ UCR4
);
1129 /* Can we enable the DMA support? */
1130 if (is_imx6q_uart(sport
) && !uart_console(port
) &&
1131 !sport
->dma_is_inited
)
1132 imx_uart_dma_init(sport
);
1134 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1135 /* Reset fifo's and state machines */
1138 temp
= readl(sport
->port
.membase
+ UCR2
);
1140 writel(temp
, sport
->port
.membase
+ UCR2
);
1142 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1146 * Finally, clear and enable interrupts
1148 writel(USR1_RTSD
, sport
->port
.membase
+ USR1
);
1149 writel(USR2_ORE
, sport
->port
.membase
+ USR2
);
1151 if (sport
->dma_is_inited
&& !sport
->dma_is_enabled
)
1152 imx_enable_dma(sport
);
1154 temp
= readl(sport
->port
.membase
+ UCR1
);
1155 temp
|= UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
;
1157 writel(temp
, sport
->port
.membase
+ UCR1
);
1159 temp
= readl(sport
->port
.membase
+ UCR4
);
1161 writel(temp
, sport
->port
.membase
+ UCR4
);
1163 temp
= readl(sport
->port
.membase
+ UCR2
);
1164 temp
|= (UCR2_RXEN
| UCR2_TXEN
);
1165 if (!sport
->have_rtscts
)
1167 writel(temp
, sport
->port
.membase
+ UCR2
);
1169 if (!is_imx1_uart(sport
)) {
1170 temp
= readl(sport
->port
.membase
+ UCR3
);
1171 temp
|= IMX21_UCR3_RXDMUXSEL
| UCR3_ADNIMP
;
1172 writel(temp
, sport
->port
.membase
+ UCR3
);
1176 * Enable modem status interrupts
1178 imx_enable_ms(&sport
->port
);
1179 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1184 static void imx_shutdown(struct uart_port
*port
)
1186 struct imx_port
*sport
= (struct imx_port
*)port
;
1188 unsigned long flags
;
1190 if (sport
->dma_is_enabled
) {
1193 /* We have to wait for the DMA to finish. */
1194 ret
= wait_event_interruptible(sport
->dma_wait
,
1195 !sport
->dma_is_rxing
&& !sport
->dma_is_txing
);
1197 sport
->dma_is_rxing
= 0;
1198 sport
->dma_is_txing
= 0;
1199 dmaengine_terminate_all(sport
->dma_chan_tx
);
1200 dmaengine_terminate_all(sport
->dma_chan_rx
);
1202 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1205 imx_disable_dma(sport
);
1206 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1207 imx_uart_dma_exit(sport
);
1210 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1211 temp
= readl(sport
->port
.membase
+ UCR2
);
1212 temp
&= ~(UCR2_TXEN
);
1213 writel(temp
, sport
->port
.membase
+ UCR2
);
1214 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1219 del_timer_sync(&sport
->timer
);
1222 * Disable all interrupts, port and break condition.
1225 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1226 temp
= readl(sport
->port
.membase
+ UCR1
);
1227 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
| UCR1_UARTEN
);
1229 writel(temp
, sport
->port
.membase
+ UCR1
);
1230 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1232 clk_disable_unprepare(sport
->clk_per
);
1233 clk_disable_unprepare(sport
->clk_ipg
);
1236 static void imx_flush_buffer(struct uart_port
*port
)
1238 struct imx_port
*sport
= (struct imx_port
*)port
;
1239 struct scatterlist
*sgl
= &sport
->tx_sgl
[0];
1241 int i
= 100, ubir
, ubmr
, uts
;
1243 if (!sport
->dma_chan_tx
)
1246 sport
->tx_bytes
= 0;
1247 dmaengine_terminate_all(sport
->dma_chan_tx
);
1248 if (sport
->dma_is_txing
) {
1249 dma_unmap_sg(sport
->port
.dev
, sgl
, sport
->dma_tx_nents
,
1251 temp
= readl(sport
->port
.membase
+ UCR1
);
1252 temp
&= ~UCR1_TDMAEN
;
1253 writel(temp
, sport
->port
.membase
+ UCR1
);
1254 sport
->dma_is_txing
= false;
1258 * According to the Reference Manual description of the UART SRST bit:
1259 * "Reset the transmit and receive state machines,
1260 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1261 * and UTS[6-3]". As we don't need to restore the old values from
1262 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1264 ubir
= readl(sport
->port
.membase
+ UBIR
);
1265 ubmr
= readl(sport
->port
.membase
+ UBMR
);
1266 uts
= readl(sport
->port
.membase
+ IMX21_UTS
);
1268 temp
= readl(sport
->port
.membase
+ UCR2
);
1270 writel(temp
, sport
->port
.membase
+ UCR2
);
1272 while (!(readl(sport
->port
.membase
+ UCR2
) & UCR2_SRST
) && (--i
> 0))
1275 /* Restore the registers */
1276 writel(ubir
, sport
->port
.membase
+ UBIR
);
1277 writel(ubmr
, sport
->port
.membase
+ UBMR
);
1278 writel(uts
, sport
->port
.membase
+ IMX21_UTS
);
1282 imx_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1283 struct ktermios
*old
)
1285 struct imx_port
*sport
= (struct imx_port
*)port
;
1286 unsigned long flags
;
1287 unsigned int ucr2
, old_ucr1
, old_ucr2
, baud
, quot
;
1288 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1289 unsigned int div
, ufcr
;
1290 unsigned long num
, denom
;
1294 * We only support CS7 and CS8.
1296 while ((termios
->c_cflag
& CSIZE
) != CS7
&&
1297 (termios
->c_cflag
& CSIZE
) != CS8
) {
1298 termios
->c_cflag
&= ~CSIZE
;
1299 termios
->c_cflag
|= old_csize
;
1303 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1304 ucr2
= UCR2_WS
| UCR2_SRST
| UCR2_IRTS
;
1306 ucr2
= UCR2_SRST
| UCR2_IRTS
;
1308 if (termios
->c_cflag
& CRTSCTS
) {
1309 if (sport
->have_rtscts
) {
1312 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
1314 * RTS is mandatory for rs485 operation, so keep
1315 * it under manual control and keep transmitter
1318 if (!(port
->rs485
.flags
&
1319 SER_RS485_RTS_AFTER_SEND
))
1325 termios
->c_cflag
&= ~CRTSCTS
;
1327 } else if (port
->rs485
.flags
& SER_RS485_ENABLED
)
1328 /* disable transmitter */
1329 if (!(port
->rs485
.flags
& SER_RS485_RTS_AFTER_SEND
))
1332 if (termios
->c_cflag
& CSTOPB
)
1334 if (termios
->c_cflag
& PARENB
) {
1336 if (termios
->c_cflag
& PARODD
)
1340 del_timer_sync(&sport
->timer
);
1343 * Ask the core to calculate the divisor for us.
1345 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1346 quot
= uart_get_divisor(port
, baud
);
1348 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1350 sport
->port
.read_status_mask
= 0;
1351 if (termios
->c_iflag
& INPCK
)
1352 sport
->port
.read_status_mask
|= (URXD_FRMERR
| URXD_PRERR
);
1353 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
1354 sport
->port
.read_status_mask
|= URXD_BRK
;
1357 * Characters to ignore
1359 sport
->port
.ignore_status_mask
= 0;
1360 if (termios
->c_iflag
& IGNPAR
)
1361 sport
->port
.ignore_status_mask
|= URXD_PRERR
| URXD_FRMERR
;
1362 if (termios
->c_iflag
& IGNBRK
) {
1363 sport
->port
.ignore_status_mask
|= URXD_BRK
;
1365 * If we're ignoring parity and break indicators,
1366 * ignore overruns too (for real raw support).
1368 if (termios
->c_iflag
& IGNPAR
)
1369 sport
->port
.ignore_status_mask
|= URXD_OVRRUN
;
1372 if ((termios
->c_cflag
& CREAD
) == 0)
1373 sport
->port
.ignore_status_mask
|= URXD_DUMMY_READ
;
1376 * Update the per-port timeout.
1378 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1381 * disable interrupts and drain transmitter
1383 old_ucr1
= readl(sport
->port
.membase
+ UCR1
);
1384 writel(old_ucr1
& ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
),
1385 sport
->port
.membase
+ UCR1
);
1387 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
))
1390 /* then, disable everything */
1391 old_ucr2
= readl(sport
->port
.membase
+ UCR2
);
1392 writel(old_ucr2
& ~(UCR2_TXEN
| UCR2_RXEN
),
1393 sport
->port
.membase
+ UCR2
);
1394 old_ucr2
&= (UCR2_TXEN
| UCR2_RXEN
| UCR2_ATEN
);
1396 /* custom-baudrate handling */
1397 div
= sport
->port
.uartclk
/ (baud
* 16);
1398 if (baud
== 38400 && quot
!= div
)
1399 baud
= sport
->port
.uartclk
/ (quot
* 16);
1401 div
= sport
->port
.uartclk
/ (baud
* 16);
1407 rational_best_approximation(16 * div
* baud
, sport
->port
.uartclk
,
1408 1 << 16, 1 << 16, &num
, &denom
);
1410 tdiv64
= sport
->port
.uartclk
;
1412 do_div(tdiv64
, denom
* 16 * div
);
1413 tty_termios_encode_baud_rate(termios
,
1414 (speed_t
)tdiv64
, (speed_t
)tdiv64
);
1419 ufcr
= readl(sport
->port
.membase
+ UFCR
);
1420 ufcr
= (ufcr
& (~UFCR_RFDIV
)) | UFCR_RFDIV_REG(div
);
1421 if (sport
->dte_mode
)
1422 ufcr
|= UFCR_DCEDTE
;
1423 writel(ufcr
, sport
->port
.membase
+ UFCR
);
1425 writel(num
, sport
->port
.membase
+ UBIR
);
1426 writel(denom
, sport
->port
.membase
+ UBMR
);
1428 if (!is_imx1_uart(sport
))
1429 writel(sport
->port
.uartclk
/ div
/ 1000,
1430 sport
->port
.membase
+ IMX21_ONEMS
);
1432 writel(old_ucr1
, sport
->port
.membase
+ UCR1
);
1434 /* set the parity, stop bits and data size */
1435 writel(ucr2
| old_ucr2
, sport
->port
.membase
+ UCR2
);
1437 if (UART_ENABLE_MS(&sport
->port
, termios
->c_cflag
))
1438 imx_enable_ms(&sport
->port
);
1440 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1443 static const char *imx_type(struct uart_port
*port
)
1445 struct imx_port
*sport
= (struct imx_port
*)port
;
1447 return sport
->port
.type
== PORT_IMX
? "IMX" : NULL
;
1451 * Configure/autoconfigure the port.
1453 static void imx_config_port(struct uart_port
*port
, int flags
)
1455 struct imx_port
*sport
= (struct imx_port
*)port
;
1457 if (flags
& UART_CONFIG_TYPE
)
1458 sport
->port
.type
= PORT_IMX
;
1462 * Verify the new serial_struct (for TIOCSSERIAL).
1463 * The only change we allow are to the flags and type, and
1464 * even then only between PORT_IMX and PORT_UNKNOWN
1467 imx_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1469 struct imx_port
*sport
= (struct imx_port
*)port
;
1472 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_IMX
)
1474 if (sport
->port
.irq
!= ser
->irq
)
1476 if (ser
->io_type
!= UPIO_MEM
)
1478 if (sport
->port
.uartclk
/ 16 != ser
->baud_base
)
1480 if (sport
->port
.mapbase
!= (unsigned long)ser
->iomem_base
)
1482 if (sport
->port
.iobase
!= ser
->port
)
1489 #if defined(CONFIG_CONSOLE_POLL)
1491 static int imx_poll_init(struct uart_port
*port
)
1493 struct imx_port
*sport
= (struct imx_port
*)port
;
1494 unsigned long flags
;
1498 retval
= clk_prepare_enable(sport
->clk_ipg
);
1501 retval
= clk_prepare_enable(sport
->clk_per
);
1503 clk_disable_unprepare(sport
->clk_ipg
);
1505 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1507 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1509 temp
= readl(sport
->port
.membase
+ UCR1
);
1510 if (is_imx1_uart(sport
))
1511 temp
|= IMX1_UCR1_UARTCLKEN
;
1512 temp
|= UCR1_UARTEN
| UCR1_RRDYEN
;
1513 temp
&= ~(UCR1_TXMPTYEN
| UCR1_RTSDEN
);
1514 writel(temp
, sport
->port
.membase
+ UCR1
);
1516 temp
= readl(sport
->port
.membase
+ UCR2
);
1518 writel(temp
, sport
->port
.membase
+ UCR2
);
1520 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1525 static int imx_poll_get_char(struct uart_port
*port
)
1527 if (!(readl_relaxed(port
->membase
+ USR2
) & USR2_RDR
))
1528 return NO_POLL_CHAR
;
1530 return readl_relaxed(port
->membase
+ URXD0
) & URXD_RX_DATA
;
1533 static void imx_poll_put_char(struct uart_port
*port
, unsigned char c
)
1535 unsigned int status
;
1539 status
= readl_relaxed(port
->membase
+ USR1
);
1540 } while (~status
& USR1_TRDY
);
1543 writel_relaxed(c
, port
->membase
+ URTX0
);
1547 status
= readl_relaxed(port
->membase
+ USR2
);
1548 } while (~status
& USR2_TXDC
);
1552 static int imx_rs485_config(struct uart_port
*port
,
1553 struct serial_rs485
*rs485conf
)
1555 struct imx_port
*sport
= (struct imx_port
*)port
;
1558 rs485conf
->delay_rts_before_send
= 0;
1559 rs485conf
->delay_rts_after_send
= 0;
1560 rs485conf
->flags
|= SER_RS485_RX_DURING_TX
;
1562 /* RTS is required to control the transmitter */
1563 if (!sport
->have_rtscts
)
1564 rs485conf
->flags
&= ~SER_RS485_ENABLED
;
1566 if (rs485conf
->flags
& SER_RS485_ENABLED
) {
1569 /* disable transmitter */
1570 temp
= readl(sport
->port
.membase
+ UCR2
);
1572 if (rs485conf
->flags
& SER_RS485_RTS_AFTER_SEND
)
1576 writel(temp
, sport
->port
.membase
+ UCR2
);
1579 port
->rs485
= *rs485conf
;
1584 static struct uart_ops imx_pops
= {
1585 .tx_empty
= imx_tx_empty
,
1586 .set_mctrl
= imx_set_mctrl
,
1587 .get_mctrl
= imx_get_mctrl
,
1588 .stop_tx
= imx_stop_tx
,
1589 .start_tx
= imx_start_tx
,
1590 .stop_rx
= imx_stop_rx
,
1591 .enable_ms
= imx_enable_ms
,
1592 .break_ctl
= imx_break_ctl
,
1593 .startup
= imx_startup
,
1594 .shutdown
= imx_shutdown
,
1595 .flush_buffer
= imx_flush_buffer
,
1596 .set_termios
= imx_set_termios
,
1598 .config_port
= imx_config_port
,
1599 .verify_port
= imx_verify_port
,
1600 #if defined(CONFIG_CONSOLE_POLL)
1601 .poll_init
= imx_poll_init
,
1602 .poll_get_char
= imx_poll_get_char
,
1603 .poll_put_char
= imx_poll_put_char
,
1607 static struct imx_port
*imx_ports
[UART_NR
];
1609 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1610 static void imx_console_putchar(struct uart_port
*port
, int ch
)
1612 struct imx_port
*sport
= (struct imx_port
*)port
;
1614 while (readl(sport
->port
.membase
+ uts_reg(sport
)) & UTS_TXFULL
)
1617 writel(ch
, sport
->port
.membase
+ URTX0
);
1621 * Interrupts are disabled on entering
1624 imx_console_write(struct console
*co
, const char *s
, unsigned int count
)
1626 struct imx_port
*sport
= imx_ports
[co
->index
];
1627 struct imx_port_ucrs old_ucr
;
1629 unsigned long flags
= 0;
1633 retval
= clk_enable(sport
->clk_per
);
1636 retval
= clk_enable(sport
->clk_ipg
);
1638 clk_disable(sport
->clk_per
);
1642 if (sport
->port
.sysrq
)
1644 else if (oops_in_progress
)
1645 locked
= spin_trylock_irqsave(&sport
->port
.lock
, flags
);
1647 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1650 * First, save UCR1/2/3 and then disable interrupts
1652 imx_port_ucrs_save(&sport
->port
, &old_ucr
);
1653 ucr1
= old_ucr
.ucr1
;
1655 if (is_imx1_uart(sport
))
1656 ucr1
|= IMX1_UCR1_UARTCLKEN
;
1657 ucr1
|= UCR1_UARTEN
;
1658 ucr1
&= ~(UCR1_TXMPTYEN
| UCR1_RRDYEN
| UCR1_RTSDEN
);
1660 writel(ucr1
, sport
->port
.membase
+ UCR1
);
1662 writel(old_ucr
.ucr2
| UCR2_TXEN
, sport
->port
.membase
+ UCR2
);
1664 uart_console_write(&sport
->port
, s
, count
, imx_console_putchar
);
1667 * Finally, wait for transmitter to become empty
1668 * and restore UCR1/2/3
1670 while (!(readl(sport
->port
.membase
+ USR2
) & USR2_TXDC
));
1672 imx_port_ucrs_restore(&sport
->port
, &old_ucr
);
1675 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1677 clk_disable(sport
->clk_ipg
);
1678 clk_disable(sport
->clk_per
);
1682 * If the port was already initialised (eg, by a boot loader),
1683 * try to determine the current setup.
1686 imx_console_get_options(struct imx_port
*sport
, int *baud
,
1687 int *parity
, int *bits
)
1690 if (readl(sport
->port
.membase
+ UCR1
) & UCR1_UARTEN
) {
1691 /* ok, the port was enabled */
1692 unsigned int ucr2
, ubir
, ubmr
, uartclk
;
1693 unsigned int baud_raw
;
1694 unsigned int ucfr_rfdiv
;
1696 ucr2
= readl(sport
->port
.membase
+ UCR2
);
1699 if (ucr2
& UCR2_PREN
) {
1700 if (ucr2
& UCR2_PROE
)
1711 ubir
= readl(sport
->port
.membase
+ UBIR
) & 0xffff;
1712 ubmr
= readl(sport
->port
.membase
+ UBMR
) & 0xffff;
1714 ucfr_rfdiv
= (readl(sport
->port
.membase
+ UFCR
) & UFCR_RFDIV
) >> 7;
1715 if (ucfr_rfdiv
== 6)
1718 ucfr_rfdiv
= 6 - ucfr_rfdiv
;
1720 uartclk
= clk_get_rate(sport
->clk_per
);
1721 uartclk
/= ucfr_rfdiv
;
1724 * The next code provides exact computation of
1725 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1726 * without need of float support or long long division,
1727 * which would be required to prevent 32bit arithmetic overflow
1729 unsigned int mul
= ubir
+ 1;
1730 unsigned int div
= 16 * (ubmr
+ 1);
1731 unsigned int rem
= uartclk
% div
;
1733 baud_raw
= (uartclk
/ div
) * mul
;
1734 baud_raw
+= (rem
* mul
+ div
/ 2) / div
;
1735 *baud
= (baud_raw
+ 50) / 100 * 100;
1738 if (*baud
!= baud_raw
)
1739 pr_info("Console IMX rounded baud rate from %d to %d\n",
1745 imx_console_setup(struct console
*co
, char *options
)
1747 struct imx_port
*sport
;
1755 * Check whether an invalid uart number has been specified, and
1756 * if so, search for the first available port that does have
1759 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(imx_ports
))
1761 sport
= imx_ports
[co
->index
];
1765 /* For setting the registers, we only need to enable the ipg clock. */
1766 retval
= clk_prepare_enable(sport
->clk_ipg
);
1771 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1773 imx_console_get_options(sport
, &baud
, &parity
, &bits
);
1775 imx_setup_ufcr(sport
, TXTL_DEFAULT
, RXTL_DEFAULT
);
1777 retval
= uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
1779 clk_disable(sport
->clk_ipg
);
1781 clk_unprepare(sport
->clk_ipg
);
1785 retval
= clk_prepare(sport
->clk_per
);
1787 clk_disable_unprepare(sport
->clk_ipg
);
1793 static struct uart_driver imx_reg
;
1794 static struct console imx_console
= {
1796 .write
= imx_console_write
,
1797 .device
= uart_console_device
,
1798 .setup
= imx_console_setup
,
1799 .flags
= CON_PRINTBUFFER
,
1804 #define IMX_CONSOLE &imx_console
1807 static void imx_console_early_putchar(struct uart_port
*port
, int ch
)
1809 while (readl_relaxed(port
->membase
+ IMX21_UTS
) & UTS_TXFULL
)
1812 writel_relaxed(ch
, port
->membase
+ URTX0
);
1815 static void imx_console_early_write(struct console
*con
, const char *s
,
1818 struct earlycon_device
*dev
= con
->data
;
1820 uart_console_write(&dev
->port
, s
, count
, imx_console_early_putchar
);
1824 imx_console_early_setup(struct earlycon_device
*dev
, const char *opt
)
1826 if (!dev
->port
.membase
)
1829 dev
->con
->write
= imx_console_early_write
;
1833 OF_EARLYCON_DECLARE(ec_imx6q
, "fsl,imx6q-uart", imx_console_early_setup
);
1834 OF_EARLYCON_DECLARE(ec_imx21
, "fsl,imx21-uart", imx_console_early_setup
);
1838 #define IMX_CONSOLE NULL
1841 static struct uart_driver imx_reg
= {
1842 .owner
= THIS_MODULE
,
1843 .driver_name
= DRIVER_NAME
,
1844 .dev_name
= DEV_NAME
,
1845 .major
= SERIAL_IMX_MAJOR
,
1846 .minor
= MINOR_START
,
1847 .nr
= ARRAY_SIZE(imx_ports
),
1848 .cons
= IMX_CONSOLE
,
1853 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1854 * could successfully get all information from dt or a negative errno.
1856 static int serial_imx_probe_dt(struct imx_port
*sport
,
1857 struct platform_device
*pdev
)
1859 struct device_node
*np
= pdev
->dev
.of_node
;
1860 const struct of_device_id
*of_id
=
1861 of_match_device(imx_uart_dt_ids
, &pdev
->dev
);
1865 /* no device tree device */
1868 ret
= of_alias_get_id(np
, "serial");
1870 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
1873 sport
->port
.line
= ret
;
1875 if (of_get_property(np
, "fsl,uart-has-rtscts", NULL
))
1876 sport
->have_rtscts
= 1;
1878 if (of_get_property(np
, "fsl,dte-mode", NULL
))
1879 sport
->dte_mode
= 1;
1881 sport
->devdata
= of_id
->data
;
1886 static inline int serial_imx_probe_dt(struct imx_port
*sport
,
1887 struct platform_device
*pdev
)
1893 static void serial_imx_probe_pdata(struct imx_port
*sport
,
1894 struct platform_device
*pdev
)
1896 struct imxuart_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
1898 sport
->port
.line
= pdev
->id
;
1899 sport
->devdata
= (struct imx_uart_data
*) pdev
->id_entry
->driver_data
;
1904 if (pdata
->flags
& IMXUART_HAVE_RTSCTS
)
1905 sport
->have_rtscts
= 1;
1908 static int serial_imx_probe(struct platform_device
*pdev
)
1910 struct imx_port
*sport
;
1913 struct resource
*res
;
1914 int txirq
, rxirq
, rtsirq
;
1916 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
1920 ret
= serial_imx_probe_dt(sport
, pdev
);
1922 serial_imx_probe_pdata(sport
, pdev
);
1926 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1927 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1929 return PTR_ERR(base
);
1931 rxirq
= platform_get_irq(pdev
, 0);
1932 txirq
= platform_get_irq(pdev
, 1);
1933 rtsirq
= platform_get_irq(pdev
, 2);
1935 sport
->port
.dev
= &pdev
->dev
;
1936 sport
->port
.mapbase
= res
->start
;
1937 sport
->port
.membase
= base
;
1938 sport
->port
.type
= PORT_IMX
,
1939 sport
->port
.iotype
= UPIO_MEM
;
1940 sport
->port
.irq
= rxirq
;
1941 sport
->port
.fifosize
= 32;
1942 sport
->port
.ops
= &imx_pops
;
1943 sport
->port
.rs485_config
= imx_rs485_config
;
1944 sport
->port
.rs485
.flags
=
1945 SER_RS485_RTS_ON_SEND
| SER_RS485_RX_DURING_TX
;
1946 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
1947 init_timer(&sport
->timer
);
1948 sport
->timer
.function
= imx_timeout
;
1949 sport
->timer
.data
= (unsigned long)sport
;
1951 sport
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
1952 if (IS_ERR(sport
->clk_ipg
)) {
1953 ret
= PTR_ERR(sport
->clk_ipg
);
1954 dev_err(&pdev
->dev
, "failed to get ipg clk: %d\n", ret
);
1958 sport
->clk_per
= devm_clk_get(&pdev
->dev
, "per");
1959 if (IS_ERR(sport
->clk_per
)) {
1960 ret
= PTR_ERR(sport
->clk_per
);
1961 dev_err(&pdev
->dev
, "failed to get per clk: %d\n", ret
);
1965 sport
->port
.uartclk
= clk_get_rate(sport
->clk_per
);
1967 /* For register access, we only need to enable the ipg clock. */
1968 ret
= clk_prepare_enable(sport
->clk_ipg
);
1972 /* Disable interrupts before requesting them */
1973 reg
= readl_relaxed(sport
->port
.membase
+ UCR1
);
1974 reg
&= ~(UCR1_ADEN
| UCR1_TRDYEN
| UCR1_IDEN
| UCR1_RRDYEN
|
1975 UCR1_TXMPTYEN
| UCR1_RTSDEN
);
1976 writel_relaxed(reg
, sport
->port
.membase
+ UCR1
);
1978 clk_disable_unprepare(sport
->clk_ipg
);
1981 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1982 * chips only have one interrupt.
1985 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_rxint
, 0,
1986 dev_name(&pdev
->dev
), sport
);
1990 ret
= devm_request_irq(&pdev
->dev
, txirq
, imx_txint
, 0,
1991 dev_name(&pdev
->dev
), sport
);
1995 ret
= devm_request_irq(&pdev
->dev
, rxirq
, imx_int
, 0,
1996 dev_name(&pdev
->dev
), sport
);
2001 imx_ports
[sport
->port
.line
] = sport
;
2003 platform_set_drvdata(pdev
, sport
);
2005 return uart_add_one_port(&imx_reg
, &sport
->port
);
2008 static int serial_imx_remove(struct platform_device
*pdev
)
2010 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2012 return uart_remove_one_port(&imx_reg
, &sport
->port
);
2015 static void serial_imx_restore_context(struct imx_port
*sport
)
2017 if (!sport
->context_saved
)
2020 writel(sport
->saved_reg
[4], sport
->port
.membase
+ UFCR
);
2021 writel(sport
->saved_reg
[5], sport
->port
.membase
+ UESC
);
2022 writel(sport
->saved_reg
[6], sport
->port
.membase
+ UTIM
);
2023 writel(sport
->saved_reg
[7], sport
->port
.membase
+ UBIR
);
2024 writel(sport
->saved_reg
[8], sport
->port
.membase
+ UBMR
);
2025 writel(sport
->saved_reg
[9], sport
->port
.membase
+ IMX21_UTS
);
2026 writel(sport
->saved_reg
[0], sport
->port
.membase
+ UCR1
);
2027 writel(sport
->saved_reg
[1] | UCR2_SRST
, sport
->port
.membase
+ UCR2
);
2028 writel(sport
->saved_reg
[2], sport
->port
.membase
+ UCR3
);
2029 writel(sport
->saved_reg
[3], sport
->port
.membase
+ UCR4
);
2030 sport
->context_saved
= false;
2033 static void serial_imx_save_context(struct imx_port
*sport
)
2035 /* Save necessary regs */
2036 sport
->saved_reg
[0] = readl(sport
->port
.membase
+ UCR1
);
2037 sport
->saved_reg
[1] = readl(sport
->port
.membase
+ UCR2
);
2038 sport
->saved_reg
[2] = readl(sport
->port
.membase
+ UCR3
);
2039 sport
->saved_reg
[3] = readl(sport
->port
.membase
+ UCR4
);
2040 sport
->saved_reg
[4] = readl(sport
->port
.membase
+ UFCR
);
2041 sport
->saved_reg
[5] = readl(sport
->port
.membase
+ UESC
);
2042 sport
->saved_reg
[6] = readl(sport
->port
.membase
+ UTIM
);
2043 sport
->saved_reg
[7] = readl(sport
->port
.membase
+ UBIR
);
2044 sport
->saved_reg
[8] = readl(sport
->port
.membase
+ UBMR
);
2045 sport
->saved_reg
[9] = readl(sport
->port
.membase
+ IMX21_UTS
);
2046 sport
->context_saved
= true;
2049 static void serial_imx_enable_wakeup(struct imx_port
*sport
, bool on
)
2053 val
= readl(sport
->port
.membase
+ UCR3
);
2057 val
&= ~UCR3_AWAKEN
;
2058 writel(val
, sport
->port
.membase
+ UCR3
);
2060 val
= readl(sport
->port
.membase
+ UCR1
);
2064 val
&= ~UCR1_RTSDEN
;
2065 writel(val
, sport
->port
.membase
+ UCR1
);
2068 static int imx_serial_port_suspend_noirq(struct device
*dev
)
2070 struct platform_device
*pdev
= to_platform_device(dev
);
2071 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2074 ret
= clk_enable(sport
->clk_ipg
);
2078 serial_imx_save_context(sport
);
2080 clk_disable(sport
->clk_ipg
);
2085 static int imx_serial_port_resume_noirq(struct device
*dev
)
2087 struct platform_device
*pdev
= to_platform_device(dev
);
2088 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2091 ret
= clk_enable(sport
->clk_ipg
);
2095 serial_imx_restore_context(sport
);
2097 clk_disable(sport
->clk_ipg
);
2102 static int imx_serial_port_suspend(struct device
*dev
)
2104 struct platform_device
*pdev
= to_platform_device(dev
);
2105 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2107 /* enable wakeup from i.MX UART */
2108 serial_imx_enable_wakeup(sport
, true);
2110 uart_suspend_port(&imx_reg
, &sport
->port
);
2115 static int imx_serial_port_resume(struct device
*dev
)
2117 struct platform_device
*pdev
= to_platform_device(dev
);
2118 struct imx_port
*sport
= platform_get_drvdata(pdev
);
2120 /* disable wakeup from i.MX UART */
2121 serial_imx_enable_wakeup(sport
, false);
2123 uart_resume_port(&imx_reg
, &sport
->port
);
2128 static const struct dev_pm_ops imx_serial_port_pm_ops
= {
2129 .suspend_noirq
= imx_serial_port_suspend_noirq
,
2130 .resume_noirq
= imx_serial_port_resume_noirq
,
2131 .suspend
= imx_serial_port_suspend
,
2132 .resume
= imx_serial_port_resume
,
2135 static struct platform_driver serial_imx_driver
= {
2136 .probe
= serial_imx_probe
,
2137 .remove
= serial_imx_remove
,
2139 .id_table
= imx_uart_devtype
,
2142 .of_match_table
= imx_uart_dt_ids
,
2143 .pm
= &imx_serial_port_pm_ops
,
2147 static int __init
imx_serial_init(void)
2149 int ret
= uart_register_driver(&imx_reg
);
2154 ret
= platform_driver_register(&serial_imx_driver
);
2156 uart_unregister_driver(&imx_reg
);
2161 static void __exit
imx_serial_exit(void)
2163 platform_driver_unregister(&serial_imx_driver
);
2164 uart_unregister_driver(&imx_reg
);
2167 module_init(imx_serial_init
);
2168 module_exit(imx_serial_exit
);
2170 MODULE_AUTHOR("Sascha Hauer");
2171 MODULE_DESCRIPTION("IMX generic serial port driver");
2172 MODULE_LICENSE("GPL");
2173 MODULE_ALIAS("platform:imx-uart");