include/video/tdfx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _TDFX_H
   3 #define _TDFX_H
   4
   5 #include <linux/i2c.h>
   6 #include <linux/i2c-algo-bit.h>
   7
   8 /* membase0 register offsets */
   9 #define STATUS          0x00
  10 #define PCIINIT0        0x04
  11 #define SIPMONITOR      0x08
  12 #define LFBMEMORYCONFIG 0x0c
  13 #define MISCINIT0       0x10
  14 #define MISCINIT1       0x14
  15 #define DRAMINIT0       0x18
  16 #define DRAMINIT1       0x1c
  17 #define AGPINIT         0x20
  18 #define TMUGBEINIT      0x24
  19 #define VGAINIT0        0x28
  20 #define VGAINIT1        0x2c
  21 #define DRAMCOMMAND     0x30
  22 #define DRAMDATA        0x34
  23 /* reserved     0x38 */
  24 /* reserved     0x3c */
  25 #define PLLCTRL0        0x40
  26 #define PLLCTRL1        0x44
  27 #define PLLCTRL2        0x48
  28 #define DACMODE         0x4c
  29 #define DACADDR         0x50
  30 #define DACDATA         0x54
  31 #define RGBMAXDELTA     0x58
  32 #define VIDPROCCFG      0x5c
  33 #define HWCURPATADDR    0x60
  34 #define HWCURLOC        0x64
  35 #define HWCURC0         0x68
  36 #define HWCURC1         0x6c
  37 #define VIDINFORMAT     0x70
  38 #define VIDINSTATUS     0x74
  39 #define VIDSERPARPORT   0x78
  40 #define VIDINXDELTA     0x7c
  41 #define VIDININITERR    0x80
  42 #define VIDINYDELTA     0x84
  43 #define VIDPIXBUFTHOLD  0x88
  44 #define VIDCHRMIN       0x8c
  45 #define VIDCHRMAX       0x90
  46 #define VIDCURLIN       0x94
  47 #define VIDSCREENSIZE   0x98
  48 #define VIDOVRSTARTCRD  0x9c
  49 #define VIDOVRENDCRD    0xa0
  50 #define VIDOVRDUDX      0xa4
  51 #define VIDOVRDUDXOFF   0xa8
  52 #define VIDOVRDVDY      0xac
  53 /* ... */
  54 #define VIDOVRDVDYOFF   0xe0
  55 #define VIDDESKSTART    0xe4
  56 #define VIDDESKSTRIDE   0xe8
  57 #define VIDINADDR0      0xec
  58 #define VIDINADDR1      0xf0
  59 #define VIDINADDR2      0xf4
  60 #define VIDINSTRIDE     0xf8
  61 #define VIDCUROVRSTART  0xfc
  62
  63 #define INTCTRL         (0x00100000 + 0x04)
  64 #define CLIP0MIN        (0x00100000 + 0x08)
  65 #define CLIP0MAX        (0x00100000 + 0x0c)
  66 #define DSTBASE         (0x00100000 + 0x10)
  67 #define DSTFORMAT       (0x00100000 + 0x14)
  68 #define SRCBASE         (0x00100000 + 0x34)
  69 #define COMMANDEXTRA_2D (0x00100000 + 0x38)
  70 #define CLIP1MIN        (0x00100000 + 0x4c)
  71 #define CLIP1MAX        (0x00100000 + 0x50)
  72 #define SRCFORMAT       (0x00100000 + 0x54)
  73 #define SRCSIZE         (0x00100000 + 0x58)
  74 #define SRCXY           (0x00100000 + 0x5c)
  75 #define COLORBACK       (0x00100000 + 0x60)
  76 #define COLORFORE       (0x00100000 + 0x64)
  77 #define DSTSIZE         (0x00100000 + 0x68)
  78 #define DSTXY           (0x00100000 + 0x6c)
  79 #define COMMAND_2D      (0x00100000 + 0x70)
  80 #define LAUNCH_2D       (0x00100000 + 0x80)
  81
  82 #define COMMAND_3D      (0x00200000 + 0x120)
  83
  84 /* register bitfields (not all, only as needed) */
  85
  86 /* COMMAND_2D reg. values */
  87 #define TDFX_ROP_COPY           0xcc    /* src */
  88 #define TDFX_ROP_INVERT         0x55    /* NOT dst */
  89 #define TDFX_ROP_XOR            0x66    /* src XOR dst */
  90
  91 #define AUTOINC_DSTX                    BIT(10)
  92 #define AUTOINC_DSTY                    BIT(11)
  93 #define COMMAND_2D_FILLRECT             0x05
  94 #define COMMAND_2D_S2S_BITBLT           0x01    /* screen to screen */
  95 #define COMMAND_2D_H2S_BITBLT           0x03    /* host to screen */
  96
  97 #define COMMAND_3D_NOP                  0x00
  98 #define STATUS_RETRACE                  BIT(6)
  99 #define STATUS_BUSY                     BIT(9)
 100 #define MISCINIT1_CLUT_INV              BIT(0)
 101 #define MISCINIT1_2DBLOCK_DIS           BIT(15)
 102 #define DRAMINIT0_SGRAM_NUM             BIT(26)
 103 #define DRAMINIT0_SGRAM_TYPE            BIT(27)
 104 #define DRAMINIT0_SGRAM_TYPE_MASK       (BIT(27) | BIT(28) | BIT(29))
 105 #define DRAMINIT0_SGRAM_TYPE_SHIFT      27
 106 #define DRAMINIT1_MEM_SDRAM             BIT(30)
 107 #define VGAINIT0_VGA_DISABLE            BIT(0)
 108 #define VGAINIT0_EXT_TIMING             BIT(1)
 109 #define VGAINIT0_8BIT_DAC               BIT(2)
 110 #define VGAINIT0_EXT_ENABLE             BIT(6)
 111 #define VGAINIT0_WAKEUP_3C3             BIT(8)
 112 #define VGAINIT0_LEGACY_DISABLE         BIT(9)
 113 #define VGAINIT0_ALT_READBACK           BIT(10)
 114 #define VGAINIT0_FAST_BLINK             BIT(11)
 115 #define VGAINIT0_EXTSHIFTOUT            BIT(12)
 116 #define VGAINIT0_DECODE_3C6             BIT(13)
 117 #define VGAINIT0_SGRAM_HBLANK_DISABLE   BIT(22)
 118 #define VGAINIT1_MASK                   0x1fffff
 119 #define VIDCFG_VIDPROC_ENABLE           BIT(0)
 120 #define VIDCFG_CURS_X11                 BIT(1)
 121 #define VIDCFG_INTERLACE                BIT(3)
 122 #define VIDCFG_HALF_MODE                BIT(4)
 123 #define VIDCFG_DESK_ENABLE              BIT(7)
 124 #define VIDCFG_CLUT_BYPASS              BIT(10)
 125 #define VIDCFG_2X                       BIT(26)
 126 #define VIDCFG_HWCURSOR_ENABLE          BIT(27)
 127 #define VIDCFG_PIXFMT_SHIFT             18
 128 #define DACMODE_2X                      BIT(0)
 129
 130 /* I2C bit locations in the VIDSERPARPORT register */
 131 #define DDC_ENAB        0x00040000
 132 #define DDC_SCL_OUT     0x00080000
 133 #define DDC_SDA_OUT     0x00100000
 134 #define DDC_SCL_IN      0x00200000
 135 #define DDC_SDA_IN      0x00400000
 136 #define I2C_ENAB        0x00800000
 137 #define I2C_SCL_OUT     0x01000000
 138 #define I2C_SDA_OUT     0x02000000
 139 #define I2C_SCL_IN      0x04000000
 140 #define I2C_SDA_IN      0x08000000
 141
 142 /* VGA rubbish, need to change this for multihead support */
 143 #define MISC_W          0x3c2
 144 #define MISC_R          0x3cc
 145 #define SEQ_I           0x3c4
 146 #define SEQ_D           0x3c5
 147 #define CRT_I           0x3d4
 148 #define CRT_D           0x3d5
 149 #define ATT_IW          0x3c0
 150 #define IS1_R           0x3da
 151 #define GRA_I           0x3ce
 152 #define GRA_D           0x3cf
 153
 154 #ifdef __KERNEL__
 155
 156 struct banshee_reg {
 157         /* VGA rubbish */
 158         unsigned char att[21];
 159         unsigned char crt[25];
 160         unsigned char gra[9];
 161         unsigned char misc[1];
 162         unsigned char seq[5];
 163
 164         /* Banshee extensions */
 165         unsigned char ext[2];
 166         unsigned long vidcfg;
 167         unsigned long vidpll;
 168         unsigned long mempll;
 169         unsigned long gfxpll;
 170         unsigned long dacmode;
 171         unsigned long vgainit0;
 172         unsigned long vgainit1;
 173         unsigned long screensize;
 174         unsigned long stride;
 175         unsigned long cursloc;
 176         unsigned long curspataddr;
 177         unsigned long cursc0;
 178         unsigned long cursc1;
 179         unsigned long startaddr;
 180         unsigned long clip0min;
 181         unsigned long clip0max;
 182         unsigned long clip1min;
 183         unsigned long clip1max;
 184         unsigned long miscinit0;
 185 };
 186
 187 struct tdfx_par;
 188
 189 struct tdfxfb_i2c_chan {
 190         struct tdfx_par *par;
 191         struct i2c_adapter adapter;
 192         struct i2c_algo_bit_data algo;
 193 };
 194
 195 struct tdfx_par {
 196         u32 max_pixclock;
 197         u32 palette[16];
 198         void __iomem *regbase_virt;
 199         unsigned long iobase;
 200         int wc_cookie;
 201 #ifdef CONFIG_FB_3DFX_I2C
 202         struct tdfxfb_i2c_chan chan[2];
 203 #endif
 204 };
 205
 206 #endif  /* __KERNEL__ */
 207
 208 #endif  /* _TDFX_H */
 209