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ieee802154: verify packet size before trying to allocate it
[linux/fpc-iii.git] / drivers / dma / imx-sdma.c
blob1dc2a4ad0026d21c43720941a2670cf0518c60e0
1 /*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/bitops.h>
24 #include <linux/mm.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/semaphore.h>
30 #include <linux/spinlock.h>
31 #include <linux/device.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <linux/platform_device.h>
36 #include <linux/dmaengine.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39
40 #include <asm/irq.h>
41 #include <mach/sdma.h>
42 #include <mach/dma.h>
43 #include <mach/hardware.h>
44
45 #include "dmaengine.h"
46
47 /* SDMA registers */
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
77
78 /*
79 * Buffer descriptor status values.
80 */
81 #define BD_DONE 0x01
82 #define BD_WRAP 0x02
83 #define BD_CONT 0x04
84 #define BD_INTR 0x08
85 #define BD_RROR 0x10
86 #define BD_LAST 0x20
87 #define BD_EXTD 0x80
88
89 /*
90 * Data Node descriptor status values.
91 */
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
94 #define DND_DONE 0x20
95 #define DND_UNUSED 0x01
96
97 /*
98 * IPCV2 descriptor status values.
99 */
100 #define BD_IPCV2_END_OF_FRAME 0x40
101
102 #define IPCV2_MAX_NODES 50
103 /*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107 #define DATA_ERROR 0x10000000
108
109 /*
110 * Buffer descriptor commands.
111 */
112 #define C0_ADDR 0x01
113 #define C0_LOAD 0x02
114 #define C0_DUMP 0x03
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
121 /*
122 * Change endianness indicator in the BD command field
123 */
124 #define CHANGE_ENDIANNESS 0x80
125
126 /*
127 * Mode/Count of data node descriptors - IPCv2
128 */
129 struct sdma_mode_count {
130 u32 count : 16; /* size of the buffer pointed by this BD */
131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
132 u32 command : 8; /* command mostlky used for channel 0 */
133 };
134
135 /*
136 * Buffer descriptor
137 */
138 struct sdma_buffer_descriptor {
139 struct sdma_mode_count mode;
140 u32 buffer_addr; /* address of the buffer described */
141 u32 ext_buffer_addr; /* extended buffer address */
142 } __attribute__ ((packed));
143
144 /**
145 * struct sdma_channel_control - Channel control Block
146 *
147 * @current_bd_ptr current buffer descriptor processed
148 * @base_bd_ptr first element of buffer descriptor array
149 * @unused padding. The SDMA engine expects an array of 128 byte
150 * control blocks
151 */
152 struct sdma_channel_control {
153 u32 current_bd_ptr;
154 u32 base_bd_ptr;
155 u32 unused[2];
156 } __attribute__ ((packed));
157
158 /**
159 * struct sdma_state_registers - SDMA context for a channel
160 *
161 * @pc: program counter
162 * @t: test bit: status of arithmetic & test instruction
163 * @rpc: return program counter
164 * @sf: source fault while loading data
165 * @spc: loop start program counter
166 * @df: destination fault while storing data
167 * @epc: loop end program counter
168 * @lm: loop mode
169 */
170 struct sdma_state_registers {
171 u32 pc :14;
172 u32 unused1: 1;
173 u32 t : 1;
174 u32 rpc :14;
175 u32 unused0: 1;
176 u32 sf : 1;
177 u32 spc :14;
178 u32 unused2: 1;
179 u32 df : 1;
180 u32 epc :14;
181 u32 lm : 2;
182 } __attribute__ ((packed));
183
184 /**
185 * struct sdma_context_data - sdma context specific to a channel
186 *
187 * @channel_state: channel state bits
188 * @gReg: general registers
189 * @mda: burst dma destination address register
190 * @msa: burst dma source address register
191 * @ms: burst dma status register
192 * @md: burst dma data register
193 * @pda: peripheral dma destination address register
194 * @psa: peripheral dma source address register
195 * @ps: peripheral dma status register
196 * @pd: peripheral dma data register
197 * @ca: CRC polynomial register
198 * @cs: CRC accumulator register
199 * @dda: dedicated core destination address register
200 * @dsa: dedicated core source address register
201 * @ds: dedicated core status register
202 * @dd: dedicated core data register
203 */
204 struct sdma_context_data {
205 struct sdma_state_registers channel_state;
206 u32 gReg[8];
207 u32 mda;
208 u32 msa;
209 u32 ms;
210 u32 md;
211 u32 pda;
212 u32 psa;
213 u32 ps;
214 u32 pd;
215 u32 ca;
216 u32 cs;
217 u32 dda;
218 u32 dsa;
219 u32 ds;
220 u32 dd;
221 u32 scratch0;
222 u32 scratch1;
223 u32 scratch2;
224 u32 scratch3;
225 u32 scratch4;
226 u32 scratch5;
227 u32 scratch6;
228 u32 scratch7;
229 } __attribute__ ((packed));
230
231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
232
233 struct sdma_engine;
234
235 /**
236 * struct sdma_channel - housekeeping for a SDMA channel
237 *
238 * @sdma pointer to the SDMA engine for this channel
239 * @channel the channel number, matches dmaengine chan_id + 1
240 * @direction transfer type. Needed for setting SDMA script
241 * @peripheral_type Peripheral type. Needed for setting SDMA script
242 * @event_id0 aka dma request line
243 * @event_id1 for channels that use 2 events
244 * @word_size peripheral access size
245 * @buf_tail ID of the buffer that was processed
246 * @done channel completion
247 * @num_bd max NUM_BD. number of descriptors currently handling
248 */
249 struct sdma_channel {
250 struct sdma_engine *sdma;
251 unsigned int channel;
252 enum dma_transfer_direction direction;
253 enum sdma_peripheral_type peripheral_type;
254 unsigned int event_id0;
255 unsigned int event_id1;
256 enum dma_slave_buswidth word_size;
257 unsigned int buf_tail;
258 struct completion done;
259 unsigned int num_bd;
260 struct sdma_buffer_descriptor *bd;
261 dma_addr_t bd_phys;
262 unsigned int pc_from_device, pc_to_device;
263 unsigned long flags;
264 dma_addr_t per_address;
265 unsigned long event_mask[2];
266 unsigned long watermark_level;
267 u32 shp_addr, per_addr;
268 struct dma_chan chan;
269 spinlock_t lock;
270 struct dma_async_tx_descriptor desc;
271 enum dma_status status;
272 unsigned int chn_count;
273 unsigned int chn_real_count;
274 struct tasklet_struct tasklet;
275 };
276
277 #define IMX_DMA_SG_LOOP BIT(0)
278
279 #define MAX_DMA_CHANNELS 32
280 #define MXC_SDMA_DEFAULT_PRIORITY 1
281 #define MXC_SDMA_MIN_PRIORITY 1
282 #define MXC_SDMA_MAX_PRIORITY 7
283
284 #define SDMA_FIRMWARE_MAGIC 0x414d4453
285
286 /**
287 * struct sdma_firmware_header - Layout of the firmware image
288 *
289 * @magic "SDMA"
290 * @version_major increased whenever layout of struct sdma_script_start_addrs
291 * changes.
292 * @version_minor firmware minor version (for binary compatible changes)
293 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
294 * @num_script_addrs Number of script addresses in this image
295 * @ram_code_start offset of SDMA ram image in this firmware image
296 * @ram_code_size size of SDMA ram image
297 * @script_addrs Stores the start address of the SDMA scripts
298 * (in SDMA memory space)
299 */
300 struct sdma_firmware_header {
301 u32 magic;
302 u32 version_major;
303 u32 version_minor;
304 u32 script_addrs_start;
305 u32 num_script_addrs;
306 u32 ram_code_start;
307 u32 ram_code_size;
308 };
309
310 enum sdma_devtype {
311 IMX31_SDMA, /* runs on i.mx31 */
312 IMX35_SDMA, /* runs on i.mx35 and later */
313 };
314
315 struct sdma_engine {
316 struct device *dev;
317 struct device_dma_parameters dma_parms;
318 struct sdma_channel channel[MAX_DMA_CHANNELS];
319 struct sdma_channel_control *channel_control;
320 void __iomem *regs;
321 enum sdma_devtype devtype;
322 unsigned int num_events;
323 struct sdma_context_data *context;
324 dma_addr_t context_phys;
325 struct dma_device dma_device;
326 struct clk *clk_ipg;
327 struct clk *clk_ahb;
328 spinlock_t channel_0_lock;
329 struct sdma_script_start_addrs *script_addrs;
330 };
331
332 static struct platform_device_id sdma_devtypes[] = {
333 {
334 .name = "imx31-sdma",
335 .driver_data = IMX31_SDMA,
336 }, {
337 .name = "imx35-sdma",
338 .driver_data = IMX35_SDMA,
339 }, {
340 /* sentinel */
341 }
342 };
343 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
344
345 static const struct of_device_id sdma_dt_ids[] = {
346 { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
347 { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
348 { /* sentinel */ }
349 };
350 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
351
352 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
353 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
354 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
355 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
356
357 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
358 {
359 u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
360 SDMA_CHNENBL0_IMX35);
361 return chnenbl0 + event * 4;
362 }
363
364 static int sdma_config_ownership(struct sdma_channel *sdmac,
365 bool event_override, bool mcu_override, bool dsp_override)
366 {
367 struct sdma_engine *sdma = sdmac->sdma;
368 int channel = sdmac->channel;
369 unsigned long evt, mcu, dsp;
370
371 if (event_override && mcu_override && dsp_override)
372 return -EINVAL;
373
374 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
375 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
376 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
377
378 if (dsp_override)
379 __clear_bit(channel, &dsp);
380 else
381 __set_bit(channel, &dsp);
382
383 if (event_override)
384 __clear_bit(channel, &evt);
385 else
386 __set_bit(channel, &evt);
387
388 if (mcu_override)
389 __clear_bit(channel, &mcu);
390 else
391 __set_bit(channel, &mcu);
392
393 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
394 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
395 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
396
397 return 0;
398 }
399
400 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
401 {
402 writel(BIT(channel), sdma->regs + SDMA_H_START);
403 }
404
405 /*
406 * sdma_run_channel0 - run a channel and wait till it's done
407 */
408 static int sdma_run_channel0(struct sdma_engine *sdma)
409 {
410 int ret;
411 unsigned long timeout = 500;
412
413 sdma_enable_channel(sdma, 0);
414
415 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
416 if (timeout-- <= 0)
417 break;
418 udelay(1);
419 }
420
421 if (ret) {
422 /* Clear the interrupt status */
423 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
424 } else {
425 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
426 }
427
428 return ret ? 0 : -ETIMEDOUT;
429 }
430
431 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
432 u32 address)
433 {
434 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
435 void *buf_virt;
436 dma_addr_t buf_phys;
437 int ret;
438 unsigned long flags;
439
440 buf_virt = dma_alloc_coherent(NULL,
441 size,
442 &buf_phys, GFP_KERNEL);
443 if (!buf_virt) {
444 return -ENOMEM;
445 }
446
447 spin_lock_irqsave(&sdma->channel_0_lock, flags);
448
449 bd0->mode.command = C0_SETPM;
450 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
451 bd0->mode.count = size / 2;
452 bd0->buffer_addr = buf_phys;
453 bd0->ext_buffer_addr = address;
454
455 memcpy(buf_virt, buf, size);
456
457 ret = sdma_run_channel0(sdma);
458
459 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
460
461 dma_free_coherent(NULL, size, buf_virt, buf_phys);
462
463 return ret;
464 }
465
466 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
467 {
468 struct sdma_engine *sdma = sdmac->sdma;
469 int channel = sdmac->channel;
470 unsigned long val;
471 u32 chnenbl = chnenbl_ofs(sdma, event);
472
473 val = readl_relaxed(sdma->regs + chnenbl);
474 __set_bit(channel, &val);
475 writel_relaxed(val, sdma->regs + chnenbl);
476 }
477
478 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
479 {
480 struct sdma_engine *sdma = sdmac->sdma;
481 int channel = sdmac->channel;
482 u32 chnenbl = chnenbl_ofs(sdma, event);
483 unsigned long val;
484
485 val = readl_relaxed(sdma->regs + chnenbl);
486 __clear_bit(channel, &val);
487 writel_relaxed(val, sdma->regs + chnenbl);
488 }
489
490 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
491 {
492 struct sdma_buffer_descriptor *bd;
493
494 /*
495 * loop mode. Iterate over descriptors, re-setup them and
496 * call callback function.
497 */
498 while (1) {
499 bd = &sdmac->bd[sdmac->buf_tail];
500
501 if (bd->mode.status & BD_DONE)
502 break;
503
504 if (bd->mode.status & BD_RROR)
505 sdmac->status = DMA_ERROR;
506 else
507 sdmac->status = DMA_IN_PROGRESS;
508
509 bd->mode.status |= BD_DONE;
510 sdmac->buf_tail++;
511 sdmac->buf_tail %= sdmac->num_bd;
512
513 if (sdmac->desc.callback)
514 sdmac->desc.callback(sdmac->desc.callback_param);
515 }
516 }
517
518 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
519 {
520 struct sdma_buffer_descriptor *bd;
521 int i, error = 0;
522
523 sdmac->chn_real_count = 0;
524 /*
525 * non loop mode. Iterate over all descriptors, collect
526 * errors and call callback function
527 */
528 for (i = 0; i < sdmac->num_bd; i++) {
529 bd = &sdmac->bd[i];
530
531 if (bd->mode.status & (BD_DONE | BD_RROR))
532 error = -EIO;
533 sdmac->chn_real_count += bd->mode.count;
534 }
535
536 if (error)
537 sdmac->status = DMA_ERROR;
538 else
539 sdmac->status = DMA_SUCCESS;
540
541 dma_cookie_complete(&sdmac->desc);
542 if (sdmac->desc.callback)
543 sdmac->desc.callback(sdmac->desc.callback_param);
544 }
545
546 static void sdma_tasklet(unsigned long data)
547 {
548 struct sdma_channel *sdmac = (struct sdma_channel *) data;
549
550 complete(&sdmac->done);
551
552 if (sdmac->flags & IMX_DMA_SG_LOOP)
553 sdma_handle_channel_loop(sdmac);
554 else
555 mxc_sdma_handle_channel_normal(sdmac);
556 }
557
558 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
559 {
560 struct sdma_engine *sdma = dev_id;
561 unsigned long stat;
562
563 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
564 /* not interested in channel 0 interrupts */
565 stat &= ~1;
566 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
567
568 while (stat) {
569 int channel = fls(stat) - 1;
570 struct sdma_channel *sdmac = &sdma->channel[channel];
571
572 tasklet_schedule(&sdmac->tasklet);
573
574 __clear_bit(channel, &stat);
575 }
576
577 return IRQ_HANDLED;
578 }
579
580 /*
581 * sets the pc of SDMA script according to the peripheral type
582 */
583 static void sdma_get_pc(struct sdma_channel *sdmac,
584 enum sdma_peripheral_type peripheral_type)
585 {
586 struct sdma_engine *sdma = sdmac->sdma;
587 int per_2_emi = 0, emi_2_per = 0;
588 /*
589 * These are needed once we start to support transfers between
590 * two peripherals or memory-to-memory transfers
591 */
592 int per_2_per = 0, emi_2_emi = 0;
593
594 sdmac->pc_from_device = 0;
595 sdmac->pc_to_device = 0;
596
597 switch (peripheral_type) {
598 case IMX_DMATYPE_MEMORY:
599 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
600 break;
601 case IMX_DMATYPE_DSP:
602 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
603 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
604 break;
605 case IMX_DMATYPE_FIRI:
606 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
607 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
608 break;
609 case IMX_DMATYPE_UART:
610 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
611 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
612 break;
613 case IMX_DMATYPE_UART_SP:
614 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
615 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
616 break;
617 case IMX_DMATYPE_ATA:
618 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
619 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
620 break;
621 case IMX_DMATYPE_CSPI:
622 case IMX_DMATYPE_EXT:
623 case IMX_DMATYPE_SSI:
624 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
625 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
626 break;
627 case IMX_DMATYPE_SSI_SP:
628 case IMX_DMATYPE_MMC:
629 case IMX_DMATYPE_SDHC:
630 case IMX_DMATYPE_CSPI_SP:
631 case IMX_DMATYPE_ESAI:
632 case IMX_DMATYPE_MSHC_SP:
633 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
634 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
635 break;
636 case IMX_DMATYPE_ASRC:
637 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
638 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
639 per_2_per = sdma->script_addrs->per_2_per_addr;
640 break;
641 case IMX_DMATYPE_MSHC:
642 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
643 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
644 break;
645 case IMX_DMATYPE_CCM:
646 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
647 break;
648 case IMX_DMATYPE_SPDIF:
649 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
650 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
651 break;
652 case IMX_DMATYPE_IPU_MEMORY:
653 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
654 break;
655 default:
656 break;
657 }
658
659 sdmac->pc_from_device = per_2_emi;
660 sdmac->pc_to_device = emi_2_per;
661 }
662
663 static int sdma_load_context(struct sdma_channel *sdmac)
664 {
665 struct sdma_engine *sdma = sdmac->sdma;
666 int channel = sdmac->channel;
667 int load_address;
668 struct sdma_context_data *context = sdma->context;
669 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
670 int ret;
671 unsigned long flags;
672
673 if (sdmac->direction == DMA_DEV_TO_MEM) {
674 load_address = sdmac->pc_from_device;
675 } else {
676 load_address = sdmac->pc_to_device;
677 }
678
679 if (load_address < 0)
680 return load_address;
681
682 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
683 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
684 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
685 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
686 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
687 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
688
689 spin_lock_irqsave(&sdma->channel_0_lock, flags);
690
691 memset(context, 0, sizeof(*context));
692 context->channel_state.pc = load_address;
693
694 /* Send by context the event mask,base address for peripheral
695 * and watermark level
696 */
697 context->gReg[0] = sdmac->event_mask[1];
698 context->gReg[1] = sdmac->event_mask[0];
699 context->gReg[2] = sdmac->per_addr;
700 context->gReg[6] = sdmac->shp_addr;
701 context->gReg[7] = sdmac->watermark_level;
702
703 bd0->mode.command = C0_SETDM;
704 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
705 bd0->mode.count = sizeof(*context) / 4;
706 bd0->buffer_addr = sdma->context_phys;
707 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
708 ret = sdma_run_channel0(sdma);
709
710 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
711
712 return ret;
713 }
714
715 static void sdma_disable_channel(struct sdma_channel *sdmac)
716 {
717 struct sdma_engine *sdma = sdmac->sdma;
718 int channel = sdmac->channel;
719
720 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
721 sdmac->status = DMA_ERROR;
722 }
723
724 static int sdma_config_channel(struct sdma_channel *sdmac)
725 {
726 int ret;
727
728 sdma_disable_channel(sdmac);
729
730 sdmac->event_mask[0] = 0;
731 sdmac->event_mask[1] = 0;
732 sdmac->shp_addr = 0;
733 sdmac->per_addr = 0;
734
735 if (sdmac->event_id0) {
736 if (sdmac->event_id0 >= sdmac->sdma->num_events)
737 return -EINVAL;
738 sdma_event_enable(sdmac, sdmac->event_id0);
739 }
740
741 switch (sdmac->peripheral_type) {
742 case IMX_DMATYPE_DSP:
743 sdma_config_ownership(sdmac, false, true, true);
744 break;
745 case IMX_DMATYPE_MEMORY:
746 sdma_config_ownership(sdmac, false, true, false);
747 break;
748 default:
749 sdma_config_ownership(sdmac, true, true, false);
750 break;
751 }
752
753 sdma_get_pc(sdmac, sdmac->peripheral_type);
754
755 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
756 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
757 /* Handle multiple event channels differently */
758 if (sdmac->event_id1) {
759 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
760 if (sdmac->event_id1 > 31)
761 __set_bit(31, &sdmac->watermark_level);
762 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
763 if (sdmac->event_id0 > 31)
764 __set_bit(30, &sdmac->watermark_level);
765 } else {
766 __set_bit(sdmac->event_id0, sdmac->event_mask);
767 }
768 /* Watermark Level */
769 sdmac->watermark_level |= sdmac->watermark_level;
770 /* Address */
771 sdmac->shp_addr = sdmac->per_address;
772 } else {
773 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
774 }
775
776 ret = sdma_load_context(sdmac);
777
778 return ret;
779 }
780
781 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
782 unsigned int priority)
783 {
784 struct sdma_engine *sdma = sdmac->sdma;
785 int channel = sdmac->channel;
786
787 if (priority < MXC_SDMA_MIN_PRIORITY
788 || priority > MXC_SDMA_MAX_PRIORITY) {
789 return -EINVAL;
790 }
791
792 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
793
794 return 0;
795 }
796
797 static int sdma_request_channel(struct sdma_channel *sdmac)
798 {
799 struct sdma_engine *sdma = sdmac->sdma;
800 int channel = sdmac->channel;
801 int ret = -EBUSY;
802
803 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
804 if (!sdmac->bd) {
805 ret = -ENOMEM;
806 goto out;
807 }
808
809 memset(sdmac->bd, 0, PAGE_SIZE);
810
811 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
812 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
813
814 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
815
816 init_completion(&sdmac->done);
817
818 return 0;
819 out:
820
821 return ret;
822 }
823
824 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
825 {
826 return container_of(chan, struct sdma_channel, chan);
827 }
828
829 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
830 {
831 unsigned long flags;
832 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
833 dma_cookie_t cookie;
834
835 spin_lock_irqsave(&sdmac->lock, flags);
836
837 cookie = dma_cookie_assign(tx);
838
839 spin_unlock_irqrestore(&sdmac->lock, flags);
840
841 return cookie;
842 }
843
844 static int sdma_alloc_chan_resources(struct dma_chan *chan)
845 {
846 struct sdma_channel *sdmac = to_sdma_chan(chan);
847 struct imx_dma_data *data = chan->private;
848 int prio, ret;
849
850 if (!data)
851 return -EINVAL;
852
853 switch (data->priority) {
854 case DMA_PRIO_HIGH:
855 prio = 3;
856 break;
857 case DMA_PRIO_MEDIUM:
858 prio = 2;
859 break;
860 case DMA_PRIO_LOW:
861 default:
862 prio = 1;
863 break;
864 }
865
866 sdmac->peripheral_type = data->peripheral_type;
867 sdmac->event_id0 = data->dma_request;
868
869 clk_enable(sdmac->sdma->clk_ipg);
870 clk_enable(sdmac->sdma->clk_ahb);
871
872 ret = sdma_request_channel(sdmac);
873 if (ret)
874 return ret;
875
876 ret = sdma_set_channel_priority(sdmac, prio);
877 if (ret)
878 return ret;
879
880 dma_async_tx_descriptor_init(&sdmac->desc, chan);
881 sdmac->desc.tx_submit = sdma_tx_submit;
882 /* txd.flags will be overwritten in prep funcs */
883 sdmac->desc.flags = DMA_CTRL_ACK;
884
885 return 0;
886 }
887
888 static void sdma_free_chan_resources(struct dma_chan *chan)
889 {
890 struct sdma_channel *sdmac = to_sdma_chan(chan);
891 struct sdma_engine *sdma = sdmac->sdma;
892
893 sdma_disable_channel(sdmac);
894
895 if (sdmac->event_id0)
896 sdma_event_disable(sdmac, sdmac->event_id0);
897 if (sdmac->event_id1)
898 sdma_event_disable(sdmac, sdmac->event_id1);
899
900 sdmac->event_id0 = 0;
901 sdmac->event_id1 = 0;
902
903 sdma_set_channel_priority(sdmac, 0);
904
905 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
906
907 clk_disable(sdma->clk_ipg);
908 clk_disable(sdma->clk_ahb);
909 }
910
911 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
912 struct dma_chan *chan, struct scatterlist *sgl,
913 unsigned int sg_len, enum dma_transfer_direction direction,
914 unsigned long flags, void *context)
915 {
916 struct sdma_channel *sdmac = to_sdma_chan(chan);
917 struct sdma_engine *sdma = sdmac->sdma;
918 int ret, i, count;
919 int channel = sdmac->channel;
920 struct scatterlist *sg;
921
922 if (sdmac->status == DMA_IN_PROGRESS)
923 return NULL;
924 sdmac->status = DMA_IN_PROGRESS;
925
926 sdmac->flags = 0;
927
928 sdmac->buf_tail = 0;
929
930 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
931 sg_len, channel);
932
933 sdmac->direction = direction;
934 ret = sdma_load_context(sdmac);
935 if (ret)
936 goto err_out;
937
938 if (sg_len > NUM_BD) {
939 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
940 channel, sg_len, NUM_BD);
941 ret = -EINVAL;
942 goto err_out;
943 }
944
945 sdmac->chn_count = 0;
946 for_each_sg(sgl, sg, sg_len, i) {
947 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
948 int param;
949
950 bd->buffer_addr = sg->dma_address;
951
952 count = sg_dma_len(sg);
953
954 if (count > 0xffff) {
955 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
956 channel, count, 0xffff);
957 ret = -EINVAL;
958 goto err_out;
959 }
960
961 bd->mode.count = count;
962 sdmac->chn_count += count;
963
964 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
965 ret = -EINVAL;
966 goto err_out;
967 }
968
969 switch (sdmac->word_size) {
970 case DMA_SLAVE_BUSWIDTH_4_BYTES:
971 bd->mode.command = 0;
972 if (count & 3 || sg->dma_address & 3)
973 return NULL;
974 break;
975 case DMA_SLAVE_BUSWIDTH_2_BYTES:
976 bd->mode.command = 2;
977 if (count & 1 || sg->dma_address & 1)
978 return NULL;
979 break;
980 case DMA_SLAVE_BUSWIDTH_1_BYTE:
981 bd->mode.command = 1;
982 break;
983 default:
984 return NULL;
985 }
986
987 param = BD_DONE | BD_EXTD | BD_CONT;
988
989 if (i + 1 == sg_len) {
990 param |= BD_INTR;
991 param |= BD_LAST;
992 param &= ~BD_CONT;
993 }
994
995 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
996 i, count, sg->dma_address,
997 param & BD_WRAP ? "wrap" : "",
998 param & BD_INTR ? " intr" : "");
999
1000 bd->mode.status = param;
1001 }
1002
1003 sdmac->num_bd = sg_len;
1004 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1005
1006 return &sdmac->desc;
1007 err_out:
1008 sdmac->status = DMA_ERROR;
1009 return NULL;
1010 }
1011
1012 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1013 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1014 size_t period_len, enum dma_transfer_direction direction,
1015 void *context)
1016 {
1017 struct sdma_channel *sdmac = to_sdma_chan(chan);
1018 struct sdma_engine *sdma = sdmac->sdma;
1019 int num_periods = buf_len / period_len;
1020 int channel = sdmac->channel;
1021 int ret, i = 0, buf = 0;
1022
1023 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1024
1025 if (sdmac->status == DMA_IN_PROGRESS)
1026 return NULL;
1027
1028 sdmac->status = DMA_IN_PROGRESS;
1029
1030 sdmac->buf_tail = 0;
1031
1032 sdmac->flags |= IMX_DMA_SG_LOOP;
1033 sdmac->direction = direction;
1034 ret = sdma_load_context(sdmac);
1035 if (ret)
1036 goto err_out;
1037
1038 if (num_periods > NUM_BD) {
1039 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1040 channel, num_periods, NUM_BD);
1041 goto err_out;
1042 }
1043
1044 if (period_len > 0xffff) {
1045 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1046 channel, period_len, 0xffff);
1047 goto err_out;
1048 }
1049
1050 while (buf < buf_len) {
1051 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1052 int param;
1053
1054 bd->buffer_addr = dma_addr;
1055
1056 bd->mode.count = period_len;
1057
1058 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1059 goto err_out;
1060 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1061 bd->mode.command = 0;
1062 else
1063 bd->mode.command = sdmac->word_size;
1064
1065 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1066 if (i + 1 == num_periods)
1067 param |= BD_WRAP;
1068
1069 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1070 i, period_len, dma_addr,
1071 param & BD_WRAP ? "wrap" : "",
1072 param & BD_INTR ? " intr" : "");
1073
1074 bd->mode.status = param;
1075
1076 dma_addr += period_len;
1077 buf += period_len;
1078
1079 i++;
1080 }
1081
1082 sdmac->num_bd = num_periods;
1083 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1084
1085 return &sdmac->desc;
1086 err_out:
1087 sdmac->status = DMA_ERROR;
1088 return NULL;
1089 }
1090
1091 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1092 unsigned long arg)
1093 {
1094 struct sdma_channel *sdmac = to_sdma_chan(chan);
1095 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1096
1097 switch (cmd) {
1098 case DMA_TERMINATE_ALL:
1099 sdma_disable_channel(sdmac);
1100 return 0;
1101 case DMA_SLAVE_CONFIG:
1102 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1103 sdmac->per_address = dmaengine_cfg->src_addr;
1104 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1105 dmaengine_cfg->src_addr_width;
1106 sdmac->word_size = dmaengine_cfg->src_addr_width;
1107 } else {
1108 sdmac->per_address = dmaengine_cfg->dst_addr;
1109 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1110 dmaengine_cfg->dst_addr_width;
1111 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1112 }
1113 sdmac->direction = dmaengine_cfg->direction;
1114 return sdma_config_channel(sdmac);
1115 default:
1116 return -ENOSYS;
1117 }
1118
1119 return -EINVAL;
1120 }
1121
1122 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1123 dma_cookie_t cookie,
1124 struct dma_tx_state *txstate)
1125 {
1126 struct sdma_channel *sdmac = to_sdma_chan(chan);
1127 dma_cookie_t last_used;
1128
1129 last_used = chan->cookie;
1130
1131 dma_set_tx_state(txstate, chan->completed_cookie, last_used,
1132 sdmac->chn_count - sdmac->chn_real_count);
1133
1134 return sdmac->status;
1135 }
1136
1137 static void sdma_issue_pending(struct dma_chan *chan)
1138 {
1139 struct sdma_channel *sdmac = to_sdma_chan(chan);
1140 struct sdma_engine *sdma = sdmac->sdma;
1141
1142 if (sdmac->status == DMA_IN_PROGRESS)
1143 sdma_enable_channel(sdma, sdmac->channel);
1144 }
1145
1146 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1147
1148 static void sdma_add_scripts(struct sdma_engine *sdma,
1149 const struct sdma_script_start_addrs *addr)
1150 {
1151 s32 *addr_arr = (u32 *)addr;
1152 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1153 int i;
1154
1155 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1156 if (addr_arr[i] > 0)
1157 saddr_arr[i] = addr_arr[i];
1158 }
1159
1160 static void sdma_load_firmware(const struct firmware *fw, void *context)
1161 {
1162 struct sdma_engine *sdma = context;
1163 const struct sdma_firmware_header *header;
1164 const struct sdma_script_start_addrs *addr;
1165 unsigned short *ram_code;
1166
1167 if (!fw) {
1168 dev_err(sdma->dev, "firmware not found\n");
1169 return;
1170 }
1171
1172 if (fw->size < sizeof(*header))
1173 goto err_firmware;
1174
1175 header = (struct sdma_firmware_header *)fw->data;
1176
1177 if (header->magic != SDMA_FIRMWARE_MAGIC)
1178 goto err_firmware;
1179 if (header->ram_code_start + header->ram_code_size > fw->size)
1180 goto err_firmware;
1181
1182 addr = (void *)header + header->script_addrs_start;
1183 ram_code = (void *)header + header->ram_code_start;
1184
1185 clk_enable(sdma->clk_ipg);
1186 clk_enable(sdma->clk_ahb);
1187 /* download the RAM image for SDMA */
1188 sdma_load_script(sdma, ram_code,
1189 header->ram_code_size,
1190 addr->ram_code_start_addr);
1191 clk_disable(sdma->clk_ipg);
1192 clk_disable(sdma->clk_ahb);
1193
1194 sdma_add_scripts(sdma, addr);
1195
1196 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1197 header->version_major,
1198 header->version_minor);
1199
1200 err_firmware:
1201 release_firmware(fw);
1202 }
1203
1204 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1205 const char *fw_name)
1206 {
1207 int ret;
1208
1209 ret = request_firmware_nowait(THIS_MODULE,
1210 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1211 GFP_KERNEL, sdma, sdma_load_firmware);
1212
1213 return ret;
1214 }
1215
1216 static int __init sdma_init(struct sdma_engine *sdma)
1217 {
1218 int i, ret;
1219 dma_addr_t ccb_phys;
1220
1221 switch (sdma->devtype) {
1222 case IMX31_SDMA:
1223 sdma->num_events = 32;
1224 break;
1225 case IMX35_SDMA:
1226 sdma->num_events = 48;
1227 break;
1228 default:
1229 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1230 sdma->devtype);
1231 return -ENODEV;
1232 }
1233
1234 clk_enable(sdma->clk_ipg);
1235 clk_enable(sdma->clk_ahb);
1236
1237 /* Be sure SDMA has not started yet */
1238 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1239
1240 sdma->channel_control = dma_alloc_coherent(NULL,
1241 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1242 sizeof(struct sdma_context_data),
1243 &ccb_phys, GFP_KERNEL);
1244
1245 if (!sdma->channel_control) {
1246 ret = -ENOMEM;
1247 goto err_dma_alloc;
1248 }
1249
1250 sdma->context = (void *)sdma->channel_control +
1251 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1252 sdma->context_phys = ccb_phys +
1253 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1254
1255 /* Zero-out the CCB structures array just allocated */
1256 memset(sdma->channel_control, 0,
1257 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1258
1259 /* disable all channels */
1260 for (i = 0; i < sdma->num_events; i++)
1261 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1262
1263 /* All channels have priority 0 */
1264 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1265 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1266
1267 ret = sdma_request_channel(&sdma->channel[0]);
1268 if (ret)
1269 goto err_dma_alloc;
1270
1271 sdma_config_ownership(&sdma->channel[0], false, true, false);
1272
1273 /* Set Command Channel (Channel Zero) */
1274 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1275
1276 /* Set bits of CONFIG register but with static context switching */
1277 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1278 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1279
1280 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1281
1282 /* Set bits of CONFIG register with given context switching mode */
1283 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1284
1285 /* Initializes channel's priorities */
1286 sdma_set_channel_priority(&sdma->channel[0], 7);
1287
1288 clk_disable(sdma->clk_ipg);
1289 clk_disable(sdma->clk_ahb);
1290
1291 return 0;
1292
1293 err_dma_alloc:
1294 clk_disable(sdma->clk_ipg);
1295 clk_disable(sdma->clk_ahb);
1296 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1297 return ret;
1298 }
1299
1300 static int __init sdma_probe(struct platform_device *pdev)
1301 {
1302 const struct of_device_id *of_id =
1303 of_match_device(sdma_dt_ids, &pdev->dev);
1304 struct device_node *np = pdev->dev.of_node;
1305 const char *fw_name;
1306 int ret;
1307 int irq;
1308 struct resource *iores;
1309 struct sdma_platform_data *pdata = pdev->dev.platform_data;
1310 int i;
1311 struct sdma_engine *sdma;
1312 s32 *saddr_arr;
1313
1314 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1315 if (!sdma)
1316 return -ENOMEM;
1317
1318 spin_lock_init(&sdma->channel_0_lock);
1319
1320 sdma->dev = &pdev->dev;
1321
1322 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1323 irq = platform_get_irq(pdev, 0);
1324 if (!iores || irq < 0) {
1325 ret = -EINVAL;
1326 goto err_irq;
1327 }
1328
1329 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1330 ret = -EBUSY;
1331 goto err_request_region;
1332 }
1333
1334 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1335 if (IS_ERR(sdma->clk_ipg)) {
1336 ret = PTR_ERR(sdma->clk_ipg);
1337 goto err_clk;
1338 }
1339
1340 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1341 if (IS_ERR(sdma->clk_ahb)) {
1342 ret = PTR_ERR(sdma->clk_ahb);
1343 goto err_clk;
1344 }
1345
1346 clk_prepare(sdma->clk_ipg);
1347 clk_prepare(sdma->clk_ahb);
1348
1349 sdma->regs = ioremap(iores->start, resource_size(iores));
1350 if (!sdma->regs) {
1351 ret = -ENOMEM;
1352 goto err_ioremap;
1353 }
1354
1355 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1356 if (ret)
1357 goto err_request_irq;
1358
1359 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1360 if (!sdma->script_addrs) {
1361 ret = -ENOMEM;
1362 goto err_alloc;
1363 }
1364
1365 /* initially no scripts available */
1366 saddr_arr = (s32 *)sdma->script_addrs;
1367 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1368 saddr_arr[i] = -EINVAL;
1369
1370 if (of_id)
1371 pdev->id_entry = of_id->data;
1372 sdma->devtype = pdev->id_entry->driver_data;
1373
1374 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1375 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1376
1377 INIT_LIST_HEAD(&sdma->dma_device.channels);
1378 /* Initialize channel parameters */
1379 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1380 struct sdma_channel *sdmac = &sdma->channel[i];
1381
1382 sdmac->sdma = sdma;
1383 spin_lock_init(&sdmac->lock);
1384
1385 sdmac->chan.device = &sdma->dma_device;
1386 dma_cookie_init(&sdmac->chan);
1387 sdmac->channel = i;
1388
1389 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1390 (unsigned long) sdmac);
1391 /*
1392 * Add the channel to the DMAC list. Do not add channel 0 though
1393 * because we need it internally in the SDMA driver. This also means
1394 * that channel 0 in dmaengine counting matches sdma channel 1.
1395 */
1396 if (i)
1397 list_add_tail(&sdmac->chan.device_node,
1398 &sdma->dma_device.channels);
1399 }
1400
1401 ret = sdma_init(sdma);
1402 if (ret)
1403 goto err_init;
1404
1405 if (pdata && pdata->script_addrs)
1406 sdma_add_scripts(sdma, pdata->script_addrs);
1407
1408 if (pdata) {
1409 ret = sdma_get_firmware(sdma, pdata->fw_name);
1410 if (ret)
1411 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1412 } else {
1413 /*
1414 * Because that device tree does not encode ROM script address,
1415 * the RAM script in firmware is mandatory for device tree
1416 * probe, otherwise it fails.
1417 */
1418 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1419 &fw_name);
1420 if (ret)
1421 dev_warn(&pdev->dev, "failed to get firmware name\n");
1422 else {
1423 ret = sdma_get_firmware(sdma, fw_name);
1424 if (ret)
1425 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1426 }
1427 }
1428
1429 sdma->dma_device.dev = &pdev->dev;
1430
1431 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1432 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1433 sdma->dma_device.device_tx_status = sdma_tx_status;
1434 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1435 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1436 sdma->dma_device.device_control = sdma_control;
1437 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1438 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1439 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1440
1441 ret = dma_async_device_register(&sdma->dma_device);
1442 if (ret) {
1443 dev_err(&pdev->dev, "unable to register\n");
1444 goto err_init;
1445 }
1446
1447 dev_info(sdma->dev, "initialized\n");
1448
1449 return 0;
1450
1451 err_init:
1452 kfree(sdma->script_addrs);
1453 err_alloc:
1454 free_irq(irq, sdma);
1455 err_request_irq:
1456 iounmap(sdma->regs);
1457 err_ioremap:
1458 err_clk:
1459 release_mem_region(iores->start, resource_size(iores));
1460 err_request_region:
1461 err_irq:
1462 kfree(sdma);
1463 return ret;
1464 }
1465
1466 static int __exit sdma_remove(struct platform_device *pdev)
1467 {
1468 return -EBUSY;
1469 }
1470
1471 static struct platform_driver sdma_driver = {
1472 .driver = {
1473 .name = "imx-sdma",
1474 .of_match_table = sdma_dt_ids,
1475 },
1476 .id_table = sdma_devtypes,
1477 .remove = __exit_p(sdma_remove),
1478 };
1479
1480 static int __init sdma_module_init(void)
1481 {
1482 return platform_driver_probe(&sdma_driver, sdma_probe);
1483 }
1484 module_init(sdma_module_init);
1485
1486 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1487 MODULE_DESCRIPTION("i.MX SDMA driver");
1488 MODULE_LICENSE("GPL");
Linux with added FPC-III support