| blob | 15214d05fec1cf97304e4aaa254e1dc57b3c334e |
1 /*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 #include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
35 pinconf: pinconf@00140000 {
36 compatible = "pinconf-single";
37 reg = <0x00140000 0x250>;
38 pinctrl-single,register-width = <32>;
40 /* pinconf functions */
41 };
43 pinmux: pinmux@0014029c {
44 compatible = "pinctrl-single";
45 reg = <0x0014029c 0x250>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48 pinctrl-single,register-width = <32>;
49 pinctrl-single,function-mask = <0xf>;
50 pinctrl-single,gpio-range = <
51 &range 0 154 MODE_GPIO
52 >;
53 range: gpio-range {
54 #pinctrl-single,gpio-range-cells = <3>;
55 };
57 /* pinctrl functions */
58 tsio_pins: pinmux_gpio_14 {
59 pinctrl-single,pins = <
60 0x038 MODE_NITRO /* tsio_0 */
61 0x03c MODE_NITRO /* tsio_1 */
62 >;
63 };
65 nor_pins: pinmux_pnor_adv_n {
66 pinctrl-single,pins = <
67 0x0ac MODE_PNOR /* nand_ce1_n */
68 0x0b0 MODE_PNOR /* nand_ce0_n */
69 0x0b4 MODE_PNOR /* nand_we_n */
70 0x0b8 MODE_PNOR /* nand_wp_n */
71 0x0bc MODE_PNOR /* nand_re_n */
72 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
73 0x0c4 MODE_PNOR /* nand_io0_0 */
74 0x0c8 MODE_PNOR /* nand_io1_0 */
75 0x0cc MODE_PNOR /* nand_io2_0 */
76 0x0d0 MODE_PNOR /* nand_io3_0 */
77 0x0d4 MODE_PNOR /* nand_io4_0 */
78 0x0d8 MODE_PNOR /* nand_io5_0 */
79 0x0dc MODE_PNOR /* nand_io6_0 */
80 0x0e0 MODE_PNOR /* nand_io7_0 */
81 0x0e4 MODE_PNOR /* nand_io8_0 */
82 0x0e8 MODE_PNOR /* nand_io9_0 */
83 0x0ec MODE_PNOR /* nand_io10_0 */
84 0x0f0 MODE_PNOR /* nand_io11_0 */
85 0x0f4 MODE_PNOR /* nand_io12_0 */
86 0x0f8 MODE_PNOR /* nand_io13_0 */
87 0x0fc MODE_PNOR /* nand_io14_0 */
88 0x100 MODE_PNOR /* nand_io15_0 */
89 0x104 MODE_PNOR /* nand_ale_0 */
90 0x108 MODE_PNOR /* nand_cle_0 */
91 0x040 MODE_PNOR /* pnor_adv_n */
92 0x044 MODE_PNOR /* pnor_baa_n */
93 0x048 MODE_PNOR /* pnor_bls_0_n */
94 0x04c MODE_PNOR /* pnor_bls_1_n */
95 0x050 MODE_PNOR /* pnor_cre */
96 0x054 MODE_PNOR /* pnor_cs_2_n */
97 0x058 MODE_PNOR /* pnor_cs_1_n */
98 0x05c MODE_PNOR /* pnor_cs_0_n */
99 0x060 MODE_PNOR /* pnor_we_n */
100 0x064 MODE_PNOR /* pnor_oe_n */
101 0x068 MODE_PNOR /* pnor_intr */
102 0x06c MODE_PNOR /* pnor_dat_0 */
103 0x070 MODE_PNOR /* pnor_dat_1 */
104 0x074 MODE_PNOR /* pnor_dat_2 */
105 0x078 MODE_PNOR /* pnor_dat_3 */
106 0x07c MODE_PNOR /* pnor_dat_4 */
107 0x080 MODE_PNOR /* pnor_dat_5 */
108 0x084 MODE_PNOR /* pnor_dat_6 */
109 0x088 MODE_PNOR /* pnor_dat_7 */
110 0x08c MODE_PNOR /* pnor_dat_8 */
111 0x090 MODE_PNOR /* pnor_dat_9 */
112 0x094 MODE_PNOR /* pnor_dat_10 */
113 0x098 MODE_PNOR /* pnor_dat_11 */
114 0x09c MODE_PNOR /* pnor_dat_12 */
115 0x0a0 MODE_PNOR /* pnor_dat_13 */
116 0x0a4 MODE_PNOR /* pnor_dat_14 */
117 0x0a8 MODE_PNOR /* pnor_dat_15 */
118 >;
119 };
121 nand_pins: pinmux_nand_ce1_n {
122 pinctrl-single,pins = <
123 0x0ac MODE_NAND /* nand_ce1_n */
124 0x0b0 MODE_NAND /* nand_ce0_n */
125 0x0b4 MODE_NAND /* nand_we_n */
126 0x0b8 MODE_NAND /* nand_wp_n */
127 0x0bc MODE_NAND /* nand_re_n */
128 0x0c0 MODE_NAND /* nand_rdy_bsy_n */
129 0x0c4 MODE_NAND /* nand_io0_0 */
130 0x0c8 MODE_NAND /* nand_io1_0 */
131 0x0cc MODE_NAND /* nand_io2_0 */
132 0x0d0 MODE_NAND /* nand_io3_0 */
133 0x0d4 MODE_NAND /* nand_io4_0 */
134 0x0d8 MODE_NAND /* nand_io5_0 */
135 0x0dc MODE_NAND /* nand_io6_0 */
136 0x0e0 MODE_NAND /* nand_io7_0 */
137 0x0e4 MODE_NAND /* nand_io8_0 */
138 0x0e8 MODE_NAND /* nand_io9_0 */
139 0x0ec MODE_NAND /* nand_io10_0 */
140 0x0f0 MODE_NAND /* nand_io11_0 */
141 0x0f4 MODE_NAND /* nand_io12_0 */
142 0x0f8 MODE_NAND /* nand_io13_0 */
143 0x0fc MODE_NAND /* nand_io14_0 */
144 0x100 MODE_NAND /* nand_io15_0 */
145 0x104 MODE_NAND /* nand_ale_0 */
146 0x108 MODE_NAND /* nand_cle_0 */
147 >;
148 };
150 pwm0_pins: pinmux_pwm_0 {
151 pinctrl-single,pins = <
152 0x10c MODE_NITRO
153 >;
154 };
156 pwm1_pins: pinmux_pwm_1 {
157 pinctrl-single,pins = <
158 0x110 MODE_NITRO
159 >;
160 };
162 pwm2_pins: pinmux_pwm_2 {
163 pinctrl-single,pins = <
164 0x114 MODE_NITRO
165 >;
166 };
168 pwm3_pins: pinmux_pwm_3 {
169 pinctrl-single,pins = <
170 0x118 MODE_NITRO
171 >;
172 };
174 dbu_rxd_pins: pinmux_uart1_sin_nitro {
175 pinctrl-single,pins = <
176 0x11c MODE_NITRO /* dbu_rxd */
177 0x120 MODE_NITRO /* dbu_txd */
178 >;
179 };
181 uart1_pins: pinmux_uart1_sin_nand {
182 pinctrl-single,pins = <
183 0x11c MODE_NAND /* uart1_sin */
184 0x120 MODE_NAND /* uart1_out */
185 >;
186 };
188 uart2_pins: pinmux_uart2_sin {
189 pinctrl-single,pins = <
190 0x124 MODE_NITRO /* uart2_sin */
191 0x128 MODE_NITRO /* uart2_out */
192 >;
193 };
195 uart3_pins: pinmux_uart3_sin {
196 pinctrl-single,pins = <
197 0x12c MODE_NITRO /* uart3_sin */
198 0x130 MODE_NITRO /* uart3_out */
199 >;
200 };
202 i2s_pins: pinmux_i2s_bitclk {
203 pinctrl-single,pins = <
204 0x134 MODE_NITRO /* i2s_bitclk */
205 0x138 MODE_NITRO /* i2s_sdout */
206 0x13c MODE_NITRO /* i2s_sdin */
207 0x140 MODE_NITRO /* i2s_ws */
208 0x144 MODE_NITRO /* i2s_mclk */
209 0x148 MODE_NITRO /* i2s_spdif_out */
210 >;
211 };
213 qspi_pins: pinumx_qspi_hold_n {
214 pinctrl-single,pins = <
215 0x14c MODE_NAND /* qspi_hold_n */
216 0x150 MODE_NAND /* qspi_wp_n */
217 0x154 MODE_NAND /* qspi_sck */
218 0x158 MODE_NAND /* qspi_cs_n */
219 0x15c MODE_NAND /* qspi_mosi */
220 0x160 MODE_NAND /* qspi_miso */
221 >;
222 };
224 mdio_pins: pinumx_ext_mdio {
225 pinctrl-single,pins = <
226 0x164 MODE_NITRO /* ext_mdio */
227 0x168 MODE_NITRO /* ext_mdc */
228 >;
229 };
231 i2c0_pins: pinmux_i2c0_sda {
232 pinctrl-single,pins = <
233 0x16c MODE_NITRO /* i2c0_sda */
234 0x170 MODE_NITRO /* i2c0_scl */
235 >;
236 };
238 i2c1_pins: pinmux_i2c1_sda {
239 pinctrl-single,pins = <
240 0x174 MODE_NITRO /* i2c1_sda */
241 0x178 MODE_NITRO /* i2c1_scl */
242 >;
243 };
245 sdio0_pins: pinmux_sdio0_cd_l {
246 pinctrl-single,pins = <
247 0x17c MODE_NITRO /* sdio0_cd_l */
248 0x180 MODE_NITRO /* sdio0_clk_sdcard */
249 0x184 MODE_NITRO /* sdio0_data0 */
250 0x188 MODE_NITRO /* sdio0_data1 */
251 0x18c MODE_NITRO /* sdio0_data2 */
252 0x190 MODE_NITRO /* sdio0_data3 */
253 0x194 MODE_NITRO /* sdio0_data4 */
254 0x198 MODE_NITRO /* sdio0_data5 */
255 0x19c MODE_NITRO /* sdio0_data6 */
256 0x1a0 MODE_NITRO /* sdio0_data7 */
257 0x1a4 MODE_NITRO /* sdio0_cmd */
258 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
259 0x1ac MODE_NITRO /* sdio0_led_on */
260 0x1b0 MODE_NITRO /* sdio0_wp */
261 >;
262 };
264 sdio1_pins: pinmux_sdio1_cd_l {
265 pinctrl-single,pins = <
266 0x1b4 MODE_NITRO /* sdio1_cd_l */
267 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
268 0x1bc MODE_NITRO /* sdio1_data0 */
269 0x1c0 MODE_NITRO /* sdio1_data1 */
270 0x1c4 MODE_NITRO /* sdio1_data2 */
271 0x1c8 MODE_NITRO /* sdio1_data3 */
272 0x1cc MODE_NITRO /* sdio1_data4 */
273 0x1d0 MODE_NITRO /* sdio1_data5 */
274 0x1d4 MODE_NITRO /* sdio1_data6 */
275 0x1d8 MODE_NITRO /* sdio1_data7 */
276 0x1dc MODE_NITRO /* sdio1_cmd */
277 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
278 0x1e4 MODE_NITRO /* sdio1_led_on */
279 0x1e8 MODE_NITRO /* sdio1_wp */
280 >;
281 };
283 spi0_pins: pinmux_spi0_sck_nand {
284 pinctrl-single,pins = <
285 0x1ec MODE_NITRO /* spi0_sck */
286 0x1f0 MODE_NITRO /* spi0_rxd */
287 0x1f4 MODE_NITRO /* spi0_fss */
288 0x1f8 MODE_NITRO /* spi0_txd */
289 >;
290 };
292 spi1_pins: pinmux_spi1_sck_nand {
293 pinctrl-single,pins = <
294 0x1fc MODE_NITRO /* spi1_sck */
295 0x200 MODE_NITRO /* spi1_rxd */
296 0x204 MODE_NITRO /* spi1_fss */
297 0x208 MODE_NITRO /* spi1_txd */
298 >;
299 };
301 nuart_pins: pinmux_uart0_sin_nitro {
302 pinctrl-single,pins = <
303 0x20c MODE_NITRO /* nuart_rxd */
304 0x210 MODE_NITRO /* nuart_txd */
305 >;
306 };
308 uart0_pins: pinumux_uart0_sin_nand {
309 pinctrl-single,pins = <
310 0x20c MODE_NAND /* uart0_sin */
311 0x210 MODE_NAND /* uart0_out */
312 0x214 MODE_NAND /* uart0_rts */
313 0x218 MODE_NAND /* uart0_cts */
314 0x21c MODE_NAND /* uart0_dtr */
315 0x220 MODE_NAND /* uart0_dcd */
316 0x224 MODE_NAND /* uart0_dsr */
317 0x228 MODE_NAND /* uart0_ri */
318 >;
319 };
321 drdu2_pins: pinmux_drdu2_overcurrent {
322 pinctrl-single,pins = <
323 0x22c MODE_NITRO /* drdu2_overcurrent */
324 0x230 MODE_NITRO /* drdu2_vbus_ppc */
325 0x234 MODE_NITRO /* drdu2_vbus_present */
326 0x238 MODE_NITRO /* drdu2_id */
327 >;
328 };
330 drdu3_pins: pinmux_drdu3_overcurrent {
331 pinctrl-single,pins = <
332 0x23c MODE_NITRO /* drdu3_overcurrent */
333 0x240 MODE_NITRO /* drdu3_vbus_ppc */
334 0x244 MODE_NITRO /* drdu3_vbus_present */
335 0x248 MODE_NITRO /* drdu3_id */
336 >;
337 };
339 usb3h_pins: pinmux_usb3h_overcurrent {
340 pinctrl-single,pins = <
341 0x24c MODE_NITRO /* usb3h_overcurrent */
342 0x250 MODE_NITRO /* usb3h_vbus_ppc */
343 >;
344 };
345 };