arch/arm64/boot/dts/mediatek/mt6797.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Mars.C <mars.cheng@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt6797-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         compatible = "mediatek,mt6797";
  20         interrupt-parent = <&sysirq>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         psci {
  25                 compatible = "arm,psci-0.2";
  26                 method = "smc";
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         enable-method = "psci";
  37                         reg = <0x000>;
  38                 };
  39
  40                 cpu1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53";
  43                         enable-method = "psci";
  44                         reg = <0x001>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         enable-method = "psci";
  51                         reg = <0x002>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a53";
  57                         enable-method = "psci";
  58                         reg = <0x003>;
  59                 };
  60
  61                 cpu4: cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         enable-method = "psci";
  65                         reg = <0x100>;
  66                 };
  67
  68                 cpu5: cpu@101 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53";
  71                         enable-method = "psci";
  72                         reg = <0x101>;
  73                 };
  74
  75                 cpu6: cpu@102 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53";
  78                         enable-method = "psci";
  79                         reg = <0x102>;
  80                 };
  81
  82                 cpu7: cpu@103 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         enable-method = "psci";
  86                         reg = <0x103>;
  87                 };
  88
  89                 cpu8: cpu@200 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a72";
  92                         enable-method = "psci";
  93                         reg = <0x200>;
  94                 };
  95
  96                 cpu9: cpu@201 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a72";
  99                         enable-method = "psci";
 100                         reg = <0x201>;
 101                 };
 102         };
 103
 104         clk26m: oscillator@0 {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <26000000>;
 108                 clock-output-names = "clk26m";
 109         };
 110
 111         clk32k: oscillator@1 {
 112                 compatible = "fixed-clock";
 113                 #clock-cells = <0>;
 114                 clock-frequency = <32000>;
 115                 clock-output-names = "clk32k";
 116         };
 117
 118         timer {
 119                 compatible = "arm,armv8-timer";
 120                 interrupt-parent = <&gic>;
 121                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 122                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 123                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 124                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 125         };
 126
 127         topckgen: topckgen@10000000 {
 128                 compatible = "mediatek,mt6797-topckgen";
 129                 reg = <0 0x10000000 0 0x1000>;
 130                 #clock-cells = <1>;
 131         };
 132
 133         infrasys: infracfg_ao@10001000 {
 134                 compatible = "mediatek,mt6797-infracfg", "syscon";
 135                 reg = <0 0x10001000 0 0x1000>;
 136                 #clock-cells = <1>;
 137         };
 138
 139         scpsys: scpsys@10006000 {
 140                 compatible = "mediatek,mt6797-scpsys";
 141                 #power-domain-cells = <1>;
 142                 reg = <0 0x10006000 0 0x1000>;
 143                 clocks = <&topckgen CLK_TOP_MUX_MFG>,
 144                          <&topckgen CLK_TOP_MUX_MM>,
 145                          <&topckgen CLK_TOP_MUX_VDEC>;
 146                 clock-names = "mfg", "mm", "vdec";
 147                 infracfg = <&infrasys>;
 148         };
 149
 150         apmixedsys: apmixed@1000c000 {
 151                 compatible = "mediatek,mt6797-apmixedsys";
 152                 reg = <0 0x1000c000 0 0x1000>;
 153                 #clock-cells = <1>;
 154         };
 155
 156         sysirq: intpol-controller@10200620 {
 157                 compatible = "mediatek,mt6797-sysirq",
 158                              "mediatek,mt6577-sysirq";
 159                 interrupt-controller;
 160                 #interrupt-cells = <3>;
 161                 interrupt-parent = <&gic>;
 162                 reg = <0 0x10220620 0 0x20>,
 163                       <0 0x10220690 0 0x10>;
 164         };
 165
 166         uart0: serial@11002000 {
 167                 compatible = "mediatek,mt6797-uart",
 168                              "mediatek,mt6577-uart";
 169                 reg = <0 0x11002000 0 0x400>;
 170                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 171                 clocks = <&infrasys CLK_INFRA_UART0>,
 172                          <&infrasys CLK_INFRA_AP_DMA>;
 173                 clock-names = "baud", "bus";
 174                 status = "disabled";
 175         };
 176
 177         uart1: serial@11003000 {
 178                 compatible = "mediatek,mt6797-uart",
 179                              "mediatek,mt6577-uart";
 180                 reg = <0 0x11003000 0 0x400>;
 181                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 182                 clocks = <&infrasys CLK_INFRA_UART1>,
 183                          <&infrasys CLK_INFRA_AP_DMA>;
 184                 clock-names = "baud", "bus";
 185                 status = "disabled";
 186         };
 187
 188         uart2: serial@11004000 {
 189                 compatible = "mediatek,mt6797-uart",
 190                              "mediatek,mt6577-uart";
 191                 reg = <0 0x11004000 0 0x400>;
 192                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 193                 clocks = <&infrasys CLK_INFRA_UART2>,
 194                          <&infrasys CLK_INFRA_AP_DMA>;
 195                 clock-names = "baud", "bus";
 196                 status = "disabled";
 197         };
 198
 199         uart3: serial@11005000 {
 200                 compatible = "mediatek,mt6797-uart",
 201                              "mediatek,mt6577-uart";
 202                 reg = <0 0x11005000 0 0x400>;
 203                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 204                 clocks = <&infrasys CLK_INFRA_UART3>,
 205                          <&infrasys CLK_INFRA_AP_DMA>;
 206                 clock-names = "baud", "bus";
 207                 status = "disabled";
 208         };
 209
 210         mmsys: mmsys_config@14000000 {
 211                 compatible = "mediatek,mt6797-mmsys", "syscon";
 212                 reg = <0 0x14000000 0 0x1000>;
 213                 #clock-cells = <1>;
 214         };
 215
 216         imgsys: imgsys_config@15000000  {
 217                 compatible = "mediatek,mt6797-imgsys", "syscon";
 218                 reg = <0 0x15000000 0 0x1000>;
 219                 #clock-cells = <1>;
 220         };
 221
 222         vdecsys: vdec_gcon@16000000 {
 223                 compatible = "mediatek,mt6797-vdecsys", "syscon";
 224                 reg = <0 0x16000000 0 0x10000>;
 225                 #clock-cells = <1>;
 226         };
 227
 228         vencsys: venc_gcon@17000000 {
 229                 compatible = "mediatek,mt6797-vencsys", "syscon";
 230                 reg = <0 0x17000000 0 0x1000>;
 231                 #clock-cells = <1>;
 232         };
 233
 234         gic: interrupt-controller@19000000 {
 235                 compatible = "arm,gic-v3";
 236                 #interrupt-cells = <3>;
 237                 interrupt-parent = <&gic>;
 238                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 239                 interrupt-controller;
 240                 reg = <0 0x19000000 0 0x10000>,    /* GICD */
 241                       <0 0x19200000 0 0x200000>,   /* GICR */
 242                       <0 0x10240000 0 0x2000>;     /* GICC */
 243         };
 244 };