2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
23 #include <asm/asmmacro.h>
25 #include <asm/kregs.h>
26 #include <asm/mmu_context.h>
27 #include <asm/asm-offsets.h>
29 #include <asm/pgtable.h>
30 #include <asm/processor.h>
31 #include <asm/ptrace.h>
32 #include <asm/mca_asm.h>
33 #include <linux/init.h>
34 #include <linux/linkage.h>
35 #include <asm/export.h>
37 #ifdef CONFIG_HOTPLUG_CPU
38 #define SAL_PSR_BITS_TO_SET \
39 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
41 #define SAVE_FROM_REG(src, ptr, dest) \
45 #define RESTORE_REG(reg, ptr, _tmp) \
46 ld8 _tmp=[ptr],0x08;; \
49 #define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
50 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
53 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
57 #define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
58 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
60 _lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
62 br.cloop.sptk.many _lbl
64 #define SAVE_ONE_RR(num, _reg, _tmp) \
65 movl _tmp=(num<<61);; \
68 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
69 SAVE_ONE_RR(0,_r0, _tmp);; \
70 SAVE_ONE_RR(1,_r1, _tmp);; \
71 SAVE_ONE_RR(2,_r2, _tmp);; \
72 SAVE_ONE_RR(3,_r3, _tmp);; \
73 SAVE_ONE_RR(4,_r4, _tmp);; \
74 SAVE_ONE_RR(5,_r5, _tmp);; \
75 SAVE_ONE_RR(6,_r6, _tmp);; \
76 SAVE_ONE_RR(7,_r7, _tmp);;
78 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
88 #define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
92 dep.z _idx2=_idx1,61,3;; \
94 mov rr[_idx2]=_tmp;; \
97 br.cloop.sptk.few RestRR
99 #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
100 movl reg1=sal_state_for_booting_cpu;; \
104 * Adjust region registers saved before starting to save
105 * break regs and rest of the states that need to be preserved.
107 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
108 SAVE_FROM_REG(b0,_reg1,_reg2);; \
109 SAVE_FROM_REG(b1,_reg1,_reg2);; \
110 SAVE_FROM_REG(b2,_reg1,_reg2);; \
111 SAVE_FROM_REG(b3,_reg1,_reg2);; \
112 SAVE_FROM_REG(b4,_reg1,_reg2);; \
113 SAVE_FROM_REG(b5,_reg1,_reg2);; \
114 st8 [_reg1]=r1,0x08;; \
115 st8 [_reg1]=r12,0x08;; \
116 st8 [_reg1]=r13,0x08;; \
117 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
118 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
119 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
120 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
121 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
122 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
123 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
128 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
129 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
130 st8 [_reg1]=r4,0x08;; \
131 st8 [_reg1]=r5,0x08;; \
132 st8 [_reg1]=r6,0x08;; \
133 st8 [_reg1]=r7,0x08;; \
134 st8 [_reg1]=_pred,0x08;; \
135 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
136 stf.spill.nta [_reg1]=f2,16;; \
137 stf.spill.nta [_reg1]=f3,16;; \
138 stf.spill.nta [_reg1]=f4,16;; \
139 stf.spill.nta [_reg1]=f5,16;; \
140 stf.spill.nta [_reg1]=f16,16;; \
141 stf.spill.nta [_reg1]=f17,16;; \
142 stf.spill.nta [_reg1]=f18,16;; \
143 stf.spill.nta [_reg1]=f19,16;; \
144 stf.spill.nta [_reg1]=f20,16;; \
145 stf.spill.nta [_reg1]=f21,16;; \
146 stf.spill.nta [_reg1]=f22,16;; \
147 stf.spill.nta [_reg1]=f23,16;; \
148 stf.spill.nta [_reg1]=f24,16;; \
149 stf.spill.nta [_reg1]=f25,16;; \
150 stf.spill.nta [_reg1]=f26,16;; \
151 stf.spill.nta [_reg1]=f27,16;; \
152 stf.spill.nta [_reg1]=f28,16;; \
153 stf.spill.nta [_reg1]=f29,16;; \
154 stf.spill.nta [_reg1]=f30,16;; \
155 stf.spill.nta [_reg1]=f31,16;;
158 #define SET_AREA_FOR_BOOTING_CPU(a1, a2)
159 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
160 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
161 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
164 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
165 movl _tmp1=(num << 61);; \
166 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
171 .global empty_zero_page
172 EXPORT_DATA_SYMBOL_GPL(empty_zero_page)
176 .global swapper_pg_dir
182 stringz "Halting kernel\n"
189 * Start the kernel. When the bootloader passes control to _start(), r28
190 * points to the address of the boot parameter area. Execution reaches
191 * here in physical mode.
196 .save rp, r0 // terminate unwind chain with a NULL rp
204 flushrs // must be first insn in group
209 * Save the region registers, predicate before they get clobbered
211 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
215 * Initialize kernel region registers:
216 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
217 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
218 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
219 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
220 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
221 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
222 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
223 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
224 * We initialize all of them to prevent inadvertently assuming
225 * something about the state of address translation early in boot.
227 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
228 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
229 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
230 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
231 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
232 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
233 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
234 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
236 * Now pin mappings into the TLB for kernel text and data
238 mov r18=KERNEL_TR_PAGE_SHIFT<<2
239 movl r17=KERNEL_START
243 mov r16=IA64_TR_KERNEL
247 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
260 * Switch into virtual mode:
262 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
273 1: // now we are in virtual mode
275 SET_AREA_FOR_BOOTING_CPU(r2, r16);
277 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
278 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
281 // set IVT entry point---can't access I/O ports without it
293 #define isAP p2 // are we an Application Processor?
294 #define isBP p3 // are we the Bootstrap Processor?
298 * Find the init_task for the currently booting CPU. At poweron, and in
299 * UP mode, task_for_booting_cpu is NULL.
301 movl r3=task_for_booting_cpu
306 cmp.eq isBP,isAP=r3,r0
311 cmp.eq isBP,isAP=r0,r0
314 tpa r3=r2 // r3 == phys addr of task struct
316 (isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
318 // load mapping for stack (virtaddr in r2, physaddr in r3)
326 dep r2=-1,r3,61,3 // IMVA of task
329 shr.u r16=r3,IA64_GRANULE_SHIFT
336 mov r19=IA64_TR_CURRENT_STACK
345 // load the "current" pointer (r13) and ar.k6 with the current task
346 mov IA64_KR(CURRENT)=r2 // virtual address
347 mov IA64_KR(CURRENT_STACK)=r16
350 * Reserve space at the top of the stack for "struct pt_regs". Kernel
351 * threads don't store interesting values in that structure, but the space
352 * still needs to be there because time-critical stuff such as the context
353 * switching can be implemented more efficiently (for example, __switch_to()
354 * always sets the psr.dfh bit of the task it is switching to).
357 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
358 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
359 mov ar.rsc=0 // place RSE in enforced lazy mode
361 loadrs // clear the dirty partition
362 movl r19=__phys_per_cpu_start
363 mov r18=PERCPU_PAGE_SIZE
370 movl r20=__cpu0_per_cpu
378 (p7) br.cond.dptk.few 1b
385 .pred.rel.mutex isBP,isAP
386 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
387 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
389 mov ar.bspstore=r2 // establish the new RSE stack
391 mov ar.rsc=0x3 // place RSE in eager mode
393 (isBP) dep r28=-1,r28,61,3 // make address virtual
394 (isBP) movl r2=ia64_boot_param
396 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
399 (isAP) br.call.sptk.many rp=start_secondary
401 (isAP) br.cond.sptk self
404 // This is executed by the bootstrap processor (bsp) only:
406 #ifdef CONFIG_IA64_FW_EMU
407 // initialize PAL & SAL emulator:
408 br.call.sptk.many rp=sys_fw_init
411 br.call.sptk.many rp=start_kernel
412 .ret2: addl r3=@ltoff(halt_msg),gp
414 alloc r2=ar.pfs,8,0,2,0
417 br.call.sptk.many b0=console_print
420 br.sptk.many self // endless loop
425 GLOBAL_ENTRY(ia64_save_debug_regs)
426 alloc r16=ar.pfs,1,0,0,0
427 mov r20=ar.lc // preserve ar.lc
428 mov ar.lc=IA64_NUM_DBG_REGS-1
430 add r19=IA64_NUM_DBG_REGS*8,in0
433 #ifdef CONFIG_ITANIUM
442 br.cloop.sptk.many 1b
444 mov ar.lc=r20 // restore ar.lc
446 END(ia64_save_debug_regs)
448 GLOBAL_ENTRY(ia64_load_debug_regs)
449 alloc r16=ar.pfs,1,0,0,0
451 mov r20=ar.lc // preserve ar.lc
452 add r19=IA64_NUM_DBG_REGS*8,in0
453 mov ar.lc=IA64_NUM_DBG_REGS-1
456 1: ld8.nta r16=[in0],8
461 #ifdef CONFIG_ITANIUM
463 srlz.d // Errata 132 (NoFix status)
466 br.cloop.sptk.many 1b
468 mov ar.lc=r20 // restore ar.lc
470 END(ia64_load_debug_regs)
472 GLOBAL_ENTRY(__ia64_save_fpu)
473 alloc r2=ar.pfs,1,4,0,0
474 adds loc0=96*16-16,in0
475 adds loc1=96*16-16-128,in0
477 stf.spill.nta [loc0]=f127,-256
478 stf.spill.nta [loc1]=f119,-256
480 stf.spill.nta [loc0]=f111,-256
481 stf.spill.nta [loc1]=f103,-256
483 stf.spill.nta [loc0]=f95,-256
484 stf.spill.nta [loc1]=f87,-256
486 stf.spill.nta [loc0]=f79,-256
487 stf.spill.nta [loc1]=f71,-256
489 stf.spill.nta [loc0]=f63,-256
490 stf.spill.nta [loc1]=f55,-256
491 adds loc2=96*16-32,in0
493 stf.spill.nta [loc0]=f47,-256
494 stf.spill.nta [loc1]=f39,-256
495 adds loc3=96*16-32-128,in0
497 stf.spill.nta [loc2]=f126,-256
498 stf.spill.nta [loc3]=f118,-256
500 stf.spill.nta [loc2]=f110,-256
501 stf.spill.nta [loc3]=f102,-256
503 stf.spill.nta [loc2]=f94,-256
504 stf.spill.nta [loc3]=f86,-256
506 stf.spill.nta [loc2]=f78,-256
507 stf.spill.nta [loc3]=f70,-256
509 stf.spill.nta [loc2]=f62,-256
510 stf.spill.nta [loc3]=f54,-256
511 adds loc0=96*16-48,in0
513 stf.spill.nta [loc2]=f46,-256
514 stf.spill.nta [loc3]=f38,-256
515 adds loc1=96*16-48-128,in0
517 stf.spill.nta [loc0]=f125,-256
518 stf.spill.nta [loc1]=f117,-256
520 stf.spill.nta [loc0]=f109,-256
521 stf.spill.nta [loc1]=f101,-256
523 stf.spill.nta [loc0]=f93,-256
524 stf.spill.nta [loc1]=f85,-256
526 stf.spill.nta [loc0]=f77,-256
527 stf.spill.nta [loc1]=f69,-256
529 stf.spill.nta [loc0]=f61,-256
530 stf.spill.nta [loc1]=f53,-256
531 adds loc2=96*16-64,in0
533 stf.spill.nta [loc0]=f45,-256
534 stf.spill.nta [loc1]=f37,-256
535 adds loc3=96*16-64-128,in0
537 stf.spill.nta [loc2]=f124,-256
538 stf.spill.nta [loc3]=f116,-256
540 stf.spill.nta [loc2]=f108,-256
541 stf.spill.nta [loc3]=f100,-256
543 stf.spill.nta [loc2]=f92,-256
544 stf.spill.nta [loc3]=f84,-256
546 stf.spill.nta [loc2]=f76,-256
547 stf.spill.nta [loc3]=f68,-256
549 stf.spill.nta [loc2]=f60,-256
550 stf.spill.nta [loc3]=f52,-256
551 adds loc0=96*16-80,in0
553 stf.spill.nta [loc2]=f44,-256
554 stf.spill.nta [loc3]=f36,-256
555 adds loc1=96*16-80-128,in0
557 stf.spill.nta [loc0]=f123,-256
558 stf.spill.nta [loc1]=f115,-256
560 stf.spill.nta [loc0]=f107,-256
561 stf.spill.nta [loc1]=f99,-256
563 stf.spill.nta [loc0]=f91,-256
564 stf.spill.nta [loc1]=f83,-256
566 stf.spill.nta [loc0]=f75,-256
567 stf.spill.nta [loc1]=f67,-256
569 stf.spill.nta [loc0]=f59,-256
570 stf.spill.nta [loc1]=f51,-256
571 adds loc2=96*16-96,in0
573 stf.spill.nta [loc0]=f43,-256
574 stf.spill.nta [loc1]=f35,-256
575 adds loc3=96*16-96-128,in0
577 stf.spill.nta [loc2]=f122,-256
578 stf.spill.nta [loc3]=f114,-256
580 stf.spill.nta [loc2]=f106,-256
581 stf.spill.nta [loc3]=f98,-256
583 stf.spill.nta [loc2]=f90,-256
584 stf.spill.nta [loc3]=f82,-256
586 stf.spill.nta [loc2]=f74,-256
587 stf.spill.nta [loc3]=f66,-256
589 stf.spill.nta [loc2]=f58,-256
590 stf.spill.nta [loc3]=f50,-256
591 adds loc0=96*16-112,in0
593 stf.spill.nta [loc2]=f42,-256
594 stf.spill.nta [loc3]=f34,-256
595 adds loc1=96*16-112-128,in0
597 stf.spill.nta [loc0]=f121,-256
598 stf.spill.nta [loc1]=f113,-256
600 stf.spill.nta [loc0]=f105,-256
601 stf.spill.nta [loc1]=f97,-256
603 stf.spill.nta [loc0]=f89,-256
604 stf.spill.nta [loc1]=f81,-256
606 stf.spill.nta [loc0]=f73,-256
607 stf.spill.nta [loc1]=f65,-256
609 stf.spill.nta [loc0]=f57,-256
610 stf.spill.nta [loc1]=f49,-256
611 adds loc2=96*16-128,in0
613 stf.spill.nta [loc0]=f41,-256
614 stf.spill.nta [loc1]=f33,-256
615 adds loc3=96*16-128-128,in0
617 stf.spill.nta [loc2]=f120,-256
618 stf.spill.nta [loc3]=f112,-256
620 stf.spill.nta [loc2]=f104,-256
621 stf.spill.nta [loc3]=f96,-256
623 stf.spill.nta [loc2]=f88,-256
624 stf.spill.nta [loc3]=f80,-256
626 stf.spill.nta [loc2]=f72,-256
627 stf.spill.nta [loc3]=f64,-256
629 stf.spill.nta [loc2]=f56,-256
630 stf.spill.nta [loc3]=f48,-256
632 stf.spill.nta [loc2]=f40
633 stf.spill.nta [loc3]=f32
637 GLOBAL_ENTRY(__ia64_load_fpu)
638 alloc r2=ar.pfs,1,2,0,0
645 ldf.fill.nta f32=[in0],loc0
646 ldf.fill.nta f40=[ r3],loc0
647 ldf.fill.nta f48=[r14],loc0
648 ldf.fill.nta f56=[r15],loc0
650 ldf.fill.nta f64=[in0],loc0
651 ldf.fill.nta f72=[ r3],loc0
652 ldf.fill.nta f80=[r14],loc0
653 ldf.fill.nta f88=[r15],loc0
655 ldf.fill.nta f96=[in0],loc1
656 ldf.fill.nta f104=[ r3],loc1
657 ldf.fill.nta f112=[r14],loc1
658 ldf.fill.nta f120=[r15],loc1
660 ldf.fill.nta f33=[in0],loc0
661 ldf.fill.nta f41=[ r3],loc0
662 ldf.fill.nta f49=[r14],loc0
663 ldf.fill.nta f57=[r15],loc0
665 ldf.fill.nta f65=[in0],loc0
666 ldf.fill.nta f73=[ r3],loc0
667 ldf.fill.nta f81=[r14],loc0
668 ldf.fill.nta f89=[r15],loc0
670 ldf.fill.nta f97=[in0],loc1
671 ldf.fill.nta f105=[ r3],loc1
672 ldf.fill.nta f113=[r14],loc1
673 ldf.fill.nta f121=[r15],loc1
675 ldf.fill.nta f34=[in0],loc0
676 ldf.fill.nta f42=[ r3],loc0
677 ldf.fill.nta f50=[r14],loc0
678 ldf.fill.nta f58=[r15],loc0
680 ldf.fill.nta f66=[in0],loc0
681 ldf.fill.nta f74=[ r3],loc0
682 ldf.fill.nta f82=[r14],loc0
683 ldf.fill.nta f90=[r15],loc0
685 ldf.fill.nta f98=[in0],loc1
686 ldf.fill.nta f106=[ r3],loc1
687 ldf.fill.nta f114=[r14],loc1
688 ldf.fill.nta f122=[r15],loc1
690 ldf.fill.nta f35=[in0],loc0
691 ldf.fill.nta f43=[ r3],loc0
692 ldf.fill.nta f51=[r14],loc0
693 ldf.fill.nta f59=[r15],loc0
695 ldf.fill.nta f67=[in0],loc0
696 ldf.fill.nta f75=[ r3],loc0
697 ldf.fill.nta f83=[r14],loc0
698 ldf.fill.nta f91=[r15],loc0
700 ldf.fill.nta f99=[in0],loc1
701 ldf.fill.nta f107=[ r3],loc1
702 ldf.fill.nta f115=[r14],loc1
703 ldf.fill.nta f123=[r15],loc1
705 ldf.fill.nta f36=[in0],loc0
706 ldf.fill.nta f44=[ r3],loc0
707 ldf.fill.nta f52=[r14],loc0
708 ldf.fill.nta f60=[r15],loc0
710 ldf.fill.nta f68=[in0],loc0
711 ldf.fill.nta f76=[ r3],loc0
712 ldf.fill.nta f84=[r14],loc0
713 ldf.fill.nta f92=[r15],loc0
715 ldf.fill.nta f100=[in0],loc1
716 ldf.fill.nta f108=[ r3],loc1
717 ldf.fill.nta f116=[r14],loc1
718 ldf.fill.nta f124=[r15],loc1
720 ldf.fill.nta f37=[in0],loc0
721 ldf.fill.nta f45=[ r3],loc0
722 ldf.fill.nta f53=[r14],loc0
723 ldf.fill.nta f61=[r15],loc0
725 ldf.fill.nta f69=[in0],loc0
726 ldf.fill.nta f77=[ r3],loc0
727 ldf.fill.nta f85=[r14],loc0
728 ldf.fill.nta f93=[r15],loc0
730 ldf.fill.nta f101=[in0],loc1
731 ldf.fill.nta f109=[ r3],loc1
732 ldf.fill.nta f117=[r14],loc1
733 ldf.fill.nta f125=[r15],loc1
735 ldf.fill.nta f38 =[in0],loc0
736 ldf.fill.nta f46 =[ r3],loc0
737 ldf.fill.nta f54 =[r14],loc0
738 ldf.fill.nta f62 =[r15],loc0
740 ldf.fill.nta f70 =[in0],loc0
741 ldf.fill.nta f78 =[ r3],loc0
742 ldf.fill.nta f86 =[r14],loc0
743 ldf.fill.nta f94 =[r15],loc0
745 ldf.fill.nta f102=[in0],loc1
746 ldf.fill.nta f110=[ r3],loc1
747 ldf.fill.nta f118=[r14],loc1
748 ldf.fill.nta f126=[r15],loc1
750 ldf.fill.nta f39 =[in0],loc0
751 ldf.fill.nta f47 =[ r3],loc0
752 ldf.fill.nta f55 =[r14],loc0
753 ldf.fill.nta f63 =[r15],loc0
755 ldf.fill.nta f71 =[in0],loc0
756 ldf.fill.nta f79 =[ r3],loc0
757 ldf.fill.nta f87 =[r14],loc0
758 ldf.fill.nta f95 =[r15],loc0
760 ldf.fill.nta f103=[in0]
761 ldf.fill.nta f111=[ r3]
762 ldf.fill.nta f119=[r14]
763 ldf.fill.nta f127=[r15]
767 GLOBAL_ENTRY(__ia64_init_fpu)
768 stf.spill [sp]=f0 // M3
772 ldfps f33,f34=[sp] // M0
773 ldfps f35,f36=[sp] // M1
781 ldfps f41,f42=[sp] // M0
782 ldfps f43,f44=[sp] // M1
789 ldfps f49,f50=[sp] // M0
790 ldfps f51,f52=[sp] // M1
797 ldfps f57,f58=[sp] // M0
798 ldfps f59,f60=[sp] // M1
805 ldfps f65,f66=[sp] // M0
806 ldfps f67,f68=[sp] // M1
813 ldfps f73,f74=[sp] // M0
814 ldfps f75,f76=[sp] // M1
821 ldfps f81,f82=[sp] // M0
822 ldfps f83,f84=[sp] // M1
830 * When the instructions are cached, it would be faster to initialize
831 * the remaining registers with simply mov instructions (F-unit).
832 * This gets the time down to ~29 cycles. However, this would use up
833 * 33 bundles, whereas continuing with the above pattern yields
834 * 10 bundles and ~30 cycles.
837 ldfps f89,f90=[sp] // M0
838 ldfps f91,f92=[sp] // M1
845 ldfps f97,f98=[sp] // M0
846 ldfps f99,f100=[sp] // M1
853 ldfps f105,f106=[sp] // M0
854 ldfps f107,f108=[sp] // M1
861 ldfps f113,f114=[sp] // M0
862 ldfps f115,f116=[sp] // M1
869 ldfps f121,f122=[sp] // M0
870 ldfps f123,f124=[sp] // M1
875 br.ret.sptk.many rp // F
879 * Switch execution mode from virtual to physical
882 * r16 = new psr to establish
884 * r19 = old virtual address of ar.bsp
885 * r20 = old virtual address of sp
887 * Note: RSE must already be in enforced lazy mode
889 GLOBAL_ENTRY(ia64_switch_mode_phys)
891 rsm psr.i | psr.ic // disable interrupts and interrupt collection
896 flushrs // must be first insn in group
900 mov cr.ipsr=r16 // set new PSR
901 add r3=1f-ia64_switch_mode_phys,r15
905 mov r14=rp // get return address into a general register
908 // going to physical mode, use tpa to translate virt->phys
915 mov r18=ar.rnat // save ar.rnat
916 mov ar.bspstore=r17 // this steps on ar.rnat
920 mov ar.rnat=r18 // restore ar.rnat
921 rfi // must be last insn in group
925 END(ia64_switch_mode_phys)
928 * Switch execution mode from physical to virtual
931 * r16 = new psr to establish
932 * r19 = new bspstore to establish
933 * r20 = new sp to establish
935 * Note: RSE must already be in enforced lazy mode
937 GLOBAL_ENTRY(ia64_switch_mode_virt)
939 rsm psr.i | psr.ic // disable interrupts and interrupt collection
944 flushrs // must be first insn in group
948 mov cr.ipsr=r16 // set new PSR
949 add r3=1f-ia64_switch_mode_virt,r15
951 mov r14=rp // get return address into a general register
955 // - for code addresses, set upper bits of addr to KERNEL_START
956 // - for stack addresses, copy from input argument
957 movl r18=KERNEL_START
958 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
959 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
966 mov r18=ar.rnat // save ar.rnat
967 mov ar.bspstore=r19 // this steps on ar.rnat
971 mov ar.rnat=r18 // restore ar.rnat
972 rfi // must be last insn in group
976 END(ia64_switch_mode_virt)
978 GLOBAL_ENTRY(ia64_delay_loop)
980 { nop 0 // work around GAS unwind info generation bug...
988 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
989 // inside function body without corrupting unwind info).
991 1: br.cloop.sptk.few 1b
998 * Return a CPU-local timestamp in nano-seconds. This timestamp is
999 * NOT synchronized across CPUs its return value must never be
1000 * compared against the values returned on another CPU. The usage in
1001 * kernel/sched/core.c ensures that.
1003 * The return-value of sched_clock() is NOT supposed to wrap-around.
1004 * If it did, it would cause some scheduling hiccups (at the worst).
1005 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1006 * that would happen only once every 5+ years.
1008 * The code below basically calculates:
1010 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1012 * except that the multiplication and the shift are done with 128-bit
1013 * intermediate precision so that we can produce a full 64-bit result.
1015 GLOBAL_ENTRY(ia64_native_sched_clock)
1016 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1017 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1021 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
1023 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1024 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1026 getf.sig r8=f10 // (5 cyc)
1029 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1031 END(ia64_native_sched_clock)
1033 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
1034 GLOBAL_ENTRY(cycle_to_nsec)
1035 alloc r16=ar.pfs,1,0,0,0
1036 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1042 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1043 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1045 getf.sig r8=f10 // (5 cyc)
1048 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1051 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
1053 #ifdef CONFIG_IA64_BRL_EMU
1056 * Assembly routines used by brl_emu.c to set preserved register state.
1059 #define SET_REG(reg) \
1060 GLOBAL_ENTRY(ia64_set_##reg); \
1061 alloc r16=ar.pfs,1,0,0,0; \
1064 br.ret.sptk.many rp; \
1073 #endif /* CONFIG_IA64_BRL_EMU */
1077 #ifdef CONFIG_HOTPLUG_CPU
1078 GLOBAL_ENTRY(ia64_jump_to_sal)
1079 alloc r16=ar.pfs,1,0,0,0;;
1086 movl r18=tlb_purge_done;;
1087 DATA_VA_TO_PA(r18);;
1088 mov b1=r18 // Return location
1089 movl r18=ia64_do_tlb_purge;;
1090 DATA_VA_TO_PA(r18);;
1091 mov b2=r18 // doing tlb_flush work
1092 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1094 DATA_VA_TO_PA(r17);;
1096 movl r16=SAL_PSR_BITS_TO_SET;;
1099 rfi;; // note: this unmask MCA/INIT (psr.mc)
1102 * Invalidate all TLB data/inst
1104 br.sptk.many b2;; // jump to tlb purge code
1107 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1108 RESTORE_REG(b0, r25, r17);;
1109 RESTORE_REG(b1, r25, r17);;
1110 RESTORE_REG(b2, r25, r17);;
1111 RESTORE_REG(b3, r25, r17);;
1112 RESTORE_REG(b4, r25, r17);;
1113 RESTORE_REG(b5, r25, r17);;
1115 ld8 r12=[r25],0x08;;
1116 ld8 r13=[r25],0x08;;
1117 RESTORE_REG(ar.fpsr, r25, r17);;
1118 RESTORE_REG(ar.pfs, r25, r17);;
1119 RESTORE_REG(ar.rnat, r25, r17);;
1120 RESTORE_REG(ar.unat, r25, r17);;
1121 RESTORE_REG(ar.bspstore, r25, r17);;
1122 RESTORE_REG(cr.dcr, r25, r17);;
1123 RESTORE_REG(cr.iva, r25, r17);;
1124 RESTORE_REG(cr.pta, r25, r17);;
1125 srlz.d;; // required not to violate RAW dependency
1126 RESTORE_REG(cr.itv, r25, r17);;
1127 RESTORE_REG(cr.pmv, r25, r17);;
1128 RESTORE_REG(cr.cmcv, r25, r17);;
1129 RESTORE_REG(cr.lrr0, r25, r17);;
1130 RESTORE_REG(cr.lrr1, r25, r17);;
1135 ld8 r17=[r25],0x08;;
1137 RESTORE_REG(ar.lc, r25, r17);;
1139 * Now Restore floating point regs
1141 ldf.fill.nta f2=[r25],16;;
1142 ldf.fill.nta f3=[r25],16;;
1143 ldf.fill.nta f4=[r25],16;;
1144 ldf.fill.nta f5=[r25],16;;
1145 ldf.fill.nta f16=[r25],16;;
1146 ldf.fill.nta f17=[r25],16;;
1147 ldf.fill.nta f18=[r25],16;;
1148 ldf.fill.nta f19=[r25],16;;
1149 ldf.fill.nta f20=[r25],16;;
1150 ldf.fill.nta f21=[r25],16;;
1151 ldf.fill.nta f22=[r25],16;;
1152 ldf.fill.nta f23=[r25],16;;
1153 ldf.fill.nta f24=[r25],16;;
1154 ldf.fill.nta f25=[r25],16;;
1155 ldf.fill.nta f26=[r25],16;;
1156 ldf.fill.nta f27=[r25],16;;
1157 ldf.fill.nta f28=[r25],16;;
1158 ldf.fill.nta f29=[r25],16;;
1159 ldf.fill.nta f30=[r25],16;;
1160 ldf.fill.nta f31=[r25],16;;
1163 * Now that we have done all the register restores
1164 * we are now ready for the big DIVE to SAL Land
1168 br.ret.sptk.many b0;;
1169 END(ia64_jump_to_sal)
1170 #endif /* CONFIG_HOTPLUG_CPU */
1172 #endif /* CONFIG_SMP */