arch/m68k/coldfire/m527x.c

   1 /***************************************************************************/
   2
   3 /*
   4  *      m527x.c  -- platform support for ColdFire 527x based boards
   5  *
   6  *      Sub-architcture dependent initialization code for the Freescale
   7  *      5270/5271 and 5274/5275 CPUs.
   8  *
   9  *      Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
  10  *      Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
  11  */
  12
  13 /***************************************************************************/
  14
  15 #include <linux/kernel.h>
  16 #include <linux/param.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <asm/machdep.h>
  20 #include <asm/coldfire.h>
  21 #include <asm/mcfsim.h>
  22 #include <asm/mcfuart.h>
  23 #include <asm/mcfclk.h>
  24
  25 /***************************************************************************/
  26
  27 DEFINE_CLK(pll, "pll.0", MCF_CLK);
  28 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  29 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
  30 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
  31 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
  32 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
  33 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  34 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  35 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
  36 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
  37 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
  38 DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
  39 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
  40
  41 struct clk *mcf_clks[] = {
  42         &clk_pll,
  43         &clk_sys,
  44         &clk_mcfpit0,
  45         &clk_mcfpit1,
  46         &clk_mcfpit2,
  47         &clk_mcfpit3,
  48         &clk_mcfuart0,
  49         &clk_mcfuart1,
  50         &clk_mcfuart2,
  51         &clk_mcfqspi0,
  52         &clk_fec0,
  53         &clk_fec1,
  54         &clk_mcfi2c0,
  55         NULL
  56 };
  57
  58 /***************************************************************************/
  59
  60 static void __init m527x_qspi_init(void)
  61 {
  62 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  63 #if defined(CONFIG_M5271)
  64         u16 par;
  65
  66         /* setup QSPS pins for QSPI with gpio CS control */
  67         writeb(0x1f, MCFGPIO_PAR_QSPI);
  68         /* and CS2 & CS3 as gpio */
  69         par = readw(MCFGPIO_PAR_TIMER);
  70         par &= 0x3f3f;
  71         writew(par, MCFGPIO_PAR_TIMER);
  72 #elif defined(CONFIG_M5275)
  73         /* setup QSPS pins for QSPI with gpio CS control */
  74         writew(0x003e, MCFGPIO_PAR_QSPI);
  75 #endif
  76 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  77 }
  78
  79 /***************************************************************************/
  80
  81 static void __init m527x_i2c_init(void)
  82 {
  83 #if IS_ENABLED(CONFIG_I2C_IMX)
  84 #if defined(CONFIG_M5271)
  85         u8 par;
  86
  87         /* setup Port FECI2C Pin Assignment Register for I2C */
  88         /*  set PAR_SCL to SCL and PAR_SDA to SDA */
  89         par = readb(MCFGPIO_PAR_FECI2C);
  90         par |= 0x0f;
  91         writeb(par, MCFGPIO_PAR_FECI2C);
  92 #elif defined(CONFIG_M5275)
  93         u16 par;
  94
  95         /* setup Port FECI2C Pin Assignment Register for I2C */
  96         /*  set PAR_SCL to SCL and PAR_SDA to SDA */
  97         par = readw(MCFGPIO_PAR_FECI2C);
  98         par |= 0x0f;
  99         writew(par, MCFGPIO_PAR_FECI2C);
 100 #endif
 101 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
 102 }
 103
 104 /***************************************************************************/
 105
 106 static void __init m527x_uarts_init(void)
 107 {
 108         u16 sepmask;
 109
 110         /*
 111          * External Pin Mask Setting & Enable External Pin for Interface
 112          */
 113         sepmask = readw(MCFGPIO_PAR_UART);
 114         sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
 115         writew(sepmask, MCFGPIO_PAR_UART);
 116 }
 117
 118 /***************************************************************************/
 119
 120 static void __init m527x_fec_init(void)
 121 {
 122         u8 v;
 123
 124         /* Set multi-function pins to ethernet mode for fec0 */
 125 #if defined(CONFIG_M5271)
 126         v = readb(MCFGPIO_PAR_FECI2C);
 127         writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
 128 #else
 129         u16 par;
 130
 131         par = readw(MCFGPIO_PAR_FECI2C);
 132         writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
 133         v = readb(MCFGPIO_PAR_FEC0HL);
 134         writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
 135
 136         /* Set multi-function pins to ethernet mode for fec1 */
 137         par = readw(MCFGPIO_PAR_FECI2C);
 138         writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
 139         v = readb(MCFGPIO_PAR_FEC1HL);
 140         writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
 141 #endif
 142 }
 143
 144 /***************************************************************************/
 145
 146 void __init config_BSP(char *commandp, int size)
 147 {
 148         mach_sched_init = hw_timer_init;
 149         m527x_uarts_init();
 150         m527x_fec_init();
 151         m527x_qspi_init();
 152         m527x_i2c_init();
 153 }
 154
 155 /***************************************************************************/