| blob | 291454c75ddad117d1d4345d992116bff7cd3cfb |
1 /*
2 * P1021 MDS Device Tree Source
3 *
4 * Copyright 2010,2012 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /include/ "p1021si-pre.dtsi"
13 / {
14 model = "fsl,P1021";
15 compatible = "fsl,P1021MDS";
17 aliases {
18 ethernet3 = &enet3;
19 ethernet4 = &enet4;
20 };
22 memory {
23 device_type = "memory";
24 };
26 lbc: localbus@ffe05000 {
27 reg = <0x0 0xffe05000 0x0 0x1000>;
29 /* NAND Flash, BCSR, PMC0/1*/
30 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
31 0x1 0x0 0x0 0xf8000000 0x00008000
32 0x2 0x0 0x0 0xf8010000 0x00020000
33 0x3 0x0 0x0 0xf8020000 0x00020000>;
35 nand@0,0 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-fcm-nand",
39 "fsl,elbc-fcm-nand";
40 reg = <0x0 0x0 0x40000>;
42 partition@0 {
43 /* This location must not be altered */
44 /* 1MB for u-boot Bootloader Image */
45 reg = <0x0 0x00100000>;
46 label = "NAND (RO) U-Boot Image";
47 read-only;
48 };
50 partition@100000 {
51 /* 1MB for DTB Image */
52 reg = <0x00100000 0x00100000>;
53 label = "NAND (RO) DTB Image";
54 read-only;
55 };
57 partition@200000 {
58 /* 4MB for Linux Kernel Image */
59 reg = <0x00200000 0x00400000>;
60 label = "NAND (RO) Linux Kernel Image";
61 read-only;
62 };
64 partition@600000 {
65 /* 5MB for Compressed Root file System Image */
66 reg = <0x00600000 0x00500000>;
67 label = "NAND (RO) Compressed RFS Image";
68 read-only;
69 };
71 partition@b00000 {
72 /* 6MB for JFFS2 based Root file System */
73 reg = <0x00a00000 0x00600000>;
74 label = "NAND (RW) JFFS2 Root File System";
75 };
77 partition@1100000 {
78 /* 14MB for JFFS2 based Root file System */
79 reg = <0x01100000 0x00e00000>;
80 label = "NAND (RW) Writable User area";
81 };
83 partition@1f00000 {
84 /* 1MB for microcode */
85 reg = <0x01f00000 0x00100000>;
86 label = "NAND (RO) QE Ucode";
87 read-only;
88 };
89 };
91 bcsr@1,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,p1021mds-bcsr";
95 reg = <1 0 0x8000>;
96 ranges = <0 1 0 0x8000>;
97 };
99 pib@2,0 {
100 compatible = "fsl,p1021mds-pib";
101 reg = <2 0 0x10000>;
102 };
104 pib@3,0 {
105 compatible = "fsl,p1021mds-pib";
106 reg = <3 0 0x10000>;
107 };
108 };
110 soc: soc@ffe00000 {
111 compatible = "fsl,p1021-immr", "simple-bus";
112 ranges = <0x0 0x0 0xffe00000 0x100000>;
114 i2c@3000 {
115 rtc@68 {
116 compatible = "dallas,ds1374";
117 reg = <0x68>;
118 };
119 };
121 spi@7000 {
123 flash@0 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "spansion,s25sl12801", "jedec,spi-nor";
127 reg = <0>;
128 spi-max-frequency = <40000000>; /* input clock */
130 partition@u-boot {
131 label = "u-boot-spi";
132 reg = <0x00000000 0x00100000>;
133 read-only;
134 };
135 partition@kernel {
136 label = "kernel-spi";
137 reg = <0x00100000 0x00500000>;
138 read-only;
139 };
140 partition@dtb {
141 label = "dtb-spi";
142 reg = <0x00600000 0x00100000>;
143 read-only;
144 };
145 partition@fs {
146 label = "file system-spi";
147 reg = <0x00700000 0x00900000>;
148 };
149 };
150 };
152 usb@22000 {
153 phy_type = "ulpi";
154 dr_mode = "host";
155 };
157 mdio@24000 {
158 phy0: ethernet-phy@0 {
159 interrupts = <1 1 0 0>;
160 reg = <0x0>;
161 };
162 phy1: ethernet-phy@1 {
163 interrupts = <2 1 0 0>;
164 reg = <0x1>;
165 };
166 phy4: ethernet-phy@4 {
167 reg = <0x4>;
168 };
169 tbi-phy@5 {
170 device_type = "tbi-phy";
171 reg = <0x5>;
172 };
173 };
175 mdio@25000 {
176 tbi0: tbi-phy@11 {
177 reg = <0x11>;
178 device_type = "tbi-phy";
179 };
180 };
182 ethernet@b0000 {
183 phy-handle = <&phy0>;
184 phy-connection-type = "rgmii-id";
185 };
187 ethernet@b1000 {
188 phy-handle = <&phy4>;
189 tbi-handle = <&tbi0>;
190 phy-connection-type = "sgmii";
191 };
193 ethernet@b2000 {
194 phy-handle = <&phy1>;
195 phy-connection-type = "rgmii-id";
196 };
198 par_io@e0100 {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 reg = <0xe0100 0x60>;
202 ranges = <0x0 0xe0100 0x60>;
203 device_type = "par_io";
204 num-ports = <3>;
205 pio1: ucc_pin@01 {
206 pio-map = <
207 /* port pin dir open_drain assignment has_irq */
208 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
209 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
210 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
211 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
212 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
213 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
214 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
215 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
216 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
217 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
218 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
219 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
220 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
221 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
222 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
223 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
224 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
225 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
226 };
228 pio2: ucc_pin@02 {
229 pio-map = <
230 /* port pin dir open_drain assignment has_irq */
231 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
232 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
233 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
234 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
235 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
236 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
237 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
238 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
239 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
240 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
241 };
242 };
243 };
245 pci0: pcie@ffe09000 {
246 reg = <0 0xffe09000 0 0x1000>;
247 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
248 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
249 pcie@0 {
250 ranges = <0x2000000 0x0 0xa0000000
251 0x2000000 0x0 0xa0000000
252 0x0 0x20000000
254 0x1000000 0x0 0x0
255 0x1000000 0x0 0x0
256 0x0 0x100000>;
257 };
258 };
260 pci1: pcie@ffe0a000 {
261 reg = <0 0xffe0a000 0 0x1000>;
262 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
263 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
264 pcie@0 {
265 ranges = <0x2000000 0x0 0xc0000000
266 0x2000000 0x0 0xc0000000
267 0x0 0x20000000
269 0x1000000 0x0 0x0
270 0x1000000 0x0 0x0
271 0x0 0x100000>;
272 };
273 };
275 qe: qe@ffe80000 {
276 ranges = <0x0 0x0 0xffe80000 0x40000>;
277 reg = <0 0xffe80000 0 0x480>;
278 brg-frequency = <0>;
279 bus-frequency = <0>;
280 status = "disabled"; /* no firmware loaded */
282 enet3: ucc@2000 {
283 device_type = "network";
284 compatible = "ucc_geth";
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 rx-clock-name = "clk12";
287 tx-clock-name = "clk9";
288 pio-handle = <&pio1>;
289 phy-handle = <&qe_phy0>;
290 phy-connection-type = "mii";
291 };
293 mdio@2120 {
294 qe_phy0: ethernet-phy@0 {
295 interrupt-parent = <&mpic>;
296 interrupts = <4 1 0 0>;
297 reg = <0x0>;
298 };
299 qe_phy1: ethernet-phy@03 {
300 interrupt-parent = <&mpic>;
301 interrupts = <5 1 0 0>;
302 reg = <0x3>;
303 };
304 tbi-phy@11 {
305 reg = <0x11>;
306 device_type = "tbi-phy";
307 };
308 };
310 enet4: ucc@2400 {
311 device_type = "network";
312 compatible = "ucc_geth";
313 local-mac-address = [ 00 00 00 00 00 00 ];
314 rx-clock-name = "none";
315 tx-clock-name = "clk13";
316 pio-handle = <&pio2>;
317 phy-handle = <&qe_phy1>;
318 phy-connection-type = "rmii";
319 };
320 };
321 };
323 /include/ "p1021si-post.dtsi"