arch/powerpc/boot/dts/fsl/t2081qds.dts

   1 /*
   2  * T2081QDS Device Tree Source
   3  *
   4  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "t208xsi-pre.dtsi"
  36 /include/ "t208xqds.dtsi"
  37
  38 / {
  39         model = "fsl,T2081QDS";
  40         compatible = "fsl,T2081QDS";
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43         interrupt-parent = <&mpic>;
  44
  45         aliases {
  46                 emi1_slot1 = &t2081mdio2;
  47                 emi1_slot2 = &t2081mdio3;
  48                 emi1_slot3 = &t2081mdio4;
  49                 emi1_slot5 = &t2081mdio5;
  50                 emi1_slot6 = &t2081mdio6;
  51                 emi1_slot7 = &t2081mdio7;
  52         };
  53 };
  54
  55 &soc {
  56         fman@400000 {
  57                 ethernet@e0000 {
  58                         phy-handle = <&phy_sgmii_s7_1c>;
  59                         phy-connection-type = "sgmii";
  60                 };
  61
  62                 ethernet@e2000 {
  63                         phy-handle = <&phy_sgmii_s7_1d>;
  64                         phy-connection-type = "sgmii";
  65                 };
  66
  67                 ethernet@e4000 {
  68                         phy-handle = <&rgmii_phy1>;
  69                         phy-connection-type = "rgmii";
  70                 };
  71
  72                 ethernet@e6000 {
  73                         phy-handle = <&rgmii_phy2>;
  74                         phy-connection-type = "rgmii";
  75                 };
  76
  77                 ethernet@e8000 {
  78                         phy-handle = <&phy_sgmii_s3_1c>;
  79                         phy-connection-type = "sgmii";
  80                 };
  81
  82                 ethernet@ea000 {
  83                         phy-handle = <&phy_sgmii_s7_1f>;
  84                         phy-connection-type = "sgmii";
  85                 };
  86
  87                 ethernet@f0000 {
  88                         phy-handle = <&phy_sgmii_s2_1c>;
  89                         phy-connection-type = "xgmii";
  90                 };
  91
  92                 ethernet@f2000 {
  93                         phy-handle = <&phy_sgmii_s7_1e>;
  94                         phy-connection-type = "xgmii";
  95                 };
  96         };
  97 };
  98
  99 &boardctrl {
 100         mdio-mux-emi1 {
 101                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 102                 mdio-parent-bus = <&mdio0>;
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105                 reg = <0x54 1>;
 106                 mux-mask = <0xe0>;
 107
 108                 t2081mdio0: mdio@0 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         reg = <0>;
 112
 113                         rgmii_phy1: ethernet-phy@1 {
 114                                 reg = <0x1>;
 115                         };
 116                 };
 117
 118                 t2081mdio1: mdio@20 {
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         reg = <0x20>;
 122
 123                         rgmii_phy2: ethernet-phy@2 {
 124                                 reg = <0x2>;
 125                         };
 126                 };
 127
 128                 t2081mdio2: mdio@40 {
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         reg = <0x40>;
 132
 133                         phy_sgmii_s1_1c: ethernet-phy@1c {
 134                                 reg = <0x1c>;
 135                         };
 136
 137                         phy_sgmii_s1_1d: ethernet-phy@1d {
 138                                 reg = <0x1d>;
 139                         };
 140
 141                         phy_sgmii_s1_1e: ethernet-phy@1e {
 142                                 reg = <0x1e>;
 143                         };
 144
 145                         phy_sgmii_s1_1f: ethernet-phy@1f {
 146                                 reg = <0x1f>;
 147                         };
 148                 };
 149
 150                 t2081mdio3: mdio@60 {
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         reg = <0x60>;
 154
 155                         phy_sgmii_s2_1c: ethernet-phy@1c {
 156                                 reg = <0x1c>;
 157                         };
 158
 159                         phy_sgmii_s2_1d: ethernet-phy@1d {
 160                                 reg = <0x1d>;
 161                         };
 162
 163                         phy_sgmii_s2_1e: ethernet-phy@1e {
 164                                 reg = <0x1e>;
 165                         };
 166
 167                         phy_sgmii_s2_1f: ethernet-phy@1f {
 168                                 reg = <0x1f>;
 169                         };
 170                 };
 171
 172                 t2081mdio4: mdio@80 {
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         reg = <0x80>;
 176                         status = "disabled";
 177
 178                         phy_sgmii_s3_1c: ethernet-phy@1c {
 179                                 reg = <0x1c>;
 180                         };
 181
 182                         phy_sgmii_s3_1d: ethernet-phy@1d {
 183                                 reg = <0x1d>;
 184                         };
 185
 186                         phy_sgmii_s3_1e: ethernet-phy@1e {
 187                                 reg = <0x1e>;
 188                         };
 189
 190                         phy_sgmii_s3_1f: ethernet-phy@1f {
 191                                 reg = <0x1f>;
 192                         };
 193                 };
 194
 195                 t2081mdio5: mdio@a0 {
 196                         #address-cells = <1>;
 197                         #size-cells = <0>;
 198                         reg = <0xa0>;
 199                         status = "disabled";
 200
 201                         phy_sgmii_s5_1c: ethernet-phy@1c {
 202                                 reg = <0x1c>;
 203                         };
 204
 205                         phy_sgmii_s5_1d: ethernet-phy@1d {
 206                                 reg = <0x1d>;
 207                         };
 208
 209                         phy_sgmii_s5_1e: ethernet-phy@1e {
 210                                 reg = <0x1e>;
 211                         };
 212
 213                         phy_sgmii_s5_1f: ethernet-phy@1f {
 214                                 reg = <0x1f>;
 215                         };
 216                 };
 217
 218                 t2081mdio6: mdio@c0 {
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221                         reg = <0xc0>;
 222                         status = "disabled";
 223
 224                         phy_sgmii_s6_1c: ethernet-phy@1c {
 225                                 reg = <0x1c>;
 226                         };
 227
 228                         phy_sgmii_s6_1d: ethernet-phy@1d {
 229                                 reg = <0x1d>;
 230                         };
 231
 232                         phy_sgmii_s6_1e: ethernet-phy@1e {
 233                                 reg = <0x1e>;
 234                         };
 235
 236                         phy_sgmii_s6_1f: ethernet-phy@1f {
 237                                 reg = <0x1f>;
 238                         };
 239                 };
 240
 241                 t2081mdio7: mdio@e0 {
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         reg = <0xe0>;
 245
 246                         phy_sgmii_s7_1c: ethernet-phy@1c {
 247                                 reg = <0x1c>;
 248                         };
 249
 250                         phy_sgmii_s7_1d: ethernet-phy@1d {
 251                                 reg = <0x1d>;
 252                         };
 253
 254                         phy_sgmii_s7_1e: ethernet-phy@1e {
 255                                 reg = <0x1e>;
 256                         };
 257
 258                         phy_sgmii_s7_1f: ethernet-phy@1f {
 259                                 reg = <0x1f>;
 260                         };
 261                 };
 262         };
 263 };
 264
 265 /include/ "t2081si-post.dtsi"