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Linux 4.13.16
[linux/fpc-iii.git] / arch / powerpc / include / asm / cputable.h
blobd02ad93bf70892f8d342b9d8890a4e1b8065eed6
1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
3
4
5 #include <linux/types.h>
6 #include <asm/asm-compat.h>
7 #include <asm/feature-fixups.h>
8 #include <uapi/asm/cputable.h>
9
10 #ifndef __ASSEMBLY__
11
12 /* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
14 */
15 struct cpu_spec;
16
17 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
18 typedef void (*cpu_restore_t)(void);
19
20 enum powerpc_oprofile_type {
21 PPC_OPROFILE_INVALID = 0,
22 PPC_OPROFILE_RS64 = 1,
23 PPC_OPROFILE_POWER4 = 2,
24 PPC_OPROFILE_G4 = 3,
25 PPC_OPROFILE_FSL_EMB = 4,
26 PPC_OPROFILE_CELL = 5,
27 PPC_OPROFILE_PA6T = 6,
28 };
29
30 enum powerpc_pmc_type {
31 PPC_PMC_DEFAULT = 0,
32 PPC_PMC_IBM = 1,
33 PPC_PMC_PA6T = 2,
34 PPC_PMC_G4 = 3,
35 };
36
37 struct pt_regs;
38
39 extern int machine_check_generic(struct pt_regs *regs);
40 extern int machine_check_4xx(struct pt_regs *regs);
41 extern int machine_check_440A(struct pt_regs *regs);
42 extern int machine_check_e500mc(struct pt_regs *regs);
43 extern int machine_check_e500(struct pt_regs *regs);
44 extern int machine_check_e200(struct pt_regs *regs);
45 extern int machine_check_47x(struct pt_regs *regs);
46 int machine_check_8xx(struct pt_regs *regs);
47
48 extern void cpu_down_flush_e500v2(void);
49 extern void cpu_down_flush_e500mc(void);
50 extern void cpu_down_flush_e5500(void);
51 extern void cpu_down_flush_e6500(void);
52
53 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
54 struct cpu_spec {
55 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
56 unsigned int pvr_mask;
57 unsigned int pvr_value;
58
59 char *cpu_name;
60 unsigned long cpu_features; /* Kernel features */
61 unsigned int cpu_user_features; /* Userland features */
62 unsigned int cpu_user_features2; /* Userland features v2 */
63 unsigned int mmu_features; /* MMU features */
64
65 /* cache line sizes */
66 unsigned int icache_bsize;
67 unsigned int dcache_bsize;
68
69 /* flush caches inside the current cpu */
70 void (*cpu_down_flush)(void);
71
72 /* number of performance monitor counters */
73 unsigned int num_pmcs;
74 enum powerpc_pmc_type pmc_type;
75
76 /* this is called to initialize various CPU bits like L1 cache,
77 * BHT, SPD, etc... from head.S before branching to identify_machine
78 */
79 cpu_setup_t cpu_setup;
80 /* Used to restore cpu setup on secondary processors and at resume */
81 cpu_restore_t cpu_restore;
82
83 /* Used by oprofile userspace to select the right counters */
84 char *oprofile_cpu_type;
85
86 /* Processor specific oprofile operations */
87 enum powerpc_oprofile_type oprofile_type;
88
89 /* Bit locations inside the mmcra change */
90 unsigned long oprofile_mmcra_sihv;
91 unsigned long oprofile_mmcra_sipr;
92
93 /* Bits to clear during an oprofile exception */
94 unsigned long oprofile_mmcra_clear;
95
96 /* Name of processor class, for the ELF AT_PLATFORM entry */
97 char *platform;
98
99 /* Processor specific machine check handling. Return negative
100 * if the error is fatal, 1 if it was fully recovered and 0 to
101 * pass up (not CPU originated) */
102 int (*machine_check)(struct pt_regs *regs);
103
104 /*
105 * Processor specific early machine check handler which is
106 * called in real mode to handle SLB and TLB errors.
107 */
108 long (*machine_check_early)(struct pt_regs *regs);
109
110 /*
111 * Processor specific routine to flush tlbs.
112 */
113 void (*flush_tlb)(unsigned int action);
114
115 };
116
117 extern struct cpu_spec *cur_cpu_spec;
118
119 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
120
121 extern void set_cur_cpu_spec(struct cpu_spec *s);
122 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
123 extern void identify_cpu_name(unsigned int pvr);
124 extern void do_feature_fixups(unsigned long value, void *fixup_start,
125 void *fixup_end);
126
127 extern const char *powerpc_base_platform;
128
129 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
130 extern void cpu_feature_keys_init(void);
131 #else
132 static inline void cpu_feature_keys_init(void) { }
133 #endif
134
135 /* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
136 enum {
137 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
138 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
139 };
140
141 #endif /* __ASSEMBLY__ */
142
143 /* CPU kernel features */
144
145 /* Retain the 32b definitions all use bottom half of word */
146 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
147 #define CPU_FTR_L2CR ASM_CONST(0x00000002)
148 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
149 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
150 #define CPU_FTR_TAU ASM_CONST(0x00000010)
151 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
152 #define CPU_FTR_USE_TB ASM_CONST(0x00000040)
153 #define CPU_FTR_L2CSR ASM_CONST(0x00000080)
154 #define CPU_FTR_601 ASM_CONST(0x00000100)
155 #define CPU_FTR_DBELL ASM_CONST(0x00000200)
156 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
157 #define CPU_FTR_L3CR ASM_CONST(0x00000800)
158 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
159 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
160 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
161 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
162 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
163 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
164 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
165 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
166 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
167 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
168 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
169 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
170 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
171 #define CPU_FTR_SPE ASM_CONST(0x02000000)
172 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
173 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
174 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
175 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
176 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
177
178 /*
179 * Add the 64-bit processor unique features in the top half of the word;
180 * on 32-bit, make the names available but defined to be 0.
181 */
182 #ifdef __powerpc64__
183 #define LONG_ASM_CONST(x) ASM_CONST(x)
184 #else
185 #define LONG_ASM_CONST(x) 0
186 #endif
187
188 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
189 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
190 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
191 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
192 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
193 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
194 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
195 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
196 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
197 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
198 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
199 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
200 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
201 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
202 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
203 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
204 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
205 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
206 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
207 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
208 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
209 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
210 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
211 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
212 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
213 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
214 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
215 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
216 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
217 #define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000)
218
219 #ifndef __ASSEMBLY__
220
221 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
222
223 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
224
225 /* We only set the altivec features if the kernel was compiled with altivec
226 * support
227 */
228 #ifdef CONFIG_ALTIVEC
229 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
230 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
231 #else
232 #define CPU_FTR_ALTIVEC_COMP 0
233 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
234 #endif
235
236 /* We only set the VSX features if the kernel was compiled with VSX
237 * support
238 */
239 #ifdef CONFIG_VSX
240 #define CPU_FTR_VSX_COMP CPU_FTR_VSX
241 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
242 #else
243 #define CPU_FTR_VSX_COMP 0
244 #define PPC_FEATURE_HAS_VSX_COMP 0
245 #endif
246
247 /* We only set the spe features if the kernel was compiled with spe
248 * support
249 */
250 #ifdef CONFIG_SPE
251 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
252 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
253 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
254 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
255 #else
256 #define CPU_FTR_SPE_COMP 0
257 #define PPC_FEATURE_HAS_SPE_COMP 0
258 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
259 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
260 #endif
261
262 /* We only set the TM feature if the kernel was compiled with TM supprt */
263 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
264 #define CPU_FTR_TM_COMP CPU_FTR_TM
265 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
266 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
267 #else
268 #define CPU_FTR_TM_COMP 0
269 #define PPC_FEATURE2_HTM_COMP 0
270 #define PPC_FEATURE2_HTM_NOSC_COMP 0
271 #endif
272
273 /* We need to mark all pages as being coherent if we're SMP or we have a
274 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
275 * require it for PCI "streaming/prefetch" to work properly.
276 * This is also required by 52xx family.
277 */
278 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
279 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
280 || defined(CONFIG_PPC_MPC52xx)
281 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
282 #else
283 #define CPU_FTR_COMMON 0
284 #endif
285
286 /* The powersave features NAP & DOZE seems to confuse BDI when
287 debugging. So if a BDI is used, disable theses
288 */
289 #ifndef CONFIG_BDI_SWITCH
290 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
291 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
292 #else
293 #define CPU_FTR_MAYBE_CAN_DOZE 0
294 #define CPU_FTR_MAYBE_CAN_NAP 0
295 #endif
296
297 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
298 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
299 #define CPU_FTRS_603 (CPU_FTR_COMMON | \
300 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
302 #define CPU_FTRS_604 (CPU_FTR_COMMON | \
303 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
304 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
305 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
306 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
307 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
308 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
309 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
310 CPU_FTR_PPC_LE)
311 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
312 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
313 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
314 CPU_FTR_PPC_LE)
315 #define CPU_FTRS_750CL (CPU_FTRS_750)
316 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
317 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
318 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
319 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
320 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
321 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
322 CPU_FTR_ALTIVEC_COMP | \
323 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
324 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
325 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
326 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
328 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
329 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
330 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
331 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
332 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
333 CPU_FTR_USE_TB | \
334 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
335 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
336 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
337 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
338 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
339 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
341 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
342 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
343 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
344 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
345 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
346 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
347 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
348 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
349 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
350 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
351 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
352 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
353 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
354 CPU_FTR_USE_TB | \
355 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
356 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
357 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
358 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
359 CPU_FTR_USE_TB | \
360 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
361 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
362 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
363 CPU_FTR_NEED_PAIRED_STWCX)
364 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
365 CPU_FTR_USE_TB | \
366 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
367 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
368 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
369 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
370 CPU_FTR_USE_TB | \
371 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
372 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
373 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
374 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
375 CPU_FTR_USE_TB | \
376 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
377 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
378 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
379 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \
380 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
381 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
382 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
383 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
384 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
385 CPU_FTR_COMMON)
386 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
387 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
388 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
389 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
390 #define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
391 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
392 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
393 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
394 CPU_FTR_INDEXED_DCR)
395 #define CPU_FTRS_47X (CPU_FTRS_440x6)
396 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
397 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
398 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
399 CPU_FTR_DEBUG_LVL_EXC)
400 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
401 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
402 CPU_FTR_NOEXECUTE)
403 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
404 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
405 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
406 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
407 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
408 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
409 /*
410 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
411 * same workaround as CPU_FTR_CELL_TB_BUG.
412 */
413 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
414 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
415 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
416 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
417 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
418 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
419 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
420 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
421 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
422 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
423
424 /* 64-bit CPUs */
425 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
427 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
428 CPU_FTR_STCX_CHECKS_ADDRESS)
429 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
431 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
432 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
433 CPU_FTR_HVMODE | CPU_FTR_DABRX)
434 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
435 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
436 CPU_FTR_MMCRA | CPU_FTR_SMT | \
437 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
438 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
439 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
440 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
441 CPU_FTR_MMCRA | CPU_FTR_SMT | \
442 CPU_FTR_COHERENT_ICACHE | \
443 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
444 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
445 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
446 CPU_FTR_DABRX)
447 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
448 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
449 CPU_FTR_MMCRA | CPU_FTR_SMT | \
450 CPU_FTR_COHERENT_ICACHE | \
451 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
452 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
453 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
454 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
455 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
456 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
457 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
458 CPU_FTR_MMCRA | CPU_FTR_SMT | \
459 CPU_FTR_COHERENT_ICACHE | \
460 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
461 CPU_FTR_DSCR | CPU_FTR_SAO | \
462 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
463 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
464 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
465 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
466 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
467 #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
468 #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
469 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
470 CPU_FTR_MMCRA | CPU_FTR_SMT | \
471 CPU_FTR_COHERENT_ICACHE | \
472 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
473 CPU_FTR_DSCR | CPU_FTR_SAO | \
474 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
475 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
476 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
477 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300)
478 #define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
479 (~CPU_FTR_SAO))
480 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
481 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
482 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
483 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
484 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
485 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
486 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
487 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
488 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
489
490 #ifdef __powerpc64__
491 #ifdef CONFIG_PPC_BOOK3E
492 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
493 #else
494 #define CPU_FTRS_POSSIBLE \
495 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
496 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
497 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
498 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD1)
499 #endif
500 #else
501 enum {
502 CPU_FTRS_POSSIBLE =
503 #ifdef CONFIG_PPC_BOOK3S_32
504 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
505 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
506 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
507 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
508 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
509 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
510 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
511 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
512 CPU_FTRS_CLASSIC32 |
513 #else
514 CPU_FTRS_GENERIC_32 |
515 #endif
516 #ifdef CONFIG_8xx
517 CPU_FTRS_8XX |
518 #endif
519 #ifdef CONFIG_40x
520 CPU_FTRS_40X |
521 #endif
522 #ifdef CONFIG_44x
523 CPU_FTRS_44X | CPU_FTRS_440x6 |
524 #endif
525 #ifdef CONFIG_PPC_47x
526 CPU_FTRS_47X | CPU_FTR_476_DD2 |
527 #endif
528 #ifdef CONFIG_E200
529 CPU_FTRS_E200 |
530 #endif
531 #ifdef CONFIG_E500
532 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
533 #endif
534 #ifdef CONFIG_PPC_E500MC
535 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
536 #endif
537 0,
538 };
539 #endif /* __powerpc64__ */
540
541 #ifdef __powerpc64__
542 #ifdef CONFIG_PPC_BOOK3E
543 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
544 #else
545 #define CPU_FTRS_ALWAYS \
546 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
547 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
548 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
549 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
550 CPU_FTRS_POWER9)
551 #endif
552 #else
553 enum {
554 CPU_FTRS_ALWAYS =
555 #ifdef CONFIG_PPC_BOOK3S_32
556 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
557 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
558 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
559 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
560 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
561 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
562 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
563 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
564 CPU_FTRS_CLASSIC32 &
565 #else
566 CPU_FTRS_GENERIC_32 &
567 #endif
568 #ifdef CONFIG_8xx
569 CPU_FTRS_8XX &
570 #endif
571 #ifdef CONFIG_40x
572 CPU_FTRS_40X &
573 #endif
574 #ifdef CONFIG_44x
575 CPU_FTRS_44X & CPU_FTRS_440x6 &
576 #endif
577 #ifdef CONFIG_E200
578 CPU_FTRS_E200 &
579 #endif
580 #ifdef CONFIG_E500
581 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
582 #endif
583 #ifdef CONFIG_PPC_E500MC
584 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
585 #endif
586 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
587 CPU_FTRS_POSSIBLE,
588 };
589 #endif /* __powerpc64__ */
590
591 #define HBP_NUM 1
592
593 #endif /* !__ASSEMBLY__ */
594
595 #endif /* __ASM_POWERPC_CPUTABLE_H */
Linux with added FPC-III support