arch/powerpc/include/uapi/asm/auxvec.h

   1 #ifndef _ASM_POWERPC_AUXVEC_H
   2 #define _ASM_POWERPC_AUXVEC_H
   3
   4 /*
   5  * We need to put in some extra aux table entries to tell glibc what
   6  * the cache block size is, so it can use the dcbz instruction safely.
   7  */
   8 #define AT_DCACHEBSIZE          19
   9 #define AT_ICACHEBSIZE          20
  10 #define AT_UCACHEBSIZE          21
  11 /* A special ignored type value for PPC, for glibc compatibility.  */
  12 #define AT_IGNOREPPC            22
  13
  14 /* The vDSO location. We have to use the same value as x86 for glibc's
  15  * sake :-)
  16  */
  17 #define AT_SYSINFO_EHDR         33
  18
  19 /*
  20  * AT_*CACHEBSIZE above represent the cache *block* size which is
  21  * the size that is affected by the cache management instructions.
  22  *
  23  * It doesn't nececssarily matches the cache *line* size which is
  24  * more of a performance tuning hint. Additionally the latter can
  25  * be different for the different cache levels.
  26  *
  27  * The set of entries below represent more extensive information
  28  * about the caches, in the form of two entry per cache type,
  29  * one entry containing the cache size in bytes, and the other
  30  * containing the cache line size in bytes in the bottom 16 bits
  31  * and the cache associativity in the next 16 bits.
  32  *
  33  * The associativity is such that if N is the 16-bit value, the
  34  * cache is N way set associative. A value if 0xffff means fully
  35  * associative, a value of 1 means directly mapped.
  36  *
  37  * For all these fields, a value of 0 means that the information
  38  * is not known.
  39  */
  40
  41 #define AT_L1I_CACHESIZE        40
  42 #define AT_L1I_CACHEGEOMETRY    41
  43 #define AT_L1D_CACHESIZE        42
  44 #define AT_L1D_CACHEGEOMETRY    43
  45 #define AT_L2_CACHESIZE         44
  46 #define AT_L2_CACHEGEOMETRY     45
  47 #define AT_L3_CACHESIZE         46
  48 #define AT_L3_CACHEGEOMETRY     47
  49
  50 #define AT_VECTOR_SIZE_ARCH     14 /* entries in ARCH_DLINFO */
  51
  52 #endif