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Linux 4.13.16
[linux/fpc-iii.git] / arch / powerpc / kernel / align.c
blobfd3c1fcc73eb3cab19c1c36481e039f00b1cd6ea
1 /* align.c - handle alignment exceptions for the Power PC.
2 *
3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
4 * Copyright (c) 1998-1999 TiVo, Inc.
5 * PowerPC 403GCX modifications.
6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
7 * PowerPC 403GCX/405GP modifications.
8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
9 * 64-bit and Power4 support
10 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
11 * <benh@kernel.crashing.org>
12 * Merge ppc32 and ppc64 implementations
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <asm/processor.h>
23 #include <linux/uaccess.h>
24 #include <asm/cache.h>
25 #include <asm/cputable.h>
26 #include <asm/emulated_ops.h>
27 #include <asm/switch_to.h>
28 #include <asm/disassemble.h>
29 #include <asm/cpu_has_feature.h>
30
31 struct aligninfo {
32 unsigned char len;
33 unsigned char flags;
34 };
35
36
37 #define INVALID { 0, 0 }
38
39 /* Bits in the flags field */
40 #define LD 0 /* load */
41 #define ST 1 /* store */
42 #define SE 2 /* sign-extend value, or FP ld/st as word */
43 #define F 4 /* to/from fp regs */
44 #define U 8 /* update index register */
45 #define M 0x10 /* multiple load/store */
46 #define SW 0x20 /* byte swap */
47 #define S 0x40 /* single-precision fp or... */
48 #define SX 0x40 /* ... byte count in XER */
49 #define HARD 0x80 /* string, stwcx. */
50 #define E4 0x40 /* SPE endianness is word */
51 #define E8 0x80 /* SPE endianness is double word */
52 #define SPLT 0x80 /* VSX SPLAT load */
53
54 /* DSISR bits reported for a DCBZ instruction: */
55 #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
56
57 /*
58 * The PowerPC stores certain bits of the instruction that caused the
59 * alignment exception in the DSISR register. This array maps those
60 * bits to information about the operand length and what the
61 * instruction would do.
62 */
63 static struct aligninfo aligninfo[128] = {
64 { 4, LD }, /* 00 0 0000: lwz / lwarx */
65 INVALID, /* 00 0 0001 */
66 { 4, ST }, /* 00 0 0010: stw */
67 INVALID, /* 00 0 0011 */
68 { 2, LD }, /* 00 0 0100: lhz */
69 { 2, LD+SE }, /* 00 0 0101: lha */
70 { 2, ST }, /* 00 0 0110: sth */
71 { 4, LD+M }, /* 00 0 0111: lmw */
72 { 4, LD+F+S }, /* 00 0 1000: lfs */
73 { 8, LD+F }, /* 00 0 1001: lfd */
74 { 4, ST+F+S }, /* 00 0 1010: stfs */
75 { 8, ST+F }, /* 00 0 1011: stfd */
76 { 16, LD }, /* 00 0 1100: lq */
77 { 8, LD }, /* 00 0 1101: ld/ldu/lwa */
78 INVALID, /* 00 0 1110 */
79 { 8, ST }, /* 00 0 1111: std/stdu */
80 { 4, LD+U }, /* 00 1 0000: lwzu */
81 INVALID, /* 00 1 0001 */
82 { 4, ST+U }, /* 00 1 0010: stwu */
83 INVALID, /* 00 1 0011 */
84 { 2, LD+U }, /* 00 1 0100: lhzu */
85 { 2, LD+SE+U }, /* 00 1 0101: lhau */
86 { 2, ST+U }, /* 00 1 0110: sthu */
87 { 4, ST+M }, /* 00 1 0111: stmw */
88 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
89 { 8, LD+F+U }, /* 00 1 1001: lfdu */
90 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
91 { 8, ST+F+U }, /* 00 1 1011: stfdu */
92 { 16, LD+F }, /* 00 1 1100: lfdp */
93 INVALID, /* 00 1 1101 */
94 { 16, ST+F }, /* 00 1 1110: stfdp */
95 INVALID, /* 00 1 1111 */
96 { 8, LD }, /* 01 0 0000: ldx */
97 INVALID, /* 01 0 0001 */
98 { 8, ST }, /* 01 0 0010: stdx */
99 INVALID, /* 01 0 0011 */
100 INVALID, /* 01 0 0100 */
101 { 4, LD+SE }, /* 01 0 0101: lwax */
102 INVALID, /* 01 0 0110 */
103 INVALID, /* 01 0 0111 */
104 { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
105 { 4, LD+M+HARD }, /* 01 0 1001: lswi */
106 { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
107 { 4, ST+M+HARD }, /* 01 0 1011: stswi */
108 INVALID, /* 01 0 1100 */
109 { 8, LD+U }, /* 01 0 1101: ldu */
110 INVALID, /* 01 0 1110 */
111 { 8, ST+U }, /* 01 0 1111: stdu */
112 { 8, LD+U }, /* 01 1 0000: ldux */
113 INVALID, /* 01 1 0001 */
114 { 8, ST+U }, /* 01 1 0010: stdux */
115 INVALID, /* 01 1 0011 */
116 INVALID, /* 01 1 0100 */
117 { 4, LD+SE+U }, /* 01 1 0101: lwaux */
118 INVALID, /* 01 1 0110 */
119 INVALID, /* 01 1 0111 */
120 INVALID, /* 01 1 1000 */
121 INVALID, /* 01 1 1001 */
122 INVALID, /* 01 1 1010 */
123 INVALID, /* 01 1 1011 */
124 INVALID, /* 01 1 1100 */
125 INVALID, /* 01 1 1101 */
126 INVALID, /* 01 1 1110 */
127 INVALID, /* 01 1 1111 */
128 INVALID, /* 10 0 0000 */
129 INVALID, /* 10 0 0001 */
130 INVALID, /* 10 0 0010: stwcx. */
131 INVALID, /* 10 0 0011 */
132 INVALID, /* 10 0 0100 */
133 INVALID, /* 10 0 0101 */
134 INVALID, /* 10 0 0110 */
135 INVALID, /* 10 0 0111 */
136 { 4, LD+SW }, /* 10 0 1000: lwbrx */
137 INVALID, /* 10 0 1001 */
138 { 4, ST+SW }, /* 10 0 1010: stwbrx */
139 INVALID, /* 10 0 1011 */
140 { 2, LD+SW }, /* 10 0 1100: lhbrx */
141 { 4, LD+SE }, /* 10 0 1101 lwa */
142 { 2, ST+SW }, /* 10 0 1110: sthbrx */
143 { 16, ST }, /* 10 0 1111: stq */
144 INVALID, /* 10 1 0000 */
145 INVALID, /* 10 1 0001 */
146 INVALID, /* 10 1 0010 */
147 INVALID, /* 10 1 0011 */
148 INVALID, /* 10 1 0100 */
149 INVALID, /* 10 1 0101 */
150 INVALID, /* 10 1 0110 */
151 INVALID, /* 10 1 0111 */
152 INVALID, /* 10 1 1000 */
153 INVALID, /* 10 1 1001 */
154 INVALID, /* 10 1 1010 */
155 INVALID, /* 10 1 1011 */
156 INVALID, /* 10 1 1100 */
157 INVALID, /* 10 1 1101 */
158 INVALID, /* 10 1 1110 */
159 { 0, ST+HARD }, /* 10 1 1111: dcbz */
160 { 4, LD }, /* 11 0 0000: lwzx */
161 INVALID, /* 11 0 0001 */
162 { 4, ST }, /* 11 0 0010: stwx */
163 INVALID, /* 11 0 0011 */
164 { 2, LD }, /* 11 0 0100: lhzx */
165 { 2, LD+SE }, /* 11 0 0101: lhax */
166 { 2, ST }, /* 11 0 0110: sthx */
167 INVALID, /* 11 0 0111 */
168 { 4, LD+F+S }, /* 11 0 1000: lfsx */
169 { 8, LD+F }, /* 11 0 1001: lfdx */
170 { 4, ST+F+S }, /* 11 0 1010: stfsx */
171 { 8, ST+F }, /* 11 0 1011: stfdx */
172 { 16, LD+F }, /* 11 0 1100: lfdpx */
173 { 4, LD+F+SE }, /* 11 0 1101: lfiwax */
174 { 16, ST+F }, /* 11 0 1110: stfdpx */
175 { 4, ST+F }, /* 11 0 1111: stfiwx */
176 { 4, LD+U }, /* 11 1 0000: lwzux */
177 INVALID, /* 11 1 0001 */
178 { 4, ST+U }, /* 11 1 0010: stwux */
179 INVALID, /* 11 1 0011 */
180 { 2, LD+U }, /* 11 1 0100: lhzux */
181 { 2, LD+SE+U }, /* 11 1 0101: lhaux */
182 { 2, ST+U }, /* 11 1 0110: sthux */
183 INVALID, /* 11 1 0111 */
184 { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
185 { 8, LD+F+U }, /* 11 1 1001: lfdux */
186 { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
187 { 8, ST+F+U }, /* 11 1 1011: stfdux */
188 INVALID, /* 11 1 1100 */
189 { 4, LD+F }, /* 11 1 1101: lfiwzx */
190 INVALID, /* 11 1 1110 */
191 INVALID, /* 11 1 1111 */
192 };
193
194 /*
195 * The dcbz (data cache block zero) instruction
196 * gives an alignment fault if used on non-cacheable
197 * memory. We handle the fault mainly for the
198 * case when we are running with the cache disabled
199 * for debugging.
200 */
201 static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
202 {
203 long __user *p;
204 int i, size;
205
206 #ifdef __powerpc64__
207 size = ppc64_caches.l1d.block_size;
208 #else
209 size = L1_CACHE_BYTES;
210 #endif
211 p = (long __user *) (regs->dar & -size);
212 if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
213 return -EFAULT;
214 for (i = 0; i < size / sizeof(long); ++i)
215 if (__put_user_inatomic(0, p+i))
216 return -EFAULT;
217 return 1;
218 }
219
220 /*
221 * Emulate load & store multiple instructions
222 * On 64-bit machines, these instructions only affect/use the
223 * bottom 4 bytes of each register, and the loads clear the
224 * top 4 bytes of the affected register.
225 */
226 #ifdef __BIG_ENDIAN__
227 #ifdef CONFIG_PPC64
228 #define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
229 #else
230 #define REG_BYTE(rp, i) *((u8 *)(rp) + (i))
231 #endif
232 #else
233 #define REG_BYTE(rp, i) (*(((u8 *)((rp) + ((i)>>2)) + ((i)&3))))
234 #endif
235
236 #define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz))
237
238 #define __get_user_or_set_dar(_regs, _dest, _addr) \
239 ({ \
240 int rc = 0; \
241 typeof(_addr) __addr = (_addr); \
242 if (__get_user_inatomic(_dest, __addr)) { \
243 _regs->dar = (unsigned long)__addr; \
244 rc = -EFAULT; \
245 } \
246 rc; \
247 })
248
249 #define __put_user_or_set_dar(_regs, _src, _addr) \
250 ({ \
251 int rc = 0; \
252 typeof(_addr) __addr = (_addr); \
253 if (__put_user_inatomic(_src, __addr)) { \
254 _regs->dar = (unsigned long)__addr; \
255 rc = -EFAULT; \
256 } \
257 rc; \
258 })
259
260 static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
261 unsigned int reg, unsigned int nb,
262 unsigned int flags, unsigned int instr,
263 unsigned long swiz)
264 {
265 unsigned long *rptr;
266 unsigned int nb0, i, bswiz;
267 unsigned long p;
268
269 /*
270 * We do not try to emulate 8 bytes multiple as they aren't really
271 * available in our operating environments and we don't try to
272 * emulate multiples operations in kernel land as they should never
273 * be used/generated there at least not on unaligned boundaries
274 */
275 if (unlikely((nb > 4) || !user_mode(regs)))
276 return 0;
277
278 /* lmw, stmw, lswi/x, stswi/x */
279 nb0 = 0;
280 if (flags & HARD) {
281 if (flags & SX) {
282 nb = regs->xer & 127;
283 if (nb == 0)
284 return 1;
285 } else {
286 unsigned long pc = regs->nip ^ (swiz & 4);
287
288 if (__get_user_or_set_dar(regs, instr,
289 (unsigned int __user *)pc))
290 return -EFAULT;
291
292 if (swiz == 0 && (flags & SW))
293 instr = cpu_to_le32(instr);
294 nb = (instr >> 11) & 0x1f;
295 if (nb == 0)
296 nb = 32;
297 }
298 if (nb + reg * 4 > 128) {
299 nb0 = nb + reg * 4 - 128;
300 nb = 128 - reg * 4;
301 }
302 #ifdef __LITTLE_ENDIAN__
303 /*
304 * String instructions are endian neutral but the code
305 * below is not. Force byte swapping on so that the
306 * effects of swizzling are undone in the load/store
307 * loops below.
308 */
309 flags ^= SW;
310 #endif
311 } else {
312 /* lwm, stmw */
313 nb = (32 - reg) * 4;
314 }
315
316 if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
317 return -EFAULT; /* bad address */
318
319 rptr = &regs->gpr[reg];
320 p = (unsigned long) addr;
321 bswiz = (flags & SW)? 3: 0;
322
323 if (!(flags & ST)) {
324 /*
325 * This zeroes the top 4 bytes of the affected registers
326 * in 64-bit mode, and also zeroes out any remaining
327 * bytes of the last register for lsw*.
328 */
329 memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
330 if (nb0 > 0)
331 memset(&regs->gpr[0], 0,
332 ((nb0 + 3) / 4) * sizeof(unsigned long));
333
334 for (i = 0; i < nb; ++i, ++p)
335 if (__get_user_or_set_dar(regs, REG_BYTE(rptr, i ^ bswiz),
336 SWIZ_PTR(p)))
337 return -EFAULT;
338 if (nb0 > 0) {
339 rptr = &regs->gpr[0];
340 addr += nb;
341 for (i = 0; i < nb0; ++i, ++p)
342 if (__get_user_or_set_dar(regs,
343 REG_BYTE(rptr, i ^ bswiz),
344 SWIZ_PTR(p)))
345 return -EFAULT;
346 }
347
348 } else {
349 for (i = 0; i < nb; ++i, ++p)
350 if (__put_user_or_set_dar(regs, REG_BYTE(rptr, i ^ bswiz),
351 SWIZ_PTR(p)))
352 return -EFAULT;
353 if (nb0 > 0) {
354 rptr = &regs->gpr[0];
355 addr += nb;
356 for (i = 0; i < nb0; ++i, ++p)
357 if (__put_user_or_set_dar(regs,
358 REG_BYTE(rptr, i ^ bswiz),
359 SWIZ_PTR(p)))
360 return -EFAULT;
361 }
362 }
363 return 1;
364 }
365
366 /*
367 * Emulate floating-point pair loads and stores.
368 * Only POWER6 has these instructions, and it does true little-endian,
369 * so we don't need the address swizzling.
370 */
371 static int emulate_fp_pair(struct pt_regs *regs, unsigned char __user *addr,
372 unsigned int reg, unsigned int flags)
373 {
374 char *ptr0 = (char *) &current->thread.TS_FPR(reg);
375 char *ptr1 = (char *) &current->thread.TS_FPR(reg+1);
376 int i, sw = 0;
377
378 if (reg & 1)
379 return 0; /* invalid form: FRS/FRT must be even */
380 if (flags & SW)
381 sw = 7;
382
383 for (i = 0; i < 8; ++i) {
384 if (!(flags & ST)) {
385 if (__get_user_or_set_dar(regs, ptr0[i^sw], addr + i))
386 return -EFAULT;
387 if (__get_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
388 return -EFAULT;
389 } else {
390 if (__put_user_or_set_dar(regs, ptr0[i^sw], addr + i))
391 return -EFAULT;
392 if (__put_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
393 return -EFAULT;
394 }
395 }
396
397 return 1; /* exception handled and fixed up */
398 }
399
400 #ifdef CONFIG_PPC64
401 static int emulate_lq_stq(struct pt_regs *regs, unsigned char __user *addr,
402 unsigned int reg, unsigned int flags)
403 {
404 char *ptr0 = (char *)&regs->gpr[reg];
405 char *ptr1 = (char *)&regs->gpr[reg+1];
406 int i, sw = 0;
407
408 if (reg & 1)
409 return 0; /* invalid form: GPR must be even */
410 if (flags & SW)
411 sw = 7;
412
413 for (i = 0; i < 8; ++i) {
414 if (!(flags & ST)) {
415 if (__get_user_or_set_dar(regs, ptr0[i^sw], addr + i))
416 return -EFAULT;
417 if (__get_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
418 return -EFAULT;
419 } else {
420 if (__put_user_or_set_dar(regs, ptr0[i^sw], addr + i))
421 return -EFAULT;
422 if (__put_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
423 return -EFAULT;
424 }
425 }
426
427 return 1; /* exception handled and fixed up */
428 }
429 #endif /* CONFIG_PPC64 */
430
431 #ifdef CONFIG_SPE
432
433 static struct aligninfo spe_aligninfo[32] = {
434 { 8, LD+E8 }, /* 0 00 00: evldd[x] */
435 { 8, LD+E4 }, /* 0 00 01: evldw[x] */
436 { 8, LD }, /* 0 00 10: evldh[x] */
437 INVALID, /* 0 00 11 */
438 { 2, LD }, /* 0 01 00: evlhhesplat[x] */
439 INVALID, /* 0 01 01 */
440 { 2, LD }, /* 0 01 10: evlhhousplat[x] */
441 { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */
442 { 4, LD }, /* 0 10 00: evlwhe[x] */
443 INVALID, /* 0 10 01 */
444 { 4, LD }, /* 0 10 10: evlwhou[x] */
445 { 4, LD+SE }, /* 0 10 11: evlwhos[x] */
446 { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */
447 INVALID, /* 0 11 01 */
448 { 4, LD }, /* 0 11 10: evlwhsplat[x] */
449 INVALID, /* 0 11 11 */
450
451 { 8, ST+E8 }, /* 1 00 00: evstdd[x] */
452 { 8, ST+E4 }, /* 1 00 01: evstdw[x] */
453 { 8, ST }, /* 1 00 10: evstdh[x] */
454 INVALID, /* 1 00 11 */
455 INVALID, /* 1 01 00 */
456 INVALID, /* 1 01 01 */
457 INVALID, /* 1 01 10 */
458 INVALID, /* 1 01 11 */
459 { 4, ST }, /* 1 10 00: evstwhe[x] */
460 INVALID, /* 1 10 01 */
461 { 4, ST }, /* 1 10 10: evstwho[x] */
462 INVALID, /* 1 10 11 */
463 { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */
464 INVALID, /* 1 11 01 */
465 { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */
466 INVALID, /* 1 11 11 */
467 };
468
469 #define EVLDD 0x00
470 #define EVLDW 0x01
471 #define EVLDH 0x02
472 #define EVLHHESPLAT 0x04
473 #define EVLHHOUSPLAT 0x06
474 #define EVLHHOSSPLAT 0x07
475 #define EVLWHE 0x08
476 #define EVLWHOU 0x0A
477 #define EVLWHOS 0x0B
478 #define EVLWWSPLAT 0x0C
479 #define EVLWHSPLAT 0x0E
480 #define EVSTDD 0x10
481 #define EVSTDW 0x11
482 #define EVSTDH 0x12
483 #define EVSTWHE 0x18
484 #define EVSTWHO 0x1A
485 #define EVSTWWE 0x1C
486 #define EVSTWWO 0x1E
487
488 /*
489 * Emulate SPE loads and stores.
490 * Only Book-E has these instructions, and it does true little-endian,
491 * so we don't need the address swizzling.
492 */
493 static int emulate_spe(struct pt_regs *regs, unsigned int reg,
494 unsigned int instr)
495 {
496 int ret;
497 union {
498 u64 ll;
499 u32 w[2];
500 u16 h[4];
501 u8 v[8];
502 } data, temp;
503 unsigned char __user *p, *addr;
504 unsigned long *evr = &current->thread.evr[reg];
505 unsigned int nb, flags;
506
507 instr = (instr >> 1) & 0x1f;
508
509 /* DAR has the operand effective address */
510 addr = (unsigned char __user *)regs->dar;
511
512 nb = spe_aligninfo[instr].len;
513 flags = spe_aligninfo[instr].flags;
514
515 /* Verify the address of the operand */
516 if (unlikely(user_mode(regs) &&
517 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
518 addr, nb)))
519 return -EFAULT;
520
521 /* userland only */
522 if (unlikely(!user_mode(regs)))
523 return 0;
524
525 flush_spe_to_thread(current);
526
527 /* If we are loading, get the data from user space, else
528 * get it from register values
529 */
530 if (flags & ST) {
531 data.ll = 0;
532 switch (instr) {
533 case EVSTDD:
534 case EVSTDW:
535 case EVSTDH:
536 data.w[0] = *evr;
537 data.w[1] = regs->gpr[reg];
538 break;
539 case EVSTWHE:
540 data.h[2] = *evr >> 16;
541 data.h[3] = regs->gpr[reg] >> 16;
542 break;
543 case EVSTWHO:
544 data.h[2] = *evr & 0xffff;
545 data.h[3] = regs->gpr[reg] & 0xffff;
546 break;
547 case EVSTWWE:
548 data.w[1] = *evr;
549 break;
550 case EVSTWWO:
551 data.w[1] = regs->gpr[reg];
552 break;
553 default:
554 return -EINVAL;
555 }
556 } else {
557 temp.ll = data.ll = 0;
558 ret = 0;
559 p = addr;
560
561 switch (nb) {
562 case 8:
563 ret |= __get_user_inatomic(temp.v[0], p++);
564 ret |= __get_user_inatomic(temp.v[1], p++);
565 ret |= __get_user_inatomic(temp.v[2], p++);
566 ret |= __get_user_inatomic(temp.v[3], p++);
567 case 4:
568 ret |= __get_user_inatomic(temp.v[4], p++);
569 ret |= __get_user_inatomic(temp.v[5], p++);
570 case 2:
571 ret |= __get_user_inatomic(temp.v[6], p++);
572 ret |= __get_user_inatomic(temp.v[7], p++);
573 if (unlikely(ret))
574 return -EFAULT;
575 }
576
577 switch (instr) {
578 case EVLDD:
579 case EVLDW:
580 case EVLDH:
581 data.ll = temp.ll;
582 break;
583 case EVLHHESPLAT:
584 data.h[0] = temp.h[3];
585 data.h[2] = temp.h[3];
586 break;
587 case EVLHHOUSPLAT:
588 case EVLHHOSSPLAT:
589 data.h[1] = temp.h[3];
590 data.h[3] = temp.h[3];
591 break;
592 case EVLWHE:
593 data.h[0] = temp.h[2];
594 data.h[2] = temp.h[3];
595 break;
596 case EVLWHOU:
597 case EVLWHOS:
598 data.h[1] = temp.h[2];
599 data.h[3] = temp.h[3];
600 break;
601 case EVLWWSPLAT:
602 data.w[0] = temp.w[1];
603 data.w[1] = temp.w[1];
604 break;
605 case EVLWHSPLAT:
606 data.h[0] = temp.h[2];
607 data.h[1] = temp.h[2];
608 data.h[2] = temp.h[3];
609 data.h[3] = temp.h[3];
610 break;
611 default:
612 return -EINVAL;
613 }
614 }
615
616 if (flags & SW) {
617 switch (flags & 0xf0) {
618 case E8:
619 data.ll = swab64(data.ll);
620 break;
621 case E4:
622 data.w[0] = swab32(data.w[0]);
623 data.w[1] = swab32(data.w[1]);
624 break;
625 /* Its half word endian */
626 default:
627 data.h[0] = swab16(data.h[0]);
628 data.h[1] = swab16(data.h[1]);
629 data.h[2] = swab16(data.h[2]);
630 data.h[3] = swab16(data.h[3]);
631 break;
632 }
633 }
634
635 if (flags & SE) {
636 data.w[0] = (s16)data.h[1];
637 data.w[1] = (s16)data.h[3];
638 }
639
640 /* Store result to memory or update registers */
641 if (flags & ST) {
642 ret = 0;
643 p = addr;
644 switch (nb) {
645 case 8:
646 ret |= __put_user_inatomic(data.v[0], p++);
647 ret |= __put_user_inatomic(data.v[1], p++);
648 ret |= __put_user_inatomic(data.v[2], p++);
649 ret |= __put_user_inatomic(data.v[3], p++);
650 case 4:
651 ret |= __put_user_inatomic(data.v[4], p++);
652 ret |= __put_user_inatomic(data.v[5], p++);
653 case 2:
654 ret |= __put_user_inatomic(data.v[6], p++);
655 ret |= __put_user_inatomic(data.v[7], p++);
656 }
657 if (unlikely(ret))
658 return -EFAULT;
659 } else {
660 *evr = data.w[0];
661 regs->gpr[reg] = data.w[1];
662 }
663
664 return 1;
665 }
666 #endif /* CONFIG_SPE */
667
668 #ifdef CONFIG_VSX
669 /*
670 * Emulate VSX instructions...
671 */
672 static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
673 unsigned int areg, struct pt_regs *regs,
674 unsigned int flags, unsigned int length,
675 unsigned int elsize)
676 {
677 char *ptr;
678 unsigned long *lptr;
679 int ret = 0;
680 int sw = 0;
681 int i, j;
682
683 /* userland only */
684 if (unlikely(!user_mode(regs)))
685 return 0;
686
687 flush_vsx_to_thread(current);
688
689 if (reg < 32)
690 ptr = (char *) &current->thread.fp_state.fpr[reg][0];
691 else
692 ptr = (char *) &current->thread.vr_state.vr[reg - 32];
693
694 lptr = (unsigned long *) ptr;
695
696 #ifdef __LITTLE_ENDIAN__
697 if (flags & SW) {
698 elsize = length;
699 sw = length-1;
700 } else {
701 /*
702 * The elements are BE ordered, even in LE mode, so process
703 * them in reverse order.
704 */
705 addr += length - elsize;
706
707 /* 8 byte memory accesses go in the top 8 bytes of the VR */
708 if (length == 8)
709 ptr += 8;
710 }
711 #else
712 if (flags & SW)
713 sw = elsize-1;
714 #endif
715
716 for (j = 0; j < length; j += elsize) {
717 for (i = 0; i < elsize; ++i) {
718 if (flags & ST)
719 ret = __put_user_or_set_dar(regs, ptr[i^sw],
720 addr + i);
721 else
722 ret = __get_user_or_set_dar(regs, ptr[i^sw],
723 addr + i);
724
725 if (ret)
726 return ret;
727 }
728 ptr += elsize;
729 #ifdef __LITTLE_ENDIAN__
730 addr -= elsize;
731 #else
732 addr += elsize;
733 #endif
734 }
735
736 #ifdef __BIG_ENDIAN__
737 #define VSX_HI 0
738 #define VSX_LO 1
739 #else
740 #define VSX_HI 1
741 #define VSX_LO 0
742 #endif
743
744 if (!ret) {
745 if (flags & U)
746 regs->gpr[areg] = regs->dar;
747
748 /* Splat load copies the same data to top and bottom 8 bytes */
749 if (flags & SPLT)
750 lptr[VSX_LO] = lptr[VSX_HI];
751 /* For 8 byte loads, zero the low 8 bytes */
752 else if (!(flags & ST) && (8 == length))
753 lptr[VSX_LO] = 0;
754 } else
755 return -EFAULT;
756
757 return 1;
758 }
759 #endif
760
761 /*
762 * Called on alignment exception. Attempts to fixup
763 *
764 * Return 1 on success
765 * Return 0 if unable to handle the interrupt
766 * Return -EFAULT if data address is bad
767 */
768
769 int fix_alignment(struct pt_regs *regs)
770 {
771 unsigned int instr, nb, flags, instruction = 0;
772 unsigned int reg, areg;
773 unsigned int dsisr;
774 unsigned char __user *addr;
775 unsigned long p, swiz;
776 int i;
777 union data {
778 u64 ll;
779 double dd;
780 unsigned char v[8];
781 struct {
782 #ifdef __LITTLE_ENDIAN__
783 int low32;
784 unsigned hi32;
785 #else
786 unsigned hi32;
787 int low32;
788 #endif
789 } x32;
790 struct {
791 #ifdef __LITTLE_ENDIAN__
792 short low16;
793 unsigned char hi48[6];
794 #else
795 unsigned char hi48[6];
796 short low16;
797 #endif
798 } x16;
799 } data;
800
801 /*
802 * We require a complete register set, if not, then our assembly
803 * is broken
804 */
805 CHECK_FULL_REGS(regs);
806
807 dsisr = regs->dsisr;
808
809 /* Some processors don't provide us with a DSISR we can use here,
810 * let's make one up from the instruction
811 */
812 if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
813 unsigned long pc = regs->nip;
814
815 if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE))
816 pc ^= 4;
817 if (unlikely(__get_user_inatomic(instr,
818 (unsigned int __user *)pc)))
819 return -EFAULT;
820 if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE))
821 instr = cpu_to_le32(instr);
822 dsisr = make_dsisr(instr);
823 instruction = instr;
824 }
825
826 /* extract the operation and registers from the dsisr */
827 reg = (dsisr >> 5) & 0x1f; /* source/dest register */
828 areg = dsisr & 0x1f; /* register to update */
829
830 #ifdef CONFIG_SPE
831 if ((instr >> 26) == 0x4) {
832 PPC_WARN_ALIGNMENT(spe, regs);
833 return emulate_spe(regs, reg, instr);
834 }
835 #endif
836
837 instr = (dsisr >> 10) & 0x7f;
838 instr |= (dsisr >> 13) & 0x60;
839
840 /* Lookup the operation in our table */
841 nb = aligninfo[instr].len;
842 flags = aligninfo[instr].flags;
843
844 /*
845 * Handle some cases which give overlaps in the DSISR values.
846 */
847 if (IS_XFORM(instruction)) {
848 switch (get_xop(instruction)) {
849 case 532: /* ldbrx */
850 nb = 8;
851 flags = LD+SW;
852 break;
853 case 660: /* stdbrx */
854 nb = 8;
855 flags = ST+SW;
856 break;
857 case 20: /* lwarx */
858 case 84: /* ldarx */
859 case 116: /* lharx */
860 case 276: /* lqarx */
861 return 0; /* not emulated ever */
862 }
863 }
864
865 /* Byteswap little endian loads and stores */
866 swiz = 0;
867 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
868 flags ^= SW;
869 #ifdef __BIG_ENDIAN__
870 /*
871 * So-called "PowerPC little endian" mode works by
872 * swizzling addresses rather than by actually doing
873 * any byte-swapping. To emulate this, we XOR each
874 * byte address with 7. We also byte-swap, because
875 * the processor's address swizzling depends on the
876 * operand size (it xors the address with 7 for bytes,
877 * 6 for halfwords, 4 for words, 0 for doublewords) but
878 * we will xor with 7 and load/store each byte separately.
879 */
880 if (cpu_has_feature(CPU_FTR_PPC_LE))
881 swiz = 7;
882 #endif
883 }
884
885 /* DAR has the operand effective address */
886 addr = (unsigned char __user *)regs->dar;
887
888 #ifdef CONFIG_VSX
889 if ((instruction & 0xfc00003e) == 0x7c000018) {
890 unsigned int elsize;
891
892 /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
893 reg |= (instruction & 0x1) << 5;
894 /* Simple inline decoder instead of a table */
895 /* VSX has only 8 and 16 byte memory accesses */
896 nb = 8;
897 if (instruction & 0x200)
898 nb = 16;
899
900 /* Vector stores in little-endian mode swap individual
901 elements, so process them separately */
902 elsize = 4;
903 if (instruction & 0x80)
904 elsize = 8;
905
906 flags = 0;
907 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE))
908 flags |= SW;
909 if (instruction & 0x100)
910 flags |= ST;
911 if (instruction & 0x040)
912 flags |= U;
913 /* splat load needs a special decoder */
914 if ((instruction & 0x400) == 0){
915 flags |= SPLT;
916 nb = 8;
917 }
918 PPC_WARN_ALIGNMENT(vsx, regs);
919 return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
920 }
921 #endif
922
923 /*
924 * ISA 3.0 (such as P9) copy, copy_first, paste and paste_last alignment
925 * check.
926 *
927 * Send a SIGBUS to the process that caused the fault.
928 *
929 * We do not emulate these because paste may contain additional metadata
930 * when pasting to a co-processor. Furthermore, paste_last is the
931 * synchronisation point for preceding copy/paste sequences.
932 */
933 if ((instruction & 0xfc0006fe) == PPC_INST_COPY)
934 return -EIO;
935
936 /* A size of 0 indicates an instruction we don't support, with
937 * the exception of DCBZ which is handled as a special case here
938 */
939 if (instr == DCBZ) {
940 PPC_WARN_ALIGNMENT(dcbz, regs);
941 return emulate_dcbz(regs, addr);
942 }
943 if (unlikely(nb == 0))
944 return 0;
945
946 /* Load/Store Multiple instructions are handled in their own
947 * function
948 */
949 if (flags & M) {
950 PPC_WARN_ALIGNMENT(multiple, regs);
951 return emulate_multiple(regs, addr, reg, nb,
952 flags, instr, swiz);
953 }
954
955 /* Verify the address of the operand */
956 if (unlikely(user_mode(regs) &&
957 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
958 addr, nb)))
959 return -EFAULT;
960
961 /* Force the fprs into the save area so we can reference them */
962 if (flags & F) {
963 /* userland only */
964 if (unlikely(!user_mode(regs)))
965 return 0;
966 flush_fp_to_thread(current);
967 }
968
969 if (nb == 16) {
970 if (flags & F) {
971 /* Special case for 16-byte FP loads and stores */
972 PPC_WARN_ALIGNMENT(fp_pair, regs);
973 return emulate_fp_pair(regs, addr, reg, flags);
974 } else {
975 #ifdef CONFIG_PPC64
976 /* Special case for 16-byte loads and stores */
977 PPC_WARN_ALIGNMENT(lq_stq, regs);
978 return emulate_lq_stq(regs, addr, reg, flags);
979 #else
980 return 0;
981 #endif
982 }
983 }
984
985 PPC_WARN_ALIGNMENT(unaligned, regs);
986
987 /* If we are loading, get the data from user space, else
988 * get it from register values
989 */
990 if (!(flags & ST)) {
991 unsigned int start = 0;
992
993 switch (nb) {
994 case 4:
995 start = offsetof(union data, x32.low32);
996 break;
997 case 2:
998 start = offsetof(union data, x16.low16);
999 break;
1000 }
1001
1002 data.ll = 0;
1003 p = (unsigned long)addr;
1004
1005 for (i = 0; i < nb; i++)
1006 if (__get_user_or_set_dar(regs, data.v[start + i],
1007 SWIZ_PTR(p++)))
1008 return -EFAULT;
1009
1010 } else if (flags & F) {
1011 data.ll = current->thread.TS_FPR(reg);
1012 if (flags & S) {
1013 /* Single-precision FP store requires conversion... */
1014 #ifdef CONFIG_PPC_FPU
1015 preempt_disable();
1016 enable_kernel_fp();
1017 cvt_df(&data.dd, (float *)&data.x32.low32);
1018 disable_kernel_fp();
1019 preempt_enable();
1020 #else
1021 return 0;
1022 #endif
1023 }
1024 } else
1025 data.ll = regs->gpr[reg];
1026
1027 if (flags & SW) {
1028 switch (nb) {
1029 case 8:
1030 data.ll = swab64(data.ll);
1031 break;
1032 case 4:
1033 data.x32.low32 = swab32(data.x32.low32);
1034 break;
1035 case 2:
1036 data.x16.low16 = swab16(data.x16.low16);
1037 break;
1038 }
1039 }
1040
1041 /* Perform other misc operations like sign extension
1042 * or floating point single precision conversion
1043 */
1044 switch (flags & ~(U|SW)) {
1045 case LD+SE: /* sign extending integer loads */
1046 case LD+F+SE: /* sign extend for lfiwax */
1047 if ( nb == 2 )
1048 data.ll = data.x16.low16;
1049 else /* nb must be 4 */
1050 data.ll = data.x32.low32;
1051 break;
1052
1053 /* Single-precision FP load requires conversion... */
1054 case LD+F+S:
1055 #ifdef CONFIG_PPC_FPU
1056 preempt_disable();
1057 enable_kernel_fp();
1058 cvt_fd((float *)&data.x32.low32, &data.dd);
1059 disable_kernel_fp();
1060 preempt_enable();
1061 #else
1062 return 0;
1063 #endif
1064 break;
1065 }
1066
1067 /* Store result to memory or update registers */
1068 if (flags & ST) {
1069 unsigned int start = 0;
1070
1071 switch (nb) {
1072 case 4:
1073 start = offsetof(union data, x32.low32);
1074 break;
1075 case 2:
1076 start = offsetof(union data, x16.low16);
1077 break;
1078 }
1079
1080 p = (unsigned long)addr;
1081
1082 for (i = 0; i < nb; i++)
1083 if (__put_user_or_set_dar(regs, data.v[start + i],
1084 SWIZ_PTR(p++)))
1085 return -EFAULT;
1086
1087 } else if (flags & F)
1088 current->thread.TS_FPR(reg) = data.ll;
1089 else
1090 regs->gpr[reg] = data.ll;
1091
1092 /* Update RA as needed */
1093 if (flags & U)
1094 regs->gpr[areg] = regs->dar;
1095
1096 return 1;
1097 }
Linux with added FPC-III support