| blob | d9dfdf7ede45ffc96156ba56dd2a95352d5a76b7 |
1 /*
2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
6 *
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
9 *
10 * Most of this originates from head_64.S and thus has the same
11 * copyright history.
12 *
13 */
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
21 /*
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
27 * must be used.
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
29 * virtual 0xc00...
30 * - Conditional branch targets must be within +/-32K of caller.
31 *
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
37 *
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
44 *
45 * It's impossible to receive interrupts below 0x300 via AIL.
46 *
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
49 *
50 *
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
60 *
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
63 * vectors there.
64 */
65 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
70 /*
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
75 */
76 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77 OPEN_TEXT_SECTION(0x8000)
78 #else
79 OPEN_TEXT_SECTION(0x7000)
80 #endif
82 USE_FIXED_SECTION(real_vectors)
84 /*
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
91 */
92 .globl __start_interrupts
93 __start_interrupts:
95 /* No virt vectors corresponding with 0x0..0x100 */
96 EXC_VIRT_NONE(0x4000, 0x100)
99 #ifdef CONFIG_PPC_P7_NAP
100 /*
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
103 * bits 46:47. A non-0 value indicates that we are coming from a power
104 * saving state. The idle wakeup handler initially runs in real mode,
105 * but we branch to the 0xc000... address so we can turn on relocation
106 * with mtmsr.
107 */
108 #define IDLETEST(n) \
109 BEGIN_FTR_SECTION ; \
110 mfspr r10,SPRN_SRR1 ; \
111 rlwinm. r10,r10,47-31,30,31 ; \
112 beq- 1f ; \
113 cmpwi cr3,r10,2 ; \
114 BRANCH_TO_C000(r10, system_reset_idle_common) ; \
115 1: \
116 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
117 #else
118 #define IDLETEST NOTEST
119 #endif
121 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
122 SET_SCRATCH0(r13)
123 /*
124 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
125 * being used, so a nested NMI exception would corrupt it.
126 */
127 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
128 IDLETEST, 0x100)
130 EXC_REAL_END(system_reset, 0x100, 0x100)
131 EXC_VIRT_NONE(0x4100, 0x100)
133 #ifdef CONFIG_PPC_P7_NAP
134 EXC_COMMON_BEGIN(system_reset_idle_common)
135 mfspr r12,SPRN_SRR1
136 b pnv_powersave_wakeup
137 #endif
139 EXC_COMMON_BEGIN(system_reset_common)
140 /*
141 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
142 * to recover, but nested NMI will notice in_nmi and not recover
143 * because of the use of the NMI stack. in_nmi reentrancy is tested in
144 * system_reset_exception.
145 */
146 lhz r10,PACA_IN_NMI(r13)
147 addi r10,r10,1
148 sth r10,PACA_IN_NMI(r13)
149 li r10,MSR_RI
150 mtmsrd r10,1
152 mr r10,r1
153 ld r1,PACA_NMI_EMERG_SP(r13)
154 subi r1,r1,INT_FRAME_SIZE
155 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
156 system_reset, system_reset_exception,
157 ADD_NVGPRS;ADD_RECONCILE)
159 /*
160 * The stack is no longer in use, decrement in_nmi.
161 */
162 lhz r10,PACA_IN_NMI(r13)
163 subi r10,r10,1
164 sth r10,PACA_IN_NMI(r13)
166 b ret_from_except
168 #ifdef CONFIG_PPC_PSERIES
169 /*
170 * Vectors for the FWNMI option. Share common code.
171 */
172 TRAMP_REAL_BEGIN(system_reset_fwnmi)
173 SET_SCRATCH0(r13) /* save r13 */
174 /* See comment at system_reset exception */
175 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
176 EXC_STD, NOTEST, 0x100)
177 #endif /* CONFIG_PPC_PSERIES */
180 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
181 /* This is moved out of line as it can be patched by FW, but
182 * some code path might still want to branch into the original
183 * vector
184 */
185 SET_SCRATCH0(r13) /* save r13 */
186 EXCEPTION_PROLOG_0(PACA_EXMC)
187 BEGIN_FTR_SECTION
188 b machine_check_powernv_early
189 FTR_SECTION_ELSE
190 b machine_check_pSeries_0
191 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
192 EXC_REAL_END(machine_check, 0x200, 0x100)
193 EXC_VIRT_NONE(0x4200, 0x100)
194 TRAMP_REAL_BEGIN(machine_check_powernv_early)
195 BEGIN_FTR_SECTION
196 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
197 /*
198 * Register contents:
199 * R13 = PACA
200 * R9 = CR
201 * Original R9 to R13 is saved on PACA_EXMC
202 *
203 * Switch to mc_emergency stack and handle re-entrancy (we limit
204 * the nested MCE upto level 4 to avoid stack overflow).
205 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
206 *
207 * We use paca->in_mce to check whether this is the first entry or
208 * nested machine check. We increment paca->in_mce to track nested
209 * machine checks.
210 *
211 * If this is the first entry then set stack pointer to
212 * paca->mc_emergency_sp, otherwise r1 is already pointing to
213 * stack frame on mc_emergency stack.
214 *
215 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
216 * checkstop if we get another machine check exception before we do
217 * rfid with MSR_ME=1.
218 *
219 * This interrupt can wake directly from idle. If that is the case,
220 * the machine check is handled then the idle wakeup code is called
221 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
222 * is not applied in the early machine check code, which will cause
223 * bugs.
224 */
225 mr r11,r1 /* Save r1 */
226 lhz r10,PACA_IN_MCE(r13)
227 cmpwi r10,0 /* Are we in nested machine check */
228 bne 0f /* Yes, we are. */
229 /* First machine check entry */
230 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
231 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
232 addi r10,r10,1 /* increment paca->in_mce */
233 sth r10,PACA_IN_MCE(r13)
234 /* Limit nested MCE to level 4 to avoid stack overflow */
235 cmpwi r10,4
236 bgt 2f /* Check if we hit limit of 4 */
237 std r11,GPR1(r1) /* Save r1 on the stack. */
238 std r11,0(r1) /* make stack chain pointer */
239 mfspr r11,SPRN_SRR0 /* Save SRR0 */
240 std r11,_NIP(r1)
241 mfspr r11,SPRN_SRR1 /* Save SRR1 */
242 std r11,_MSR(r1)
243 mfspr r11,SPRN_DAR /* Save DAR */
244 std r11,_DAR(r1)
245 mfspr r11,SPRN_DSISR /* Save DSISR */
246 std r11,_DSISR(r1)
247 std r9,_CCR(r1) /* Save CR in stackframe */
248 /* Save r9 through r13 from EXMC save area to stack frame. */
249 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
250 mfmsr r11 /* get MSR value */
251 ori r11,r11,MSR_ME /* turn on ME bit */
252 ori r11,r11,MSR_RI /* turn on RI bit */
253 LOAD_HANDLER(r12, machine_check_handle_early)
254 1: mtspr SPRN_SRR0,r12
255 mtspr SPRN_SRR1,r11
256 rfid
257 b . /* prevent speculative execution */
258 2:
259 /* Stack overflow. Stay on emergency stack and panic.
260 * Keep the ME bit off while panic-ing, so that if we hit
261 * another machine check we checkstop.
262 */
263 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
264 ld r11,PACAKMSR(r13)
265 LOAD_HANDLER(r12, unrecover_mce)
266 li r10,MSR_ME
267 andc r11,r11,r10 /* Turn off MSR_ME */
268 b 1b
269 b . /* prevent speculative execution */
270 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
272 TRAMP_REAL_BEGIN(machine_check_pSeries)
273 .globl machine_check_fwnmi
274 machine_check_fwnmi:
275 SET_SCRATCH0(r13) /* save r13 */
276 EXCEPTION_PROLOG_0(PACA_EXMC)
277 machine_check_pSeries_0:
278 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
279 /*
280 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
281 * nested machine check corrupts it. machine_check_common enables
282 * MSR_RI.
283 */
284 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
286 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
288 EXC_COMMON_BEGIN(machine_check_common)
289 /*
290 * Machine check is different because we use a different
291 * save area: PACA_EXMC instead of PACA_EXGEN.
292 */
293 mfspr r10,SPRN_DAR
294 std r10,PACA_EXMC+EX_DAR(r13)
295 mfspr r10,SPRN_DSISR
296 stw r10,PACA_EXMC+EX_DSISR(r13)
297 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
298 FINISH_NAP
299 RECONCILE_IRQ_STATE(r10, r11)
300 ld r3,PACA_EXMC+EX_DAR(r13)
301 lwz r4,PACA_EXMC+EX_DSISR(r13)
302 /* Enable MSR_RI when finished with PACA_EXMC */
303 li r10,MSR_RI
304 mtmsrd r10,1
305 std r3,_DAR(r1)
306 std r4,_DSISR(r1)
307 bl save_nvgprs
308 addi r3,r1,STACK_FRAME_OVERHEAD
309 bl machine_check_exception
310 b ret_from_except
312 #define MACHINE_CHECK_HANDLER_WINDUP \
313 /* Clear MSR_RI before setting SRR0 and SRR1. */\
314 li r0,MSR_RI; \
315 mfmsr r9; /* get MSR value */ \
316 andc r9,r9,r0; \
317 mtmsrd r9,1; /* Clear MSR_RI */ \
318 /* Move original SRR0 and SRR1 into the respective regs */ \
319 ld r9,_MSR(r1); \
320 mtspr SPRN_SRR1,r9; \
321 ld r3,_NIP(r1); \
322 mtspr SPRN_SRR0,r3; \
323 ld r9,_CTR(r1); \
324 mtctr r9; \
325 ld r9,_XER(r1); \
326 mtxer r9; \
327 ld r9,_LINK(r1); \
328 mtlr r9; \
329 REST_GPR(0, r1); \
330 REST_8GPRS(2, r1); \
331 REST_GPR(10, r1); \
332 ld r11,_CCR(r1); \
333 mtcr r11; \
334 /* Decrement paca->in_mce. */ \
335 lhz r12,PACA_IN_MCE(r13); \
336 subi r12,r12,1; \
337 sth r12,PACA_IN_MCE(r13); \
338 REST_GPR(11, r1); \
339 REST_2GPRS(12, r1); \
340 /* restore original r1. */ \
341 ld r1,GPR1(r1)
343 #ifdef CONFIG_PPC_P7_NAP
344 /*
345 * This is an idle wakeup. Low level machine check has already been
346 * done. Queue the event then call the idle code to do the wake up.
347 */
348 EXC_COMMON_BEGIN(machine_check_idle_common)
349 bl machine_check_queue_event
351 /*
352 * We have not used any non-volatile GPRs here, and as a rule
353 * most exception code including machine check does not.
354 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
355 * wakeup will restore volatile registers.
356 *
357 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
358 *
359 * Then decrement MCE nesting after finishing with the stack.
360 */
361 ld r3,_MSR(r1)
363 lhz r11,PACA_IN_MCE(r13)
364 subi r11,r11,1
365 sth r11,PACA_IN_MCE(r13)
367 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
368 /* Recoverability could be improved by reducing the use of SRR1. */
369 li r11,0
370 mtmsrd r11,1
372 b pnv_powersave_wakeup_mce
373 #endif
374 /*
375 * Handle machine check early in real mode. We come here with
376 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
377 */
378 EXC_COMMON_BEGIN(machine_check_handle_early)
379 std r0,GPR0(r1) /* Save r0 */
380 EXCEPTION_PROLOG_COMMON_3(0x200)
381 bl save_nvgprs
382 addi r3,r1,STACK_FRAME_OVERHEAD
383 bl machine_check_early
384 std r3,RESULT(r1) /* Save result */
385 ld r12,_MSR(r1)
387 #ifdef CONFIG_PPC_P7_NAP
388 /*
389 * Check if thread was in power saving mode. We come here when any
390 * of the following is true:
391 * a. thread wasn't in power saving mode
392 * b. thread was in power saving mode with no state loss,
393 * supervisor state loss or hypervisor state loss.
394 *
395 * Go back to nap/sleep/winkle mode again if (b) is true.
396 */
397 BEGIN_FTR_SECTION
398 rlwinm. r11,r12,47-31,30,31
399 bne machine_check_idle_common
400 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
401 #endif
403 /*
404 * Check if we are coming from hypervisor userspace. If yes then we
405 * continue in host kernel in V mode to deliver the MC event.
406 */
407 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
408 beq 5f
409 andi. r11,r12,MSR_PR /* See if coming from user. */
410 bne 9f /* continue in V mode if we are. */
412 5:
413 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
414 /*
415 * We are coming from kernel context. Check if we are coming from
416 * guest. if yes, then we can continue. We will fall through
417 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
418 */
419 lbz r11,HSTATE_IN_GUEST(r13)
420 cmpwi r11,0 /* Check if coming from guest */
421 bne 9f /* continue if we are. */
422 #endif
423 /*
424 * At this point we are not sure about what context we come from.
425 * Queue up the MCE event and return from the interrupt.
426 * But before that, check if this is an un-recoverable exception.
427 * If yes, then stay on emergency stack and panic.
428 */
429 andi. r11,r12,MSR_RI
430 bne 2f
431 1: mfspr r11,SPRN_SRR0
432 LOAD_HANDLER(r10,unrecover_mce)
433 mtspr SPRN_SRR0,r10
434 ld r10,PACAKMSR(r13)
435 /*
436 * We are going down. But there are chances that we might get hit by
437 * another MCE during panic path and we may run into unstable state
438 * with no way out. Hence, turn ME bit off while going down, so that
439 * when another MCE is hit during panic path, system will checkstop
440 * and hypervisor will get restarted cleanly by SP.
441 */
442 li r3,MSR_ME
443 andc r10,r10,r3 /* Turn off MSR_ME */
444 mtspr SPRN_SRR1,r10
445 rfid
446 b .
447 2:
448 /*
449 * Check if we have successfully handled/recovered from error, if not
450 * then stay on emergency stack and panic.
451 */
452 ld r3,RESULT(r1) /* Load result */
453 cmpdi r3,0 /* see if we handled MCE successfully */
455 beq 1b /* if !handled then panic */
456 /*
457 * Return from MC interrupt.
458 * Queue up the MCE event so that we can log it later, while
459 * returning from kernel or opal call.
460 */
461 bl machine_check_queue_event
462 MACHINE_CHECK_HANDLER_WINDUP
463 rfid
464 9:
465 /* Deliver the machine check to host kernel in V mode. */
466 MACHINE_CHECK_HANDLER_WINDUP
467 b machine_check_pSeries
469 EXC_COMMON_BEGIN(unrecover_mce)
470 /* Invoke machine_check_exception to print MCE event and panic. */
471 addi r3,r1,STACK_FRAME_OVERHEAD
472 bl machine_check_exception
473 /*
474 * We will not reach here. Even if we did, there is no way out. Call
475 * unrecoverable_exception and die.
476 */
477 1: addi r3,r1,STACK_FRAME_OVERHEAD
478 bl unrecoverable_exception
479 b 1b
482 EXC_REAL(data_access, 0x300, 0x80)
483 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
484 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
486 EXC_COMMON_BEGIN(data_access_common)
487 /*
488 * Here r13 points to the paca, r9 contains the saved CR,
489 * SRR0 and SRR1 are saved in r11 and r12,
490 * r9 - r13 are saved in paca->exgen.
491 */
492 mfspr r10,SPRN_DAR
493 std r10,PACA_EXGEN+EX_DAR(r13)
494 mfspr r10,SPRN_DSISR
495 stw r10,PACA_EXGEN+EX_DSISR(r13)
496 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
497 RECONCILE_IRQ_STATE(r10, r11)
498 ld r12,_MSR(r1)
499 ld r3,PACA_EXGEN+EX_DAR(r13)
500 lwz r4,PACA_EXGEN+EX_DSISR(r13)
501 li r5,0x300
502 std r3,_DAR(r1)
503 std r4,_DSISR(r1)
504 BEGIN_MMU_FTR_SECTION
505 b do_hash_page /* Try to handle as hpte fault */
506 MMU_FTR_SECTION_ELSE
507 b handle_page_fault
508 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
511 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
512 SET_SCRATCH0(r13)
513 EXCEPTION_PROLOG_0(PACA_EXSLB)
514 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
515 mr r12,r3 /* save r3 */
516 mfspr r3,SPRN_DAR
517 mfspr r11,SPRN_SRR1
518 crset 4*cr6+eq
519 BRANCH_TO_COMMON(r10, slb_miss_common)
520 EXC_REAL_END(data_access_slb, 0x380, 0x80)
522 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
523 SET_SCRATCH0(r13)
524 EXCEPTION_PROLOG_0(PACA_EXSLB)
525 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
526 mr r12,r3 /* save r3 */
527 mfspr r3,SPRN_DAR
528 mfspr r11,SPRN_SRR1
529 crset 4*cr6+eq
530 BRANCH_TO_COMMON(r10, slb_miss_common)
531 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
532 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
535 EXC_REAL(instruction_access, 0x400, 0x80)
536 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
537 TRAMP_KVM(PACA_EXGEN, 0x400)
539 EXC_COMMON_BEGIN(instruction_access_common)
540 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
541 RECONCILE_IRQ_STATE(r10, r11)
542 ld r12,_MSR(r1)
543 ld r3,_NIP(r1)
544 andis. r4,r12,0x5820
545 li r5,0x400
546 std r3,_DAR(r1)
547 std r4,_DSISR(r1)
548 BEGIN_MMU_FTR_SECTION
549 b do_hash_page /* Try to handle as hpte fault */
550 MMU_FTR_SECTION_ELSE
551 b handle_page_fault
552 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
555 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
556 SET_SCRATCH0(r13)
557 EXCEPTION_PROLOG_0(PACA_EXSLB)
558 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
559 mr r12,r3 /* save r3 */
560 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
561 mfspr r11,SPRN_SRR1
562 crclr 4*cr6+eq
563 BRANCH_TO_COMMON(r10, slb_miss_common)
564 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
566 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
567 SET_SCRATCH0(r13)
568 EXCEPTION_PROLOG_0(PACA_EXSLB)
569 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
570 mr r12,r3 /* save r3 */
571 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
572 mfspr r11,SPRN_SRR1
573 crclr 4*cr6+eq
574 BRANCH_TO_COMMON(r10, slb_miss_common)
575 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
576 TRAMP_KVM(PACA_EXSLB, 0x480)
579 /*
580 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as
581 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled.
582 */
583 EXC_COMMON_BEGIN(slb_miss_common)
584 /*
585 * r13 points to the PACA, r9 contains the saved CR,
586 * r12 contains the saved r3,
587 * r11 contain the saved SRR1, SRR0 is still ready for return
588 * r3 has the faulting address
589 * r9 - r13 are saved in paca->exslb.
590 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
591 * We assume we aren't going to take any exceptions during this
592 * procedure.
593 */
594 mflr r10
595 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
596 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
598 /*
599 * Test MSR_RI before calling slb_allocate_realmode, because the
600 * MSR in r11 gets clobbered. However we still want to allocate
601 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in
602 * recursive SLB faults. So use cr5 for this, which is preserved.
603 */
604 andi. r11,r11,MSR_RI /* check for unrecoverable exception */
605 cmpdi cr5,r11,MSR_RI
607 crset 4*cr0+eq
608 #ifdef CONFIG_PPC_STD_MMU_64
609 BEGIN_MMU_FTR_SECTION
610 bl slb_allocate
611 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
612 #endif
614 ld r10,PACA_EXSLB+EX_LR(r13)
615 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
616 mtlr r10
618 beq- 8f /* if bad address, make full stack frame */
620 bne- cr5,2f /* if unrecoverable exception, oops */
622 /* All done -- return from exception. */
624 .machine push
625 .machine "power4"
626 mtcrf 0x80,r9
627 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
628 mtcrf 0x02,r9 /* I/D indication is in cr6 */
629 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
630 .machine pop
632 RESTORE_CTR(r9, PACA_EXSLB)
633 RESTORE_PPR_PACA(PACA_EXSLB, r9)
634 mr r3,r12
635 ld r9,PACA_EXSLB+EX_R9(r13)
636 ld r10,PACA_EXSLB+EX_R10(r13)
637 ld r11,PACA_EXSLB+EX_R11(r13)
638 ld r12,PACA_EXSLB+EX_R12(r13)
639 ld r13,PACA_EXSLB+EX_R13(r13)
640 rfid
641 b . /* prevent speculative execution */
643 2: std r3,PACA_EXSLB+EX_DAR(r13)
644 mr r3,r12
645 mfspr r11,SPRN_SRR0
646 mfspr r12,SPRN_SRR1
647 LOAD_HANDLER(r10,unrecov_slb)
648 mtspr SPRN_SRR0,r10
649 ld r10,PACAKMSR(r13)
650 mtspr SPRN_SRR1,r10
651 rfid
652 b .
654 8: std r3,PACA_EXSLB+EX_DAR(r13)
655 mr r3,r12
656 mfspr r11,SPRN_SRR0
657 mfspr r12,SPRN_SRR1
658 LOAD_HANDLER(r10,bad_addr_slb)
659 mtspr SPRN_SRR0,r10
660 ld r10,PACAKMSR(r13)
661 mtspr SPRN_SRR1,r10
662 rfid
663 b .
665 EXC_COMMON_BEGIN(unrecov_slb)
666 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
667 RECONCILE_IRQ_STATE(r10, r11)
668 bl save_nvgprs
669 1: addi r3,r1,STACK_FRAME_OVERHEAD
670 bl unrecoverable_exception
671 b 1b
673 EXC_COMMON_BEGIN(bad_addr_slb)
674 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
675 RECONCILE_IRQ_STATE(r10, r11)
676 ld r3, PACA_EXSLB+EX_DAR(r13)
677 std r3, _DAR(r1)
678 beq cr6, 2f
679 li r10, 0x480 /* fix trap number for I-SLB miss */
680 std r10, _TRAP(r1)
681 2: bl save_nvgprs
682 addi r3, r1, STACK_FRAME_OVERHEAD
683 bl slb_miss_bad_addr
684 b ret_from_except
686 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
687 .globl hardware_interrupt_hv;
688 hardware_interrupt_hv:
689 BEGIN_FTR_SECTION
690 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
691 EXC_HV, SOFTEN_TEST_HV)
692 FTR_SECTION_ELSE
693 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
694 EXC_STD, SOFTEN_TEST_PR)
695 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
696 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
698 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
699 .globl hardware_interrupt_relon_hv;
700 hardware_interrupt_relon_hv:
701 BEGIN_FTR_SECTION
702 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
703 FTR_SECTION_ELSE
704 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
705 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
706 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
708 TRAMP_KVM(PACA_EXGEN, 0x500)
709 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
710 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
713 EXC_REAL(alignment, 0x600, 0x100)
714 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
715 TRAMP_KVM(PACA_EXGEN, 0x600)
716 EXC_COMMON_BEGIN(alignment_common)
717 mfspr r10,SPRN_DAR
718 std r10,PACA_EXGEN+EX_DAR(r13)
719 mfspr r10,SPRN_DSISR
720 stw r10,PACA_EXGEN+EX_DSISR(r13)
721 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
722 ld r3,PACA_EXGEN+EX_DAR(r13)
723 lwz r4,PACA_EXGEN+EX_DSISR(r13)
724 std r3,_DAR(r1)
725 std r4,_DSISR(r1)
726 bl save_nvgprs
727 RECONCILE_IRQ_STATE(r10, r11)
728 addi r3,r1,STACK_FRAME_OVERHEAD
729 bl alignment_exception
730 b ret_from_except
733 EXC_REAL(program_check, 0x700, 0x100)
734 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
735 TRAMP_KVM(PACA_EXGEN, 0x700)
736 EXC_COMMON_BEGIN(program_check_common)
737 /*
738 * It's possible to receive a TM Bad Thing type program check with
739 * userspace register values (in particular r1), but with SRR1 reporting
740 * that we came from the kernel. Normally that would confuse the bad
741 * stack logic, and we would report a bad kernel stack pointer. Instead
742 * we switch to the emergency stack if we're taking a TM Bad Thing from
743 * the kernel.
744 */
745 li r10,MSR_PR /* Build a mask of MSR_PR .. */
746 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */
747 and r10,r10,r12 /* Mask SRR1 with that. */
748 srdi r10,r10,8 /* Shift it so we can compare */
749 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */
750 bne 1f /* If != go to normal path. */
752 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */
753 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */
754 /* 3 in EXCEPTION_PROLOG_COMMON */
755 mr r10,r1 /* Save r1 */
756 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
757 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
758 b 3f /* Jump into the macro !! */
759 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
760 bl save_nvgprs
761 RECONCILE_IRQ_STATE(r10, r11)
762 addi r3,r1,STACK_FRAME_OVERHEAD
763 bl program_check_exception
764 b ret_from_except
767 EXC_REAL(fp_unavailable, 0x800, 0x100)
768 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
769 TRAMP_KVM(PACA_EXGEN, 0x800)
770 EXC_COMMON_BEGIN(fp_unavailable_common)
771 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
772 bne 1f /* if from user, just load it up */
773 bl save_nvgprs
774 RECONCILE_IRQ_STATE(r10, r11)
775 addi r3,r1,STACK_FRAME_OVERHEAD
776 bl kernel_fp_unavailable_exception
777 BUG_OPCODE
778 1:
779 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
780 BEGIN_FTR_SECTION
781 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
782 * transaction), go do TM stuff
783 */
784 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
785 bne- 2f
786 END_FTR_SECTION_IFSET(CPU_FTR_TM)
787 #endif
788 bl load_up_fpu
789 b fast_exception_return
790 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
791 2: /* User process was in a transaction */
792 bl save_nvgprs
793 RECONCILE_IRQ_STATE(r10, r11)
794 addi r3,r1,STACK_FRAME_OVERHEAD
795 bl fp_unavailable_tm
796 b ret_from_except
797 #endif
800 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
801 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
802 TRAMP_KVM(PACA_EXGEN, 0x900)
803 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
806 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
807 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
808 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
809 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
812 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100)
813 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00)
814 TRAMP_KVM(PACA_EXGEN, 0xa00)
815 #ifdef CONFIG_PPC_DOORBELL
816 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
817 #else
818 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
819 #endif
822 EXC_REAL(trap_0b, 0xb00, 0x100)
823 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
824 TRAMP_KVM(PACA_EXGEN, 0xb00)
825 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
827 /*
828 * system call / hypercall (0xc00, 0x4c00)
829 *
830 * The system call exception is invoked with "sc 0" and does not alter HV bit.
831 * There is support for kernel code to invoke system calls but there are no
832 * in-tree users.
833 *
834 * The hypercall is invoked with "sc 1" and sets HV=1.
835 *
836 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
837 * 0x4c00 virtual mode.
838 *
839 * Call convention:
840 *
841 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
842 *
843 * For hypercalls, the register convention is as follows:
844 * r0 volatile
845 * r1-2 nonvolatile
846 * r3 volatile parameter and return value for status
847 * r4-r10 volatile input and output value
848 * r11 volatile hypercall number and output value
849 * r12 volatile input and output value
850 * r13-r31 nonvolatile
851 * LR nonvolatile
852 * CTR volatile
853 * XER volatile
854 * CR0-1 CR5-7 volatile
855 * CR2-4 nonvolatile
856 * Other registers nonvolatile
857 *
858 * The intersection of volatile registers that don't contain possible
859 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
860 * without saving, though xer is not a good idea to use, as hardware may
861 * interpret some bits so it may be costly to change them.
862 */
863 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
864 /*
865 * There is a little bit of juggling to get syscall and hcall
866 * working well. Save r13 in ctr to avoid using SPRG scratch
867 * register.
868 *
869 * Userspace syscalls have already saved the PPR, hcalls must save
870 * it before setting HMT_MEDIUM.
871 */
872 #define SYSCALL_KVMTEST \
873 mtctr r13; \
874 GET_PACA(r13); \
875 std r10,PACA_EXGEN+EX_R10(r13); \
876 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
877 HMT_MEDIUM; \
878 mfctr r9;
880 #else
881 #define SYSCALL_KVMTEST \
882 HMT_MEDIUM; \
883 mr r9,r13; \
884 GET_PACA(r13);
885 #endif
887 #define LOAD_SYSCALL_HANDLER(reg) \
888 __LOAD_HANDLER(reg, system_call_common)
890 #define SYSCALL_FASTENDIAN_TEST \
891 BEGIN_FTR_SECTION \
892 cmpdi r0,0x1ebe ; \
893 beq- 1f ; \
894 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
896 /*
897 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
898 * and HMT_MEDIUM.
899 */
900 #define SYSCALL_REAL \
901 mfspr r11,SPRN_SRR0 ; \
902 mfspr r12,SPRN_SRR1 ; \
903 LOAD_SYSCALL_HANDLER(r10) ; \
904 mtspr SPRN_SRR0,r10 ; \
905 ld r10,PACAKMSR(r13) ; \
906 mtspr SPRN_SRR1,r10 ; \
907 rfid ; \
908 b . ; /* prevent speculative execution */
910 #define SYSCALL_FASTENDIAN \
911 /* Fast LE/BE switch system call */ \
912 1: mfspr r12,SPRN_SRR1 ; \
913 xori r12,r12,MSR_LE ; \
914 mtspr SPRN_SRR1,r12 ; \
915 mr r13,r9 ; \
916 rfid ; /* return to userspace */ \
917 b . ; /* prevent speculative execution */
919 #if defined(CONFIG_RELOCATABLE)
920 /*
921 * We can't branch directly so we do it via the CTR which
922 * is volatile across system calls.
923 */
924 #define SYSCALL_VIRT \
925 LOAD_SYSCALL_HANDLER(r10) ; \
926 mtctr r10 ; \
927 mfspr r11,SPRN_SRR0 ; \
928 mfspr r12,SPRN_SRR1 ; \
929 li r10,MSR_RI ; \
930 mtmsrd r10,1 ; \
931 bctr ;
932 #else
933 /* We can branch directly */
934 #define SYSCALL_VIRT \
935 mfspr r11,SPRN_SRR0 ; \
936 mfspr r12,SPRN_SRR1 ; \
937 li r10,MSR_RI ; \
938 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
939 b system_call_common ;
940 #endif
942 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
943 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
944 SYSCALL_FASTENDIAN_TEST
945 SYSCALL_REAL
946 SYSCALL_FASTENDIAN
947 EXC_REAL_END(system_call, 0xc00, 0x100)
949 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
950 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
951 SYSCALL_FASTENDIAN_TEST
952 SYSCALL_VIRT
953 SYSCALL_FASTENDIAN
954 EXC_VIRT_END(system_call, 0x4c00, 0x100)
956 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
957 /*
958 * This is a hcall, so register convention is as above, with these
959 * differences:
960 * r13 = PACA
961 * ctr = orig r13
962 * orig r10 saved in PACA
963 */
964 TRAMP_KVM_BEGIN(do_kvm_0xc00)
965 /*
966 * Save the PPR (on systems that support it) before changing to
967 * HMT_MEDIUM. That allows the KVM code to save that value into the
968 * guest state (it is the guest's PPR value).
969 */
970 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
971 HMT_MEDIUM
972 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
973 mfctr r10
974 SET_SCRATCH0(r10)
975 std r9,PACA_EXGEN+EX_R9(r13)
976 mfcr r9
977 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
978 #endif
981 EXC_REAL(single_step, 0xd00, 0x100)
982 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
983 TRAMP_KVM(PACA_EXGEN, 0xd00)
984 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
986 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
987 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
988 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
989 EXC_COMMON_BEGIN(h_data_storage_common)
990 mfspr r10,SPRN_HDAR
991 std r10,PACA_EXGEN+EX_DAR(r13)
992 mfspr r10,SPRN_HDSISR
993 stw r10,PACA_EXGEN+EX_DSISR(r13)
994 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
995 bl save_nvgprs
996 RECONCILE_IRQ_STATE(r10, r11)
997 addi r3,r1,STACK_FRAME_OVERHEAD
998 bl unknown_exception
999 b ret_from_except
1002 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1003 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1004 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1005 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1008 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1009 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1010 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1011 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1014 /*
1015 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1016 * first, and then eventaully from there to the trampoline to get into virtual
1017 * mode.
1018 */
1019 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1020 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
1021 EXC_VIRT_NONE(0x4e60, 0x20)
1022 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1023 TRAMP_REAL_BEGIN(hmi_exception_early)
1024 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1025 mr r10,r1 /* Save r1 */
1026 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1027 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1028 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1029 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1030 EXCEPTION_PROLOG_COMMON_1()
1031 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1032 EXCEPTION_PROLOG_COMMON_3(0xe60)
1033 addi r3,r1,STACK_FRAME_OVERHEAD
1034 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
1035 /* Windup the stack. */
1036 /* Move original HSRR0 and HSRR1 into the respective regs */
1037 ld r9,_MSR(r1)
1038 mtspr SPRN_HSRR1,r9
1039 ld r3,_NIP(r1)
1040 mtspr SPRN_HSRR0,r3
1041 ld r9,_CTR(r1)
1042 mtctr r9
1043 ld r9,_XER(r1)
1044 mtxer r9
1045 ld r9,_LINK(r1)
1046 mtlr r9
1047 REST_GPR(0, r1)
1048 REST_8GPRS(2, r1)
1049 REST_GPR(10, r1)
1050 ld r11,_CCR(r1)
1051 mtcr r11
1052 REST_GPR(11, r1)
1053 REST_2GPRS(12, r1)
1054 /* restore original r1. */
1055 ld r1,GPR1(r1)
1057 /*
1058 * Go to virtual mode and pull the HMI event information from
1059 * firmware.
1060 */
1061 .globl hmi_exception_after_realmode
1062 hmi_exception_after_realmode:
1063 SET_SCRATCH0(r13)
1064 EXCEPTION_PROLOG_0(PACA_EXGEN)
1065 b tramp_real_hmi_exception
1067 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1070 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20)
1071 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80)
1072 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1073 #ifdef CONFIG_PPC_DOORBELL
1074 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1075 #else
1076 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1077 #endif
1080 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20)
1081 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0)
1082 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1083 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1086 EXC_REAL_NONE(0xec0, 0x20)
1087 EXC_VIRT_NONE(0x4ec0, 0x20)
1088 EXC_REAL_NONE(0xee0, 0x20)
1089 EXC_VIRT_NONE(0x4ee0, 0x20)
1092 EXC_REAL_OOL(performance_monitor, 0xf00, 0x20)
1093 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00)
1094 TRAMP_KVM(PACA_EXGEN, 0xf00)
1095 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1098 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1099 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1100 TRAMP_KVM(PACA_EXGEN, 0xf20)
1101 EXC_COMMON_BEGIN(altivec_unavailable_common)
1102 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1103 #ifdef CONFIG_ALTIVEC
1104 BEGIN_FTR_SECTION
1105 beq 1f
1106 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1107 BEGIN_FTR_SECTION_NESTED(69)
1108 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1109 * transaction), go do TM stuff
1110 */
1111 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1112 bne- 2f
1113 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1114 #endif
1115 bl load_up_altivec
1116 b fast_exception_return
1117 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1118 2: /* User process was in a transaction */
1119 bl save_nvgprs
1120 RECONCILE_IRQ_STATE(r10, r11)
1121 addi r3,r1,STACK_FRAME_OVERHEAD
1122 bl altivec_unavailable_tm
1123 b ret_from_except
1124 #endif
1125 1:
1126 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1127 #endif
1128 bl save_nvgprs
1129 RECONCILE_IRQ_STATE(r10, r11)
1130 addi r3,r1,STACK_FRAME_OVERHEAD
1131 bl altivec_unavailable_exception
1132 b ret_from_except
1135 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1136 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1137 TRAMP_KVM(PACA_EXGEN, 0xf40)
1138 EXC_COMMON_BEGIN(vsx_unavailable_common)
1139 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1140 #ifdef CONFIG_VSX
1141 BEGIN_FTR_SECTION
1142 beq 1f
1143 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1144 BEGIN_FTR_SECTION_NESTED(69)
1145 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1146 * transaction), go do TM stuff
1147 */
1148 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1149 bne- 2f
1150 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1151 #endif
1152 b load_up_vsx
1153 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1154 2: /* User process was in a transaction */
1155 bl save_nvgprs
1156 RECONCILE_IRQ_STATE(r10, r11)
1157 addi r3,r1,STACK_FRAME_OVERHEAD
1158 bl vsx_unavailable_tm
1159 b ret_from_except
1160 #endif
1161 1:
1162 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1163 #endif
1164 bl save_nvgprs
1165 RECONCILE_IRQ_STATE(r10, r11)
1166 addi r3,r1,STACK_FRAME_OVERHEAD
1167 bl vsx_unavailable_exception
1168 b ret_from_except
1171 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1172 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1173 TRAMP_KVM(PACA_EXGEN, 0xf60)
1174 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1177 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1178 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1179 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1180 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1183 EXC_REAL_NONE(0xfa0, 0x20)
1184 EXC_VIRT_NONE(0x4fa0, 0x20)
1185 EXC_REAL_NONE(0xfc0, 0x20)
1186 EXC_VIRT_NONE(0x4fc0, 0x20)
1187 EXC_REAL_NONE(0xfe0, 0x20)
1188 EXC_VIRT_NONE(0x4fe0, 0x20)
1190 EXC_REAL_NONE(0x1000, 0x100)
1191 EXC_VIRT_NONE(0x5000, 0x100)
1192 EXC_REAL_NONE(0x1100, 0x100)
1193 EXC_VIRT_NONE(0x5100, 0x100)
1195 #ifdef CONFIG_CBE_RAS
1196 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1197 EXC_VIRT_NONE(0x5200, 0x100)
1198 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1199 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1200 #else /* CONFIG_CBE_RAS */
1201 EXC_REAL_NONE(0x1200, 0x100)
1202 EXC_VIRT_NONE(0x5200, 0x100)
1203 #endif
1206 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1207 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1208 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1209 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1211 EXC_REAL_NONE(0x1400, 0x100)
1212 EXC_VIRT_NONE(0x5400, 0x100)
1214 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1215 mtspr SPRN_SPRG_HSCRATCH0,r13
1216 EXCEPTION_PROLOG_0(PACA_EXGEN)
1217 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1219 #ifdef CONFIG_PPC_DENORMALISATION
1220 mfspr r10,SPRN_HSRR1
1221 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1222 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1223 addi r11,r11,-4 /* HSRR0 is next instruction */
1224 bne+ denorm_assist
1225 #endif
1227 KVMTEST_PR(0x1500)
1228 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1229 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1231 #ifdef CONFIG_PPC_DENORMALISATION
1232 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1233 b exc_real_0x1500_denorm_exception_hv
1234 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1235 #else
1236 EXC_VIRT_NONE(0x5500, 0x100)
1237 #endif
1239 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1241 #ifdef CONFIG_PPC_DENORMALISATION
1242 TRAMP_REAL_BEGIN(denorm_assist)
1243 BEGIN_FTR_SECTION
1244 /*
1245 * To denormalise we need to move a copy of the register to itself.
1246 * For POWER6 do that here for all FP regs.
1247 */
1248 mfmsr r10
1249 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1250 xori r10,r10,(MSR_FE0|MSR_FE1)
1251 mtmsrd r10
1252 sync
1254 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1255 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1256 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1257 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1258 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1259 FMR32(0)
1261 FTR_SECTION_ELSE
1262 /*
1263 * To denormalise we need to move a copy of the register to itself.
1264 * For POWER7 do that here for the first 32 VSX registers only.
1265 */
1266 mfmsr r10
1267 oris r10,r10,MSR_VSX@h
1268 mtmsrd r10
1269 sync
1271 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1272 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1273 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1274 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1275 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1276 XVCPSGNDP32(0)
1278 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1280 BEGIN_FTR_SECTION
1281 b denorm_done
1282 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1283 /*
1284 * To denormalise we need to move a copy of the register to itself.
1285 * For POWER8 we need to do that for all 64 VSX registers
1286 */
1287 XVCPSGNDP32(32)
1288 denorm_done:
1289 mtspr SPRN_HSRR0,r11
1290 mtcrf 0x80,r9
1291 ld r9,PACA_EXGEN+EX_R9(r13)
1292 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1293 BEGIN_FTR_SECTION
1294 ld r10,PACA_EXGEN+EX_CFAR(r13)
1295 mtspr SPRN_CFAR,r10
1296 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1297 ld r10,PACA_EXGEN+EX_R10(r13)
1298 ld r11,PACA_EXGEN+EX_R11(r13)
1299 ld r12,PACA_EXGEN+EX_R12(r13)
1300 ld r13,PACA_EXGEN+EX_R13(r13)
1301 HRFID
1302 b .
1303 #endif
1305 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1308 #ifdef CONFIG_CBE_RAS
1309 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1310 EXC_VIRT_NONE(0x5600, 0x100)
1311 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1312 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1313 #else /* CONFIG_CBE_RAS */
1314 EXC_REAL_NONE(0x1600, 0x100)
1315 EXC_VIRT_NONE(0x5600, 0x100)
1316 #endif
1319 EXC_REAL(altivec_assist, 0x1700, 0x100)
1320 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1321 TRAMP_KVM(PACA_EXGEN, 0x1700)
1322 #ifdef CONFIG_ALTIVEC
1323 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1324 #else
1325 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1326 #endif
1329 #ifdef CONFIG_CBE_RAS
1330 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1331 EXC_VIRT_NONE(0x5800, 0x100)
1332 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1333 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1334 #else /* CONFIG_CBE_RAS */
1335 EXC_REAL_NONE(0x1800, 0x100)
1336 EXC_VIRT_NONE(0x5800, 0x100)
1337 #endif
1339 #if defined(CONFIG_HARDLOCKUP_DETECTOR) && defined(CONFIG_HAVE_HARDLOCKUP_DETECTOR_ARCH)
1341 #define MASKED_DEC_HANDLER_LABEL 3f
1343 #define MASKED_DEC_HANDLER(_H) \
1344 3: /* soft-nmi */ \
1345 std r12,PACA_EXGEN+EX_R12(r13); \
1346 GET_SCRATCH0(r10); \
1347 std r10,PACA_EXGEN+EX_R13(r13); \
1348 EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H)
1350 /*
1351 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1352 * stack is one that is usable by maskable interrupts so long as MSR_EE
1353 * remains off. It is used for recovery when something has corrupted the
1354 * normal kernel stack, for example. The "soft NMI" must not use the process
1355 * stack because we want irq disabled sections to avoid touching the stack
1356 * at all (other than PMU interrupts), so use the emergency stack for this,
1357 * and run it entirely with interrupts hard disabled.
1358 */
1359 EXC_COMMON_BEGIN(soft_nmi_common)
1360 mr r10,r1
1361 ld r1,PACAEMERGSP(r13)
1362 subi r1,r1,INT_FRAME_SIZE
1363 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
1364 system_reset, soft_nmi_interrupt,
1365 ADD_NVGPRS;ADD_RECONCILE)
1366 b ret_from_except
1368 #else
1369 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1370 #define MASKED_DEC_HANDLER(_H)
1371 #endif
1373 /*
1374 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1375 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1376 * - If it was a doorbell we return immediately since doorbells are edge
1377 * triggered and won't automatically refire.
1378 * - If it was a HMI we return immediately since we handled it in realmode
1379 * and it won't refire.
1380 * - else we hard disable and return.
1381 * This is called with r10 containing the value to OR to the paca field.
1382 */
1383 #define MASKED_INTERRUPT(_H) \
1384 masked_##_H##interrupt: \
1385 std r11,PACA_EXGEN+EX_R11(r13); \
1386 lbz r11,PACAIRQHAPPENED(r13); \
1387 or r11,r11,r10; \
1388 stb r11,PACAIRQHAPPENED(r13); \
1389 cmpwi r10,PACA_IRQ_DEC; \
1390 bne 1f; \
1391 lis r10,0x7fff; \
1392 ori r10,r10,0xffff; \
1393 mtspr SPRN_DEC,r10; \
1394 b MASKED_DEC_HANDLER_LABEL; \
1395 1: cmpwi r10,PACA_IRQ_DBELL; \
1396 beq 2f; \
1397 cmpwi r10,PACA_IRQ_HMI; \
1398 beq 2f; \
1399 mfspr r10,SPRN_##_H##SRR1; \
1400 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1401 rotldi r10,r10,16; \
1402 mtspr SPRN_##_H##SRR1,r10; \
1403 2: mtcrf 0x80,r9; \
1404 ld r9,PACA_EXGEN+EX_R9(r13); \
1405 ld r10,PACA_EXGEN+EX_R10(r13); \
1406 ld r11,PACA_EXGEN+EX_R11(r13); \
1407 GET_SCRATCH0(r13); \
1408 ##_H##rfid; \
1409 b .; \
1410 MASKED_DEC_HANDLER(_H)
1412 /*
1413 * Real mode exceptions actually use this too, but alternate
1414 * instruction code patches (which end up in the common .text area)
1415 * cannot reach these if they are put there.
1416 */
1417 USE_FIXED_SECTION(virt_trampolines)
1418 MASKED_INTERRUPT()
1419 MASKED_INTERRUPT(H)
1421 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1422 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1423 /*
1424 * Here all GPRs are unchanged from when the interrupt happened
1425 * except for r13, which is saved in SPRG_SCRATCH0.
1426 */
1427 mfspr r13, SPRN_SRR0
1428 addi r13, r13, 4
1429 mtspr SPRN_SRR0, r13
1430 GET_SCRATCH0(r13)
1431 rfid
1432 b .
1434 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1435 /*
1436 * Here all GPRs are unchanged from when the interrupt happened
1437 * except for r13, which is saved in SPRG_SCRATCH0.
1438 */
1439 mfspr r13, SPRN_HSRR0
1440 addi r13, r13, 4
1441 mtspr SPRN_HSRR0, r13
1442 GET_SCRATCH0(r13)
1443 hrfid
1444 b .
1445 #endif
1447 /*
1448 * Ensure that any handlers that get invoked from the exception prologs
1449 * above are below the first 64KB (0x10000) of the kernel image because
1450 * the prologs assemble the addresses of these handlers using the
1451 * LOAD_HANDLER macro, which uses an ori instruction.
1452 */
1454 /*** Common interrupt handlers ***/
1457 /*
1458 * Relocation-on interrupts: A subset of the interrupts can be delivered
1459 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1460 * it. Addresses are the same as the original interrupt addresses, but
1461 * offset by 0xc000000000004000.
1462 * It's impossible to receive interrupts below 0x300 via this mechanism.
1463 * KVM: None of these traps are from the guest ; anything that escalated
1464 * to HV=1 from HV=0 is delivered via real mode handlers.
1465 */
1467 /*
1468 * This uses the standard macro, since the original 0x300 vector
1469 * only has extra guff for STAB-based processors -- which never
1470 * come here.
1471 */
1473 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1474 b __ppc64_runlatch_on
1476 USE_FIXED_SECTION(virt_trampolines)
1477 /*
1478 * The __end_interrupts marker must be past the out-of-line (OOL)
1479 * handlers, so that they are copied to real address 0x100 when running
1480 * a relocatable kernel. This ensures they can be reached from the short
1481 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1482 * directly, without using LOAD_HANDLER().
1483 */
1484 .align 7
1485 .globl __end_interrupts
1486 __end_interrupts:
1487 DEFINE_FIXED_SYMBOL(__end_interrupts)
1489 #ifdef CONFIG_PPC_970_NAP
1490 EXC_COMMON_BEGIN(power4_fixup_nap)
1491 andc r9,r9,r10
1492 std r9,TI_LOCAL_FLAGS(r11)
1493 ld r10,_LINK(r1) /* make idle task do the */
1494 std r10,_NIP(r1) /* equivalent of a blr */
1495 blr
1496 #endif
1498 CLOSE_FIXED_SECTION(real_vectors);
1499 CLOSE_FIXED_SECTION(real_trampolines);
1500 CLOSE_FIXED_SECTION(virt_vectors);
1501 CLOSE_FIXED_SECTION(virt_trampolines);
1503 USE_TEXT_SECTION()
1505 /*
1506 * Hash table stuff
1507 */
1508 .balign IFETCH_ALIGN_BYTES
1509 do_hash_page:
1510 #ifdef CONFIG_PPC_STD_MMU_64
1511 andis. r0,r4,0xa450 /* weird error? */
1512 bne- handle_page_fault /* if not, try to insert a HPTE */
1513 CURRENT_THREAD_INFO(r11, r1)
1514 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1515 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1516 bne 77f /* then don't call hash_page now */
1518 /*
1519 * r3 contains the faulting address
1520 * r4 msr
1521 * r5 contains the trap number
1522 * r6 contains dsisr
1523 *
1524 * at return r3 = 0 for success, 1 for page fault, negative for error
1525 */
1526 mr r4,r12
1527 ld r6,_DSISR(r1)
1528 bl __hash_page /* build HPTE if possible */
1529 cmpdi r3,0 /* see if __hash_page succeeded */
1531 /* Success */
1532 beq fast_exc_return_irq /* Return from exception on success */
1534 /* Error */
1535 blt- 13f
1537 /* Reload DSISR into r4 for the DABR check below */
1538 ld r4,_DSISR(r1)
1539 #endif /* CONFIG_PPC_STD_MMU_64 */
1541 /* Here we have a page fault that hash_page can't handle. */
1542 handle_page_fault:
1543 11: andis. r0,r4,DSISR_DABRMATCH@h
1544 bne- handle_dabr_fault
1545 ld r4,_DAR(r1)
1546 ld r5,_DSISR(r1)
1547 addi r3,r1,STACK_FRAME_OVERHEAD
1548 bl do_page_fault
1549 cmpdi r3,0
1550 beq+ 12f
1551 bl save_nvgprs
1552 mr r5,r3
1553 addi r3,r1,STACK_FRAME_OVERHEAD
1554 lwz r4,_DAR(r1)
1555 bl bad_page_fault
1556 b ret_from_except
1558 /* We have a data breakpoint exception - handle it */
1559 handle_dabr_fault:
1560 bl save_nvgprs
1561 ld r4,_DAR(r1)
1562 ld r5,_DSISR(r1)
1563 addi r3,r1,STACK_FRAME_OVERHEAD
1564 bl do_break
1565 12: b ret_from_except_lite
1568 #ifdef CONFIG_PPC_STD_MMU_64
1569 /* We have a page fault that hash_page could handle but HV refused
1570 * the PTE insertion
1571 */
1572 13: bl save_nvgprs
1573 mr r5,r3
1574 addi r3,r1,STACK_FRAME_OVERHEAD
1575 ld r4,_DAR(r1)
1576 bl low_hash_fault
1577 b ret_from_except
1578 #endif
1580 /*
1581 * We come here as a result of a DSI at a point where we don't want
1582 * to call hash_page, such as when we are accessing memory (possibly
1583 * user memory) inside a PMU interrupt that occurred while interrupts
1584 * were soft-disabled. We want to invoke the exception handler for
1585 * the access, or panic if there isn't a handler.
1586 */
1587 77: bl save_nvgprs
1588 mr r4,r3
1589 addi r3,r1,STACK_FRAME_OVERHEAD
1590 li r5,SIGSEGV
1591 bl bad_page_fault
1592 b ret_from_except
1594 /*
1595 * Here we have detected that the kernel stack pointer is bad.
1596 * R9 contains the saved CR, r13 points to the paca,
1597 * r10 contains the (bad) kernel stack pointer,
1598 * r11 and r12 contain the saved SRR0 and SRR1.
1599 * We switch to using an emergency stack, save the registers there,
1600 * and call kernel_bad_stack(), which panics.
1601 */
1602 bad_stack:
1603 ld r1,PACAEMERGSP(r13)
1604 subi r1,r1,64+INT_FRAME_SIZE
1605 std r9,_CCR(r1)
1606 std r10,GPR1(r1)
1607 std r11,_NIP(r1)
1608 std r12,_MSR(r1)
1609 mfspr r11,SPRN_DAR
1610 mfspr r12,SPRN_DSISR
1611 std r11,_DAR(r1)
1612 std r12,_DSISR(r1)
1613 mflr r10
1614 mfctr r11
1615 mfxer r12
1616 std r10,_LINK(r1)
1617 std r11,_CTR(r1)
1618 std r12,_XER(r1)
1619 SAVE_GPR(0,r1)
1620 SAVE_GPR(2,r1)
1621 ld r10,EX_R3(r3)
1622 std r10,GPR3(r1)
1623 SAVE_GPR(4,r1)
1624 SAVE_4GPRS(5,r1)
1625 ld r9,EX_R9(r3)
1626 ld r10,EX_R10(r3)
1627 SAVE_2GPRS(9,r1)
1628 ld r9,EX_R11(r3)
1629 ld r10,EX_R12(r3)
1630 ld r11,EX_R13(r3)
1631 std r9,GPR11(r1)
1632 std r10,GPR12(r1)
1633 std r11,GPR13(r1)
1634 BEGIN_FTR_SECTION
1635 ld r10,EX_CFAR(r3)
1636 std r10,ORIG_GPR3(r1)
1637 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1638 SAVE_8GPRS(14,r1)
1639 SAVE_10GPRS(22,r1)
1640 lhz r12,PACA_TRAP_SAVE(r13)
1641 std r12,_TRAP(r1)
1642 addi r11,r1,INT_FRAME_SIZE
1643 std r11,0(r1)
1644 li r12,0
1645 std r12,0(r11)
1646 ld r2,PACATOC(r13)
1647 ld r11,exception_marker@toc(r2)
1648 std r12,RESULT(r1)
1649 std r11,STACK_FRAME_OVERHEAD-16(r1)
1650 1: addi r3,r1,STACK_FRAME_OVERHEAD
1651 bl kernel_bad_stack
1652 b 1b
1653 _ASM_NOKPROBE_SYMBOL(bad_stack);
1655 /*
1656 * When doorbell is triggered from system reset wakeup, the message is
1657 * not cleared, so it would fire again when EE is enabled.
1658 *
1659 * When coming from local_irq_enable, there may be the same problem if
1660 * we were hard disabled.
1661 *
1662 * Execute msgclr to clear pending exceptions before handling it.
1663 */
1664 h_doorbell_common_msgclr:
1665 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1666 PPC_MSGCLR(3)
1667 b h_doorbell_common
1669 doorbell_super_common_msgclr:
1670 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1671 PPC_MSGCLRP(3)
1672 b doorbell_super_common
1674 /*
1675 * Called from arch_local_irq_enable when an interrupt needs
1676 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1677 * which kind of interrupt. MSR:EE is already off. We generate a
1678 * stackframe like if a real interrupt had happened.
1679 *
1680 * Note: While MSR:EE is off, we need to make sure that _MSR
1681 * in the generated frame has EE set to 1 or the exception
1682 * handler will not properly re-enable them.
1683 *
1684 * Note that we don't specify LR as the NIP (return address) for
1685 * the interrupt because that would unbalance the return branch
1686 * predictor.
1687 */
1688 _GLOBAL(__replay_interrupt)
1689 /* We are going to jump to the exception common code which
1690 * will retrieve various register values from the PACA which
1691 * we don't give a damn about, so we don't bother storing them.
1692 */
1693 mfmsr r12
1694 LOAD_REG_ADDR(r11, 1f)
1695 mfcr r9
1696 ori r12,r12,MSR_EE
1697 cmpwi r3,0x900
1698 beq decrementer_common
1699 cmpwi r3,0x500
1700 beq hardware_interrupt_common
1701 BEGIN_FTR_SECTION
1702 cmpwi r3,0xe80
1703 beq h_doorbell_common_msgclr
1704 cmpwi r3,0xea0
1705 beq h_virt_irq_common
1706 cmpwi r3,0xe60
1707 beq hmi_exception_common
1708 FTR_SECTION_ELSE
1709 cmpwi r3,0xa00
1710 beq doorbell_super_common_msgclr
1711 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1712 1:
1713 blr
1715 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)