2 * Derived from arch/i386/kernel/irq.c
3 * Copyright (C) 1992 Linus Torvalds
4 * Adapted from arch/i386 by Gary Thomas
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Updated and modified by Cort Dougan <cort@fsmlabs.com>
7 * Copyright (C) 1996-2001 Cort Dougan
8 * Adapted for Power Macintosh by Paul Mackerras
9 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
16 * This file contains the code used by various IRQ handling routines:
17 * asking for different IRQ's should be done through these routines
18 * instead of just grabbing them. Thus setups with different IRQ numbers
19 * shouldn't result in any weird surprises, and installing new handlers
22 * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the
23 * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit
24 * mask register (of which only 16 are defined), hence the weird shifting
25 * and complement of the cached_irq_mask. I want to be able to stuff
26 * this right into the SIU SMASK register.
27 * Many of the prep/chrp functions are conditional compiled on CONFIG_8xx
28 * to reduce code space and undefined function references.
33 #include <linux/export.h>
34 #include <linux/threads.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/signal.h>
37 #include <linux/sched.h>
38 #include <linux/ptrace.h>
39 #include <linux/ioport.h>
40 #include <linux/interrupt.h>
41 #include <linux/timex.h>
42 #include <linux/init.h>
43 #include <linux/slab.h>
44 #include <linux/delay.h>
45 #include <linux/irq.h>
46 #include <linux/seq_file.h>
47 #include <linux/cpumask.h>
48 #include <linux/profile.h>
49 #include <linux/bitops.h>
50 #include <linux/list.h>
51 #include <linux/radix-tree.h>
52 #include <linux/mutex.h>
53 #include <linux/pci.h>
54 #include <linux/debugfs.h>
56 #include <linux/of_irq.h>
58 #include <linux/uaccess.h>
60 #include <asm/pgtable.h>
62 #include <asm/cache.h>
64 #include <asm/ptrace.h>
65 #include <asm/machdep.h>
68 #include <asm/livepatch.h>
69 #include <asm/asm-prototypes.h>
73 #include <asm/firmware.h>
74 #include <asm/lv1call.h>
76 #define CREATE_TRACE_POINTS
77 #include <asm/trace.h>
78 #include <asm/cpu_has_feature.h>
80 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t
, irq_stat
);
81 EXPORT_PER_CPU_SYMBOL(irq_stat
);
83 int __irq_offset_value
;
86 EXPORT_SYMBOL(__irq_offset_value
);
87 atomic_t ppc_n_lost_interrupts
;
90 extern int tau_initialized
;
91 extern int tau_interrupts(int);
93 #endif /* CONFIG_PPC32 */
97 int distribute_irqs
= 1;
99 static inline notrace
unsigned long get_irq_happened(void)
101 unsigned long happened
;
103 __asm__
__volatile__("lbz %0,%1(13)"
104 : "=r" (happened
) : "i" (offsetof(struct paca_struct
, irq_happened
)));
109 static inline notrace
void set_soft_enabled(unsigned long enable
)
111 __asm__
__volatile__("stb %0,%1(13)"
112 : : "r" (enable
), "i" (offsetof(struct paca_struct
, soft_enabled
)));
115 static inline notrace
int decrementer_check_overflow(void)
117 u64 now
= get_tb_or_rtc();
118 u64
*next_tb
= this_cpu_ptr(&decrementers_next_tb
);
120 return now
>= *next_tb
;
123 /* This is called whenever we are re-enabling interrupts
124 * and returns either 0 (nothing to do) or 500/900/280/a00/e80 if
125 * there's an EE, DEC or DBELL to generate.
127 * This is called in two contexts: From arch_local_irq_restore()
128 * before soft-enabling interrupts, and from the exception exit
129 * path when returning from an interrupt from a soft-disabled to
130 * a soft enabled context. In both case we have interrupts hard
133 * We take care of only clearing the bits we handled in the
134 * PACA irq_happened field since we can only re-emit one at a
135 * time and we don't want to "lose" one.
137 notrace
unsigned int __check_irq_replay(void)
140 * We use local_paca rather than get_paca() to avoid all
141 * the debug_smp_processor_id() business in this low level
144 unsigned char happened
= local_paca
->irq_happened
;
146 /* Clear bit 0 which we wouldn't clear otherwise */
147 local_paca
->irq_happened
&= ~PACA_IRQ_HARD_DIS
;
148 if (happened
& PACA_IRQ_HARD_DIS
) {
150 * We may have missed a decrementer interrupt if hard disabled.
151 * Check the decrementer register in case we had a rollover
152 * while hard disabled.
154 if (!(happened
& PACA_IRQ_DEC
)) {
155 if (decrementer_check_overflow()) {
156 local_paca
->irq_happened
|= PACA_IRQ_DEC
;
157 happened
|= PACA_IRQ_DEC
;
163 * Force the delivery of pending soft-disabled interrupts on PS3.
164 * Any HV call will have this side effect.
166 if (firmware_has_feature(FW_FEATURE_PS3_LV1
)) {
168 lv1_get_version_info(&tmp
, &tmp2
);
172 * Check if an hypervisor Maintenance interrupt happened.
173 * This is a higher priority interrupt than the others, so
176 local_paca
->irq_happened
&= ~PACA_IRQ_HMI
;
177 if (happened
& PACA_IRQ_HMI
)
181 * We may have missed a decrementer interrupt. We check the
182 * decrementer itself rather than the paca irq_happened field
183 * in case we also had a rollover while hard disabled
185 local_paca
->irq_happened
&= ~PACA_IRQ_DEC
;
186 if (happened
& PACA_IRQ_DEC
)
189 /* Finally check if an external interrupt happened */
190 local_paca
->irq_happened
&= ~PACA_IRQ_EE
;
191 if (happened
& PACA_IRQ_EE
)
194 #ifdef CONFIG_PPC_BOOK3E
195 /* Finally check if an EPR external interrupt happened
196 * this bit is typically set if we need to handle another
197 * "edge" interrupt from within the MPIC "EPR" handler
199 local_paca
->irq_happened
&= ~PACA_IRQ_EE_EDGE
;
200 if (happened
& PACA_IRQ_EE_EDGE
)
203 local_paca
->irq_happened
&= ~PACA_IRQ_DBELL
;
204 if (happened
& PACA_IRQ_DBELL
)
207 local_paca
->irq_happened
&= ~PACA_IRQ_DBELL
;
208 if (happened
& PACA_IRQ_DBELL
) {
209 if (cpu_has_feature(CPU_FTR_HVMODE
))
213 #endif /* CONFIG_PPC_BOOK3E */
215 /* There should be nothing left ! */
216 BUG_ON(local_paca
->irq_happened
!= 0);
221 notrace
void arch_local_irq_restore(unsigned long en
)
223 unsigned char irq_happened
;
226 /* Write the new soft-enabled value */
227 set_soft_enabled(en
);
231 * From this point onward, we can take interrupts, preempt,
232 * etc... unless we got hard-disabled. We check if an event
233 * happened. If none happened, we know we can just return.
235 * We may have preempted before the check below, in which case
236 * we are checking the "new" CPU instead of the old one. This
237 * is only a problem if an event happened on the "old" CPU.
239 * External interrupt events will have caused interrupts to
240 * be hard-disabled, so there is no problem, we
241 * cannot have preempted.
243 irq_happened
= get_irq_happened();
248 * We need to hard disable to get a trusted value from
249 * __check_irq_replay(). We also need to soft-disable
250 * again to avoid warnings in there due to the use of
253 * We know that if the value in irq_happened is exactly 0x01
254 * then we are already hard disabled (there are other less
255 * common cases that we'll ignore for now), so we skip the
256 * (expensive) mtmsrd.
258 if (unlikely(irq_happened
!= PACA_IRQ_HARD_DIS
))
259 __hard_irq_disable();
260 #ifdef CONFIG_TRACE_IRQFLAGS
263 * We should already be hard disabled here. We had bugs
264 * where that wasn't the case so let's dbl check it and
265 * warn if we are wrong. Only do that when IRQ tracing
266 * is enabled as mfmsr() can be costly.
268 if (WARN_ON(mfmsr() & MSR_EE
))
269 __hard_irq_disable();
271 #endif /* CONFIG_TRACE_IRQFLAGS */
276 * Check if anything needs to be re-emitted. We haven't
277 * soft-enabled yet to avoid warnings in decrementer_check_overflow
278 * accessing per-cpu variables
280 replay
= __check_irq_replay();
282 /* We can soft-enable now */
286 * And replay if we have to. This will return with interrupts
290 __replay_interrupt(replay
);
294 /* Finally, let's ensure we are hard enabled */
297 EXPORT_SYMBOL(arch_local_irq_restore
);
300 * This is specifically called by assembly code to re-enable interrupts
301 * if they are currently disabled. This is typically called before
302 * schedule() or do_signal() when returning to userspace. We do it
303 * in C to avoid the burden of dealing with lockdep etc...
305 * NOTE: This is called with interrupts hard disabled but not marked
306 * as such in paca->irq_happened, so we need to resync this.
308 void notrace
restore_interrupts(void)
310 if (irqs_disabled()) {
311 local_paca
->irq_happened
|= PACA_IRQ_HARD_DIS
;
318 * This is a helper to use when about to go into idle low-power
319 * when the latter has the side effect of re-enabling interrupts
320 * (such as calling H_CEDE under pHyp).
322 * You call this function with interrupts soft-disabled (this is
323 * already the case when ppc_md.power_save is called). The function
324 * will return whether to enter power save or just return.
326 * In the former case, it will have notified lockdep of interrupts
327 * being re-enabled and generally sanitized the lazy irq state,
328 * and in the latter case it will leave with interrupts hard
329 * disabled and marked as such, so the local_irq_enable() call
330 * in arch_cpu_idle() will properly re-enable everything.
332 bool prep_irq_for_idle(void)
335 * First we need to hard disable to ensure no interrupt
336 * occurs before we effectively enter the low power state
338 __hard_irq_disable();
339 local_paca
->irq_happened
|= PACA_IRQ_HARD_DIS
;
342 * If anything happened while we were soft-disabled,
343 * we return now and do not enter the low power state.
345 if (lazy_irq_pending())
348 /* Tell lockdep we are about to re-enable */
352 * Mark interrupts as soft-enabled and clear the
353 * PACA_IRQ_HARD_DIS from the pending mask since we
354 * are about to hard enable as well as a side effect
355 * of entering the low power state.
357 local_paca
->irq_happened
&= ~PACA_IRQ_HARD_DIS
;
358 local_paca
->soft_enabled
= 1;
360 /* Tell the caller to enter the low power state */
364 #ifdef CONFIG_PPC_BOOK3S
366 * This is for idle sequences that return with IRQs off, but the
367 * idle state itself wakes on interrupt. Tell the irq tracer that
368 * IRQs are enabled for the duration of idle so it does not get long
369 * off times. Must be paired with fini_irq_for_idle_irqsoff.
371 bool prep_irq_for_idle_irqsoff(void)
373 WARN_ON(!irqs_disabled());
376 * First we need to hard disable to ensure no interrupt
377 * occurs before we effectively enter the low power state
379 __hard_irq_disable();
380 local_paca
->irq_happened
|= PACA_IRQ_HARD_DIS
;
383 * If anything happened while we were soft-disabled,
384 * we return now and do not enter the low power state.
386 if (lazy_irq_pending())
389 /* Tell lockdep we are about to re-enable */
396 * Take the SRR1 wakeup reason, index into this table to find the
397 * appropriate irq_happened bit.
399 static const u8 srr1_to_lazyirq
[0x10] = {
411 void irq_set_pending_from_srr1(unsigned long srr1
)
413 unsigned int idx
= (srr1
& SRR1_WAKEMASK_P8
) >> 18;
416 * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,
417 * so this can be called unconditionally with srr1 wake reason.
419 local_paca
->irq_happened
|= srr1_to_lazyirq
[idx
];
421 #endif /* CONFIG_PPC_BOOK3S */
424 * Force a replay of the external interrupt handler on this CPU.
426 void force_external_irq_replay(void)
429 * This must only be called with interrupts soft-disabled,
430 * the replay will happen when re-enabling.
432 WARN_ON(!arch_irqs_disabled());
434 /* Indicate in the PACA that we have an interrupt to replay */
435 local_paca
->irq_happened
|= PACA_IRQ_EE
;
438 #endif /* CONFIG_PPC64 */
440 int arch_show_interrupts(struct seq_file
*p
, int prec
)
444 #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
445 if (tau_initialized
) {
446 seq_printf(p
, "%*s: ", prec
, "TAU");
447 for_each_online_cpu(j
)
448 seq_printf(p
, "%10u ", tau_interrupts(j
));
449 seq_puts(p
, " PowerPC Thermal Assist (cpu temp)\n");
451 #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
453 seq_printf(p
, "%*s: ", prec
, "LOC");
454 for_each_online_cpu(j
)
455 seq_printf(p
, "%10u ", per_cpu(irq_stat
, j
).timer_irqs_event
);
456 seq_printf(p
, " Local timer interrupts for timer event device\n");
458 seq_printf(p
, "%*s: ", prec
, "LOC");
459 for_each_online_cpu(j
)
460 seq_printf(p
, "%10u ", per_cpu(irq_stat
, j
).timer_irqs_others
);
461 seq_printf(p
, " Local timer interrupts for others\n");
463 seq_printf(p
, "%*s: ", prec
, "SPU");
464 for_each_online_cpu(j
)
465 seq_printf(p
, "%10u ", per_cpu(irq_stat
, j
).spurious_irqs
);
466 seq_printf(p
, " Spurious interrupts\n");
468 seq_printf(p
, "%*s: ", prec
, "PMI");
469 for_each_online_cpu(j
)
470 seq_printf(p
, "%10u ", per_cpu(irq_stat
, j
).pmu_irqs
);
471 seq_printf(p
, " Performance monitoring interrupts\n");
473 seq_printf(p
, "%*s: ", prec
, "MCE");
474 for_each_online_cpu(j
)
475 seq_printf(p
, "%10u ", per_cpu(irq_stat
, j
).mce_exceptions
);
476 seq_printf(p
, " Machine check exceptions\n");
478 if (cpu_has_feature(CPU_FTR_HVMODE
)) {
479 seq_printf(p
, "%*s: ", prec
, "HMI");
480 for_each_online_cpu(j
)
481 seq_printf(p
, "%10u ",
482 per_cpu(irq_stat
, j
).hmi_exceptions
);
483 seq_printf(p
, " Hypervisor Maintenance Interrupts\n");
486 #ifdef CONFIG_PPC_DOORBELL
487 if (cpu_has_feature(CPU_FTR_DBELL
)) {
488 seq_printf(p
, "%*s: ", prec
, "DBL");
489 for_each_online_cpu(j
)
490 seq_printf(p
, "%10u ", per_cpu(irq_stat
, j
).doorbell_irqs
);
491 seq_printf(p
, " Doorbell interrupts\n");
501 u64
arch_irq_stat_cpu(unsigned int cpu
)
503 u64 sum
= per_cpu(irq_stat
, cpu
).timer_irqs_event
;
505 sum
+= per_cpu(irq_stat
, cpu
).pmu_irqs
;
506 sum
+= per_cpu(irq_stat
, cpu
).mce_exceptions
;
507 sum
+= per_cpu(irq_stat
, cpu
).spurious_irqs
;
508 sum
+= per_cpu(irq_stat
, cpu
).timer_irqs_others
;
509 sum
+= per_cpu(irq_stat
, cpu
).hmi_exceptions
;
510 #ifdef CONFIG_PPC_DOORBELL
511 sum
+= per_cpu(irq_stat
, cpu
).doorbell_irqs
;
517 static inline void check_stack_overflow(void)
519 #ifdef CONFIG_DEBUG_STACKOVERFLOW
522 sp
= current_stack_pointer() & (THREAD_SIZE
-1);
524 /* check for stack overflow: is there less than 2KB free? */
525 if (unlikely(sp
< (sizeof(struct thread_info
) + 2048))) {
526 pr_err("do_IRQ: stack overflow: %ld\n",
527 sp
- sizeof(struct thread_info
));
533 void __do_irq(struct pt_regs
*regs
)
539 trace_irq_entry(regs
);
541 check_stack_overflow();
544 * Query the platform PIC for the interrupt & ack it.
546 * This will typically lower the interrupt line to the CPU
548 irq
= ppc_md
.get_irq();
550 /* We can hard enable interrupts now to allow perf interrupts */
551 may_hard_irq_enable();
553 /* And finally process it */
555 __this_cpu_inc(irq_stat
.spurious_irqs
);
557 generic_handle_irq(irq
);
559 trace_irq_exit(regs
);
564 void do_IRQ(struct pt_regs
*regs
)
566 struct pt_regs
*old_regs
= set_irq_regs(regs
);
567 struct thread_info
*curtp
, *irqtp
, *sirqtp
;
569 /* Switch to the irq stack to handle this */
570 curtp
= current_thread_info();
571 irqtp
= hardirq_ctx
[raw_smp_processor_id()];
572 sirqtp
= softirq_ctx
[raw_smp_processor_id()];
574 /* Already there ? */
575 if (unlikely(curtp
== irqtp
|| curtp
== sirqtp
)) {
577 set_irq_regs(old_regs
);
581 /* Prepare the thread_info in the irq stack */
582 irqtp
->task
= curtp
->task
;
585 /* Copy the preempt_count so that the [soft]irq checks work. */
586 irqtp
->preempt_count
= curtp
->preempt_count
;
588 /* Switch stack and call */
589 call_do_irq(regs
, irqtp
);
591 /* Restore stack limit */
594 /* Copy back updates to the thread_info */
596 set_bits(irqtp
->flags
, &curtp
->flags
);
598 set_irq_regs(old_regs
);
601 void __init
init_IRQ(void)
611 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
612 struct thread_info
*critirq_ctx
[NR_CPUS
] __read_mostly
;
613 struct thread_info
*dbgirq_ctx
[NR_CPUS
] __read_mostly
;
614 struct thread_info
*mcheckirq_ctx
[NR_CPUS
] __read_mostly
;
616 void exc_lvl_ctx_init(void)
618 struct thread_info
*tp
;
621 for_each_possible_cpu(i
) {
626 cpu_nr
= get_hard_smp_processor_id(i
);
632 memset((void *)critirq_ctx
[cpu_nr
], 0, THREAD_SIZE
);
633 tp
= critirq_ctx
[cpu_nr
];
635 tp
->preempt_count
= 0;
638 memset((void *)dbgirq_ctx
[cpu_nr
], 0, THREAD_SIZE
);
639 tp
= dbgirq_ctx
[cpu_nr
];
641 tp
->preempt_count
= 0;
643 memset((void *)mcheckirq_ctx
[cpu_nr
], 0, THREAD_SIZE
);
644 tp
= mcheckirq_ctx
[cpu_nr
];
646 tp
->preempt_count
= HARDIRQ_OFFSET
;
652 struct thread_info
*softirq_ctx
[NR_CPUS
] __read_mostly
;
653 struct thread_info
*hardirq_ctx
[NR_CPUS
] __read_mostly
;
655 void irq_ctx_init(void)
657 struct thread_info
*tp
;
660 for_each_possible_cpu(i
) {
661 memset((void *)softirq_ctx
[i
], 0, THREAD_SIZE
);
664 klp_init_thread_info(tp
);
666 memset((void *)hardirq_ctx
[i
], 0, THREAD_SIZE
);
669 klp_init_thread_info(tp
);
673 void do_softirq_own_stack(void)
675 struct thread_info
*curtp
, *irqtp
;
677 curtp
= current_thread_info();
678 irqtp
= softirq_ctx
[smp_processor_id()];
679 irqtp
->task
= curtp
->task
;
681 call_do_softirq(irqtp
);
684 /* Set any flag that may have been set on the
688 set_bits(irqtp
->flags
, &curtp
->flags
);
691 irq_hw_number_t
virq_to_hw(unsigned int virq
)
693 struct irq_data
*irq_data
= irq_get_irq_data(virq
);
694 return WARN_ON(!irq_data
) ? 0 : irq_data
->hwirq
;
696 EXPORT_SYMBOL_GPL(virq_to_hw
);
699 int irq_choose_cpu(const struct cpumask
*mask
)
703 if (cpumask_equal(mask
, cpu_online_mask
)) {
704 static int irq_rover
;
705 static DEFINE_RAW_SPINLOCK(irq_rover_lock
);
708 /* Round-robin distribution... */
710 raw_spin_lock_irqsave(&irq_rover_lock
, flags
);
712 irq_rover
= cpumask_next(irq_rover
, cpu_online_mask
);
713 if (irq_rover
>= nr_cpu_ids
)
714 irq_rover
= cpumask_first(cpu_online_mask
);
718 raw_spin_unlock_irqrestore(&irq_rover_lock
, flags
);
720 cpuid
= cpumask_first_and(mask
, cpu_online_mask
);
721 if (cpuid
>= nr_cpu_ids
)
725 return get_hard_smp_processor_id(cpuid
);
728 int irq_choose_cpu(const struct cpumask
*mask
)
730 return hard_smp_processor_id();
734 int arch_early_irq_init(void)
740 static int __init
setup_noirqdistrib(char *str
)
746 __setup("noirqdistrib", setup_noirqdistrib
);
747 #endif /* CONFIG_PPC64 */