arch/powerpc/kernel/setup_32.c

   1 /*
   2  * Common prep/pmac/chrp boot and setup code.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/string.h>
   7 #include <linux/sched.h>
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/reboot.h>
  11 #include <linux/delay.h>
  12 #include <linux/initrd.h>
  13 #include <linux/tty.h>
  14 #include <linux/seq_file.h>
  15 #include <linux/root_dev.h>
  16 #include <linux/cpu.h>
  17 #include <linux/console.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/prom.h>
  23 #include <asm/processor.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/setup.h>
  26 #include <asm/smp.h>
  27 #include <asm/elf.h>
  28 #include <asm/cputable.h>
  29 #include <asm/bootx.h>
  30 #include <asm/btext.h>
  31 #include <asm/machdep.h>
  32 #include <linux/uaccess.h>
  33 #include <asm/pmac_feature.h>
  34 #include <asm/sections.h>
  35 #include <asm/nvram.h>
  36 #include <asm/xmon.h>
  37 #include <asm/time.h>
  38 #include <asm/serial.h>
  39 #include <asm/udbg.h>
  40 #include <asm/code-patching.h>
  41 #include <asm/cpu_has_feature.h>
  42
  43 #define DBG(fmt...)
  44
  45 extern void bootx_init(unsigned long r4, unsigned long phys);
  46
  47 int boot_cpuid_phys;
  48 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
  49
  50 int smp_hw_index[NR_CPUS];
  51 EXPORT_SYMBOL(smp_hw_index);
  52
  53 unsigned long ISA_DMA_THRESHOLD;
  54 unsigned int DMA_MODE_READ;
  55 unsigned int DMA_MODE_WRITE;
  56
  57 EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
  58 EXPORT_SYMBOL(DMA_MODE_READ);
  59 EXPORT_SYMBOL(DMA_MODE_WRITE);
  60
  61 /*
  62  * We're called here very early in the boot.
  63  *
  64  * Note that the kernel may be running at an address which is different
  65  * from the address that it was linked at, so we must use RELOC/PTRRELOC
  66  * to access static data (including strings).  -- paulus
  67  */
  68 notrace unsigned long __init early_init(unsigned long dt_ptr)
  69 {
  70         unsigned long offset = reloc_offset();
  71
  72         /* First zero the BSS -- use memset_io, some platforms don't have
  73          * caches on yet */
  74         memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
  75                         __bss_stop - __bss_start);
  76
  77         /*
  78          * Identify the CPU type and fix up code sections
  79          * that depend on which cpu we have.
  80          */
  81         identify_cpu(offset, mfspr(SPRN_PVR));
  82
  83         apply_feature_fixups();
  84
  85         return KERNELBASE + offset;
  86 }
  87
  88
  89 /*
  90  * This is run before start_kernel(), the kernel has been relocated
  91  * and we are running with enough of the MMU enabled to have our
  92  * proper kernel virtual addresses
  93  *
  94  * We do the initial parsing of the flat device-tree and prepares
  95  * for the MMU to be fully initialized.
  96  */
  97 extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
  98
  99 notrace void __init machine_init(u64 dt_ptr)
 100 {
 101         /* Configure static keys first, now that we're relocated. */
 102         setup_feature_keys();
 103
 104         /* Enable early debugging if any specified (see udbg.h) */
 105         udbg_early_init();
 106
 107         patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
 108         patch_instruction(&memset_nocache_branch, PPC_INST_NOP);
 109
 110         /* Do some early initialization based on the flat device tree */
 111         early_init_devtree(__va(dt_ptr));
 112
 113         early_init_mmu();
 114
 115         setup_kdump_trampoline();
 116 }
 117
 118 /* Checks "l2cr=xxxx" command-line option */
 119 int __init ppc_setup_l2cr(char *str)
 120 {
 121         if (cpu_has_feature(CPU_FTR_L2CR)) {
 122                 unsigned long val = simple_strtoul(str, NULL, 0);
 123                 printk(KERN_INFO "l2cr set to %lx\n", val);
 124                 _set_L2CR(0);           /* force invalidate by disable cache */
 125                 _set_L2CR(val);         /* and enable it */
 126         }
 127         return 1;
 128 }
 129 __setup("l2cr=", ppc_setup_l2cr);
 130
 131 /* Checks "l3cr=xxxx" command-line option */
 132 int __init ppc_setup_l3cr(char *str)
 133 {
 134         if (cpu_has_feature(CPU_FTR_L3CR)) {
 135                 unsigned long val = simple_strtoul(str, NULL, 0);
 136                 printk(KERN_INFO "l3cr set to %lx\n", val);
 137                 _set_L3CR(val);         /* and enable it */
 138         }
 139         return 1;
 140 }
 141 __setup("l3cr=", ppc_setup_l3cr);
 142
 143 #ifdef CONFIG_GENERIC_NVRAM
 144
 145 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
 146 unsigned char nvram_read_byte(int addr)
 147 {
 148         if (ppc_md.nvram_read_val)
 149                 return ppc_md.nvram_read_val(addr);
 150         return 0xff;
 151 }
 152 EXPORT_SYMBOL(nvram_read_byte);
 153
 154 void nvram_write_byte(unsigned char val, int addr)
 155 {
 156         if (ppc_md.nvram_write_val)
 157                 ppc_md.nvram_write_val(addr, val);
 158 }
 159 EXPORT_SYMBOL(nvram_write_byte);
 160
 161 ssize_t nvram_get_size(void)
 162 {
 163         if (ppc_md.nvram_size)
 164                 return ppc_md.nvram_size();
 165         return -1;
 166 }
 167 EXPORT_SYMBOL(nvram_get_size);
 168
 169 void nvram_sync(void)
 170 {
 171         if (ppc_md.nvram_sync)
 172                 ppc_md.nvram_sync();
 173 }
 174 EXPORT_SYMBOL(nvram_sync);
 175
 176 #endif /* CONFIG_NVRAM */
 177
 178 int __init ppc_init(void)
 179 {
 180         /* clear the progress line */
 181         if (ppc_md.progress)
 182                 ppc_md.progress("             ", 0xffff);
 183
 184         /* call platform init */
 185         if (ppc_md.init != NULL) {
 186                 ppc_md.init();
 187         }
 188         return 0;
 189 }
 190
 191 arch_initcall(ppc_init);
 192
 193 void __init irqstack_early_init(void)
 194 {
 195         unsigned int i;
 196
 197         /* interrupt stacks must be in lowmem, we get that for free on ppc32
 198          * as the memblock is limited to lowmem by default */
 199         for_each_possible_cpu(i) {
 200                 softirq_ctx[i] = (struct thread_info *)
 201                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 202                 hardirq_ctx[i] = (struct thread_info *)
 203                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 204         }
 205 }
 206
 207 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 208 void __init exc_lvl_early_init(void)
 209 {
 210         unsigned int i, hw_cpu;
 211
 212         /* interrupt stacks must be in lowmem, we get that for free on ppc32
 213          * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
 214         for_each_possible_cpu(i) {
 215 #ifdef CONFIG_SMP
 216                 hw_cpu = get_hard_smp_processor_id(i);
 217 #else
 218                 hw_cpu = 0;
 219 #endif
 220
 221                 critirq_ctx[hw_cpu] = (struct thread_info *)
 222                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 223 #ifdef CONFIG_BOOKE
 224                 dbgirq_ctx[hw_cpu] = (struct thread_info *)
 225                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 226                 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
 227                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 228 #endif
 229         }
 230 }
 231 #endif
 232
 233 void __init setup_power_save(void)
 234 {
 235 #ifdef CONFIG_6xx
 236         if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
 237             cpu_has_feature(CPU_FTR_CAN_NAP))
 238                 ppc_md.power_save = ppc6xx_idle;
 239 #endif
 240
 241 #ifdef CONFIG_E500
 242         if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
 243             cpu_has_feature(CPU_FTR_CAN_NAP))
 244                 ppc_md.power_save = e500_idle;
 245 #endif
 246 }
 247
 248 __init void initialize_cache_info(void)
 249 {
 250         /*
 251          * Set cache line size based on type of cpu as a default.
 252          * Systems with OF can look in the properties on the cpu node(s)
 253          * for a possibly more accurate value.
 254          */
 255         dcache_bsize = cur_cpu_spec->dcache_bsize;
 256         icache_bsize = cur_cpu_spec->icache_bsize;
 257         ucache_bsize = 0;
 258         if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
 259                 ucache_bsize = icache_bsize = dcache_bsize;
 260 }