2 * Memory copy functions for 32-bit PowerPC.
4 * Copyright (C) 1996-2005 Paul Mackerras.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/errno.h>
14 #include <asm/ppc_asm.h>
15 #include <asm/export.h>
17 #define COPY_16_BYTES \
27 #define COPY_16_BYTES_WITHEX(n) \
45 #define COPY_16_BYTES_EXCODE(n) \
47 addi r5,r5,-(16 * n); \
50 addi r5,r5,-(16 * n); \
52 EX_TABLE(8 ## n ## 0b,9 ## n ## 0b); \
53 EX_TABLE(8 ## n ## 1b,9 ## n ## 0b); \
54 EX_TABLE(8 ## n ## 2b,9 ## n ## 0b); \
55 EX_TABLE(8 ## n ## 3b,9 ## n ## 0b); \
56 EX_TABLE(8 ## n ## 4b,9 ## n ## 1b); \
57 EX_TABLE(8 ## n ## 5b,9 ## n ## 1b); \
58 EX_TABLE(8 ## n ## 6b,9 ## n ## 1b); \
59 EX_TABLE(8 ## n ## 7b,9 ## n ## 1b)
62 .stabs "arch/powerpc/lib/",N_SO,0,0,0f
63 .stabs "copy_32.S",N_SO,0,0,0f
66 CACHELINE_BYTES = L1_CACHE_BYTES
67 LG_CACHELINE_BYTES = L1_CACHE_SHIFT
68 CACHELINE_MASK = (L1_CACHE_BYTES-1)
71 * Use dcbz on the complete cache lines in the destination
72 * to set them to zero. This requires that the destination
73 * area is cacheable. -- paulus
75 * During early init, cache might not be active yet, so dcbz cannot be used.
76 * We therefore skip the optimised bloc that uses dcbz. This jump is
77 * replaced by a nop once cache is active. This is done in machine_init()
92 bne 2f /* Use normal procedure if r4 is not zero */
94 _GLOBAL(memset_nocache_branch)
95 b 2f /* Skip optimised bloc until cache is enabled */
97 clrlwi r7,r6,32-LG_CACHELINE_BYTES
99 srwi r9,r8,LG_CACHELINE_BYTES
100 addic. r9,r9,-1 /* total number of complete cachelines */
102 xori r0,r7,CACHELINE_MASK & ~3
111 addi r6,r6,CACHELINE_BYTES
113 clrlwi r5,r8,32-LG_CACHELINE_BYTES
131 * This version uses dcbz on the complete cache lines in the
132 * destination area to reduce memory traffic. This requires that
133 * the destination area is cacheable.
134 * We only use this version if the source and dest don't overlap.
137 * During early init, cache might not be active yet, so dcbz cannot be used.
138 * We therefore jump to generic_memcpy which doesn't use dcbz. This jump is
139 * replaced by a nop once cache is active. This is done in machine_init()
148 add r7,r3,r5 /* test if the src & dst overlap */
152 crand 0,0,4 /* cr0.lt &= cr1.lt */
153 blt generic_memcpy /* if regions overlap */
158 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
161 cmplw 0,r5,r0 /* is this more than total to do? */
162 blt 63f /* if not much to do */
163 andi. r8,r0,3 /* get it word-aligned first */
167 70: lbz r9,4(r4) /* do some bytes */
175 72: lwzu r9,4(r4) /* do some words */
179 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
180 clrlwi r5,r5,32-LG_CACHELINE_BYTES
187 #if L1_CACHE_BYTES >= 32
189 #if L1_CACHE_BYTES >= 64
192 #if L1_CACHE_BYTES >= 128
218 EXPORT_SYMBOL(memcpy)
219 EXPORT_SYMBOL(memmove)
225 beq 2f /* if less than 8 bytes to do */
226 andi. r0,r6,3 /* get dest word aligned */
257 rlwinm. r7,r5,32-3,3,31
262 _GLOBAL(backwards_memcpy)
263 rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
293 rlwinm. r7,r5,32-3,3,31
298 _GLOBAL(__copy_tofrom_user)
302 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
305 cmplw 0,r5,r0 /* is this more than total to do? */
306 blt 63f /* if not much to do */
307 andi. r8,r0,3 /* get it word-aligned first */
310 70: lbz r9,4(r4) /* do some bytes */
319 72: lwzu r9,4(r4) /* do some words */
328 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
329 clrlwi r5,r5,32-LG_CACHELINE_BYTES
333 /* Here we decide how far ahead to prefetch the source */
339 #if MAX_COPY_PREFETCH > 1
340 /* Heuristically, for large transfers we prefetch
341 MAX_COPY_PREFETCH cachelines ahead. For small transfers
342 we prefetch 1 cacheline ahead. */
343 cmpwi r0,MAX_COPY_PREFETCH
345 li r7,MAX_COPY_PREFETCH
348 addi r3,r3,CACHELINE_BYTES
352 addi r3,r3,CACHELINE_BYTES
353 #endif /* MAX_COPY_PREFETCH > 1 */
362 /* the main body of the cacheline loop */
363 COPY_16_BYTES_WITHEX(0)
364 #if L1_CACHE_BYTES >= 32
365 COPY_16_BYTES_WITHEX(1)
366 #if L1_CACHE_BYTES >= 64
367 COPY_16_BYTES_WITHEX(2)
368 COPY_16_BYTES_WITHEX(3)
369 #if L1_CACHE_BYTES >= 128
370 COPY_16_BYTES_WITHEX(4)
371 COPY_16_BYTES_WITHEX(5)
372 COPY_16_BYTES_WITHEX(6)
373 COPY_16_BYTES_WITHEX(7)
401 /* read fault, initial single-byte copy */
404 /* write fault, initial single-byte copy */
409 /* read fault, initial word copy */
412 /* write fault, initial word copy */
418 * this stuff handles faults in the cacheline loop and branches to either
419 * 104f (if in read part) or 105f (if in write part), after updating r5
421 COPY_16_BYTES_EXCODE(0)
422 #if L1_CACHE_BYTES >= 32
423 COPY_16_BYTES_EXCODE(1)
424 #if L1_CACHE_BYTES >= 64
425 COPY_16_BYTES_EXCODE(2)
426 COPY_16_BYTES_EXCODE(3)
427 #if L1_CACHE_BYTES >= 128
428 COPY_16_BYTES_EXCODE(4)
429 COPY_16_BYTES_EXCODE(5)
430 COPY_16_BYTES_EXCODE(6)
431 COPY_16_BYTES_EXCODE(7)
436 /* read fault in cacheline loop */
439 /* fault on dcbz (effectively a write fault) */
440 /* or write fault in cacheline loop */
442 92: li r3,LG_CACHELINE_BYTES
446 /* read fault in final word loop */
449 /* write fault in final word loop */
454 /* read fault in final byte loop */
457 /* write fault in final byte loop */
462 * At this stage the number of bytes not copied is
463 * r5 + (ctr << r3), and r9 is 0 for read or 1 for write.
468 beq 120f /* shouldn't happen */
471 /* for a read fault, first try to continue the copy one byte at a time */
478 /* then clear out the destination: r3 bytes starting at 4(r6) */
489 EXPORT_SYMBOL(__copy_tofrom_user)