2 * Hardware-accelerated CRC-32 variants for Linux on z Systems
4 * Use the z/Architecture Vector Extension Facility to accelerate the
5 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
8 * This CRC-32 implementation algorithm is bitreflected and processes
9 * the least-significant bit first (Little-Endian).
11 * Copyright IBM Corp. 2015
12 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
15 #include <linux/linkage.h>
16 #include <asm/vx-insn.h>
18 /* Vector register range containing CRC-32 constants */
19 #define CONST_PERM_LE2BE %v9
20 #define CONST_R2R1 %v10
21 #define CONST_R4R3 %v11
23 #define CONST_RU_POLY %v13
24 #define CONST_CRC_POLY %v14
30 * The CRC-32 constant block contains reduction constants to fold and
31 * process particular chunks of the input data stream in parallel.
33 * For the CRC-32 variants, the constants are precomputed according to
36 * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
37 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
38 * R3 = [(x128+32 mod P'(x) << 32)]' << 1
39 * R4 = [(x128-32 mod P'(x) << 32)]' << 1
40 * R5 = [(x64 mod P'(x) << 32)]' << 1
41 * R6 = [(x32 mod P'(x) << 32)]' << 1
43 * The bitreflected Barret reduction constant, u', is defined as
44 * the bit reversal of floor(x**64 / P(x)).
46 * where P(x) is the polynomial in the normal domain and the P'(x) is the
47 * polynomial in the reversed (bitreflected) domain.
49 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
54 * CRC-32C (Castagnoli) polynomials:
60 .Lconstants_CRC_32_LE:
61 .octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask
62 .quad 0x1c6e41596, 0x154442bd4 # R2, R1
63 .quad 0x0ccaa009e, 0x1751997d0 # R4, R3
64 .octa 0x163cd6124 # R5
65 .octa 0x1F7011641 # u'
66 .octa 0x1DB710641 # P'(x) << 1
68 .Lconstants_CRC_32C_LE:
69 .octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask
70 .quad 0x09e4addf8, 0x740eef02 # R2, R1
71 .quad 0x14cd00bd6, 0xf20c0dfe # R4, R3
72 .octa 0x0dd45aab8 # R5
73 .octa 0x0dea713f1 # u'
74 .octa 0x105ec76f0 # P'(x) << 1
82 * The CRC-32 functions use these calling conventions:
86 * %r2: Initial CRC value, typically ~0; and final CRC (return) value.
87 * %r3: Input buffer pointer, performance might be improved if the
88 * buffer is on a doubleword boundary.
89 * %r4: Length of the buffer, must be 64 bytes or greater.
93 * %r5: CRC-32 constant pool base pointer.
94 * V0: Initial CRC value and intermediate constants and results.
95 * V1..V4: Data for CRC computation.
96 * V5..V8: Next data chunks that are fetched from the input buffer.
97 * V9: Constant for BE->LE conversion and shift operations
99 * V10..V14: CRC-32 constants.
102 ENTRY(crc32_le_vgfm_16)
103 larl %r5,.Lconstants_CRC_32_LE
104 j crc32_le_vgfm_generic
106 ENTRY(crc32c_le_vgfm_16)
107 larl %r5,.Lconstants_CRC_32C_LE
108 j crc32_le_vgfm_generic
111 crc32_le_vgfm_generic:
112 /* Load CRC-32 constants */
113 VLM CONST_PERM_LE2BE,CONST_CRC_POLY,0,%r5
116 * Load the initial CRC value.
118 * The CRC value is loaded into the rightmost word of the
119 * vector register and is later XORed with the LSB portion
120 * of the loaded input data.
122 VZERO %v0 /* Clear V0 */
123 VLVGF %v0,%r2,3 /* Load CRC into rightmost word */
125 /* Load a 64-byte data chunk and XOR with CRC */
126 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
127 VPERM %v1,%v1,%v1,CONST_PERM_LE2BE
128 VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
129 VPERM %v3,%v3,%v3,CONST_PERM_LE2BE
130 VPERM %v4,%v4,%v4,CONST_PERM_LE2BE
132 VX %v1,%v0,%v1 /* V1 ^= CRC */
133 aghi %r3,64 /* BUF = BUF + 64 */
134 aghi %r4,-64 /* LEN = LEN - 64 */
137 jl .Lless_than_64bytes
140 /* Load the next 64-byte data chunk into V5 to V8 */
142 VPERM %v5,%v5,%v5,CONST_PERM_LE2BE
143 VPERM %v6,%v6,%v6,CONST_PERM_LE2BE
144 VPERM %v7,%v7,%v7,CONST_PERM_LE2BE
145 VPERM %v8,%v8,%v8,CONST_PERM_LE2BE
148 * Perform a GF(2) multiplication of the doublewords in V1 with
149 * the R1 and R2 reduction constants in V0. The intermediate result
150 * is then folded (accumulated) with the next data chunk in V5 and
151 * stored in V1. Repeat this step for the register contents
152 * in V2, V3, and V4 respectively.
154 VGFMAG %v1,CONST_R2R1,%v1,%v5
155 VGFMAG %v2,CONST_R2R1,%v2,%v6
156 VGFMAG %v3,CONST_R2R1,%v3,%v7
157 VGFMAG %v4,CONST_R2R1,%v4,%v8
159 aghi %r3,64 /* BUF = BUF + 64 */
160 aghi %r4,-64 /* LEN = LEN - 64 */
163 jnl .Lfold_64bytes_loop
167 * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3
168 * and R4 and accumulating the next 128-bit chunk until a single 128-bit
171 VGFMAG %v1,CONST_R4R3,%v1,%v2
172 VGFMAG %v1,CONST_R4R3,%v1,%v3
173 VGFMAG %v1,CONST_R4R3,%v1,%v4
180 VL %v2,0,,%r3 /* Load next data chunk */
181 VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
182 VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */
188 jnl .Lfold_16bytes_loop
192 * Set up a vector register for byte shifts. The shift value must
193 * be loaded in bits 1-4 in byte element 7 of a vector register.
194 * Shift by 8 bytes: 0x40
195 * Shift by 4 bytes: 0x20
200 * Prepare V0 for the next GF(2) multiplication: shift V0 by 8 bytes
201 * to move R4 into the rightmost doubleword and set the leftmost
204 VSRLB %v0,CONST_R4R3,%v9
208 * Compute GF(2) product of V1 and V0. The rightmost doubleword
209 * of V1 is multiplied with R4. The leftmost doubleword of V1 is
210 * multiplied by 0x1 and is then XORed with rightmost product.
211 * Implicitly, the intermediate leftmost product becomes padded
216 * Now do the final 32-bit fold by multiplying the rightmost word
217 * in V1 with R5 and XOR the result with the remaining bits in V1.
219 * To achieve this by a single VGFMAG, right shift V1 by a word
220 * and store the result in V2 which is then accumulated. Use the
221 * vector unpack instruction to load the rightmost half of the
222 * doubleword into the rightmost doubleword element of V1; the other
223 * half is loaded in the leftmost doubleword.
224 * The vector register with CONST_R5 contains the R5 constant in the
225 * rightmost doubleword and the leftmost doubleword is zero to ignore
226 * the leftmost product of V1.
228 VLEIB %v9,0x20,7 /* Shift by words */
229 VSRLB %v2,%v1,%v9 /* Store remaining bits in V2 */
230 VUPLLF %v1,%v1 /* Split rightmost doubleword */
231 VGFMAG %v1,CONST_R5,%v1,%v2 /* V1 = (V1 * R5) XOR V2 */
234 * Apply a Barret reduction to compute the final 32-bit CRC value.
236 * The input values to the Barret reduction are the degree-63 polynomial
237 * in V1 (R(x)), degree-32 generator polynomial, and the reduction
238 * constant u. The Barret reduction result is the CRC value of R(x) mod
241 * The Barret reduction algorithm is defined as:
243 * 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u
244 * 2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x)
245 * 3. C(x) = R(x) XOR T2(x) mod x^32
247 * Note: The leftmost doubleword of vector register containing
248 * CONST_RU_POLY is zero and, thus, the intermediate GF(2) product
249 * is zero and does not contribute to the final result.
252 /* T1(x) = floor( R(x) / x^32 ) GF2MUL u */
254 VGFMG %v2,CONST_RU_POLY,%v2
257 * Compute the GF(2) product of the CRC polynomial with T1(x) in
258 * V2 and XOR the intermediate result, T2(x), with the value in V1.
259 * The final result is stored in word element 2 of V2.
262 VGFMAG %v2,CONST_CRC_POLY,%v2,%v1