1 /* NG4memset.S: Niagara-4 optimized memset/bzero.
3 * Copyright (C) 2012 David S. Miller (davem@davemloft.net)
8 .register %g2, #scratch
9 .register %g3, #scratch
25 .size NG4memset,.-NG4memset
36 brz,pt %g1, .Laligned8
38 1: stb %o4, [%o0 + 0x00]
43 cmp %o1, 64 + (64 - 8)
46 andcc %g1, (64 - 1), %g1
47 brz,pn %g1, .Laligned64
49 1: stx %o4, [%o0 + 0x00]
56 brnz,pn %o4, .Lnon_bzero_loop
58 1: stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
60 stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
66 membar #StoreStore|#StoreLoad
70 1: stx %o4, [%o0 + 0x00]
92 1: stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
94 stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
95 stxa %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
96 stxa %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P
98 stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
99 stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
100 stxa %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
101 stxa %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P
104 ba,a,pt %icc, .Lpostloop
106 .size NG4bzero,.-NG4bzero