?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.13.16
[linux/fpc-iii.git] / arch / x86 / events / intel / ds.c
bloba322fed5f8edcab18401e2745438c362f80e0851
1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/insn.h>
7
8 #include "../perf_event.h"
9
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
12
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
16
17 /*
18 * pebs_record_32 for p4 and core not supported
19
20 struct pebs_record_32 {
21 u32 flags, ip;
22 u32 ax, bc, cx, dx;
23 u32 si, di, bp, sp;
24 };
25
26 */
27
28 union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43 };
44
45
46 /*
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
49 */
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54 /* Version for Sandy Bridge and later */
55 static u64 pebs_data_source[] = {
56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
57 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
58 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
59 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
70 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
71 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
72 };
73
74 /* Patch up minor differences in the bits */
75 void __init intel_pmu_pebs_data_source_nhm(void)
76 {
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT);
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
80 }
81
82 static u64 precise_store_data(u64 status)
83 {
84 union intel_x86_pebs_dse dse;
85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
86
87 dse.val = status;
88
89 /*
90 * bit 4: TLB access
91 * 1 = stored missed 2nd level TLB
92 *
93 * so it either hit the walker or the OS
94 * otherwise hit 2nd level TLB
95 */
96 if (dse.st_stlb_miss)
97 val |= P(TLB, MISS);
98 else
99 val |= P(TLB, HIT);
100
101 /*
102 * bit 0: hit L1 data cache
103 * if not set, then all we know is that
104 * it missed L1D
105 */
106 if (dse.st_l1d_hit)
107 val |= P(LVL, HIT);
108 else
109 val |= P(LVL, MISS);
110
111 /*
112 * bit 5: Locked prefix
113 */
114 if (dse.st_locked)
115 val |= P(LOCK, LOCKED);
116
117 return val;
118 }
119
120 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
121 {
122 union perf_mem_data_src dse;
123
124 dse.val = PERF_MEM_NA;
125
126 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
127 dse.mem_op = PERF_MEM_OP_STORE;
128 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
129 dse.mem_op = PERF_MEM_OP_LOAD;
130
131 /*
132 * L1 info only valid for following events:
133 *
134 * MEM_UOPS_RETIRED.STLB_MISS_STORES
135 * MEM_UOPS_RETIRED.LOCK_STORES
136 * MEM_UOPS_RETIRED.SPLIT_STORES
137 * MEM_UOPS_RETIRED.ALL_STORES
138 */
139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
140 if (status & 1)
141 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
142 else
143 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
144 }
145 return dse.val;
146 }
147
148 static u64 load_latency_data(u64 status)
149 {
150 union intel_x86_pebs_dse dse;
151 u64 val;
152 int model = boot_cpu_data.x86_model;
153 int fam = boot_cpu_data.x86;
154
155 dse.val = status;
156
157 /*
158 * use the mapping table for bit 0-3
159 */
160 val = pebs_data_source[dse.ld_dse];
161
162 /*
163 * Nehalem models do not support TLB, Lock infos
164 */
165 if (fam == 0x6 && (model == 26 || model == 30
166 || model == 31 || model == 46)) {
167 val |= P(TLB, NA) | P(LOCK, NA);
168 return val;
169 }
170 /*
171 * bit 4: TLB access
172 * 0 = did not miss 2nd level TLB
173 * 1 = missed 2nd level TLB
174 */
175 if (dse.ld_stlb_miss)
176 val |= P(TLB, MISS) | P(TLB, L2);
177 else
178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
179
180 /*
181 * bit 5: locked prefix
182 */
183 if (dse.ld_locked)
184 val |= P(LOCK, LOCKED);
185
186 return val;
187 }
188
189 struct pebs_record_core {
190 u64 flags, ip;
191 u64 ax, bx, cx, dx;
192 u64 si, di, bp, sp;
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
195 };
196
197 struct pebs_record_nhm {
198 u64 flags, ip;
199 u64 ax, bx, cx, dx;
200 u64 si, di, bp, sp;
201 u64 r8, r9, r10, r11;
202 u64 r12, r13, r14, r15;
203 u64 status, dla, dse, lat;
204 };
205
206 /*
207 * Same as pebs_record_nhm, with two additional fields.
208 */
209 struct pebs_record_hsw {
210 u64 flags, ip;
211 u64 ax, bx, cx, dx;
212 u64 si, di, bp, sp;
213 u64 r8, r9, r10, r11;
214 u64 r12, r13, r14, r15;
215 u64 status, dla, dse, lat;
216 u64 real_ip, tsx_tuning;
217 };
218
219 union hsw_tsx_tuning {
220 struct {
221 u32 cycles_last_block : 32,
222 hle_abort : 1,
223 rtm_abort : 1,
224 instruction_abort : 1,
225 non_instruction_abort : 1,
226 retry : 1,
227 data_conflict : 1,
228 capacity_writes : 1,
229 capacity_reads : 1;
230 };
231 u64 value;
232 };
233
234 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
235
236 /* Same as HSW, plus TSC */
237
238 struct pebs_record_skl {
239 u64 flags, ip;
240 u64 ax, bx, cx, dx;
241 u64 si, di, bp, sp;
242 u64 r8, r9, r10, r11;
243 u64 r12, r13, r14, r15;
244 u64 status, dla, dse, lat;
245 u64 real_ip, tsx_tuning;
246 u64 tsc;
247 };
248
249 void init_debug_store_on_cpu(int cpu)
250 {
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
252
253 if (!ds)
254 return;
255
256 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
257 (u32)((u64)(unsigned long)ds),
258 (u32)((u64)(unsigned long)ds >> 32));
259 }
260
261 void fini_debug_store_on_cpu(int cpu)
262 {
263 if (!per_cpu(cpu_hw_events, cpu).ds)
264 return;
265
266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
267 }
268
269 static DEFINE_PER_CPU(void *, insn_buffer);
270
271 static int alloc_pebs_buffer(int cpu)
272 {
273 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
274 int node = cpu_to_node(cpu);
275 int max;
276 void *buffer, *ibuffer;
277
278 if (!x86_pmu.pebs)
279 return 0;
280
281 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
282 if (unlikely(!buffer))
283 return -ENOMEM;
284
285 /*
286 * HSW+ already provides us the eventing ip; no need to allocate this
287 * buffer then.
288 */
289 if (x86_pmu.intel_cap.pebs_format < 2) {
290 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
291 if (!ibuffer) {
292 kfree(buffer);
293 return -ENOMEM;
294 }
295 per_cpu(insn_buffer, cpu) = ibuffer;
296 }
297
298 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
299
300 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
301 ds->pebs_index = ds->pebs_buffer_base;
302 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
303 max * x86_pmu.pebs_record_size;
304
305 return 0;
306 }
307
308 static void release_pebs_buffer(int cpu)
309 {
310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
311
312 if (!ds || !x86_pmu.pebs)
313 return;
314
315 kfree(per_cpu(insn_buffer, cpu));
316 per_cpu(insn_buffer, cpu) = NULL;
317
318 kfree((void *)(unsigned long)ds->pebs_buffer_base);
319 ds->pebs_buffer_base = 0;
320 }
321
322 static int alloc_bts_buffer(int cpu)
323 {
324 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
325 int node = cpu_to_node(cpu);
326 int max, thresh;
327 void *buffer;
328
329 if (!x86_pmu.bts)
330 return 0;
331
332 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
333 if (unlikely(!buffer)) {
334 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
335 return -ENOMEM;
336 }
337
338 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
339 thresh = max / 16;
340
341 ds->bts_buffer_base = (u64)(unsigned long)buffer;
342 ds->bts_index = ds->bts_buffer_base;
343 ds->bts_absolute_maximum = ds->bts_buffer_base +
344 max * BTS_RECORD_SIZE;
345 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
346 thresh * BTS_RECORD_SIZE;
347
348 return 0;
349 }
350
351 static void release_bts_buffer(int cpu)
352 {
353 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
354
355 if (!ds || !x86_pmu.bts)
356 return;
357
358 kfree((void *)(unsigned long)ds->bts_buffer_base);
359 ds->bts_buffer_base = 0;
360 }
361
362 static int alloc_ds_buffer(int cpu)
363 {
364 int node = cpu_to_node(cpu);
365 struct debug_store *ds;
366
367 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
368 if (unlikely(!ds))
369 return -ENOMEM;
370
371 per_cpu(cpu_hw_events, cpu).ds = ds;
372
373 return 0;
374 }
375
376 static void release_ds_buffer(int cpu)
377 {
378 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
379
380 if (!ds)
381 return;
382
383 per_cpu(cpu_hw_events, cpu).ds = NULL;
384 kfree(ds);
385 }
386
387 void release_ds_buffers(void)
388 {
389 int cpu;
390
391 if (!x86_pmu.bts && !x86_pmu.pebs)
392 return;
393
394 get_online_cpus();
395 for_each_online_cpu(cpu)
396 fini_debug_store_on_cpu(cpu);
397
398 for_each_possible_cpu(cpu) {
399 release_pebs_buffer(cpu);
400 release_bts_buffer(cpu);
401 release_ds_buffer(cpu);
402 }
403 put_online_cpus();
404 }
405
406 void reserve_ds_buffers(void)
407 {
408 int bts_err = 0, pebs_err = 0;
409 int cpu;
410
411 x86_pmu.bts_active = 0;
412 x86_pmu.pebs_active = 0;
413
414 if (!x86_pmu.bts && !x86_pmu.pebs)
415 return;
416
417 if (!x86_pmu.bts)
418 bts_err = 1;
419
420 if (!x86_pmu.pebs)
421 pebs_err = 1;
422
423 get_online_cpus();
424
425 for_each_possible_cpu(cpu) {
426 if (alloc_ds_buffer(cpu)) {
427 bts_err = 1;
428 pebs_err = 1;
429 }
430
431 if (!bts_err && alloc_bts_buffer(cpu))
432 bts_err = 1;
433
434 if (!pebs_err && alloc_pebs_buffer(cpu))
435 pebs_err = 1;
436
437 if (bts_err && pebs_err)
438 break;
439 }
440
441 if (bts_err) {
442 for_each_possible_cpu(cpu)
443 release_bts_buffer(cpu);
444 }
445
446 if (pebs_err) {
447 for_each_possible_cpu(cpu)
448 release_pebs_buffer(cpu);
449 }
450
451 if (bts_err && pebs_err) {
452 for_each_possible_cpu(cpu)
453 release_ds_buffer(cpu);
454 } else {
455 if (x86_pmu.bts && !bts_err)
456 x86_pmu.bts_active = 1;
457
458 if (x86_pmu.pebs && !pebs_err)
459 x86_pmu.pebs_active = 1;
460
461 for_each_online_cpu(cpu)
462 init_debug_store_on_cpu(cpu);
463 }
464
465 put_online_cpus();
466 }
467
468 /*
469 * BTS
470 */
471
472 struct event_constraint bts_constraint =
473 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
474
475 void intel_pmu_enable_bts(u64 config)
476 {
477 unsigned long debugctlmsr;
478
479 debugctlmsr = get_debugctlmsr();
480
481 debugctlmsr |= DEBUGCTLMSR_TR;
482 debugctlmsr |= DEBUGCTLMSR_BTS;
483 if (config & ARCH_PERFMON_EVENTSEL_INT)
484 debugctlmsr |= DEBUGCTLMSR_BTINT;
485
486 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
487 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
488
489 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
490 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
491
492 update_debugctlmsr(debugctlmsr);
493 }
494
495 void intel_pmu_disable_bts(void)
496 {
497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
498 unsigned long debugctlmsr;
499
500 if (!cpuc->ds)
501 return;
502
503 debugctlmsr = get_debugctlmsr();
504
505 debugctlmsr &=
506 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
507 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
508
509 update_debugctlmsr(debugctlmsr);
510 }
511
512 int intel_pmu_drain_bts_buffer(void)
513 {
514 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
515 struct debug_store *ds = cpuc->ds;
516 struct bts_record {
517 u64 from;
518 u64 to;
519 u64 flags;
520 };
521 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
522 struct bts_record *at, *base, *top;
523 struct perf_output_handle handle;
524 struct perf_event_header header;
525 struct perf_sample_data data;
526 unsigned long skip = 0;
527 struct pt_regs regs;
528
529 if (!event)
530 return 0;
531
532 if (!x86_pmu.bts_active)
533 return 0;
534
535 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
536 top = (struct bts_record *)(unsigned long)ds->bts_index;
537
538 if (top <= base)
539 return 0;
540
541 memset(&regs, 0, sizeof(regs));
542
543 ds->bts_index = ds->bts_buffer_base;
544
545 perf_sample_data_init(&data, 0, event->hw.last_period);
546
547 /*
548 * BTS leaks kernel addresses in branches across the cpl boundary,
549 * such as traps or system calls, so unless the user is asking for
550 * kernel tracing (and right now it's not possible), we'd need to
551 * filter them out. But first we need to count how many of those we
552 * have in the current batch. This is an extra O(n) pass, however,
553 * it's much faster than the other one especially considering that
554 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
555 * alloc_bts_buffer()).
556 */
557 for (at = base; at < top; at++) {
558 /*
559 * Note that right now *this* BTS code only works if
560 * attr::exclude_kernel is set, but let's keep this extra
561 * check here in case that changes.
562 */
563 if (event->attr.exclude_kernel &&
564 (kernel_ip(at->from) || kernel_ip(at->to)))
565 skip++;
566 }
567
568 /*
569 * Prepare a generic sample, i.e. fill in the invariant fields.
570 * We will overwrite the from and to address before we output
571 * the sample.
572 */
573 rcu_read_lock();
574 perf_prepare_sample(&header, &data, event, &regs);
575
576 if (perf_output_begin(&handle, event, header.size *
577 (top - base - skip)))
578 goto unlock;
579
580 for (at = base; at < top; at++) {
581 /* Filter out any records that contain kernel addresses. */
582 if (event->attr.exclude_kernel &&
583 (kernel_ip(at->from) || kernel_ip(at->to)))
584 continue;
585
586 data.ip = at->from;
587 data.addr = at->to;
588
589 perf_output_sample(&handle, &header, &data, event);
590 }
591
592 perf_output_end(&handle);
593
594 /* There's new data available. */
595 event->hw.interrupts++;
596 event->pending_kill = POLL_IN;
597 unlock:
598 rcu_read_unlock();
599 return 1;
600 }
601
602 static inline void intel_pmu_drain_pebs_buffer(void)
603 {
604 struct pt_regs regs;
605
606 x86_pmu.drain_pebs(&regs);
607 }
608
609 /*
610 * PEBS
611 */
612 struct event_constraint intel_core2_pebs_event_constraints[] = {
613 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
614 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
615 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
616 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
617 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
618 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
619 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
620 EVENT_CONSTRAINT_END
621 };
622
623 struct event_constraint intel_atom_pebs_event_constraints[] = {
624 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
625 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
626 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
627 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
628 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
629 /* Allow all events as PEBS with no flags */
630 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
631 EVENT_CONSTRAINT_END
632 };
633
634 struct event_constraint intel_slm_pebs_event_constraints[] = {
635 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
636 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
637 /* Allow all events as PEBS with no flags */
638 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
639 EVENT_CONSTRAINT_END
640 };
641
642 struct event_constraint intel_glm_pebs_event_constraints[] = {
643 /* Allow all events as PEBS with no flags */
644 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
645 EVENT_CONSTRAINT_END
646 };
647
648 struct event_constraint intel_glp_pebs_event_constraints[] = {
649 /* Allow all events as PEBS with no flags */
650 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
651 EVENT_CONSTRAINT_END
652 };
653
654 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
655 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
656 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
657 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
658 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
659 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
660 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
661 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
662 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
663 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
664 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
665 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
666 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
667 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
668 EVENT_CONSTRAINT_END
669 };
670
671 struct event_constraint intel_westmere_pebs_event_constraints[] = {
672 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
673 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
674 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
675 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
676 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
677 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
678 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
679 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
680 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
681 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
683 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
684 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
685 EVENT_CONSTRAINT_END
686 };
687
688 struct event_constraint intel_snb_pebs_event_constraints[] = {
689 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
690 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
691 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
692 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
693 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
694 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
695 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
696 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
697 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
698 /* Allow all events as PEBS with no flags */
699 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
700 EVENT_CONSTRAINT_END
701 };
702
703 struct event_constraint intel_ivb_pebs_event_constraints[] = {
704 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
705 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
706 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
707 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
708 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
709 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
710 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
711 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
712 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
713 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
714 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
715 /* Allow all events as PEBS with no flags */
716 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
717 EVENT_CONSTRAINT_END
718 };
719
720 struct event_constraint intel_hsw_pebs_event_constraints[] = {
721 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
722 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
723 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
724 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
725 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
726 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
727 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
728 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
729 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
730 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
731 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
732 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
733 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
734 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
735 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
736 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
737 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
738 /* Allow all events as PEBS with no flags */
739 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
740 EVENT_CONSTRAINT_END
741 };
742
743 struct event_constraint intel_bdw_pebs_event_constraints[] = {
744 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
745 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
746 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
747 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
748 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
749 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
750 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
751 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
752 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
753 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
754 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
755 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
756 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
757 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
758 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
759 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
760 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
761 /* Allow all events as PEBS with no flags */
762 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
763 EVENT_CONSTRAINT_END
764 };
765
766
767 struct event_constraint intel_skl_pebs_event_constraints[] = {
768 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
769 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
770 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
771 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
772 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
773 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
774 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
775 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
776 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
777 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
778 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
779 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
780 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
781 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
782 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
783 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
784 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
785 /* Allow all events as PEBS with no flags */
786 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
787 EVENT_CONSTRAINT_END
788 };
789
790 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
791 {
792 struct event_constraint *c;
793
794 if (!event->attr.precise_ip)
795 return NULL;
796
797 if (x86_pmu.pebs_constraints) {
798 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
799 if ((event->hw.config & c->cmask) == c->code) {
800 event->hw.flags |= c->flags;
801 return c;
802 }
803 }
804 }
805
806 return &emptyconstraint;
807 }
808
809 /*
810 * We need the sched_task callback even for per-cpu events when we use
811 * the large interrupt threshold, such that we can provide PID and TID
812 * to PEBS samples.
813 */
814 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
815 {
816 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
817 }
818
819 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
820 {
821 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
822
823 if (!sched_in && pebs_needs_sched_cb(cpuc))
824 intel_pmu_drain_pebs_buffer();
825 }
826
827 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
828 {
829 struct debug_store *ds = cpuc->ds;
830 u64 threshold;
831
832 if (cpuc->n_pebs == cpuc->n_large_pebs) {
833 threshold = ds->pebs_absolute_maximum -
834 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
835 } else {
836 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
837 }
838
839 ds->pebs_interrupt_threshold = threshold;
840 }
841
842 static void
843 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu)
844 {
845 /*
846 * Make sure we get updated with the first PEBS
847 * event. It will trigger also during removal, but
848 * that does not hurt:
849 */
850 bool update = cpuc->n_pebs == 1;
851
852 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
853 if (!needed_cb)
854 perf_sched_cb_inc(pmu);
855 else
856 perf_sched_cb_dec(pmu);
857
858 update = true;
859 }
860
861 if (update)
862 pebs_update_threshold(cpuc);
863 }
864
865 void intel_pmu_pebs_add(struct perf_event *event)
866 {
867 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
868 struct hw_perf_event *hwc = &event->hw;
869 bool needed_cb = pebs_needs_sched_cb(cpuc);
870
871 cpuc->n_pebs++;
872 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
873 cpuc->n_large_pebs++;
874
875 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
876 }
877
878 void intel_pmu_pebs_enable(struct perf_event *event)
879 {
880 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
881 struct hw_perf_event *hwc = &event->hw;
882 struct debug_store *ds = cpuc->ds;
883
884 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
885
886 cpuc->pebs_enabled |= 1ULL << hwc->idx;
887
888 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
889 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
890 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
891 cpuc->pebs_enabled |= 1ULL << 63;
892
893 /*
894 * Use auto-reload if possible to save a MSR write in the PMI.
895 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
896 */
897 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
898 ds->pebs_event_reset[hwc->idx] =
899 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
900 } else {
901 ds->pebs_event_reset[hwc->idx] = 0;
902 }
903 }
904
905 void intel_pmu_pebs_del(struct perf_event *event)
906 {
907 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
908 struct hw_perf_event *hwc = &event->hw;
909 bool needed_cb = pebs_needs_sched_cb(cpuc);
910
911 cpuc->n_pebs--;
912 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
913 cpuc->n_large_pebs--;
914
915 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
916 }
917
918 void intel_pmu_pebs_disable(struct perf_event *event)
919 {
920 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
921 struct hw_perf_event *hwc = &event->hw;
922
923 if (cpuc->n_pebs == cpuc->n_large_pebs)
924 intel_pmu_drain_pebs_buffer();
925
926 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
927
928 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
929 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
930 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
931 cpuc->pebs_enabled &= ~(1ULL << 63);
932
933 if (cpuc->enabled)
934 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
935
936 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
937 }
938
939 void intel_pmu_pebs_enable_all(void)
940 {
941 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
942
943 if (cpuc->pebs_enabled)
944 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
945 }
946
947 void intel_pmu_pebs_disable_all(void)
948 {
949 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
950
951 if (cpuc->pebs_enabled)
952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
953 }
954
955 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
956 {
957 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
958 unsigned long from = cpuc->lbr_entries[0].from;
959 unsigned long old_to, to = cpuc->lbr_entries[0].to;
960 unsigned long ip = regs->ip;
961 int is_64bit = 0;
962 void *kaddr;
963 int size;
964
965 /*
966 * We don't need to fixup if the PEBS assist is fault like
967 */
968 if (!x86_pmu.intel_cap.pebs_trap)
969 return 1;
970
971 /*
972 * No LBR entry, no basic block, no rewinding
973 */
974 if (!cpuc->lbr_stack.nr || !from || !to)
975 return 0;
976
977 /*
978 * Basic blocks should never cross user/kernel boundaries
979 */
980 if (kernel_ip(ip) != kernel_ip(to))
981 return 0;
982
983 /*
984 * unsigned math, either ip is before the start (impossible) or
985 * the basic block is larger than 1 page (sanity)
986 */
987 if ((ip - to) > PEBS_FIXUP_SIZE)
988 return 0;
989
990 /*
991 * We sampled a branch insn, rewind using the LBR stack
992 */
993 if (ip == to) {
994 set_linear_ip(regs, from);
995 return 1;
996 }
997
998 size = ip - to;
999 if (!kernel_ip(ip)) {
1000 int bytes;
1001 u8 *buf = this_cpu_read(insn_buffer);
1002
1003 /* 'size' must fit our buffer, see above */
1004 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1005 if (bytes != 0)
1006 return 0;
1007
1008 kaddr = buf;
1009 } else {
1010 kaddr = (void *)to;
1011 }
1012
1013 do {
1014 struct insn insn;
1015
1016 old_to = to;
1017
1018 #ifdef CONFIG_X86_64
1019 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
1020 #endif
1021 insn_init(&insn, kaddr, size, is_64bit);
1022 insn_get_length(&insn);
1023 /*
1024 * Make sure there was not a problem decoding the
1025 * instruction and getting the length. This is
1026 * doubly important because we have an infinite
1027 * loop if insn.length=0.
1028 */
1029 if (!insn.length)
1030 break;
1031
1032 to += insn.length;
1033 kaddr += insn.length;
1034 size -= insn.length;
1035 } while (to < ip);
1036
1037 if (to == ip) {
1038 set_linear_ip(regs, old_to);
1039 return 1;
1040 }
1041
1042 /*
1043 * Even though we decoded the basic block, the instruction stream
1044 * never matched the given IP, either the TO or the IP got corrupted.
1045 */
1046 return 0;
1047 }
1048
1049 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
1050 {
1051 if (pebs->tsx_tuning) {
1052 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
1053 return tsx.cycles_last_block;
1054 }
1055 return 0;
1056 }
1057
1058 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1059 {
1060 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1061
1062 /* For RTM XABORTs also log the abort code from AX */
1063 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
1064 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1065 return txn;
1066 }
1067
1068 static void setup_pebs_sample_data(struct perf_event *event,
1069 struct pt_regs *iregs, void *__pebs,
1070 struct perf_sample_data *data,
1071 struct pt_regs *regs)
1072 {
1073 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1074 (PERF_X86_EVENT_PEBS_ST_HSW | \
1075 PERF_X86_EVENT_PEBS_LD_HSW | \
1076 PERF_X86_EVENT_PEBS_NA_HSW)
1077 /*
1078 * We cast to the biggest pebs_record but are careful not to
1079 * unconditionally access the 'extra' entries.
1080 */
1081 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1082 struct pebs_record_skl *pebs = __pebs;
1083 u64 sample_type;
1084 int fll, fst, dsrc;
1085 int fl = event->hw.flags;
1086
1087 if (pebs == NULL)
1088 return;
1089
1090 sample_type = event->attr.sample_type;
1091 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1092
1093 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1094 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1095
1096 perf_sample_data_init(data, 0, event->hw.last_period);
1097
1098 data->period = event->hw.last_period;
1099
1100 /*
1101 * Use latency for weight (only avail with PEBS-LL)
1102 */
1103 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1104 data->weight = pebs->lat;
1105
1106 /*
1107 * data.data_src encodes the data source
1108 */
1109 if (dsrc) {
1110 u64 val = PERF_MEM_NA;
1111 if (fll)
1112 val = load_latency_data(pebs->dse);
1113 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1114 val = precise_datala_hsw(event, pebs->dse);
1115 else if (fst)
1116 val = precise_store_data(pebs->dse);
1117 data->data_src.val = val;
1118 }
1119
1120 /*
1121 * We use the interrupt regs as a base because the PEBS record does not
1122 * contain a full regs set, specifically it seems to lack segment
1123 * descriptors, which get used by things like user_mode().
1124 *
1125 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1126 *
1127 * We must however always use BP,SP from iregs for the unwinder to stay
1128 * sane; the record BP,SP can point into thin air when the record is
1129 * from a previous PMI context or an (I)RET happend between the record
1130 * and PMI.
1131 */
1132 *regs = *iregs;
1133 regs->flags = pebs->flags;
1134 set_linear_ip(regs, pebs->ip);
1135
1136 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1137 regs->ax = pebs->ax;
1138 regs->bx = pebs->bx;
1139 regs->cx = pebs->cx;
1140 regs->dx = pebs->dx;
1141 regs->si = pebs->si;
1142 regs->di = pebs->di;
1143
1144 /*
1145 * Per the above; only set BP,SP if we don't need callchains.
1146 *
1147 * XXX: does this make sense?
1148 */
1149 if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) {
1150 regs->bp = pebs->bp;
1151 regs->sp = pebs->sp;
1152 }
1153
1154 /*
1155 * Preserve PERF_EFLAGS_VM from set_linear_ip().
1156 */
1157 regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM);
1158 #ifndef CONFIG_X86_32
1159 regs->r8 = pebs->r8;
1160 regs->r9 = pebs->r9;
1161 regs->r10 = pebs->r10;
1162 regs->r11 = pebs->r11;
1163 regs->r12 = pebs->r12;
1164 regs->r13 = pebs->r13;
1165 regs->r14 = pebs->r14;
1166 regs->r15 = pebs->r15;
1167 #endif
1168 }
1169
1170 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1171 regs->ip = pebs->real_ip;
1172 regs->flags |= PERF_EFLAGS_EXACT;
1173 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1174 regs->flags |= PERF_EFLAGS_EXACT;
1175 else
1176 regs->flags &= ~PERF_EFLAGS_EXACT;
1177
1178 if ((sample_type & PERF_SAMPLE_ADDR) &&
1179 x86_pmu.intel_cap.pebs_format >= 1)
1180 data->addr = pebs->dla;
1181
1182 if (x86_pmu.intel_cap.pebs_format >= 2) {
1183 /* Only set the TSX weight when no memory weight. */
1184 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1185 data->weight = intel_hsw_weight(pebs);
1186
1187 if (sample_type & PERF_SAMPLE_TRANSACTION)
1188 data->txn = intel_hsw_transaction(pebs);
1189 }
1190
1191 /*
1192 * v3 supplies an accurate time stamp, so we use that
1193 * for the time stamp.
1194 *
1195 * We can only do this for the default trace clock.
1196 */
1197 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1198 event->attr.use_clockid == 0)
1199 data->time = native_sched_clock_from_tsc(pebs->tsc);
1200
1201 if (has_branch_stack(event))
1202 data->br_stack = &cpuc->lbr_stack;
1203 }
1204
1205 static inline void *
1206 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1207 {
1208 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1209 void *at;
1210 u64 pebs_status;
1211
1212 /*
1213 * fmt0 does not have a status bitfield (does not use
1214 * perf_record_nhm format)
1215 */
1216 if (x86_pmu.intel_cap.pebs_format < 1)
1217 return base;
1218
1219 if (base == NULL)
1220 return NULL;
1221
1222 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1223 struct pebs_record_nhm *p = at;
1224
1225 if (test_bit(bit, (unsigned long *)&p->status)) {
1226 /* PEBS v3 has accurate status bits */
1227 if (x86_pmu.intel_cap.pebs_format >= 3)
1228 return at;
1229
1230 if (p->status == (1 << bit))
1231 return at;
1232
1233 /* clear non-PEBS bit and re-check */
1234 pebs_status = p->status & cpuc->pebs_enabled;
1235 pebs_status &= PEBS_COUNTER_MASK;
1236 if (pebs_status == (1 << bit))
1237 return at;
1238 }
1239 }
1240 return NULL;
1241 }
1242
1243 static void __intel_pmu_pebs_event(struct perf_event *event,
1244 struct pt_regs *iregs,
1245 void *base, void *top,
1246 int bit, int count)
1247 {
1248 struct perf_sample_data data;
1249 struct pt_regs regs;
1250 void *at = get_next_pebs_record_by_bit(base, top, bit);
1251
1252 if (!intel_pmu_save_and_restart(event) &&
1253 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1254 return;
1255
1256 while (count > 1) {
1257 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1258 perf_event_output(event, &data, &regs);
1259 at += x86_pmu.pebs_record_size;
1260 at = get_next_pebs_record_by_bit(at, top, bit);
1261 count--;
1262 }
1263
1264 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1265
1266 /*
1267 * All but the last records are processed.
1268 * The last one is left to be able to call the overflow handler.
1269 */
1270 if (perf_event_overflow(event, &data, &regs)) {
1271 x86_pmu_stop(event, 0);
1272 return;
1273 }
1274
1275 }
1276
1277 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1278 {
1279 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1280 struct debug_store *ds = cpuc->ds;
1281 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1282 struct pebs_record_core *at, *top;
1283 int n;
1284
1285 if (!x86_pmu.pebs_active)
1286 return;
1287
1288 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1289 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1290
1291 /*
1292 * Whatever else happens, drain the thing
1293 */
1294 ds->pebs_index = ds->pebs_buffer_base;
1295
1296 if (!test_bit(0, cpuc->active_mask))
1297 return;
1298
1299 WARN_ON_ONCE(!event);
1300
1301 if (!event->attr.precise_ip)
1302 return;
1303
1304 n = top - at;
1305 if (n <= 0)
1306 return;
1307
1308 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1309 }
1310
1311 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1312 {
1313 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1314 struct debug_store *ds = cpuc->ds;
1315 struct perf_event *event;
1316 void *base, *at, *top;
1317 short counts[MAX_PEBS_EVENTS] = {};
1318 short error[MAX_PEBS_EVENTS] = {};
1319 int bit, i;
1320
1321 if (!x86_pmu.pebs_active)
1322 return;
1323
1324 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1325 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1326
1327 ds->pebs_index = ds->pebs_buffer_base;
1328
1329 if (unlikely(base >= top))
1330 return;
1331
1332 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1333 struct pebs_record_nhm *p = at;
1334 u64 pebs_status;
1335
1336 pebs_status = p->status & cpuc->pebs_enabled;
1337 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1338
1339 /* PEBS v3 has more accurate status bits */
1340 if (x86_pmu.intel_cap.pebs_format >= 3) {
1341 for_each_set_bit(bit, (unsigned long *)&pebs_status,
1342 x86_pmu.max_pebs_events)
1343 counts[bit]++;
1344
1345 continue;
1346 }
1347
1348 /*
1349 * On some CPUs the PEBS status can be zero when PEBS is
1350 * racing with clearing of GLOBAL_STATUS.
1351 *
1352 * Normally we would drop that record, but in the
1353 * case when there is only a single active PEBS event
1354 * we can assume it's for that event.
1355 */
1356 if (!pebs_status && cpuc->pebs_enabled &&
1357 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1358 pebs_status = cpuc->pebs_enabled;
1359
1360 bit = find_first_bit((unsigned long *)&pebs_status,
1361 x86_pmu.max_pebs_events);
1362 if (bit >= x86_pmu.max_pebs_events)
1363 continue;
1364
1365 /*
1366 * The PEBS hardware does not deal well with the situation
1367 * when events happen near to each other and multiple bits
1368 * are set. But it should happen rarely.
1369 *
1370 * If these events include one PEBS and multiple non-PEBS
1371 * events, it doesn't impact PEBS record. The record will
1372 * be handled normally. (slow path)
1373 *
1374 * If these events include two or more PEBS events, the
1375 * records for the events can be collapsed into a single
1376 * one, and it's not possible to reconstruct all events
1377 * that caused the PEBS record. It's called collision.
1378 * If collision happened, the record will be dropped.
1379 */
1380 if (p->status != (1ULL << bit)) {
1381 for_each_set_bit(i, (unsigned long *)&pebs_status,
1382 x86_pmu.max_pebs_events)
1383 error[i]++;
1384 continue;
1385 }
1386
1387 counts[bit]++;
1388 }
1389
1390 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1391 if ((counts[bit] == 0) && (error[bit] == 0))
1392 continue;
1393
1394 event = cpuc->events[bit];
1395 if (WARN_ON_ONCE(!event))
1396 continue;
1397
1398 if (WARN_ON_ONCE(!event->attr.precise_ip))
1399 continue;
1400
1401 /* log dropped samples number */
1402 if (error[bit]) {
1403 perf_log_lost_samples(event, error[bit]);
1404
1405 if (perf_event_account_interrupt(event))
1406 x86_pmu_stop(event, 0);
1407 }
1408
1409 if (counts[bit]) {
1410 __intel_pmu_pebs_event(event, iregs, base,
1411 top, bit, counts[bit]);
1412 }
1413 }
1414 }
1415
1416 /*
1417 * BTS, PEBS probe and setup
1418 */
1419
1420 void __init intel_ds_init(void)
1421 {
1422 /*
1423 * No support for 32bit formats
1424 */
1425 if (!boot_cpu_has(X86_FEATURE_DTES64))
1426 return;
1427
1428 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1429 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1430 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1431 if (x86_pmu.pebs) {
1432 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1433 int format = x86_pmu.intel_cap.pebs_format;
1434
1435 switch (format) {
1436 case 0:
1437 pr_cont("PEBS fmt0%c, ", pebs_type);
1438 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1439 /*
1440 * Using >PAGE_SIZE buffers makes the WRMSR to
1441 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1442 * mysteriously hang on Core2.
1443 *
1444 * As a workaround, we don't do this.
1445 */
1446 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1447 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1448 break;
1449
1450 case 1:
1451 pr_cont("PEBS fmt1%c, ", pebs_type);
1452 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1453 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1454 break;
1455
1456 case 2:
1457 pr_cont("PEBS fmt2%c, ", pebs_type);
1458 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1459 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1460 break;
1461
1462 case 3:
1463 pr_cont("PEBS fmt3%c, ", pebs_type);
1464 x86_pmu.pebs_record_size =
1465 sizeof(struct pebs_record_skl);
1466 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1467 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1468 break;
1469
1470 default:
1471 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
1472 x86_pmu.pebs = 0;
1473 }
1474 }
1475 }
1476
1477 void perf_restore_debug_store(void)
1478 {
1479 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1480
1481 if (!x86_pmu.bts && !x86_pmu.pebs)
1482 return;
1483
1484 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1485 }
Linux with added FPC-III support