Linux 4.13.16
[linux/fpc-iii.git] / arch / x86 / events / intel / uncore.c
blob1c5390f1cf0992787afa8d34bb361f622b00dcb2
1 #include <linux/module.h>
3 #include <asm/cpu_device_id.h>
4 #include <asm/intel-family.h>
5 #include "uncore.h"
7 static struct intel_uncore_type *empty_uncore[] = { NULL, };
8 struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
9 struct intel_uncore_type **uncore_pci_uncores = empty_uncore;
11 static bool pcidrv_registered;
12 struct pci_driver *uncore_pci_driver;
13 /* pci bus to socket mapping */
14 DEFINE_RAW_SPINLOCK(pci2phy_map_lock);
15 struct list_head pci2phy_map_head = LIST_HEAD_INIT(pci2phy_map_head);
16 struct pci_extra_dev *uncore_extra_pci_dev;
17 static int max_packages;
19 /* mask of cpus that collect uncore events */
20 static cpumask_t uncore_cpu_mask;
22 /* constraint for the fixed counter */
23 static struct event_constraint uncore_constraint_fixed =
24 EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
25 struct event_constraint uncore_constraint_empty =
26 EVENT_CONSTRAINT(0, 0, 0);
28 MODULE_LICENSE("GPL");
30 static int uncore_pcibus_to_physid(struct pci_bus *bus)
32 struct pci2phy_map *map;
33 int phys_id = -1;
35 raw_spin_lock(&pci2phy_map_lock);
36 list_for_each_entry(map, &pci2phy_map_head, list) {
37 if (map->segment == pci_domain_nr(bus)) {
38 phys_id = map->pbus_to_physid[bus->number];
39 break;
42 raw_spin_unlock(&pci2phy_map_lock);
44 return phys_id;
47 static void uncore_free_pcibus_map(void)
49 struct pci2phy_map *map, *tmp;
51 list_for_each_entry_safe(map, tmp, &pci2phy_map_head, list) {
52 list_del(&map->list);
53 kfree(map);
57 struct pci2phy_map *__find_pci2phy_map(int segment)
59 struct pci2phy_map *map, *alloc = NULL;
60 int i;
62 lockdep_assert_held(&pci2phy_map_lock);
64 lookup:
65 list_for_each_entry(map, &pci2phy_map_head, list) {
66 if (map->segment == segment)
67 goto end;
70 if (!alloc) {
71 raw_spin_unlock(&pci2phy_map_lock);
72 alloc = kmalloc(sizeof(struct pci2phy_map), GFP_KERNEL);
73 raw_spin_lock(&pci2phy_map_lock);
75 if (!alloc)
76 return NULL;
78 goto lookup;
81 map = alloc;
82 alloc = NULL;
83 map->segment = segment;
84 for (i = 0; i < 256; i++)
85 map->pbus_to_physid[i] = -1;
86 list_add_tail(&map->list, &pci2phy_map_head);
88 end:
89 kfree(alloc);
90 return map;
93 ssize_t uncore_event_show(struct kobject *kobj,
94 struct kobj_attribute *attr, char *buf)
96 struct uncore_event_desc *event =
97 container_of(attr, struct uncore_event_desc, attr);
98 return sprintf(buf, "%s", event->config);
101 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
103 unsigned int pkgid = topology_logical_package_id(cpu);
106 * The unsigned check also catches the '-1' return value for non
107 * existent mappings in the topology map.
109 return pkgid < max_packages ? pmu->boxes[pkgid] : NULL;
112 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
114 u64 count;
116 rdmsrl(event->hw.event_base, count);
118 return count;
122 * generic get constraint function for shared match/mask registers.
124 struct event_constraint *
125 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
127 struct intel_uncore_extra_reg *er;
128 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
129 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
130 unsigned long flags;
131 bool ok = false;
134 * reg->alloc can be set due to existing state, so for fake box we
135 * need to ignore this, otherwise we might fail to allocate proper
136 * fake state for this extra reg constraint.
138 if (reg1->idx == EXTRA_REG_NONE ||
139 (!uncore_box_is_fake(box) && reg1->alloc))
140 return NULL;
142 er = &box->shared_regs[reg1->idx];
143 raw_spin_lock_irqsave(&er->lock, flags);
144 if (!atomic_read(&er->ref) ||
145 (er->config1 == reg1->config && er->config2 == reg2->config)) {
146 atomic_inc(&er->ref);
147 er->config1 = reg1->config;
148 er->config2 = reg2->config;
149 ok = true;
151 raw_spin_unlock_irqrestore(&er->lock, flags);
153 if (ok) {
154 if (!uncore_box_is_fake(box))
155 reg1->alloc = 1;
156 return NULL;
159 return &uncore_constraint_empty;
162 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
164 struct intel_uncore_extra_reg *er;
165 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
168 * Only put constraint if extra reg was actually allocated. Also
169 * takes care of event which do not use an extra shared reg.
171 * Also, if this is a fake box we shouldn't touch any event state
172 * (reg->alloc) and we don't care about leaving inconsistent box
173 * state either since it will be thrown out.
175 if (uncore_box_is_fake(box) || !reg1->alloc)
176 return;
178 er = &box->shared_regs[reg1->idx];
179 atomic_dec(&er->ref);
180 reg1->alloc = 0;
183 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
185 struct intel_uncore_extra_reg *er;
186 unsigned long flags;
187 u64 config;
189 er = &box->shared_regs[idx];
191 raw_spin_lock_irqsave(&er->lock, flags);
192 config = er->config;
193 raw_spin_unlock_irqrestore(&er->lock, flags);
195 return config;
198 static void uncore_assign_hw_event(struct intel_uncore_box *box,
199 struct perf_event *event, int idx)
201 struct hw_perf_event *hwc = &event->hw;
203 hwc->idx = idx;
204 hwc->last_tag = ++box->tags[idx];
206 if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
207 hwc->event_base = uncore_fixed_ctr(box);
208 hwc->config_base = uncore_fixed_ctl(box);
209 return;
212 hwc->config_base = uncore_event_ctl(box, hwc->idx);
213 hwc->event_base = uncore_perf_ctr(box, hwc->idx);
216 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
218 u64 prev_count, new_count, delta;
219 int shift;
221 if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
222 shift = 64 - uncore_fixed_ctr_bits(box);
223 else
224 shift = 64 - uncore_perf_ctr_bits(box);
226 /* the hrtimer might modify the previous event value */
227 again:
228 prev_count = local64_read(&event->hw.prev_count);
229 new_count = uncore_read_counter(box, event);
230 if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
231 goto again;
233 delta = (new_count << shift) - (prev_count << shift);
234 delta >>= shift;
236 local64_add(delta, &event->count);
240 * The overflow interrupt is unavailable for SandyBridge-EP, is broken
241 * for SandyBridge. So we use hrtimer to periodically poll the counter
242 * to avoid overflow.
244 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
246 struct intel_uncore_box *box;
247 struct perf_event *event;
248 unsigned long flags;
249 int bit;
251 box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
252 if (!box->n_active || box->cpu != smp_processor_id())
253 return HRTIMER_NORESTART;
255 * disable local interrupt to prevent uncore_pmu_event_start/stop
256 * to interrupt the update process
258 local_irq_save(flags);
261 * handle boxes with an active event list as opposed to active
262 * counters
264 list_for_each_entry(event, &box->active_list, active_entry) {
265 uncore_perf_event_update(box, event);
268 for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
269 uncore_perf_event_update(box, box->events[bit]);
271 local_irq_restore(flags);
273 hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
274 return HRTIMER_RESTART;
277 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
279 hrtimer_start(&box->hrtimer, ns_to_ktime(box->hrtimer_duration),
280 HRTIMER_MODE_REL_PINNED);
283 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
285 hrtimer_cancel(&box->hrtimer);
288 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
290 hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
291 box->hrtimer.function = uncore_pmu_hrtimer;
294 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type,
295 int node)
297 int i, size, numshared = type->num_shared_regs ;
298 struct intel_uncore_box *box;
300 size = sizeof(*box) + numshared * sizeof(struct intel_uncore_extra_reg);
302 box = kzalloc_node(size, GFP_KERNEL, node);
303 if (!box)
304 return NULL;
306 for (i = 0; i < numshared; i++)
307 raw_spin_lock_init(&box->shared_regs[i].lock);
309 uncore_pmu_init_hrtimer(box);
310 box->cpu = -1;
311 box->pci_phys_id = -1;
312 box->pkgid = -1;
314 /* set default hrtimer timeout */
315 box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
317 INIT_LIST_HEAD(&box->active_list);
319 return box;
323 * Using uncore_pmu_event_init pmu event_init callback
324 * as a detection point for uncore events.
326 static int uncore_pmu_event_init(struct perf_event *event);
328 static bool is_box_event(struct intel_uncore_box *box, struct perf_event *event)
330 return &box->pmu->pmu == event->pmu;
333 static int
334 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader,
335 bool dogrp)
337 struct perf_event *event;
338 int n, max_count;
340 max_count = box->pmu->type->num_counters;
341 if (box->pmu->type->fixed_ctl)
342 max_count++;
344 if (box->n_events >= max_count)
345 return -EINVAL;
347 n = box->n_events;
349 if (is_box_event(box, leader)) {
350 box->event_list[n] = leader;
351 n++;
354 if (!dogrp)
355 return n;
357 list_for_each_entry(event, &leader->sibling_list, group_entry) {
358 if (!is_box_event(box, event) ||
359 event->state <= PERF_EVENT_STATE_OFF)
360 continue;
362 if (n >= max_count)
363 return -EINVAL;
365 box->event_list[n] = event;
366 n++;
368 return n;
371 static struct event_constraint *
372 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
374 struct intel_uncore_type *type = box->pmu->type;
375 struct event_constraint *c;
377 if (type->ops->get_constraint) {
378 c = type->ops->get_constraint(box, event);
379 if (c)
380 return c;
383 if (event->attr.config == UNCORE_FIXED_EVENT)
384 return &uncore_constraint_fixed;
386 if (type->constraints) {
387 for_each_event_constraint(c, type->constraints) {
388 if ((event->hw.config & c->cmask) == c->code)
389 return c;
393 return &type->unconstrainted;
396 static void uncore_put_event_constraint(struct intel_uncore_box *box,
397 struct perf_event *event)
399 if (box->pmu->type->ops->put_constraint)
400 box->pmu->type->ops->put_constraint(box, event);
403 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
405 unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
406 struct event_constraint *c;
407 int i, wmin, wmax, ret = 0;
408 struct hw_perf_event *hwc;
410 bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
412 for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
413 c = uncore_get_event_constraint(box, box->event_list[i]);
414 box->event_constraint[i] = c;
415 wmin = min(wmin, c->weight);
416 wmax = max(wmax, c->weight);
419 /* fastpath, try to reuse previous register */
420 for (i = 0; i < n; i++) {
421 hwc = &box->event_list[i]->hw;
422 c = box->event_constraint[i];
424 /* never assigned */
425 if (hwc->idx == -1)
426 break;
428 /* constraint still honored */
429 if (!test_bit(hwc->idx, c->idxmsk))
430 break;
432 /* not already used */
433 if (test_bit(hwc->idx, used_mask))
434 break;
436 __set_bit(hwc->idx, used_mask);
437 if (assign)
438 assign[i] = hwc->idx;
440 /* slow path */
441 if (i != n)
442 ret = perf_assign_events(box->event_constraint, n,
443 wmin, wmax, n, assign);
445 if (!assign || ret) {
446 for (i = 0; i < n; i++)
447 uncore_put_event_constraint(box, box->event_list[i]);
449 return ret ? -EINVAL : 0;
452 static void uncore_pmu_event_start(struct perf_event *event, int flags)
454 struct intel_uncore_box *box = uncore_event_to_box(event);
455 int idx = event->hw.idx;
457 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
458 return;
460 if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
461 return;
463 event->hw.state = 0;
464 box->events[idx] = event;
465 box->n_active++;
466 __set_bit(idx, box->active_mask);
468 local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
469 uncore_enable_event(box, event);
471 if (box->n_active == 1) {
472 uncore_enable_box(box);
473 uncore_pmu_start_hrtimer(box);
477 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
479 struct intel_uncore_box *box = uncore_event_to_box(event);
480 struct hw_perf_event *hwc = &event->hw;
482 if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
483 uncore_disable_event(box, event);
484 box->n_active--;
485 box->events[hwc->idx] = NULL;
486 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
487 hwc->state |= PERF_HES_STOPPED;
489 if (box->n_active == 0) {
490 uncore_disable_box(box);
491 uncore_pmu_cancel_hrtimer(box);
495 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
497 * Drain the remaining delta count out of a event
498 * that we are disabling:
500 uncore_perf_event_update(box, event);
501 hwc->state |= PERF_HES_UPTODATE;
505 static int uncore_pmu_event_add(struct perf_event *event, int flags)
507 struct intel_uncore_box *box = uncore_event_to_box(event);
508 struct hw_perf_event *hwc = &event->hw;
509 int assign[UNCORE_PMC_IDX_MAX];
510 int i, n, ret;
512 if (!box)
513 return -ENODEV;
515 ret = n = uncore_collect_events(box, event, false);
516 if (ret < 0)
517 return ret;
519 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
520 if (!(flags & PERF_EF_START))
521 hwc->state |= PERF_HES_ARCH;
523 ret = uncore_assign_events(box, assign, n);
524 if (ret)
525 return ret;
527 /* save events moving to new counters */
528 for (i = 0; i < box->n_events; i++) {
529 event = box->event_list[i];
530 hwc = &event->hw;
532 if (hwc->idx == assign[i] &&
533 hwc->last_tag == box->tags[assign[i]])
534 continue;
536 * Ensure we don't accidentally enable a stopped
537 * counter simply because we rescheduled.
539 if (hwc->state & PERF_HES_STOPPED)
540 hwc->state |= PERF_HES_ARCH;
542 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
545 /* reprogram moved events into new counters */
546 for (i = 0; i < n; i++) {
547 event = box->event_list[i];
548 hwc = &event->hw;
550 if (hwc->idx != assign[i] ||
551 hwc->last_tag != box->tags[assign[i]])
552 uncore_assign_hw_event(box, event, assign[i]);
553 else if (i < box->n_events)
554 continue;
556 if (hwc->state & PERF_HES_ARCH)
557 continue;
559 uncore_pmu_event_start(event, 0);
561 box->n_events = n;
563 return 0;
566 static void uncore_pmu_event_del(struct perf_event *event, int flags)
568 struct intel_uncore_box *box = uncore_event_to_box(event);
569 int i;
571 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
573 for (i = 0; i < box->n_events; i++) {
574 if (event == box->event_list[i]) {
575 uncore_put_event_constraint(box, event);
577 for (++i; i < box->n_events; i++)
578 box->event_list[i - 1] = box->event_list[i];
580 --box->n_events;
581 break;
585 event->hw.idx = -1;
586 event->hw.last_tag = ~0ULL;
589 void uncore_pmu_event_read(struct perf_event *event)
591 struct intel_uncore_box *box = uncore_event_to_box(event);
592 uncore_perf_event_update(box, event);
596 * validation ensures the group can be loaded onto the
597 * PMU if it was the only group available.
599 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
600 struct perf_event *event)
602 struct perf_event *leader = event->group_leader;
603 struct intel_uncore_box *fake_box;
604 int ret = -EINVAL, n;
606 fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
607 if (!fake_box)
608 return -ENOMEM;
610 fake_box->pmu = pmu;
612 * the event is not yet connected with its
613 * siblings therefore we must first collect
614 * existing siblings, then add the new event
615 * before we can simulate the scheduling
617 n = uncore_collect_events(fake_box, leader, true);
618 if (n < 0)
619 goto out;
621 fake_box->n_events = n;
622 n = uncore_collect_events(fake_box, event, false);
623 if (n < 0)
624 goto out;
626 fake_box->n_events = n;
628 ret = uncore_assign_events(fake_box, NULL, n);
629 out:
630 kfree(fake_box);
631 return ret;
634 static int uncore_pmu_event_init(struct perf_event *event)
636 struct intel_uncore_pmu *pmu;
637 struct intel_uncore_box *box;
638 struct hw_perf_event *hwc = &event->hw;
639 int ret;
641 if (event->attr.type != event->pmu->type)
642 return -ENOENT;
644 pmu = uncore_event_to_pmu(event);
645 /* no device found for this pmu */
646 if (pmu->func_id < 0)
647 return -ENOENT;
650 * Uncore PMU does measure at all privilege level all the time.
651 * So it doesn't make sense to specify any exclude bits.
653 if (event->attr.exclude_user || event->attr.exclude_kernel ||
654 event->attr.exclude_hv || event->attr.exclude_idle)
655 return -EINVAL;
657 /* Sampling not supported yet */
658 if (hwc->sample_period)
659 return -EINVAL;
662 * Place all uncore events for a particular physical package
663 * onto a single cpu
665 if (event->cpu < 0)
666 return -EINVAL;
667 box = uncore_pmu_to_box(pmu, event->cpu);
668 if (!box || box->cpu < 0)
669 return -EINVAL;
670 event->cpu = box->cpu;
671 event->pmu_private = box;
673 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
675 event->hw.idx = -1;
676 event->hw.last_tag = ~0ULL;
677 event->hw.extra_reg.idx = EXTRA_REG_NONE;
678 event->hw.branch_reg.idx = EXTRA_REG_NONE;
680 if (event->attr.config == UNCORE_FIXED_EVENT) {
681 /* no fixed counter */
682 if (!pmu->type->fixed_ctl)
683 return -EINVAL;
685 * if there is only one fixed counter, only the first pmu
686 * can access the fixed counter
688 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
689 return -EINVAL;
691 /* fixed counters have event field hardcoded to zero */
692 hwc->config = 0ULL;
693 } else {
694 hwc->config = event->attr.config &
695 (pmu->type->event_mask | ((u64)pmu->type->event_mask_ext << 32));
696 if (pmu->type->ops->hw_config) {
697 ret = pmu->type->ops->hw_config(box, event);
698 if (ret)
699 return ret;
703 if (event->group_leader != event)
704 ret = uncore_validate_group(pmu, event);
705 else
706 ret = 0;
708 return ret;
711 static ssize_t uncore_get_attr_cpumask(struct device *dev,
712 struct device_attribute *attr, char *buf)
714 return cpumap_print_to_pagebuf(true, buf, &uncore_cpu_mask);
717 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
719 static struct attribute *uncore_pmu_attrs[] = {
720 &dev_attr_cpumask.attr,
721 NULL,
724 static const struct attribute_group uncore_pmu_attr_group = {
725 .attrs = uncore_pmu_attrs,
728 static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
730 int ret;
732 if (!pmu->type->pmu) {
733 pmu->pmu = (struct pmu) {
734 .attr_groups = pmu->type->attr_groups,
735 .task_ctx_nr = perf_invalid_context,
736 .event_init = uncore_pmu_event_init,
737 .add = uncore_pmu_event_add,
738 .del = uncore_pmu_event_del,
739 .start = uncore_pmu_event_start,
740 .stop = uncore_pmu_event_stop,
741 .read = uncore_pmu_event_read,
742 .module = THIS_MODULE,
744 } else {
745 pmu->pmu = *pmu->type->pmu;
746 pmu->pmu.attr_groups = pmu->type->attr_groups;
749 if (pmu->type->num_boxes == 1) {
750 if (strlen(pmu->type->name) > 0)
751 sprintf(pmu->name, "uncore_%s", pmu->type->name);
752 else
753 sprintf(pmu->name, "uncore");
754 } else {
755 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
756 pmu->pmu_idx);
759 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
760 if (!ret)
761 pmu->registered = true;
762 return ret;
765 static void uncore_pmu_unregister(struct intel_uncore_pmu *pmu)
767 if (!pmu->registered)
768 return;
769 perf_pmu_unregister(&pmu->pmu);
770 pmu->registered = false;
773 static void uncore_free_boxes(struct intel_uncore_pmu *pmu)
775 int pkg;
777 for (pkg = 0; pkg < max_packages; pkg++)
778 kfree(pmu->boxes[pkg]);
779 kfree(pmu->boxes);
782 static void uncore_type_exit(struct intel_uncore_type *type)
784 struct intel_uncore_pmu *pmu = type->pmus;
785 int i;
787 if (pmu) {
788 for (i = 0; i < type->num_boxes; i++, pmu++) {
789 uncore_pmu_unregister(pmu);
790 uncore_free_boxes(pmu);
792 kfree(type->pmus);
793 type->pmus = NULL;
795 kfree(type->events_group);
796 type->events_group = NULL;
799 static void uncore_types_exit(struct intel_uncore_type **types)
801 for (; *types; types++)
802 uncore_type_exit(*types);
805 static int __init uncore_type_init(struct intel_uncore_type *type, bool setid)
807 struct intel_uncore_pmu *pmus;
808 struct attribute_group *attr_group;
809 struct attribute **attrs;
810 size_t size;
811 int i, j;
813 pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
814 if (!pmus)
815 return -ENOMEM;
817 size = max_packages * sizeof(struct intel_uncore_box *);
819 for (i = 0; i < type->num_boxes; i++) {
820 pmus[i].func_id = setid ? i : -1;
821 pmus[i].pmu_idx = i;
822 pmus[i].type = type;
823 pmus[i].boxes = kzalloc(size, GFP_KERNEL);
824 if (!pmus[i].boxes)
825 return -ENOMEM;
828 type->pmus = pmus;
829 type->unconstrainted = (struct event_constraint)
830 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
831 0, type->num_counters, 0, 0);
833 if (type->event_descs) {
834 for (i = 0; type->event_descs[i].attr.attr.name; i++);
836 attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
837 sizeof(*attr_group), GFP_KERNEL);
838 if (!attr_group)
839 return -ENOMEM;
841 attrs = (struct attribute **)(attr_group + 1);
842 attr_group->name = "events";
843 attr_group->attrs = attrs;
845 for (j = 0; j < i; j++)
846 attrs[j] = &type->event_descs[j].attr.attr;
848 type->events_group = attr_group;
851 type->pmu_group = &uncore_pmu_attr_group;
852 return 0;
855 static int __init
856 uncore_types_init(struct intel_uncore_type **types, bool setid)
858 int ret;
860 for (; *types; types++) {
861 ret = uncore_type_init(*types, setid);
862 if (ret)
863 return ret;
865 return 0;
869 * add a pci uncore device
871 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
873 struct intel_uncore_type *type;
874 struct intel_uncore_pmu *pmu = NULL;
875 struct intel_uncore_box *box;
876 int phys_id, pkg, ret;
878 phys_id = uncore_pcibus_to_physid(pdev->bus);
879 if (phys_id < 0)
880 return -ENODEV;
882 pkg = topology_phys_to_logical_pkg(phys_id);
883 if (pkg < 0)
884 return -EINVAL;
886 if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
887 int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
889 uncore_extra_pci_dev[pkg].dev[idx] = pdev;
890 pci_set_drvdata(pdev, NULL);
891 return 0;
894 type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
897 * Some platforms, e.g. Knights Landing, use a common PCI device ID
898 * for multiple instances of an uncore PMU device type. We should check
899 * PCI slot and func to indicate the uncore box.
901 if (id->driver_data & ~0xffff) {
902 struct pci_driver *pci_drv = pdev->driver;
903 const struct pci_device_id *ids = pci_drv->id_table;
904 unsigned int devfn;
906 while (ids && ids->vendor) {
907 if ((ids->vendor == pdev->vendor) &&
908 (ids->device == pdev->device)) {
909 devfn = PCI_DEVFN(UNCORE_PCI_DEV_DEV(ids->driver_data),
910 UNCORE_PCI_DEV_FUNC(ids->driver_data));
911 if (devfn == pdev->devfn) {
912 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(ids->driver_data)];
913 break;
916 ids++;
918 if (pmu == NULL)
919 return -ENODEV;
920 } else {
922 * for performance monitoring unit with multiple boxes,
923 * each box has a different function id.
925 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
928 if (WARN_ON_ONCE(pmu->boxes[pkg] != NULL))
929 return -EINVAL;
931 box = uncore_alloc_box(type, NUMA_NO_NODE);
932 if (!box)
933 return -ENOMEM;
935 if (pmu->func_id < 0)
936 pmu->func_id = pdev->devfn;
937 else
938 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
940 atomic_inc(&box->refcnt);
941 box->pci_phys_id = phys_id;
942 box->pkgid = pkg;
943 box->pci_dev = pdev;
944 box->pmu = pmu;
945 uncore_box_init(box);
946 pci_set_drvdata(pdev, box);
948 pmu->boxes[pkg] = box;
949 if (atomic_inc_return(&pmu->activeboxes) > 1)
950 return 0;
952 /* First active box registers the pmu */
953 ret = uncore_pmu_register(pmu);
954 if (ret) {
955 pci_set_drvdata(pdev, NULL);
956 pmu->boxes[pkg] = NULL;
957 uncore_box_exit(box);
958 kfree(box);
960 return ret;
963 static void uncore_pci_remove(struct pci_dev *pdev)
965 struct intel_uncore_box *box;
966 struct intel_uncore_pmu *pmu;
967 int i, phys_id, pkg;
969 phys_id = uncore_pcibus_to_physid(pdev->bus);
970 pkg = topology_phys_to_logical_pkg(phys_id);
972 box = pci_get_drvdata(pdev);
973 if (!box) {
974 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
975 if (uncore_extra_pci_dev[pkg].dev[i] == pdev) {
976 uncore_extra_pci_dev[pkg].dev[i] = NULL;
977 break;
980 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
981 return;
984 pmu = box->pmu;
985 if (WARN_ON_ONCE(phys_id != box->pci_phys_id))
986 return;
988 pci_set_drvdata(pdev, NULL);
989 pmu->boxes[pkg] = NULL;
990 if (atomic_dec_return(&pmu->activeboxes) == 0)
991 uncore_pmu_unregister(pmu);
992 uncore_box_exit(box);
993 kfree(box);
996 static int __init uncore_pci_init(void)
998 size_t size;
999 int ret;
1001 size = max_packages * sizeof(struct pci_extra_dev);
1002 uncore_extra_pci_dev = kzalloc(size, GFP_KERNEL);
1003 if (!uncore_extra_pci_dev) {
1004 ret = -ENOMEM;
1005 goto err;
1008 ret = uncore_types_init(uncore_pci_uncores, false);
1009 if (ret)
1010 goto errtype;
1012 uncore_pci_driver->probe = uncore_pci_probe;
1013 uncore_pci_driver->remove = uncore_pci_remove;
1015 ret = pci_register_driver(uncore_pci_driver);
1016 if (ret)
1017 goto errtype;
1019 pcidrv_registered = true;
1020 return 0;
1022 errtype:
1023 uncore_types_exit(uncore_pci_uncores);
1024 kfree(uncore_extra_pci_dev);
1025 uncore_extra_pci_dev = NULL;
1026 uncore_free_pcibus_map();
1027 err:
1028 uncore_pci_uncores = empty_uncore;
1029 return ret;
1032 static void uncore_pci_exit(void)
1034 if (pcidrv_registered) {
1035 pcidrv_registered = false;
1036 pci_unregister_driver(uncore_pci_driver);
1037 uncore_types_exit(uncore_pci_uncores);
1038 kfree(uncore_extra_pci_dev);
1039 uncore_free_pcibus_map();
1043 static void uncore_change_type_ctx(struct intel_uncore_type *type, int old_cpu,
1044 int new_cpu)
1046 struct intel_uncore_pmu *pmu = type->pmus;
1047 struct intel_uncore_box *box;
1048 int i, pkg;
1050 pkg = topology_logical_package_id(old_cpu < 0 ? new_cpu : old_cpu);
1051 for (i = 0; i < type->num_boxes; i++, pmu++) {
1052 box = pmu->boxes[pkg];
1053 if (!box)
1054 continue;
1056 if (old_cpu < 0) {
1057 WARN_ON_ONCE(box->cpu != -1);
1058 box->cpu = new_cpu;
1059 continue;
1062 WARN_ON_ONCE(box->cpu != old_cpu);
1063 box->cpu = -1;
1064 if (new_cpu < 0)
1065 continue;
1067 uncore_pmu_cancel_hrtimer(box);
1068 perf_pmu_migrate_context(&pmu->pmu, old_cpu, new_cpu);
1069 box->cpu = new_cpu;
1073 static void uncore_change_context(struct intel_uncore_type **uncores,
1074 int old_cpu, int new_cpu)
1076 for (; *uncores; uncores++)
1077 uncore_change_type_ctx(*uncores, old_cpu, new_cpu);
1080 static int uncore_event_cpu_offline(unsigned int cpu)
1082 struct intel_uncore_type *type, **types = uncore_msr_uncores;
1083 struct intel_uncore_pmu *pmu;
1084 struct intel_uncore_box *box;
1085 int i, pkg, target;
1087 /* Check if exiting cpu is used for collecting uncore events */
1088 if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
1089 goto unref;
1090 /* Find a new cpu to collect uncore events */
1091 target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
1093 /* Migrate uncore events to the new target */
1094 if (target < nr_cpu_ids)
1095 cpumask_set_cpu(target, &uncore_cpu_mask);
1096 else
1097 target = -1;
1099 uncore_change_context(uncore_msr_uncores, cpu, target);
1100 uncore_change_context(uncore_pci_uncores, cpu, target);
1102 unref:
1103 /* Clear the references */
1104 pkg = topology_logical_package_id(cpu);
1105 for (; *types; types++) {
1106 type = *types;
1107 pmu = type->pmus;
1108 for (i = 0; i < type->num_boxes; i++, pmu++) {
1109 box = pmu->boxes[pkg];
1110 if (box && atomic_dec_return(&box->refcnt) == 0)
1111 uncore_box_exit(box);
1114 return 0;
1117 static int allocate_boxes(struct intel_uncore_type **types,
1118 unsigned int pkg, unsigned int cpu)
1120 struct intel_uncore_box *box, *tmp;
1121 struct intel_uncore_type *type;
1122 struct intel_uncore_pmu *pmu;
1123 LIST_HEAD(allocated);
1124 int i;
1126 /* Try to allocate all required boxes */
1127 for (; *types; types++) {
1128 type = *types;
1129 pmu = type->pmus;
1130 for (i = 0; i < type->num_boxes; i++, pmu++) {
1131 if (pmu->boxes[pkg])
1132 continue;
1133 box = uncore_alloc_box(type, cpu_to_node(cpu));
1134 if (!box)
1135 goto cleanup;
1136 box->pmu = pmu;
1137 box->pkgid = pkg;
1138 list_add(&box->active_list, &allocated);
1141 /* Install them in the pmus */
1142 list_for_each_entry_safe(box, tmp, &allocated, active_list) {
1143 list_del_init(&box->active_list);
1144 box->pmu->boxes[pkg] = box;
1146 return 0;
1148 cleanup:
1149 list_for_each_entry_safe(box, tmp, &allocated, active_list) {
1150 list_del_init(&box->active_list);
1151 kfree(box);
1153 return -ENOMEM;
1156 static int uncore_event_cpu_online(unsigned int cpu)
1158 struct intel_uncore_type *type, **types = uncore_msr_uncores;
1159 struct intel_uncore_pmu *pmu;
1160 struct intel_uncore_box *box;
1161 int i, ret, pkg, target;
1163 pkg = topology_logical_package_id(cpu);
1164 ret = allocate_boxes(types, pkg, cpu);
1165 if (ret)
1166 return ret;
1168 for (; *types; types++) {
1169 type = *types;
1170 pmu = type->pmus;
1171 for (i = 0; i < type->num_boxes; i++, pmu++) {
1172 box = pmu->boxes[pkg];
1173 if (box && atomic_inc_return(&box->refcnt) == 1)
1174 uncore_box_init(box);
1179 * Check if there is an online cpu in the package
1180 * which collects uncore events already.
1182 target = cpumask_any_and(&uncore_cpu_mask, topology_core_cpumask(cpu));
1183 if (target < nr_cpu_ids)
1184 return 0;
1186 cpumask_set_cpu(cpu, &uncore_cpu_mask);
1188 uncore_change_context(uncore_msr_uncores, -1, cpu);
1189 uncore_change_context(uncore_pci_uncores, -1, cpu);
1190 return 0;
1193 static int __init type_pmu_register(struct intel_uncore_type *type)
1195 int i, ret;
1197 for (i = 0; i < type->num_boxes; i++) {
1198 ret = uncore_pmu_register(&type->pmus[i]);
1199 if (ret)
1200 return ret;
1202 return 0;
1205 static int __init uncore_msr_pmus_register(void)
1207 struct intel_uncore_type **types = uncore_msr_uncores;
1208 int ret;
1210 for (; *types; types++) {
1211 ret = type_pmu_register(*types);
1212 if (ret)
1213 return ret;
1215 return 0;
1218 static int __init uncore_cpu_init(void)
1220 int ret;
1222 ret = uncore_types_init(uncore_msr_uncores, true);
1223 if (ret)
1224 goto err;
1226 ret = uncore_msr_pmus_register();
1227 if (ret)
1228 goto err;
1229 return 0;
1230 err:
1231 uncore_types_exit(uncore_msr_uncores);
1232 uncore_msr_uncores = empty_uncore;
1233 return ret;
1236 #define X86_UNCORE_MODEL_MATCH(model, init) \
1237 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init }
1239 struct intel_uncore_init_fun {
1240 void (*cpu_init)(void);
1241 int (*pci_init)(void);
1244 static const struct intel_uncore_init_fun nhm_uncore_init __initconst = {
1245 .cpu_init = nhm_uncore_cpu_init,
1248 static const struct intel_uncore_init_fun snb_uncore_init __initconst = {
1249 .cpu_init = snb_uncore_cpu_init,
1250 .pci_init = snb_uncore_pci_init,
1253 static const struct intel_uncore_init_fun ivb_uncore_init __initconst = {
1254 .cpu_init = snb_uncore_cpu_init,
1255 .pci_init = ivb_uncore_pci_init,
1258 static const struct intel_uncore_init_fun hsw_uncore_init __initconst = {
1259 .cpu_init = snb_uncore_cpu_init,
1260 .pci_init = hsw_uncore_pci_init,
1263 static const struct intel_uncore_init_fun bdw_uncore_init __initconst = {
1264 .cpu_init = snb_uncore_cpu_init,
1265 .pci_init = bdw_uncore_pci_init,
1268 static const struct intel_uncore_init_fun snbep_uncore_init __initconst = {
1269 .cpu_init = snbep_uncore_cpu_init,
1270 .pci_init = snbep_uncore_pci_init,
1273 static const struct intel_uncore_init_fun nhmex_uncore_init __initconst = {
1274 .cpu_init = nhmex_uncore_cpu_init,
1277 static const struct intel_uncore_init_fun ivbep_uncore_init __initconst = {
1278 .cpu_init = ivbep_uncore_cpu_init,
1279 .pci_init = ivbep_uncore_pci_init,
1282 static const struct intel_uncore_init_fun hswep_uncore_init __initconst = {
1283 .cpu_init = hswep_uncore_cpu_init,
1284 .pci_init = hswep_uncore_pci_init,
1287 static const struct intel_uncore_init_fun bdx_uncore_init __initconst = {
1288 .cpu_init = bdx_uncore_cpu_init,
1289 .pci_init = bdx_uncore_pci_init,
1292 static const struct intel_uncore_init_fun knl_uncore_init __initconst = {
1293 .cpu_init = knl_uncore_cpu_init,
1294 .pci_init = knl_uncore_pci_init,
1297 static const struct intel_uncore_init_fun skl_uncore_init __initconst = {
1298 .cpu_init = skl_uncore_cpu_init,
1299 .pci_init = skl_uncore_pci_init,
1302 static const struct intel_uncore_init_fun skx_uncore_init __initconst = {
1303 .cpu_init = skx_uncore_cpu_init,
1304 .pci_init = skx_uncore_pci_init,
1307 static const struct x86_cpu_id intel_uncore_match[] __initconst = {
1308 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM_EP, nhm_uncore_init),
1309 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM, nhm_uncore_init),
1310 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE, nhm_uncore_init),
1311 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EP, nhm_uncore_init),
1312 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE, snb_uncore_init),
1313 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE, ivb_uncore_init),
1314 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_CORE, hsw_uncore_init),
1315 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_ULT, hsw_uncore_init),
1316 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E, hsw_uncore_init),
1317 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_CORE, bdw_uncore_init),
1318 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, bdw_uncore_init),
1319 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, snbep_uncore_init),
1320 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM_EX, nhmex_uncore_init),
1321 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EX, nhmex_uncore_init),
1322 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE_X, ivbep_uncore_init),
1323 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_X, hswep_uncore_init),
1324 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, bdx_uncore_init),
1325 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, bdx_uncore_init),
1326 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_uncore_init),
1327 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM, knl_uncore_init),
1328 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP,skl_uncore_init),
1329 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_uncore_init),
1330 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, skx_uncore_init),
1331 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_uncore_init),
1332 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_uncore_init),
1336 MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);
1338 static int __init intel_uncore_init(void)
1340 const struct x86_cpu_id *id;
1341 struct intel_uncore_init_fun *uncore_init;
1342 int pret = 0, cret = 0, ret;
1344 id = x86_match_cpu(intel_uncore_match);
1345 if (!id)
1346 return -ENODEV;
1348 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1349 return -ENODEV;
1351 max_packages = topology_max_packages();
1353 uncore_init = (struct intel_uncore_init_fun *)id->driver_data;
1354 if (uncore_init->pci_init) {
1355 pret = uncore_init->pci_init();
1356 if (!pret)
1357 pret = uncore_pci_init();
1360 if (uncore_init->cpu_init) {
1361 uncore_init->cpu_init();
1362 cret = uncore_cpu_init();
1365 if (cret && pret)
1366 return -ENODEV;
1368 /* Install hotplug callbacks to setup the targets for each package */
1369 ret = cpuhp_setup_state(CPUHP_AP_PERF_X86_UNCORE_ONLINE,
1370 "perf/x86/intel/uncore:online",
1371 uncore_event_cpu_online,
1372 uncore_event_cpu_offline);
1373 if (ret)
1374 goto err;
1375 return 0;
1377 err:
1378 uncore_types_exit(uncore_msr_uncores);
1379 uncore_pci_exit();
1380 return ret;
1382 module_init(intel_uncore_init);
1384 static void __exit intel_uncore_exit(void)
1386 cpuhp_remove_state(CPUHP_AP_PERF_X86_UNCORE_ONLINE);
1387 uncore_types_exit(uncore_msr_uncores);
1388 uncore_pci_exit();
1390 module_exit(intel_uncore_exit);