?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.13.16
[linux/fpc-iii.git] / arch / x86 / kvm / vmx.c
blob118709e7597d7eaac4974ef23833dd32412e3173
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22 #include "lapic.h"
23
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
38 #include "x86.h"
39
40 #include <asm/cpu.h>
41 #include <asm/io.h>
42 #include <asm/desc.h>
43 #include <asm/vmx.h>
44 #include <asm/virtext.h>
45 #include <asm/mce.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
50 #include <asm/apic.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53
54 #include "trace.h"
55 #include "pmu.h"
56
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
60
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
63
64 static const struct x86_cpu_id vmx_cpu_id[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 {}
67 };
68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
69
70 static bool __read_mostly enable_vpid = 1;
71 module_param_named(vpid, enable_vpid, bool, 0444);
72
73 static bool __read_mostly flexpriority_enabled = 1;
74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
75
76 static bool __read_mostly enable_ept = 1;
77 module_param_named(ept, enable_ept, bool, S_IRUGO);
78
79 static bool __read_mostly enable_unrestricted_guest = 1;
80 module_param_named(unrestricted_guest,
81 enable_unrestricted_guest, bool, S_IRUGO);
82
83 static bool __read_mostly enable_ept_ad_bits = 1;
84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
85
86 static bool __read_mostly emulate_invalid_guest_state = true;
87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
88
89 static bool __read_mostly fasteoi = 1;
90 module_param(fasteoi, bool, S_IRUGO);
91
92 static bool __read_mostly enable_apicv = 1;
93 module_param(enable_apicv, bool, S_IRUGO);
94
95 static bool __read_mostly enable_shadow_vmcs = 1;
96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
97 /*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
102 static bool __read_mostly nested = 0;
103 module_param(nested, bool, S_IRUGO);
104
105 static u64 __read_mostly host_xss;
106
107 static bool __read_mostly enable_pml = 1;
108 module_param_named(pml, enable_pml, bool, S_IRUGO);
109
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
111
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi;
114 static bool __read_mostly enable_preemption_timer = 1;
115 #ifdef CONFIG_X86_64
116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
117 #endif
118
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
126
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
129
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
131
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133
134 /*
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
137 */
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143
144 /*
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
154 */
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
161
162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
163 module_param(ple_gap, int, S_IRUGO);
164
165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
166 module_param(ple_window, int, S_IRUGO);
167
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
170 module_param(ple_window_grow, int, S_IRUGO);
171
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
174 module_param(ple_window_shrink, int, S_IRUGO);
175
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, int, S_IRUGO);
180
181 extern const ulong vmx_return;
182
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
185
186 struct vmcs {
187 u32 revision_id;
188 u32 abort;
189 char data[0];
190 };
191
192 /*
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
196 */
197 struct loaded_vmcs {
198 struct vmcs *vmcs;
199 struct vmcs *shadow_vmcs;
200 int cpu;
201 bool launched;
202 bool nmi_known_unmasked;
203 unsigned long vmcs_host_cr3; /* May not match real cr3 */
204 unsigned long vmcs_host_cr4; /* May not match real cr4 */
205 struct list_head loaded_vmcss_on_cpu_link;
206 };
207
208 struct shared_msr_entry {
209 unsigned index;
210 u64 data;
211 u64 mask;
212 };
213
214 /*
215 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
216 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
217 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
218 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
219 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
220 * More than one of these structures may exist, if L1 runs multiple L2 guests.
221 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
222 * underlying hardware which will be used to run L2.
223 * This structure is packed to ensure that its layout is identical across
224 * machines (necessary for live migration).
225 * If there are changes in this struct, VMCS12_REVISION must be changed.
226 */
227 typedef u64 natural_width;
228 struct __packed vmcs12 {
229 /* According to the Intel spec, a VMCS region must start with the
230 * following two fields. Then follow implementation-specific data.
231 */
232 u32 revision_id;
233 u32 abort;
234
235 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
236 u32 padding[7]; /* room for future expansion */
237
238 u64 io_bitmap_a;
239 u64 io_bitmap_b;
240 u64 msr_bitmap;
241 u64 vm_exit_msr_store_addr;
242 u64 vm_exit_msr_load_addr;
243 u64 vm_entry_msr_load_addr;
244 u64 tsc_offset;
245 u64 virtual_apic_page_addr;
246 u64 apic_access_addr;
247 u64 posted_intr_desc_addr;
248 u64 ept_pointer;
249 u64 eoi_exit_bitmap0;
250 u64 eoi_exit_bitmap1;
251 u64 eoi_exit_bitmap2;
252 u64 eoi_exit_bitmap3;
253 u64 xss_exit_bitmap;
254 u64 guest_physical_address;
255 u64 vmcs_link_pointer;
256 u64 pml_address;
257 u64 guest_ia32_debugctl;
258 u64 guest_ia32_pat;
259 u64 guest_ia32_efer;
260 u64 guest_ia32_perf_global_ctrl;
261 u64 guest_pdptr0;
262 u64 guest_pdptr1;
263 u64 guest_pdptr2;
264 u64 guest_pdptr3;
265 u64 guest_bndcfgs;
266 u64 host_ia32_pat;
267 u64 host_ia32_efer;
268 u64 host_ia32_perf_global_ctrl;
269 u64 padding64[8]; /* room for future expansion */
270 /*
271 * To allow migration of L1 (complete with its L2 guests) between
272 * machines of different natural widths (32 or 64 bit), we cannot have
273 * unsigned long fields with no explict size. We use u64 (aliased
274 * natural_width) instead. Luckily, x86 is little-endian.
275 */
276 natural_width cr0_guest_host_mask;
277 natural_width cr4_guest_host_mask;
278 natural_width cr0_read_shadow;
279 natural_width cr4_read_shadow;
280 natural_width cr3_target_value0;
281 natural_width cr3_target_value1;
282 natural_width cr3_target_value2;
283 natural_width cr3_target_value3;
284 natural_width exit_qualification;
285 natural_width guest_linear_address;
286 natural_width guest_cr0;
287 natural_width guest_cr3;
288 natural_width guest_cr4;
289 natural_width guest_es_base;
290 natural_width guest_cs_base;
291 natural_width guest_ss_base;
292 natural_width guest_ds_base;
293 natural_width guest_fs_base;
294 natural_width guest_gs_base;
295 natural_width guest_ldtr_base;
296 natural_width guest_tr_base;
297 natural_width guest_gdtr_base;
298 natural_width guest_idtr_base;
299 natural_width guest_dr7;
300 natural_width guest_rsp;
301 natural_width guest_rip;
302 natural_width guest_rflags;
303 natural_width guest_pending_dbg_exceptions;
304 natural_width guest_sysenter_esp;
305 natural_width guest_sysenter_eip;
306 natural_width host_cr0;
307 natural_width host_cr3;
308 natural_width host_cr4;
309 natural_width host_fs_base;
310 natural_width host_gs_base;
311 natural_width host_tr_base;
312 natural_width host_gdtr_base;
313 natural_width host_idtr_base;
314 natural_width host_ia32_sysenter_esp;
315 natural_width host_ia32_sysenter_eip;
316 natural_width host_rsp;
317 natural_width host_rip;
318 natural_width paddingl[8]; /* room for future expansion */
319 u32 pin_based_vm_exec_control;
320 u32 cpu_based_vm_exec_control;
321 u32 exception_bitmap;
322 u32 page_fault_error_code_mask;
323 u32 page_fault_error_code_match;
324 u32 cr3_target_count;
325 u32 vm_exit_controls;
326 u32 vm_exit_msr_store_count;
327 u32 vm_exit_msr_load_count;
328 u32 vm_entry_controls;
329 u32 vm_entry_msr_load_count;
330 u32 vm_entry_intr_info_field;
331 u32 vm_entry_exception_error_code;
332 u32 vm_entry_instruction_len;
333 u32 tpr_threshold;
334 u32 secondary_vm_exec_control;
335 u32 vm_instruction_error;
336 u32 vm_exit_reason;
337 u32 vm_exit_intr_info;
338 u32 vm_exit_intr_error_code;
339 u32 idt_vectoring_info_field;
340 u32 idt_vectoring_error_code;
341 u32 vm_exit_instruction_len;
342 u32 vmx_instruction_info;
343 u32 guest_es_limit;
344 u32 guest_cs_limit;
345 u32 guest_ss_limit;
346 u32 guest_ds_limit;
347 u32 guest_fs_limit;
348 u32 guest_gs_limit;
349 u32 guest_ldtr_limit;
350 u32 guest_tr_limit;
351 u32 guest_gdtr_limit;
352 u32 guest_idtr_limit;
353 u32 guest_es_ar_bytes;
354 u32 guest_cs_ar_bytes;
355 u32 guest_ss_ar_bytes;
356 u32 guest_ds_ar_bytes;
357 u32 guest_fs_ar_bytes;
358 u32 guest_gs_ar_bytes;
359 u32 guest_ldtr_ar_bytes;
360 u32 guest_tr_ar_bytes;
361 u32 guest_interruptibility_info;
362 u32 guest_activity_state;
363 u32 guest_sysenter_cs;
364 u32 host_ia32_sysenter_cs;
365 u32 vmx_preemption_timer_value;
366 u32 padding32[7]; /* room for future expansion */
367 u16 virtual_processor_id;
368 u16 posted_intr_nv;
369 u16 guest_es_selector;
370 u16 guest_cs_selector;
371 u16 guest_ss_selector;
372 u16 guest_ds_selector;
373 u16 guest_fs_selector;
374 u16 guest_gs_selector;
375 u16 guest_ldtr_selector;
376 u16 guest_tr_selector;
377 u16 guest_intr_status;
378 u16 guest_pml_index;
379 u16 host_es_selector;
380 u16 host_cs_selector;
381 u16 host_ss_selector;
382 u16 host_ds_selector;
383 u16 host_fs_selector;
384 u16 host_gs_selector;
385 u16 host_tr_selector;
386 };
387
388 /*
389 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
390 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
391 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
392 */
393 #define VMCS12_REVISION 0x11e57ed0
394
395 /*
396 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
397 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
398 * current implementation, 4K are reserved to avoid future complications.
399 */
400 #define VMCS12_SIZE 0x1000
401
402 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
403 struct vmcs02_list {
404 struct list_head list;
405 gpa_t vmptr;
406 struct loaded_vmcs vmcs02;
407 };
408
409 /*
410 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
411 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
412 */
413 struct nested_vmx {
414 /* Has the level1 guest done vmxon? */
415 bool vmxon;
416 gpa_t vmxon_ptr;
417 bool pml_full;
418
419 /* The guest-physical address of the current VMCS L1 keeps for L2 */
420 gpa_t current_vmptr;
421 /*
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMCLEAR and VMPTRLD.
425 */
426 struct vmcs12 *cached_vmcs12;
427 /*
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
430 */
431 bool sync_shadow_vmcs;
432
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool;
435 int vmcs02_num;
436 bool change_vmcs01_virtual_x2apic_mode;
437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending;
439 /*
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
442 */
443 struct page *apic_access_page;
444 struct page *virtual_apic_page;
445 struct page *pi_desc_page;
446 struct pi_desc *pi_desc;
447 bool pi_pending;
448 u16 posted_intr_nv;
449
450 unsigned long *msr_bitmap;
451
452 struct hrtimer preemption_timer;
453 bool preemption_timer_expired;
454
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
456 u64 vmcs01_debugctl;
457
458 u16 vpid02;
459 u16 last_vpid;
460
461 /*
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
465 */
466 u32 nested_vmx_procbased_ctls_low;
467 u32 nested_vmx_procbased_ctls_high;
468 u32 nested_vmx_secondary_ctls_low;
469 u32 nested_vmx_secondary_ctls_high;
470 u32 nested_vmx_pinbased_ctls_low;
471 u32 nested_vmx_pinbased_ctls_high;
472 u32 nested_vmx_exit_ctls_low;
473 u32 nested_vmx_exit_ctls_high;
474 u32 nested_vmx_entry_ctls_low;
475 u32 nested_vmx_entry_ctls_high;
476 u32 nested_vmx_misc_low;
477 u32 nested_vmx_misc_high;
478 u32 nested_vmx_ept_caps;
479 u32 nested_vmx_vpid_caps;
480 u64 nested_vmx_basic;
481 u64 nested_vmx_cr0_fixed0;
482 u64 nested_vmx_cr0_fixed1;
483 u64 nested_vmx_cr4_fixed0;
484 u64 nested_vmx_cr4_fixed1;
485 u64 nested_vmx_vmcs_enum;
486 };
487
488 #define POSTED_INTR_ON 0
489 #define POSTED_INTR_SN 1
490
491 /* Posted-Interrupt Descriptor */
492 struct pi_desc {
493 u32 pir[8]; /* Posted interrupt requested */
494 union {
495 struct {
496 /* bit 256 - Outstanding Notification */
497 u16 on : 1,
498 /* bit 257 - Suppress Notification */
499 sn : 1,
500 /* bit 271:258 - Reserved */
501 rsvd_1 : 14;
502 /* bit 279:272 - Notification Vector */
503 u8 nv;
504 /* bit 287:280 - Reserved */
505 u8 rsvd_2;
506 /* bit 319:288 - Notification Destination */
507 u32 ndst;
508 };
509 u64 control;
510 };
511 u32 rsvd[6];
512 } __aligned(64);
513
514 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
515 {
516 return test_and_set_bit(POSTED_INTR_ON,
517 (unsigned long *)&pi_desc->control);
518 }
519
520 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
521 {
522 return test_and_clear_bit(POSTED_INTR_ON,
523 (unsigned long *)&pi_desc->control);
524 }
525
526 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
527 {
528 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
529 }
530
531 static inline void pi_clear_sn(struct pi_desc *pi_desc)
532 {
533 return clear_bit(POSTED_INTR_SN,
534 (unsigned long *)&pi_desc->control);
535 }
536
537 static inline void pi_set_sn(struct pi_desc *pi_desc)
538 {
539 return set_bit(POSTED_INTR_SN,
540 (unsigned long *)&pi_desc->control);
541 }
542
543 static inline void pi_clear_on(struct pi_desc *pi_desc)
544 {
545 clear_bit(POSTED_INTR_ON,
546 (unsigned long *)&pi_desc->control);
547 }
548
549 static inline int pi_test_on(struct pi_desc *pi_desc)
550 {
551 return test_bit(POSTED_INTR_ON,
552 (unsigned long *)&pi_desc->control);
553 }
554
555 static inline int pi_test_sn(struct pi_desc *pi_desc)
556 {
557 return test_bit(POSTED_INTR_SN,
558 (unsigned long *)&pi_desc->control);
559 }
560
561 struct vcpu_vmx {
562 struct kvm_vcpu vcpu;
563 unsigned long host_rsp;
564 u8 fail;
565 u32 exit_intr_info;
566 u32 idt_vectoring_info;
567 ulong rflags;
568 struct shared_msr_entry *guest_msrs;
569 int nmsrs;
570 int save_nmsrs;
571 unsigned long host_idt_base;
572 #ifdef CONFIG_X86_64
573 u64 msr_host_kernel_gs_base;
574 u64 msr_guest_kernel_gs_base;
575 #endif
576 u32 vm_entry_controls_shadow;
577 u32 vm_exit_controls_shadow;
578 /*
579 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
580 * non-nested (L1) guest, it always points to vmcs01. For a nested
581 * guest (L2), it points to a different VMCS.
582 */
583 struct loaded_vmcs vmcs01;
584 struct loaded_vmcs *loaded_vmcs;
585 bool __launched; /* temporary, used in vmx_vcpu_run */
586 struct msr_autoload {
587 unsigned nr;
588 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
589 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
590 } msr_autoload;
591 struct {
592 int loaded;
593 u16 fs_sel, gs_sel, ldt_sel;
594 #ifdef CONFIG_X86_64
595 u16 ds_sel, es_sel;
596 #endif
597 int gs_ldt_reload_needed;
598 int fs_reload_needed;
599 u64 msr_host_bndcfgs;
600 } host_state;
601 struct {
602 int vm86_active;
603 ulong save_rflags;
604 struct kvm_segment segs[8];
605 } rmode;
606 struct {
607 u32 bitmask; /* 4 bits per segment (1 bit per field) */
608 struct kvm_save_segment {
609 u16 selector;
610 unsigned long base;
611 u32 limit;
612 u32 ar;
613 } seg[8];
614 } segment_cache;
615 int vpid;
616 bool emulation_required;
617
618 u32 exit_reason;
619
620 /* Posted interrupt descriptor */
621 struct pi_desc pi_desc;
622
623 /* Support for a guest hypervisor (nested VMX) */
624 struct nested_vmx nested;
625
626 /* Dynamic PLE window. */
627 int ple_window;
628 bool ple_window_dirty;
629
630 /* Support for PML */
631 #define PML_ENTITY_NUM 512
632 struct page *pml_pg;
633
634 /* apic deadline value in host tsc */
635 u64 hv_deadline_tsc;
636
637 u64 current_tsc_ratio;
638
639 u32 host_pkru;
640
641 /*
642 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
643 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
644 * in msr_ia32_feature_control_valid_bits.
645 */
646 u64 msr_ia32_feature_control;
647 u64 msr_ia32_feature_control_valid_bits;
648 };
649
650 enum segment_cache_field {
651 SEG_FIELD_SEL = 0,
652 SEG_FIELD_BASE = 1,
653 SEG_FIELD_LIMIT = 2,
654 SEG_FIELD_AR = 3,
655
656 SEG_FIELD_NR = 4
657 };
658
659 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
660 {
661 return container_of(vcpu, struct vcpu_vmx, vcpu);
662 }
663
664 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
665 {
666 return &(to_vmx(vcpu)->pi_desc);
667 }
668
669 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
670 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
671 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
672 [number##_HIGH] = VMCS12_OFFSET(name)+4
673
674
675 static unsigned long shadow_read_only_fields[] = {
676 /*
677 * We do NOT shadow fields that are modified when L0
678 * traps and emulates any vmx instruction (e.g. VMPTRLD,
679 * VMXON...) executed by L1.
680 * For example, VM_INSTRUCTION_ERROR is read
681 * by L1 if a vmx instruction fails (part of the error path).
682 * Note the code assumes this logic. If for some reason
683 * we start shadowing these fields then we need to
684 * force a shadow sync when L0 emulates vmx instructions
685 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
686 * by nested_vmx_failValid)
687 */
688 VM_EXIT_REASON,
689 VM_EXIT_INTR_INFO,
690 VM_EXIT_INSTRUCTION_LEN,
691 IDT_VECTORING_INFO_FIELD,
692 IDT_VECTORING_ERROR_CODE,
693 VM_EXIT_INTR_ERROR_CODE,
694 EXIT_QUALIFICATION,
695 GUEST_LINEAR_ADDRESS,
696 GUEST_PHYSICAL_ADDRESS
697 };
698 static int max_shadow_read_only_fields =
699 ARRAY_SIZE(shadow_read_only_fields);
700
701 static unsigned long shadow_read_write_fields[] = {
702 TPR_THRESHOLD,
703 GUEST_RIP,
704 GUEST_RSP,
705 GUEST_CR0,
706 GUEST_CR3,
707 GUEST_CR4,
708 GUEST_INTERRUPTIBILITY_INFO,
709 GUEST_RFLAGS,
710 GUEST_CS_SELECTOR,
711 GUEST_CS_AR_BYTES,
712 GUEST_CS_LIMIT,
713 GUEST_CS_BASE,
714 GUEST_ES_BASE,
715 GUEST_BNDCFGS,
716 CR0_GUEST_HOST_MASK,
717 CR0_READ_SHADOW,
718 CR4_READ_SHADOW,
719 TSC_OFFSET,
720 EXCEPTION_BITMAP,
721 CPU_BASED_VM_EXEC_CONTROL,
722 VM_ENTRY_EXCEPTION_ERROR_CODE,
723 VM_ENTRY_INTR_INFO_FIELD,
724 VM_ENTRY_INSTRUCTION_LEN,
725 VM_ENTRY_EXCEPTION_ERROR_CODE,
726 HOST_FS_BASE,
727 HOST_GS_BASE,
728 HOST_FS_SELECTOR,
729 HOST_GS_SELECTOR
730 };
731 static int max_shadow_read_write_fields =
732 ARRAY_SIZE(shadow_read_write_fields);
733
734 static const unsigned short vmcs_field_to_offset_table[] = {
735 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
736 FIELD(POSTED_INTR_NV, posted_intr_nv),
737 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
738 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
739 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
740 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
741 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
742 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
743 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
744 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
745 FIELD(GUEST_INTR_STATUS, guest_intr_status),
746 FIELD(GUEST_PML_INDEX, guest_pml_index),
747 FIELD(HOST_ES_SELECTOR, host_es_selector),
748 FIELD(HOST_CS_SELECTOR, host_cs_selector),
749 FIELD(HOST_SS_SELECTOR, host_ss_selector),
750 FIELD(HOST_DS_SELECTOR, host_ds_selector),
751 FIELD(HOST_FS_SELECTOR, host_fs_selector),
752 FIELD(HOST_GS_SELECTOR, host_gs_selector),
753 FIELD(HOST_TR_SELECTOR, host_tr_selector),
754 FIELD64(IO_BITMAP_A, io_bitmap_a),
755 FIELD64(IO_BITMAP_B, io_bitmap_b),
756 FIELD64(MSR_BITMAP, msr_bitmap),
757 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
758 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
759 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
760 FIELD64(TSC_OFFSET, tsc_offset),
761 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
762 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
763 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
764 FIELD64(EPT_POINTER, ept_pointer),
765 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
766 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
767 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
768 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
769 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
770 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
771 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
772 FIELD64(PML_ADDRESS, pml_address),
773 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
774 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
775 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
776 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
777 FIELD64(GUEST_PDPTR0, guest_pdptr0),
778 FIELD64(GUEST_PDPTR1, guest_pdptr1),
779 FIELD64(GUEST_PDPTR2, guest_pdptr2),
780 FIELD64(GUEST_PDPTR3, guest_pdptr3),
781 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
782 FIELD64(HOST_IA32_PAT, host_ia32_pat),
783 FIELD64(HOST_IA32_EFER, host_ia32_efer),
784 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
785 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
786 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
787 FIELD(EXCEPTION_BITMAP, exception_bitmap),
788 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
789 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
790 FIELD(CR3_TARGET_COUNT, cr3_target_count),
791 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
792 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
793 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
794 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
795 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
796 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
797 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
798 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
799 FIELD(TPR_THRESHOLD, tpr_threshold),
800 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
801 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
802 FIELD(VM_EXIT_REASON, vm_exit_reason),
803 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
804 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
805 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
806 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
807 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
808 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
809 FIELD(GUEST_ES_LIMIT, guest_es_limit),
810 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
811 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
812 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
813 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
814 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
815 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
816 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
817 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
818 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
819 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
820 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
821 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
822 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
823 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
824 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
825 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
826 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
827 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
828 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
829 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
830 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
831 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
832 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
833 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
834 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
835 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
836 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
837 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
838 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
839 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
840 FIELD(EXIT_QUALIFICATION, exit_qualification),
841 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
842 FIELD(GUEST_CR0, guest_cr0),
843 FIELD(GUEST_CR3, guest_cr3),
844 FIELD(GUEST_CR4, guest_cr4),
845 FIELD(GUEST_ES_BASE, guest_es_base),
846 FIELD(GUEST_CS_BASE, guest_cs_base),
847 FIELD(GUEST_SS_BASE, guest_ss_base),
848 FIELD(GUEST_DS_BASE, guest_ds_base),
849 FIELD(GUEST_FS_BASE, guest_fs_base),
850 FIELD(GUEST_GS_BASE, guest_gs_base),
851 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
852 FIELD(GUEST_TR_BASE, guest_tr_base),
853 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
854 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
855 FIELD(GUEST_DR7, guest_dr7),
856 FIELD(GUEST_RSP, guest_rsp),
857 FIELD(GUEST_RIP, guest_rip),
858 FIELD(GUEST_RFLAGS, guest_rflags),
859 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
860 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
861 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
862 FIELD(HOST_CR0, host_cr0),
863 FIELD(HOST_CR3, host_cr3),
864 FIELD(HOST_CR4, host_cr4),
865 FIELD(HOST_FS_BASE, host_fs_base),
866 FIELD(HOST_GS_BASE, host_gs_base),
867 FIELD(HOST_TR_BASE, host_tr_base),
868 FIELD(HOST_GDTR_BASE, host_gdtr_base),
869 FIELD(HOST_IDTR_BASE, host_idtr_base),
870 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
871 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
872 FIELD(HOST_RSP, host_rsp),
873 FIELD(HOST_RIP, host_rip),
874 };
875
876 static inline short vmcs_field_to_offset(unsigned long field)
877 {
878 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
879
880 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
881 vmcs_field_to_offset_table[field] == 0)
882 return -ENOENT;
883
884 return vmcs_field_to_offset_table[field];
885 }
886
887 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
888 {
889 return to_vmx(vcpu)->nested.cached_vmcs12;
890 }
891
892 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
893 {
894 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
895 if (is_error_page(page))
896 return NULL;
897
898 return page;
899 }
900
901 static void nested_release_page(struct page *page)
902 {
903 kvm_release_page_dirty(page);
904 }
905
906 static void nested_release_page_clean(struct page *page)
907 {
908 kvm_release_page_clean(page);
909 }
910
911 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
912 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
913 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
914 static bool vmx_xsaves_supported(void);
915 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
916 static void vmx_set_segment(struct kvm_vcpu *vcpu,
917 struct kvm_segment *var, int seg);
918 static void vmx_get_segment(struct kvm_vcpu *vcpu,
919 struct kvm_segment *var, int seg);
920 static bool guest_state_valid(struct kvm_vcpu *vcpu);
921 static u32 vmx_segment_access_rights(struct kvm_segment *var);
922 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
923 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
924 static int alloc_identity_pagetable(struct kvm *kvm);
925 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
926 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
927 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
928 u16 error_code);
929
930 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
931 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
932 /*
933 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
934 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
935 */
936 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
937
938 /*
939 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
940 * can find which vCPU should be waken up.
941 */
942 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
943 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
944
945 enum {
946 VMX_IO_BITMAP_A,
947 VMX_IO_BITMAP_B,
948 VMX_MSR_BITMAP_LEGACY,
949 VMX_MSR_BITMAP_LONGMODE,
950 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
951 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
952 VMX_MSR_BITMAP_LEGACY_X2APIC,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC,
954 VMX_VMREAD_BITMAP,
955 VMX_VMWRITE_BITMAP,
956 VMX_BITMAP_NR
957 };
958
959 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
960
961 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
962 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
963 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
964 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
965 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
966 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
967 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
968 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
969 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
970 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
971
972 static bool cpu_has_load_ia32_efer;
973 static bool cpu_has_load_perf_global_ctrl;
974
975 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
976 static DEFINE_SPINLOCK(vmx_vpid_lock);
977
978 static struct vmcs_config {
979 int size;
980 int order;
981 u32 basic_cap;
982 u32 revision_id;
983 u32 pin_based_exec_ctrl;
984 u32 cpu_based_exec_ctrl;
985 u32 cpu_based_2nd_exec_ctrl;
986 u32 vmexit_ctrl;
987 u32 vmentry_ctrl;
988 } vmcs_config;
989
990 static struct vmx_capability {
991 u32 ept;
992 u32 vpid;
993 } vmx_capability;
994
995 #define VMX_SEGMENT_FIELD(seg) \
996 [VCPU_SREG_##seg] = { \
997 .selector = GUEST_##seg##_SELECTOR, \
998 .base = GUEST_##seg##_BASE, \
999 .limit = GUEST_##seg##_LIMIT, \
1000 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1001 }
1002
1003 static const struct kvm_vmx_segment_field {
1004 unsigned selector;
1005 unsigned base;
1006 unsigned limit;
1007 unsigned ar_bytes;
1008 } kvm_vmx_segment_fields[] = {
1009 VMX_SEGMENT_FIELD(CS),
1010 VMX_SEGMENT_FIELD(DS),
1011 VMX_SEGMENT_FIELD(ES),
1012 VMX_SEGMENT_FIELD(FS),
1013 VMX_SEGMENT_FIELD(GS),
1014 VMX_SEGMENT_FIELD(SS),
1015 VMX_SEGMENT_FIELD(TR),
1016 VMX_SEGMENT_FIELD(LDTR),
1017 };
1018
1019 static u64 host_efer;
1020
1021 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1022
1023 /*
1024 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1025 * away by decrementing the array size.
1026 */
1027 static const u32 vmx_msr_index[] = {
1028 #ifdef CONFIG_X86_64
1029 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1030 #endif
1031 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1032 };
1033
1034 static inline bool is_exception_n(u32 intr_info, u8 vector)
1035 {
1036 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1037 INTR_INFO_VALID_MASK)) ==
1038 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1039 }
1040
1041 static inline bool is_debug(u32 intr_info)
1042 {
1043 return is_exception_n(intr_info, DB_VECTOR);
1044 }
1045
1046 static inline bool is_breakpoint(u32 intr_info)
1047 {
1048 return is_exception_n(intr_info, BP_VECTOR);
1049 }
1050
1051 static inline bool is_page_fault(u32 intr_info)
1052 {
1053 return is_exception_n(intr_info, PF_VECTOR);
1054 }
1055
1056 static inline bool is_no_device(u32 intr_info)
1057 {
1058 return is_exception_n(intr_info, NM_VECTOR);
1059 }
1060
1061 static inline bool is_invalid_opcode(u32 intr_info)
1062 {
1063 return is_exception_n(intr_info, UD_VECTOR);
1064 }
1065
1066 static inline bool is_external_interrupt(u32 intr_info)
1067 {
1068 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1069 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1070 }
1071
1072 static inline bool is_machine_check(u32 intr_info)
1073 {
1074 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1075 INTR_INFO_VALID_MASK)) ==
1076 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1077 }
1078
1079 static inline bool cpu_has_vmx_msr_bitmap(void)
1080 {
1081 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1082 }
1083
1084 static inline bool cpu_has_vmx_tpr_shadow(void)
1085 {
1086 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1087 }
1088
1089 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1090 {
1091 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1092 }
1093
1094 static inline bool cpu_has_secondary_exec_ctrls(void)
1095 {
1096 return vmcs_config.cpu_based_exec_ctrl &
1097 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1098 }
1099
1100 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1101 {
1102 return vmcs_config.cpu_based_2nd_exec_ctrl &
1103 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1104 }
1105
1106 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1107 {
1108 return vmcs_config.cpu_based_2nd_exec_ctrl &
1109 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1110 }
1111
1112 static inline bool cpu_has_vmx_apic_register_virt(void)
1113 {
1114 return vmcs_config.cpu_based_2nd_exec_ctrl &
1115 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1116 }
1117
1118 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1119 {
1120 return vmcs_config.cpu_based_2nd_exec_ctrl &
1121 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1122 }
1123
1124 /*
1125 * Comment's format: document - errata name - stepping - processor name.
1126 * Refer from
1127 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1128 */
1129 static u32 vmx_preemption_cpu_tfms[] = {
1130 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1131 0x000206E6,
1132 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1133 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1134 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1135 0x00020652,
1136 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020655,
1138 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1139 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1140 /*
1141 * 320767.pdf - AAP86 - B1 -
1142 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1143 */
1144 0x000106E5,
1145 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1146 0x000106A0,
1147 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1148 0x000106A1,
1149 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1150 0x000106A4,
1151 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1152 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1153 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1154 0x000106A5,
1155 };
1156
1157 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1158 {
1159 u32 eax = cpuid_eax(0x00000001), i;
1160
1161 /* Clear the reserved bits */
1162 eax &= ~(0x3U << 14 | 0xfU << 28);
1163 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1164 if (eax == vmx_preemption_cpu_tfms[i])
1165 return true;
1166
1167 return false;
1168 }
1169
1170 static inline bool cpu_has_vmx_preemption_timer(void)
1171 {
1172 return vmcs_config.pin_based_exec_ctrl &
1173 PIN_BASED_VMX_PREEMPTION_TIMER;
1174 }
1175
1176 static inline bool cpu_has_vmx_posted_intr(void)
1177 {
1178 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1179 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1180 }
1181
1182 static inline bool cpu_has_vmx_apicv(void)
1183 {
1184 return cpu_has_vmx_apic_register_virt() &&
1185 cpu_has_vmx_virtual_intr_delivery() &&
1186 cpu_has_vmx_posted_intr();
1187 }
1188
1189 static inline bool cpu_has_vmx_flexpriority(void)
1190 {
1191 return cpu_has_vmx_tpr_shadow() &&
1192 cpu_has_vmx_virtualize_apic_accesses();
1193 }
1194
1195 static inline bool cpu_has_vmx_ept_execute_only(void)
1196 {
1197 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1198 }
1199
1200 static inline bool cpu_has_vmx_ept_2m_page(void)
1201 {
1202 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1203 }
1204
1205 static inline bool cpu_has_vmx_ept_1g_page(void)
1206 {
1207 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1208 }
1209
1210 static inline bool cpu_has_vmx_ept_4levels(void)
1211 {
1212 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1213 }
1214
1215 static inline bool cpu_has_vmx_ept_ad_bits(void)
1216 {
1217 return vmx_capability.ept & VMX_EPT_AD_BIT;
1218 }
1219
1220 static inline bool cpu_has_vmx_invept_context(void)
1221 {
1222 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1223 }
1224
1225 static inline bool cpu_has_vmx_invept_global(void)
1226 {
1227 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1228 }
1229
1230 static inline bool cpu_has_vmx_invvpid_single(void)
1231 {
1232 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1233 }
1234
1235 static inline bool cpu_has_vmx_invvpid_global(void)
1236 {
1237 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1238 }
1239
1240 static inline bool cpu_has_vmx_invvpid(void)
1241 {
1242 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1243 }
1244
1245 static inline bool cpu_has_vmx_ept(void)
1246 {
1247 return vmcs_config.cpu_based_2nd_exec_ctrl &
1248 SECONDARY_EXEC_ENABLE_EPT;
1249 }
1250
1251 static inline bool cpu_has_vmx_unrestricted_guest(void)
1252 {
1253 return vmcs_config.cpu_based_2nd_exec_ctrl &
1254 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1255 }
1256
1257 static inline bool cpu_has_vmx_ple(void)
1258 {
1259 return vmcs_config.cpu_based_2nd_exec_ctrl &
1260 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1261 }
1262
1263 static inline bool cpu_has_vmx_basic_inout(void)
1264 {
1265 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1266 }
1267
1268 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1269 {
1270 return flexpriority_enabled && lapic_in_kernel(vcpu);
1271 }
1272
1273 static inline bool cpu_has_vmx_vpid(void)
1274 {
1275 return vmcs_config.cpu_based_2nd_exec_ctrl &
1276 SECONDARY_EXEC_ENABLE_VPID;
1277 }
1278
1279 static inline bool cpu_has_vmx_rdtscp(void)
1280 {
1281 return vmcs_config.cpu_based_2nd_exec_ctrl &
1282 SECONDARY_EXEC_RDTSCP;
1283 }
1284
1285 static inline bool cpu_has_vmx_invpcid(void)
1286 {
1287 return vmcs_config.cpu_based_2nd_exec_ctrl &
1288 SECONDARY_EXEC_ENABLE_INVPCID;
1289 }
1290
1291 static inline bool cpu_has_vmx_wbinvd_exit(void)
1292 {
1293 return vmcs_config.cpu_based_2nd_exec_ctrl &
1294 SECONDARY_EXEC_WBINVD_EXITING;
1295 }
1296
1297 static inline bool cpu_has_vmx_shadow_vmcs(void)
1298 {
1299 u64 vmx_msr;
1300 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1301 /* check if the cpu supports writing r/o exit information fields */
1302 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1303 return false;
1304
1305 return vmcs_config.cpu_based_2nd_exec_ctrl &
1306 SECONDARY_EXEC_SHADOW_VMCS;
1307 }
1308
1309 static inline bool cpu_has_vmx_pml(void)
1310 {
1311 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1312 }
1313
1314 static inline bool cpu_has_vmx_tsc_scaling(void)
1315 {
1316 return vmcs_config.cpu_based_2nd_exec_ctrl &
1317 SECONDARY_EXEC_TSC_SCALING;
1318 }
1319
1320 static inline bool report_flexpriority(void)
1321 {
1322 return flexpriority_enabled;
1323 }
1324
1325 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1326 {
1327 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1328 }
1329
1330 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1331 {
1332 return vmcs12->cpu_based_vm_exec_control & bit;
1333 }
1334
1335 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1336 {
1337 return (vmcs12->cpu_based_vm_exec_control &
1338 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1339 (vmcs12->secondary_vm_exec_control & bit);
1340 }
1341
1342 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1343 {
1344 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1345 }
1346
1347 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1348 {
1349 return vmcs12->pin_based_vm_exec_control &
1350 PIN_BASED_VMX_PREEMPTION_TIMER;
1351 }
1352
1353 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1354 {
1355 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1356 }
1357
1358 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1359 {
1360 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1361 vmx_xsaves_supported();
1362 }
1363
1364 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1365 {
1366 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1367 }
1368
1369 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1370 {
1371 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1372 }
1373
1374 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1375 {
1376 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1377 }
1378
1379 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1380 {
1381 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1382 }
1383
1384 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1385 {
1386 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1387 }
1388
1389 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1390 {
1391 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1392 }
1393
1394 static inline bool is_nmi(u32 intr_info)
1395 {
1396 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1397 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1398 }
1399
1400 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1401 u32 exit_intr_info,
1402 unsigned long exit_qualification);
1403 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1404 struct vmcs12 *vmcs12,
1405 u32 reason, unsigned long qualification);
1406
1407 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1408 {
1409 int i;
1410
1411 for (i = 0; i < vmx->nmsrs; ++i)
1412 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1413 return i;
1414 return -1;
1415 }
1416
1417 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1418 {
1419 struct {
1420 u64 vpid : 16;
1421 u64 rsvd : 48;
1422 u64 gva;
1423 } operand = { vpid, 0, gva };
1424
1425 asm volatile (__ex(ASM_VMX_INVVPID)
1426 /* CF==1 or ZF==1 --> rc = -1 */
1427 "; ja 1f ; ud2 ; 1:"
1428 : : "a"(&operand), "c"(ext) : "cc", "memory");
1429 }
1430
1431 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1432 {
1433 struct {
1434 u64 eptp, gpa;
1435 } operand = {eptp, gpa};
1436
1437 asm volatile (__ex(ASM_VMX_INVEPT)
1438 /* CF==1 or ZF==1 --> rc = -1 */
1439 "; ja 1f ; ud2 ; 1:\n"
1440 : : "a" (&operand), "c" (ext) : "cc", "memory");
1441 }
1442
1443 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1444 {
1445 int i;
1446
1447 i = __find_msr_index(vmx, msr);
1448 if (i >= 0)
1449 return &vmx->guest_msrs[i];
1450 return NULL;
1451 }
1452
1453 static void vmcs_clear(struct vmcs *vmcs)
1454 {
1455 u64 phys_addr = __pa(vmcs);
1456 u8 error;
1457
1458 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1459 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1460 : "cc", "memory");
1461 if (error)
1462 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1463 vmcs, phys_addr);
1464 }
1465
1466 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1467 {
1468 vmcs_clear(loaded_vmcs->vmcs);
1469 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1470 vmcs_clear(loaded_vmcs->shadow_vmcs);
1471 loaded_vmcs->cpu = -1;
1472 loaded_vmcs->launched = 0;
1473 }
1474
1475 static void vmcs_load(struct vmcs *vmcs)
1476 {
1477 u64 phys_addr = __pa(vmcs);
1478 u8 error;
1479
1480 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1481 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1482 : "cc", "memory");
1483 if (error)
1484 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1485 vmcs, phys_addr);
1486 }
1487
1488 #ifdef CONFIG_KEXEC_CORE
1489 /*
1490 * This bitmap is used to indicate whether the vmclear
1491 * operation is enabled on all cpus. All disabled by
1492 * default.
1493 */
1494 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1495
1496 static inline void crash_enable_local_vmclear(int cpu)
1497 {
1498 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1499 }
1500
1501 static inline void crash_disable_local_vmclear(int cpu)
1502 {
1503 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1504 }
1505
1506 static inline int crash_local_vmclear_enabled(int cpu)
1507 {
1508 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1509 }
1510
1511 static void crash_vmclear_local_loaded_vmcss(void)
1512 {
1513 int cpu = raw_smp_processor_id();
1514 struct loaded_vmcs *v;
1515
1516 if (!crash_local_vmclear_enabled(cpu))
1517 return;
1518
1519 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1520 loaded_vmcss_on_cpu_link)
1521 vmcs_clear(v->vmcs);
1522 }
1523 #else
1524 static inline void crash_enable_local_vmclear(int cpu) { }
1525 static inline void crash_disable_local_vmclear(int cpu) { }
1526 #endif /* CONFIG_KEXEC_CORE */
1527
1528 static void __loaded_vmcs_clear(void *arg)
1529 {
1530 struct loaded_vmcs *loaded_vmcs = arg;
1531 int cpu = raw_smp_processor_id();
1532
1533 if (loaded_vmcs->cpu != cpu)
1534 return; /* vcpu migration can race with cpu offline */
1535 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1536 per_cpu(current_vmcs, cpu) = NULL;
1537 crash_disable_local_vmclear(cpu);
1538 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1539
1540 /*
1541 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1542 * is before setting loaded_vmcs->vcpu to -1 which is done in
1543 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1544 * then adds the vmcs into percpu list before it is deleted.
1545 */
1546 smp_wmb();
1547
1548 loaded_vmcs_init(loaded_vmcs);
1549 crash_enable_local_vmclear(cpu);
1550 }
1551
1552 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1553 {
1554 int cpu = loaded_vmcs->cpu;
1555
1556 if (cpu != -1)
1557 smp_call_function_single(cpu,
1558 __loaded_vmcs_clear, loaded_vmcs, 1);
1559 }
1560
1561 static inline void vpid_sync_vcpu_single(int vpid)
1562 {
1563 if (vpid == 0)
1564 return;
1565
1566 if (cpu_has_vmx_invvpid_single())
1567 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1568 }
1569
1570 static inline void vpid_sync_vcpu_global(void)
1571 {
1572 if (cpu_has_vmx_invvpid_global())
1573 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1574 }
1575
1576 static inline void vpid_sync_context(int vpid)
1577 {
1578 if (cpu_has_vmx_invvpid_single())
1579 vpid_sync_vcpu_single(vpid);
1580 else
1581 vpid_sync_vcpu_global();
1582 }
1583
1584 static inline void ept_sync_global(void)
1585 {
1586 if (cpu_has_vmx_invept_global())
1587 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1588 }
1589
1590 static inline void ept_sync_context(u64 eptp)
1591 {
1592 if (enable_ept) {
1593 if (cpu_has_vmx_invept_context())
1594 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1595 else
1596 ept_sync_global();
1597 }
1598 }
1599
1600 static __always_inline void vmcs_check16(unsigned long field)
1601 {
1602 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1603 "16-bit accessor invalid for 64-bit field");
1604 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1605 "16-bit accessor invalid for 64-bit high field");
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1607 "16-bit accessor invalid for 32-bit high field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609 "16-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check32(unsigned long field)
1613 {
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615 "32-bit accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1617 "32-bit accessor invalid for natural width field");
1618 }
1619
1620 static __always_inline void vmcs_check64(unsigned long field)
1621 {
1622 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1623 "64-bit accessor invalid for 16-bit field");
1624 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1625 "64-bit accessor invalid for 64-bit high field");
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1627 "64-bit accessor invalid for 32-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1629 "64-bit accessor invalid for natural width field");
1630 }
1631
1632 static __always_inline void vmcs_checkl(unsigned long field)
1633 {
1634 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1635 "Natural width accessor invalid for 16-bit field");
1636 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1637 "Natural width accessor invalid for 64-bit field");
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1639 "Natural width accessor invalid for 64-bit high field");
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1641 "Natural width accessor invalid for 32-bit field");
1642 }
1643
1644 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1645 {
1646 unsigned long value;
1647
1648 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1649 : "=a"(value) : "d"(field) : "cc");
1650 return value;
1651 }
1652
1653 static __always_inline u16 vmcs_read16(unsigned long field)
1654 {
1655 vmcs_check16(field);
1656 return __vmcs_readl(field);
1657 }
1658
1659 static __always_inline u32 vmcs_read32(unsigned long field)
1660 {
1661 vmcs_check32(field);
1662 return __vmcs_readl(field);
1663 }
1664
1665 static __always_inline u64 vmcs_read64(unsigned long field)
1666 {
1667 vmcs_check64(field);
1668 #ifdef CONFIG_X86_64
1669 return __vmcs_readl(field);
1670 #else
1671 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1672 #endif
1673 }
1674
1675 static __always_inline unsigned long vmcs_readl(unsigned long field)
1676 {
1677 vmcs_checkl(field);
1678 return __vmcs_readl(field);
1679 }
1680
1681 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1682 {
1683 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1684 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1685 dump_stack();
1686 }
1687
1688 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1689 {
1690 u8 error;
1691
1692 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1693 : "=q"(error) : "a"(value), "d"(field) : "cc");
1694 if (unlikely(error))
1695 vmwrite_error(field, value);
1696 }
1697
1698 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1699 {
1700 vmcs_check16(field);
1701 __vmcs_writel(field, value);
1702 }
1703
1704 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1705 {
1706 vmcs_check32(field);
1707 __vmcs_writel(field, value);
1708 }
1709
1710 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1711 {
1712 vmcs_check64(field);
1713 __vmcs_writel(field, value);
1714 #ifndef CONFIG_X86_64
1715 asm volatile ("");
1716 __vmcs_writel(field+1, value >> 32);
1717 #endif
1718 }
1719
1720 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1721 {
1722 vmcs_checkl(field);
1723 __vmcs_writel(field, value);
1724 }
1725
1726 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1727 {
1728 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1729 "vmcs_clear_bits does not support 64-bit fields");
1730 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1731 }
1732
1733 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1734 {
1735 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1736 "vmcs_set_bits does not support 64-bit fields");
1737 __vmcs_writel(field, __vmcs_readl(field) | mask);
1738 }
1739
1740 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1741 {
1742 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1743 }
1744
1745 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1746 {
1747 vmcs_write32(VM_ENTRY_CONTROLS, val);
1748 vmx->vm_entry_controls_shadow = val;
1749 }
1750
1751 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1752 {
1753 if (vmx->vm_entry_controls_shadow != val)
1754 vm_entry_controls_init(vmx, val);
1755 }
1756
1757 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1758 {
1759 return vmx->vm_entry_controls_shadow;
1760 }
1761
1762
1763 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1764 {
1765 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1766 }
1767
1768 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1769 {
1770 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1771 }
1772
1773 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1774 {
1775 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1776 }
1777
1778 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1779 {
1780 vmcs_write32(VM_EXIT_CONTROLS, val);
1781 vmx->vm_exit_controls_shadow = val;
1782 }
1783
1784 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1785 {
1786 if (vmx->vm_exit_controls_shadow != val)
1787 vm_exit_controls_init(vmx, val);
1788 }
1789
1790 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1791 {
1792 return vmx->vm_exit_controls_shadow;
1793 }
1794
1795
1796 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1797 {
1798 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1799 }
1800
1801 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1802 {
1803 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1804 }
1805
1806 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1807 {
1808 vmx->segment_cache.bitmask = 0;
1809 }
1810
1811 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1812 unsigned field)
1813 {
1814 bool ret;
1815 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1816
1817 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1818 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1819 vmx->segment_cache.bitmask = 0;
1820 }
1821 ret = vmx->segment_cache.bitmask & mask;
1822 vmx->segment_cache.bitmask |= mask;
1823 return ret;
1824 }
1825
1826 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1827 {
1828 u16 *p = &vmx->segment_cache.seg[seg].selector;
1829
1830 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1831 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1832 return *p;
1833 }
1834
1835 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1836 {
1837 ulong *p = &vmx->segment_cache.seg[seg].base;
1838
1839 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1840 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1841 return *p;
1842 }
1843
1844 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1845 {
1846 u32 *p = &vmx->segment_cache.seg[seg].limit;
1847
1848 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1849 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1850 return *p;
1851 }
1852
1853 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1854 {
1855 u32 *p = &vmx->segment_cache.seg[seg].ar;
1856
1857 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1858 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1859 return *p;
1860 }
1861
1862 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1863 {
1864 u32 eb;
1865
1866 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1867 (1u << DB_VECTOR) | (1u << AC_VECTOR);
1868 if ((vcpu->guest_debug &
1869 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1870 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1871 eb |= 1u << BP_VECTOR;
1872 if (to_vmx(vcpu)->rmode.vm86_active)
1873 eb = ~0;
1874 if (enable_ept)
1875 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1876
1877 /* When we are running a nested L2 guest and L1 specified for it a
1878 * certain exception bitmap, we must trap the same exceptions and pass
1879 * them to L1. When running L2, we will only handle the exceptions
1880 * specified above if L1 did not want them.
1881 */
1882 if (is_guest_mode(vcpu))
1883 eb |= get_vmcs12(vcpu)->exception_bitmap;
1884
1885 vmcs_write32(EXCEPTION_BITMAP, eb);
1886 }
1887
1888 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1889 unsigned long entry, unsigned long exit)
1890 {
1891 vm_entry_controls_clearbit(vmx, entry);
1892 vm_exit_controls_clearbit(vmx, exit);
1893 }
1894
1895 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1896 {
1897 unsigned i;
1898 struct msr_autoload *m = &vmx->msr_autoload;
1899
1900 switch (msr) {
1901 case MSR_EFER:
1902 if (cpu_has_load_ia32_efer) {
1903 clear_atomic_switch_msr_special(vmx,
1904 VM_ENTRY_LOAD_IA32_EFER,
1905 VM_EXIT_LOAD_IA32_EFER);
1906 return;
1907 }
1908 break;
1909 case MSR_CORE_PERF_GLOBAL_CTRL:
1910 if (cpu_has_load_perf_global_ctrl) {
1911 clear_atomic_switch_msr_special(vmx,
1912 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1913 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1914 return;
1915 }
1916 break;
1917 }
1918
1919 for (i = 0; i < m->nr; ++i)
1920 if (m->guest[i].index == msr)
1921 break;
1922
1923 if (i == m->nr)
1924 return;
1925 --m->nr;
1926 m->guest[i] = m->guest[m->nr];
1927 m->host[i] = m->host[m->nr];
1928 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1929 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1930 }
1931
1932 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1933 unsigned long entry, unsigned long exit,
1934 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1935 u64 guest_val, u64 host_val)
1936 {
1937 vmcs_write64(guest_val_vmcs, guest_val);
1938 vmcs_write64(host_val_vmcs, host_val);
1939 vm_entry_controls_setbit(vmx, entry);
1940 vm_exit_controls_setbit(vmx, exit);
1941 }
1942
1943 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1944 u64 guest_val, u64 host_val)
1945 {
1946 unsigned i;
1947 struct msr_autoload *m = &vmx->msr_autoload;
1948
1949 switch (msr) {
1950 case MSR_EFER:
1951 if (cpu_has_load_ia32_efer) {
1952 add_atomic_switch_msr_special(vmx,
1953 VM_ENTRY_LOAD_IA32_EFER,
1954 VM_EXIT_LOAD_IA32_EFER,
1955 GUEST_IA32_EFER,
1956 HOST_IA32_EFER,
1957 guest_val, host_val);
1958 return;
1959 }
1960 break;
1961 case MSR_CORE_PERF_GLOBAL_CTRL:
1962 if (cpu_has_load_perf_global_ctrl) {
1963 add_atomic_switch_msr_special(vmx,
1964 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1965 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1966 GUEST_IA32_PERF_GLOBAL_CTRL,
1967 HOST_IA32_PERF_GLOBAL_CTRL,
1968 guest_val, host_val);
1969 return;
1970 }
1971 break;
1972 case MSR_IA32_PEBS_ENABLE:
1973 /* PEBS needs a quiescent period after being disabled (to write
1974 * a record). Disabling PEBS through VMX MSR swapping doesn't
1975 * provide that period, so a CPU could write host's record into
1976 * guest's memory.
1977 */
1978 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1979 }
1980
1981 for (i = 0; i < m->nr; ++i)
1982 if (m->guest[i].index == msr)
1983 break;
1984
1985 if (i == NR_AUTOLOAD_MSRS) {
1986 printk_once(KERN_WARNING "Not enough msr switch entries. "
1987 "Can't add msr %x\n", msr);
1988 return;
1989 } else if (i == m->nr) {
1990 ++m->nr;
1991 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1992 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1993 }
1994
1995 m->guest[i].index = msr;
1996 m->guest[i].value = guest_val;
1997 m->host[i].index = msr;
1998 m->host[i].value = host_val;
1999 }
2000
2001 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2002 {
2003 u64 guest_efer = vmx->vcpu.arch.efer;
2004 u64 ignore_bits = 0;
2005
2006 if (!enable_ept) {
2007 /*
2008 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2009 * host CPUID is more efficient than testing guest CPUID
2010 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2011 */
2012 if (boot_cpu_has(X86_FEATURE_SMEP))
2013 guest_efer |= EFER_NX;
2014 else if (!(guest_efer & EFER_NX))
2015 ignore_bits |= EFER_NX;
2016 }
2017
2018 /*
2019 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2020 */
2021 ignore_bits |= EFER_SCE;
2022 #ifdef CONFIG_X86_64
2023 ignore_bits |= EFER_LMA | EFER_LME;
2024 /* SCE is meaningful only in long mode on Intel */
2025 if (guest_efer & EFER_LMA)
2026 ignore_bits &= ~(u64)EFER_SCE;
2027 #endif
2028
2029 clear_atomic_switch_msr(vmx, MSR_EFER);
2030
2031 /*
2032 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2033 * On CPUs that support "load IA32_EFER", always switch EFER
2034 * atomically, since it's faster than switching it manually.
2035 */
2036 if (cpu_has_load_ia32_efer ||
2037 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2038 if (!(guest_efer & EFER_LMA))
2039 guest_efer &= ~EFER_LME;
2040 if (guest_efer != host_efer)
2041 add_atomic_switch_msr(vmx, MSR_EFER,
2042 guest_efer, host_efer);
2043 return false;
2044 } else {
2045 guest_efer &= ~ignore_bits;
2046 guest_efer |= host_efer & ignore_bits;
2047
2048 vmx->guest_msrs[efer_offset].data = guest_efer;
2049 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2050
2051 return true;
2052 }
2053 }
2054
2055 #ifdef CONFIG_X86_32
2056 /*
2057 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2058 * VMCS rather than the segment table. KVM uses this helper to figure
2059 * out the current bases to poke them into the VMCS before entry.
2060 */
2061 static unsigned long segment_base(u16 selector)
2062 {
2063 struct desc_struct *table;
2064 unsigned long v;
2065
2066 if (!(selector & ~SEGMENT_RPL_MASK))
2067 return 0;
2068
2069 table = get_current_gdt_ro();
2070
2071 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2072 u16 ldt_selector = kvm_read_ldt();
2073
2074 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2075 return 0;
2076
2077 table = (struct desc_struct *)segment_base(ldt_selector);
2078 }
2079 v = get_desc_base(&table[selector >> 3]);
2080 return v;
2081 }
2082 #endif
2083
2084 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2085 {
2086 struct vcpu_vmx *vmx = to_vmx(vcpu);
2087 int i;
2088
2089 if (vmx->host_state.loaded)
2090 return;
2091
2092 vmx->host_state.loaded = 1;
2093 /*
2094 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2095 * allow segment selectors with cpl > 0 or ti == 1.
2096 */
2097 vmx->host_state.ldt_sel = kvm_read_ldt();
2098 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2099 savesegment(fs, vmx->host_state.fs_sel);
2100 if (!(vmx->host_state.fs_sel & 7)) {
2101 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2102 vmx->host_state.fs_reload_needed = 0;
2103 } else {
2104 vmcs_write16(HOST_FS_SELECTOR, 0);
2105 vmx->host_state.fs_reload_needed = 1;
2106 }
2107 savesegment(gs, vmx->host_state.gs_sel);
2108 if (!(vmx->host_state.gs_sel & 7))
2109 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2110 else {
2111 vmcs_write16(HOST_GS_SELECTOR, 0);
2112 vmx->host_state.gs_ldt_reload_needed = 1;
2113 }
2114
2115 #ifdef CONFIG_X86_64
2116 savesegment(ds, vmx->host_state.ds_sel);
2117 savesegment(es, vmx->host_state.es_sel);
2118 #endif
2119
2120 #ifdef CONFIG_X86_64
2121 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2122 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2123 #else
2124 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2125 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2126 #endif
2127
2128 #ifdef CONFIG_X86_64
2129 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2130 if (is_long_mode(&vmx->vcpu))
2131 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2132 #endif
2133 if (boot_cpu_has(X86_FEATURE_MPX))
2134 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2135 for (i = 0; i < vmx->save_nmsrs; ++i)
2136 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2137 vmx->guest_msrs[i].data,
2138 vmx->guest_msrs[i].mask);
2139 }
2140
2141 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2142 {
2143 if (!vmx->host_state.loaded)
2144 return;
2145
2146 ++vmx->vcpu.stat.host_state_reload;
2147 vmx->host_state.loaded = 0;
2148 #ifdef CONFIG_X86_64
2149 if (is_long_mode(&vmx->vcpu))
2150 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2151 #endif
2152 if (vmx->host_state.gs_ldt_reload_needed) {
2153 kvm_load_ldt(vmx->host_state.ldt_sel);
2154 #ifdef CONFIG_X86_64
2155 load_gs_index(vmx->host_state.gs_sel);
2156 #else
2157 loadsegment(gs, vmx->host_state.gs_sel);
2158 #endif
2159 }
2160 if (vmx->host_state.fs_reload_needed)
2161 loadsegment(fs, vmx->host_state.fs_sel);
2162 #ifdef CONFIG_X86_64
2163 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2164 loadsegment(ds, vmx->host_state.ds_sel);
2165 loadsegment(es, vmx->host_state.es_sel);
2166 }
2167 #endif
2168 invalidate_tss_limit();
2169 #ifdef CONFIG_X86_64
2170 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2171 #endif
2172 if (vmx->host_state.msr_host_bndcfgs)
2173 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2174 load_fixmap_gdt(raw_smp_processor_id());
2175 }
2176
2177 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2178 {
2179 preempt_disable();
2180 __vmx_load_host_state(vmx);
2181 preempt_enable();
2182 }
2183
2184 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2185 {
2186 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2187 struct pi_desc old, new;
2188 unsigned int dest;
2189
2190 /*
2191 * In case of hot-plug or hot-unplug, we may have to undo
2192 * vmx_vcpu_pi_put even if there is no assigned device. And we
2193 * always keep PI.NDST up to date for simplicity: it makes the
2194 * code easier, and CPU migration is not a fast path.
2195 */
2196 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2197 return;
2198
2199 /*
2200 * First handle the simple case where no cmpxchg is necessary; just
2201 * allow posting non-urgent interrupts.
2202 *
2203 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2204 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2205 * expects the VCPU to be on the blocked_vcpu_list that matches
2206 * PI.NDST.
2207 */
2208 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2209 vcpu->cpu == cpu) {
2210 pi_clear_sn(pi_desc);
2211 return;
2212 }
2213
2214 /* The full case. */
2215 do {
2216 old.control = new.control = pi_desc->control;
2217
2218 dest = cpu_physical_id(cpu);
2219
2220 if (x2apic_enabled())
2221 new.ndst = dest;
2222 else
2223 new.ndst = (dest << 8) & 0xFF00;
2224
2225 new.sn = 0;
2226 } while (cmpxchg64(&pi_desc->control, old.control,
2227 new.control) != old.control);
2228 }
2229
2230 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2231 {
2232 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2233 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2234 }
2235
2236 /*
2237 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2238 * vcpu mutex is already taken.
2239 */
2240 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2241 {
2242 struct vcpu_vmx *vmx = to_vmx(vcpu);
2243 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2244
2245 if (!already_loaded) {
2246 loaded_vmcs_clear(vmx->loaded_vmcs);
2247 local_irq_disable();
2248 crash_disable_local_vmclear(cpu);
2249
2250 /*
2251 * Read loaded_vmcs->cpu should be before fetching
2252 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2253 * See the comments in __loaded_vmcs_clear().
2254 */
2255 smp_rmb();
2256
2257 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2258 &per_cpu(loaded_vmcss_on_cpu, cpu));
2259 crash_enable_local_vmclear(cpu);
2260 local_irq_enable();
2261 }
2262
2263 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2264 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2265 vmcs_load(vmx->loaded_vmcs->vmcs);
2266 }
2267
2268 if (!already_loaded) {
2269 void *gdt = get_current_gdt_ro();
2270 unsigned long sysenter_esp;
2271
2272 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2273
2274 /*
2275 * Linux uses per-cpu TSS and GDT, so set these when switching
2276 * processors. See 22.2.4.
2277 */
2278 vmcs_writel(HOST_TR_BASE,
2279 (unsigned long)this_cpu_ptr(&cpu_tss));
2280 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2281
2282 /*
2283 * VM exits change the host TR limit to 0x67 after a VM
2284 * exit. This is okay, since 0x67 covers everything except
2285 * the IO bitmap and have have code to handle the IO bitmap
2286 * being lost after a VM exit.
2287 */
2288 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2289
2290 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2291 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2292
2293 vmx->loaded_vmcs->cpu = cpu;
2294 }
2295
2296 /* Setup TSC multiplier */
2297 if (kvm_has_tsc_control &&
2298 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2299 decache_tsc_multiplier(vmx);
2300
2301 vmx_vcpu_pi_load(vcpu, cpu);
2302 vmx->host_pkru = read_pkru();
2303 }
2304
2305 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2306 {
2307 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2308
2309 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2310 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2311 !kvm_vcpu_apicv_active(vcpu))
2312 return;
2313
2314 /* Set SN when the vCPU is preempted */
2315 if (vcpu->preempted)
2316 pi_set_sn(pi_desc);
2317 }
2318
2319 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2320 {
2321 vmx_vcpu_pi_put(vcpu);
2322
2323 __vmx_load_host_state(to_vmx(vcpu));
2324 }
2325
2326 static bool emulation_required(struct kvm_vcpu *vcpu)
2327 {
2328 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2329 }
2330
2331 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2332
2333 /*
2334 * Return the cr0 value that a nested guest would read. This is a combination
2335 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2336 * its hypervisor (cr0_read_shadow).
2337 */
2338 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2339 {
2340 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2341 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2342 }
2343 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2344 {
2345 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2346 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2347 }
2348
2349 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2350 {
2351 unsigned long rflags, save_rflags;
2352
2353 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2354 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2355 rflags = vmcs_readl(GUEST_RFLAGS);
2356 if (to_vmx(vcpu)->rmode.vm86_active) {
2357 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2358 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2359 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2360 }
2361 to_vmx(vcpu)->rflags = rflags;
2362 }
2363 return to_vmx(vcpu)->rflags;
2364 }
2365
2366 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2367 {
2368 unsigned long old_rflags = vmx_get_rflags(vcpu);
2369
2370 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2371 to_vmx(vcpu)->rflags = rflags;
2372 if (to_vmx(vcpu)->rmode.vm86_active) {
2373 to_vmx(vcpu)->rmode.save_rflags = rflags;
2374 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2375 }
2376 vmcs_writel(GUEST_RFLAGS, rflags);
2377
2378 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2379 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2380 }
2381
2382 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2383 {
2384 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2385 int ret = 0;
2386
2387 if (interruptibility & GUEST_INTR_STATE_STI)
2388 ret |= KVM_X86_SHADOW_INT_STI;
2389 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2390 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2391
2392 return ret;
2393 }
2394
2395 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2396 {
2397 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2398 u32 interruptibility = interruptibility_old;
2399
2400 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2401
2402 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2403 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2404 else if (mask & KVM_X86_SHADOW_INT_STI)
2405 interruptibility |= GUEST_INTR_STATE_STI;
2406
2407 if ((interruptibility != interruptibility_old))
2408 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2409 }
2410
2411 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2412 {
2413 unsigned long rip;
2414
2415 rip = kvm_rip_read(vcpu);
2416 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2417 kvm_rip_write(vcpu, rip);
2418
2419 /* skipping an emulated instruction also counts */
2420 vmx_set_interrupt_shadow(vcpu, 0);
2421 }
2422
2423 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2424 unsigned long exit_qual)
2425 {
2426 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2427 unsigned int nr = vcpu->arch.exception.nr;
2428 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2429
2430 if (vcpu->arch.exception.has_error_code) {
2431 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2432 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2433 }
2434
2435 if (kvm_exception_is_soft(nr))
2436 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2437 else
2438 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2439
2440 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2441 vmx_get_nmi_mask(vcpu))
2442 intr_info |= INTR_INFO_UNBLOCK_NMI;
2443
2444 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2445 }
2446
2447 /*
2448 * KVM wants to inject page-faults which it got to the guest. This function
2449 * checks whether in a nested guest, we need to inject them to L1 or L2.
2450 */
2451 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
2452 {
2453 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2454 unsigned int nr = vcpu->arch.exception.nr;
2455
2456 if (nr == PF_VECTOR) {
2457 if (vcpu->arch.exception.nested_apf) {
2458 nested_vmx_inject_exception_vmexit(vcpu,
2459 vcpu->arch.apf.nested_apf_token);
2460 return 1;
2461 }
2462 /*
2463 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2464 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2465 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2466 * can be written only when inject_pending_event runs. This should be
2467 * conditional on a new capability---if the capability is disabled,
2468 * kvm_multiple_exception would write the ancillary information to
2469 * CR2 or DR6, for backwards ABI-compatibility.
2470 */
2471 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2472 vcpu->arch.exception.error_code)) {
2473 nested_vmx_inject_exception_vmexit(vcpu, vcpu->arch.cr2);
2474 return 1;
2475 }
2476 } else {
2477 unsigned long exit_qual = 0;
2478 if (nr == DB_VECTOR)
2479 exit_qual = vcpu->arch.dr6;
2480
2481 if (vmcs12->exception_bitmap & (1u << nr)) {
2482 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
2483 return 1;
2484 }
2485 }
2486
2487 return 0;
2488 }
2489
2490 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2491 {
2492 struct vcpu_vmx *vmx = to_vmx(vcpu);
2493 unsigned nr = vcpu->arch.exception.nr;
2494 bool has_error_code = vcpu->arch.exception.has_error_code;
2495 bool reinject = vcpu->arch.exception.reinject;
2496 u32 error_code = vcpu->arch.exception.error_code;
2497 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2498
2499 if (!reinject && is_guest_mode(vcpu) &&
2500 nested_vmx_check_exception(vcpu))
2501 return;
2502
2503 if (has_error_code) {
2504 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2505 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2506 }
2507
2508 if (vmx->rmode.vm86_active) {
2509 int inc_eip = 0;
2510 if (kvm_exception_is_soft(nr))
2511 inc_eip = vcpu->arch.event_exit_inst_len;
2512 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2513 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2514 return;
2515 }
2516
2517 if (kvm_exception_is_soft(nr)) {
2518 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2519 vmx->vcpu.arch.event_exit_inst_len);
2520 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2521 } else
2522 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2523
2524 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2525 }
2526
2527 static bool vmx_rdtscp_supported(void)
2528 {
2529 return cpu_has_vmx_rdtscp();
2530 }
2531
2532 static bool vmx_invpcid_supported(void)
2533 {
2534 return cpu_has_vmx_invpcid() && enable_ept;
2535 }
2536
2537 /*
2538 * Swap MSR entry in host/guest MSR entry array.
2539 */
2540 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2541 {
2542 struct shared_msr_entry tmp;
2543
2544 tmp = vmx->guest_msrs[to];
2545 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2546 vmx->guest_msrs[from] = tmp;
2547 }
2548
2549 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2550 {
2551 unsigned long *msr_bitmap;
2552
2553 if (is_guest_mode(vcpu))
2554 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2555 else if (cpu_has_secondary_exec_ctrls() &&
2556 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2557 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2558 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2559 if (is_long_mode(vcpu))
2560 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2561 else
2562 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2563 } else {
2564 if (is_long_mode(vcpu))
2565 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2566 else
2567 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2568 }
2569 } else {
2570 if (is_long_mode(vcpu))
2571 msr_bitmap = vmx_msr_bitmap_longmode;
2572 else
2573 msr_bitmap = vmx_msr_bitmap_legacy;
2574 }
2575
2576 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2577 }
2578
2579 /*
2580 * Set up the vmcs to automatically save and restore system
2581 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2582 * mode, as fiddling with msrs is very expensive.
2583 */
2584 static void setup_msrs(struct vcpu_vmx *vmx)
2585 {
2586 int save_nmsrs, index;
2587
2588 save_nmsrs = 0;
2589 #ifdef CONFIG_X86_64
2590 if (is_long_mode(&vmx->vcpu)) {
2591 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2592 if (index >= 0)
2593 move_msr_up(vmx, index, save_nmsrs++);
2594 index = __find_msr_index(vmx, MSR_LSTAR);
2595 if (index >= 0)
2596 move_msr_up(vmx, index, save_nmsrs++);
2597 index = __find_msr_index(vmx, MSR_CSTAR);
2598 if (index >= 0)
2599 move_msr_up(vmx, index, save_nmsrs++);
2600 index = __find_msr_index(vmx, MSR_TSC_AUX);
2601 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2602 move_msr_up(vmx, index, save_nmsrs++);
2603 /*
2604 * MSR_STAR is only needed on long mode guests, and only
2605 * if efer.sce is enabled.
2606 */
2607 index = __find_msr_index(vmx, MSR_STAR);
2608 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2609 move_msr_up(vmx, index, save_nmsrs++);
2610 }
2611 #endif
2612 index = __find_msr_index(vmx, MSR_EFER);
2613 if (index >= 0 && update_transition_efer(vmx, index))
2614 move_msr_up(vmx, index, save_nmsrs++);
2615
2616 vmx->save_nmsrs = save_nmsrs;
2617
2618 if (cpu_has_vmx_msr_bitmap())
2619 vmx_set_msr_bitmap(&vmx->vcpu);
2620 }
2621
2622 /*
2623 * reads and returns guest's timestamp counter "register"
2624 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2625 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2626 */
2627 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2628 {
2629 u64 host_tsc, tsc_offset;
2630
2631 host_tsc = rdtsc();
2632 tsc_offset = vmcs_read64(TSC_OFFSET);
2633 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2634 }
2635
2636 /*
2637 * writes 'offset' into guest's timestamp counter offset register
2638 */
2639 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2640 {
2641 if (is_guest_mode(vcpu)) {
2642 /*
2643 * We're here if L1 chose not to trap WRMSR to TSC. According
2644 * to the spec, this should set L1's TSC; The offset that L1
2645 * set for L2 remains unchanged, and still needs to be added
2646 * to the newly set TSC to get L2's TSC.
2647 */
2648 struct vmcs12 *vmcs12;
2649 /* recalculate vmcs02.TSC_OFFSET: */
2650 vmcs12 = get_vmcs12(vcpu);
2651 vmcs_write64(TSC_OFFSET, offset +
2652 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2653 vmcs12->tsc_offset : 0));
2654 } else {
2655 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2656 vmcs_read64(TSC_OFFSET), offset);
2657 vmcs_write64(TSC_OFFSET, offset);
2658 }
2659 }
2660
2661 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2662 {
2663 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2664 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2665 }
2666
2667 /*
2668 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2669 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2670 * all guests if the "nested" module option is off, and can also be disabled
2671 * for a single guest by disabling its VMX cpuid bit.
2672 */
2673 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2674 {
2675 return nested && guest_cpuid_has_vmx(vcpu);
2676 }
2677
2678 /*
2679 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2680 * returned for the various VMX controls MSRs when nested VMX is enabled.
2681 * The same values should also be used to verify that vmcs12 control fields are
2682 * valid during nested entry from L1 to L2.
2683 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2684 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2685 * bit in the high half is on if the corresponding bit in the control field
2686 * may be on. See also vmx_control_verify().
2687 */
2688 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2689 {
2690 /*
2691 * Note that as a general rule, the high half of the MSRs (bits in
2692 * the control fields which may be 1) should be initialized by the
2693 * intersection of the underlying hardware's MSR (i.e., features which
2694 * can be supported) and the list of features we want to expose -
2695 * because they are known to be properly supported in our code.
2696 * Also, usually, the low half of the MSRs (bits which must be 1) can
2697 * be set to 0, meaning that L1 may turn off any of these bits. The
2698 * reason is that if one of these bits is necessary, it will appear
2699 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2700 * fields of vmcs01 and vmcs02, will turn these bits off - and
2701 * nested_vmx_exit_reflected() will not pass related exits to L1.
2702 * These rules have exceptions below.
2703 */
2704
2705 /* pin-based controls */
2706 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2707 vmx->nested.nested_vmx_pinbased_ctls_low,
2708 vmx->nested.nested_vmx_pinbased_ctls_high);
2709 vmx->nested.nested_vmx_pinbased_ctls_low |=
2710 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2711 vmx->nested.nested_vmx_pinbased_ctls_high &=
2712 PIN_BASED_EXT_INTR_MASK |
2713 PIN_BASED_NMI_EXITING |
2714 PIN_BASED_VIRTUAL_NMIS;
2715 vmx->nested.nested_vmx_pinbased_ctls_high |=
2716 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2717 PIN_BASED_VMX_PREEMPTION_TIMER;
2718 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2719 vmx->nested.nested_vmx_pinbased_ctls_high |=
2720 PIN_BASED_POSTED_INTR;
2721
2722 /* exit controls */
2723 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2724 vmx->nested.nested_vmx_exit_ctls_low,
2725 vmx->nested.nested_vmx_exit_ctls_high);
2726 vmx->nested.nested_vmx_exit_ctls_low =
2727 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2728
2729 vmx->nested.nested_vmx_exit_ctls_high &=
2730 #ifdef CONFIG_X86_64
2731 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2732 #endif
2733 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2734 vmx->nested.nested_vmx_exit_ctls_high |=
2735 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2736 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2737 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2738
2739 if (kvm_mpx_supported())
2740 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2741
2742 /* We support free control of debug control saving. */
2743 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2744
2745 /* entry controls */
2746 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2747 vmx->nested.nested_vmx_entry_ctls_low,
2748 vmx->nested.nested_vmx_entry_ctls_high);
2749 vmx->nested.nested_vmx_entry_ctls_low =
2750 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2751 vmx->nested.nested_vmx_entry_ctls_high &=
2752 #ifdef CONFIG_X86_64
2753 VM_ENTRY_IA32E_MODE |
2754 #endif
2755 VM_ENTRY_LOAD_IA32_PAT;
2756 vmx->nested.nested_vmx_entry_ctls_high |=
2757 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2758 if (kvm_mpx_supported())
2759 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2760
2761 /* We support free control of debug control loading. */
2762 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2763
2764 /* cpu-based controls */
2765 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2766 vmx->nested.nested_vmx_procbased_ctls_low,
2767 vmx->nested.nested_vmx_procbased_ctls_high);
2768 vmx->nested.nested_vmx_procbased_ctls_low =
2769 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2770 vmx->nested.nested_vmx_procbased_ctls_high &=
2771 CPU_BASED_VIRTUAL_INTR_PENDING |
2772 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2773 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2774 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2775 CPU_BASED_CR3_STORE_EXITING |
2776 #ifdef CONFIG_X86_64
2777 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2778 #endif
2779 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2780 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2781 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2782 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2783 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2784 /*
2785 * We can allow some features even when not supported by the
2786 * hardware. For example, L1 can specify an MSR bitmap - and we
2787 * can use it to avoid exits to L1 - even when L0 runs L2
2788 * without MSR bitmaps.
2789 */
2790 vmx->nested.nested_vmx_procbased_ctls_high |=
2791 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2792 CPU_BASED_USE_MSR_BITMAPS;
2793
2794 /* We support free control of CR3 access interception. */
2795 vmx->nested.nested_vmx_procbased_ctls_low &=
2796 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2797
2798 /* secondary cpu-based controls */
2799 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2800 vmx->nested.nested_vmx_secondary_ctls_low,
2801 vmx->nested.nested_vmx_secondary_ctls_high);
2802 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2803 vmx->nested.nested_vmx_secondary_ctls_high &=
2804 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2805 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2806 SECONDARY_EXEC_RDTSCP |
2807 SECONDARY_EXEC_DESC |
2808 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2809 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2810 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2811 SECONDARY_EXEC_WBINVD_EXITING |
2812 SECONDARY_EXEC_XSAVES;
2813
2814 if (enable_ept) {
2815 /* nested EPT: emulate EPT also to L1 */
2816 vmx->nested.nested_vmx_secondary_ctls_high |=
2817 SECONDARY_EXEC_ENABLE_EPT;
2818 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2819 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2820 if (cpu_has_vmx_ept_execute_only())
2821 vmx->nested.nested_vmx_ept_caps |=
2822 VMX_EPT_EXECUTE_ONLY_BIT;
2823 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2824 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2825 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2826 VMX_EPT_1GB_PAGE_BIT;
2827 if (enable_ept_ad_bits) {
2828 vmx->nested.nested_vmx_secondary_ctls_high |=
2829 SECONDARY_EXEC_ENABLE_PML;
2830 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2831 }
2832 } else
2833 vmx->nested.nested_vmx_ept_caps = 0;
2834
2835 /*
2836 * Old versions of KVM use the single-context version without
2837 * checking for support, so declare that it is supported even
2838 * though it is treated as global context. The alternative is
2839 * not failing the single-context invvpid, and it is worse.
2840 */
2841 if (enable_vpid) {
2842 vmx->nested.nested_vmx_secondary_ctls_high |=
2843 SECONDARY_EXEC_ENABLE_VPID;
2844 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2845 VMX_VPID_EXTENT_SUPPORTED_MASK;
2846 } else
2847 vmx->nested.nested_vmx_vpid_caps = 0;
2848
2849 if (enable_unrestricted_guest)
2850 vmx->nested.nested_vmx_secondary_ctls_high |=
2851 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2852
2853 /* miscellaneous data */
2854 rdmsr(MSR_IA32_VMX_MISC,
2855 vmx->nested.nested_vmx_misc_low,
2856 vmx->nested.nested_vmx_misc_high);
2857 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2858 vmx->nested.nested_vmx_misc_low |=
2859 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2860 VMX_MISC_ACTIVITY_HLT;
2861 vmx->nested.nested_vmx_misc_high = 0;
2862
2863 /*
2864 * This MSR reports some information about VMX support. We
2865 * should return information about the VMX we emulate for the
2866 * guest, and the VMCS structure we give it - not about the
2867 * VMX support of the underlying hardware.
2868 */
2869 vmx->nested.nested_vmx_basic =
2870 VMCS12_REVISION |
2871 VMX_BASIC_TRUE_CTLS |
2872 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2873 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2874
2875 if (cpu_has_vmx_basic_inout())
2876 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2877
2878 /*
2879 * These MSRs specify bits which the guest must keep fixed on
2880 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2881 * We picked the standard core2 setting.
2882 */
2883 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2884 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2885 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2886 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2887
2888 /* These MSRs specify bits which the guest must keep fixed off. */
2889 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2890 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2891
2892 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2893 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2894 }
2895
2896 /*
2897 * if fixed0[i] == 1: val[i] must be 1
2898 * if fixed1[i] == 0: val[i] must be 0
2899 */
2900 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2901 {
2902 return ((val & fixed1) | fixed0) == val;
2903 }
2904
2905 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2906 {
2907 return fixed_bits_valid(control, low, high);
2908 }
2909
2910 static inline u64 vmx_control_msr(u32 low, u32 high)
2911 {
2912 return low | ((u64)high << 32);
2913 }
2914
2915 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2916 {
2917 superset &= mask;
2918 subset &= mask;
2919
2920 return (superset | subset) == superset;
2921 }
2922
2923 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2924 {
2925 const u64 feature_and_reserved =
2926 /* feature (except bit 48; see below) */
2927 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2928 /* reserved */
2929 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2930 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2931
2932 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2933 return -EINVAL;
2934
2935 /*
2936 * KVM does not emulate a version of VMX that constrains physical
2937 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2938 */
2939 if (data & BIT_ULL(48))
2940 return -EINVAL;
2941
2942 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2943 vmx_basic_vmcs_revision_id(data))
2944 return -EINVAL;
2945
2946 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2947 return -EINVAL;
2948
2949 vmx->nested.nested_vmx_basic = data;
2950 return 0;
2951 }
2952
2953 static int
2954 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2955 {
2956 u64 supported;
2957 u32 *lowp, *highp;
2958
2959 switch (msr_index) {
2960 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2961 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2962 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2963 break;
2964 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2965 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2966 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2967 break;
2968 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2969 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2970 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2971 break;
2972 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2973 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2974 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2975 break;
2976 case MSR_IA32_VMX_PROCBASED_CTLS2:
2977 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2978 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2979 break;
2980 default:
2981 BUG();
2982 }
2983
2984 supported = vmx_control_msr(*lowp, *highp);
2985
2986 /* Check must-be-1 bits are still 1. */
2987 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2988 return -EINVAL;
2989
2990 /* Check must-be-0 bits are still 0. */
2991 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2992 return -EINVAL;
2993
2994 *lowp = data;
2995 *highp = data >> 32;
2996 return 0;
2997 }
2998
2999 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3000 {
3001 const u64 feature_and_reserved_bits =
3002 /* feature */
3003 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3004 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3005 /* reserved */
3006 GENMASK_ULL(13, 9) | BIT_ULL(31);
3007 u64 vmx_misc;
3008
3009 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3010 vmx->nested.nested_vmx_misc_high);
3011
3012 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3013 return -EINVAL;
3014
3015 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3016 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3017 vmx_misc_preemption_timer_rate(data) !=
3018 vmx_misc_preemption_timer_rate(vmx_misc))
3019 return -EINVAL;
3020
3021 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3022 return -EINVAL;
3023
3024 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3025 return -EINVAL;
3026
3027 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3028 return -EINVAL;
3029
3030 vmx->nested.nested_vmx_misc_low = data;
3031 vmx->nested.nested_vmx_misc_high = data >> 32;
3032 return 0;
3033 }
3034
3035 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3036 {
3037 u64 vmx_ept_vpid_cap;
3038
3039 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3040 vmx->nested.nested_vmx_vpid_caps);
3041
3042 /* Every bit is either reserved or a feature bit. */
3043 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3044 return -EINVAL;
3045
3046 vmx->nested.nested_vmx_ept_caps = data;
3047 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3048 return 0;
3049 }
3050
3051 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3052 {
3053 u64 *msr;
3054
3055 switch (msr_index) {
3056 case MSR_IA32_VMX_CR0_FIXED0:
3057 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3058 break;
3059 case MSR_IA32_VMX_CR4_FIXED0:
3060 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3061 break;
3062 default:
3063 BUG();
3064 }
3065
3066 /*
3067 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3068 * must be 1 in the restored value.
3069 */
3070 if (!is_bitwise_subset(data, *msr, -1ULL))
3071 return -EINVAL;
3072
3073 *msr = data;
3074 return 0;
3075 }
3076
3077 /*
3078 * Called when userspace is restoring VMX MSRs.
3079 *
3080 * Returns 0 on success, non-0 otherwise.
3081 */
3082 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3083 {
3084 struct vcpu_vmx *vmx = to_vmx(vcpu);
3085
3086 switch (msr_index) {
3087 case MSR_IA32_VMX_BASIC:
3088 return vmx_restore_vmx_basic(vmx, data);
3089 case MSR_IA32_VMX_PINBASED_CTLS:
3090 case MSR_IA32_VMX_PROCBASED_CTLS:
3091 case MSR_IA32_VMX_EXIT_CTLS:
3092 case MSR_IA32_VMX_ENTRY_CTLS:
3093 /*
3094 * The "non-true" VMX capability MSRs are generated from the
3095 * "true" MSRs, so we do not support restoring them directly.
3096 *
3097 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3098 * should restore the "true" MSRs with the must-be-1 bits
3099 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3100 * DEFAULT SETTINGS".
3101 */
3102 return -EINVAL;
3103 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3104 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3105 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3106 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3107 case MSR_IA32_VMX_PROCBASED_CTLS2:
3108 return vmx_restore_control_msr(vmx, msr_index, data);
3109 case MSR_IA32_VMX_MISC:
3110 return vmx_restore_vmx_misc(vmx, data);
3111 case MSR_IA32_VMX_CR0_FIXED0:
3112 case MSR_IA32_VMX_CR4_FIXED0:
3113 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3114 case MSR_IA32_VMX_CR0_FIXED1:
3115 case MSR_IA32_VMX_CR4_FIXED1:
3116 /*
3117 * These MSRs are generated based on the vCPU's CPUID, so we
3118 * do not support restoring them directly.
3119 */
3120 return -EINVAL;
3121 case MSR_IA32_VMX_EPT_VPID_CAP:
3122 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3123 case MSR_IA32_VMX_VMCS_ENUM:
3124 vmx->nested.nested_vmx_vmcs_enum = data;
3125 return 0;
3126 default:
3127 /*
3128 * The rest of the VMX capability MSRs do not support restore.
3129 */
3130 return -EINVAL;
3131 }
3132 }
3133
3134 /* Returns 0 on success, non-0 otherwise. */
3135 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3136 {
3137 struct vcpu_vmx *vmx = to_vmx(vcpu);
3138
3139 switch (msr_index) {
3140 case MSR_IA32_VMX_BASIC:
3141 *pdata = vmx->nested.nested_vmx_basic;
3142 break;
3143 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3144 case MSR_IA32_VMX_PINBASED_CTLS:
3145 *pdata = vmx_control_msr(
3146 vmx->nested.nested_vmx_pinbased_ctls_low,
3147 vmx->nested.nested_vmx_pinbased_ctls_high);
3148 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3149 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3150 break;
3151 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3152 case MSR_IA32_VMX_PROCBASED_CTLS:
3153 *pdata = vmx_control_msr(
3154 vmx->nested.nested_vmx_procbased_ctls_low,
3155 vmx->nested.nested_vmx_procbased_ctls_high);
3156 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3157 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3158 break;
3159 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3160 case MSR_IA32_VMX_EXIT_CTLS:
3161 *pdata = vmx_control_msr(
3162 vmx->nested.nested_vmx_exit_ctls_low,
3163 vmx->nested.nested_vmx_exit_ctls_high);
3164 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3165 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3166 break;
3167 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3168 case MSR_IA32_VMX_ENTRY_CTLS:
3169 *pdata = vmx_control_msr(
3170 vmx->nested.nested_vmx_entry_ctls_low,
3171 vmx->nested.nested_vmx_entry_ctls_high);
3172 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3173 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3174 break;
3175 case MSR_IA32_VMX_MISC:
3176 *pdata = vmx_control_msr(
3177 vmx->nested.nested_vmx_misc_low,
3178 vmx->nested.nested_vmx_misc_high);
3179 break;
3180 case MSR_IA32_VMX_CR0_FIXED0:
3181 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3182 break;
3183 case MSR_IA32_VMX_CR0_FIXED1:
3184 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3185 break;
3186 case MSR_IA32_VMX_CR4_FIXED0:
3187 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3188 break;
3189 case MSR_IA32_VMX_CR4_FIXED1:
3190 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3191 break;
3192 case MSR_IA32_VMX_VMCS_ENUM:
3193 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3194 break;
3195 case MSR_IA32_VMX_PROCBASED_CTLS2:
3196 *pdata = vmx_control_msr(
3197 vmx->nested.nested_vmx_secondary_ctls_low,
3198 vmx->nested.nested_vmx_secondary_ctls_high);
3199 break;
3200 case MSR_IA32_VMX_EPT_VPID_CAP:
3201 *pdata = vmx->nested.nested_vmx_ept_caps |
3202 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3203 break;
3204 default:
3205 return 1;
3206 }
3207
3208 return 0;
3209 }
3210
3211 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3212 uint64_t val)
3213 {
3214 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3215
3216 return !(val & ~valid_bits);
3217 }
3218
3219 /*
3220 * Reads an msr value (of 'msr_index') into 'pdata'.
3221 * Returns 0 on success, non-0 otherwise.
3222 * Assumes vcpu_load() was already called.
3223 */
3224 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3225 {
3226 struct shared_msr_entry *msr;
3227
3228 switch (msr_info->index) {
3229 #ifdef CONFIG_X86_64
3230 case MSR_FS_BASE:
3231 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3232 break;
3233 case MSR_GS_BASE:
3234 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3235 break;
3236 case MSR_KERNEL_GS_BASE:
3237 vmx_load_host_state(to_vmx(vcpu));
3238 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3239 break;
3240 #endif
3241 case MSR_EFER:
3242 return kvm_get_msr_common(vcpu, msr_info);
3243 case MSR_IA32_TSC:
3244 msr_info->data = guest_read_tsc(vcpu);
3245 break;
3246 case MSR_IA32_SYSENTER_CS:
3247 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3248 break;
3249 case MSR_IA32_SYSENTER_EIP:
3250 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3251 break;
3252 case MSR_IA32_SYSENTER_ESP:
3253 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3254 break;
3255 case MSR_IA32_BNDCFGS:
3256 if (!kvm_mpx_supported() ||
3257 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3258 return 1;
3259 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3260 break;
3261 case MSR_IA32_MCG_EXT_CTL:
3262 if (!msr_info->host_initiated &&
3263 !(to_vmx(vcpu)->msr_ia32_feature_control &
3264 FEATURE_CONTROL_LMCE))
3265 return 1;
3266 msr_info->data = vcpu->arch.mcg_ext_ctl;
3267 break;
3268 case MSR_IA32_FEATURE_CONTROL:
3269 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3270 break;
3271 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3272 if (!nested_vmx_allowed(vcpu))
3273 return 1;
3274 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3275 case MSR_IA32_XSS:
3276 if (!vmx_xsaves_supported())
3277 return 1;
3278 msr_info->data = vcpu->arch.ia32_xss;
3279 break;
3280 case MSR_TSC_AUX:
3281 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3282 return 1;
3283 /* Otherwise falls through */
3284 default:
3285 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3286 if (msr) {
3287 msr_info->data = msr->data;
3288 break;
3289 }
3290 return kvm_get_msr_common(vcpu, msr_info);
3291 }
3292
3293 return 0;
3294 }
3295
3296 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3297
3298 /*
3299 * Writes msr value into into the appropriate "register".
3300 * Returns 0 on success, non-0 otherwise.
3301 * Assumes vcpu_load() was already called.
3302 */
3303 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3304 {
3305 struct vcpu_vmx *vmx = to_vmx(vcpu);
3306 struct shared_msr_entry *msr;
3307 int ret = 0;
3308 u32 msr_index = msr_info->index;
3309 u64 data = msr_info->data;
3310
3311 switch (msr_index) {
3312 case MSR_EFER:
3313 ret = kvm_set_msr_common(vcpu, msr_info);
3314 break;
3315 #ifdef CONFIG_X86_64
3316 case MSR_FS_BASE:
3317 vmx_segment_cache_clear(vmx);
3318 vmcs_writel(GUEST_FS_BASE, data);
3319 break;
3320 case MSR_GS_BASE:
3321 vmx_segment_cache_clear(vmx);
3322 vmcs_writel(GUEST_GS_BASE, data);
3323 break;
3324 case MSR_KERNEL_GS_BASE:
3325 vmx_load_host_state(vmx);
3326 vmx->msr_guest_kernel_gs_base = data;
3327 break;
3328 #endif
3329 case MSR_IA32_SYSENTER_CS:
3330 vmcs_write32(GUEST_SYSENTER_CS, data);
3331 break;
3332 case MSR_IA32_SYSENTER_EIP:
3333 vmcs_writel(GUEST_SYSENTER_EIP, data);
3334 break;
3335 case MSR_IA32_SYSENTER_ESP:
3336 vmcs_writel(GUEST_SYSENTER_ESP, data);
3337 break;
3338 case MSR_IA32_BNDCFGS:
3339 if (!kvm_mpx_supported() ||
3340 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3341 return 1;
3342 if (is_noncanonical_address(data & PAGE_MASK) ||
3343 (data & MSR_IA32_BNDCFGS_RSVD))
3344 return 1;
3345 vmcs_write64(GUEST_BNDCFGS, data);
3346 break;
3347 case MSR_IA32_TSC:
3348 kvm_write_tsc(vcpu, msr_info);
3349 break;
3350 case MSR_IA32_CR_PAT:
3351 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3352 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3353 return 1;
3354 vmcs_write64(GUEST_IA32_PAT, data);
3355 vcpu->arch.pat = data;
3356 break;
3357 }
3358 ret = kvm_set_msr_common(vcpu, msr_info);
3359 break;
3360 case MSR_IA32_TSC_ADJUST:
3361 ret = kvm_set_msr_common(vcpu, msr_info);
3362 break;
3363 case MSR_IA32_MCG_EXT_CTL:
3364 if ((!msr_info->host_initiated &&
3365 !(to_vmx(vcpu)->msr_ia32_feature_control &
3366 FEATURE_CONTROL_LMCE)) ||
3367 (data & ~MCG_EXT_CTL_LMCE_EN))
3368 return 1;
3369 vcpu->arch.mcg_ext_ctl = data;
3370 break;
3371 case MSR_IA32_FEATURE_CONTROL:
3372 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3373 (to_vmx(vcpu)->msr_ia32_feature_control &
3374 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3375 return 1;
3376 vmx->msr_ia32_feature_control = data;
3377 if (msr_info->host_initiated && data == 0)
3378 vmx_leave_nested(vcpu);
3379 break;
3380 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3381 if (!msr_info->host_initiated)
3382 return 1; /* they are read-only */
3383 if (!nested_vmx_allowed(vcpu))
3384 return 1;
3385 return vmx_set_vmx_msr(vcpu, msr_index, data);
3386 case MSR_IA32_XSS:
3387 if (!vmx_xsaves_supported())
3388 return 1;
3389 /*
3390 * The only supported bit as of Skylake is bit 8, but
3391 * it is not supported on KVM.
3392 */
3393 if (data != 0)
3394 return 1;
3395 vcpu->arch.ia32_xss = data;
3396 if (vcpu->arch.ia32_xss != host_xss)
3397 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3398 vcpu->arch.ia32_xss, host_xss);
3399 else
3400 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3401 break;
3402 case MSR_TSC_AUX:
3403 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3404 return 1;
3405 /* Check reserved bit, higher 32 bits should be zero */
3406 if ((data >> 32) != 0)
3407 return 1;
3408 /* Otherwise falls through */
3409 default:
3410 msr = find_msr_entry(vmx, msr_index);
3411 if (msr) {
3412 u64 old_msr_data = msr->data;
3413 msr->data = data;
3414 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3415 preempt_disable();
3416 ret = kvm_set_shared_msr(msr->index, msr->data,
3417 msr->mask);
3418 preempt_enable();
3419 if (ret)
3420 msr->data = old_msr_data;
3421 }
3422 break;
3423 }
3424 ret = kvm_set_msr_common(vcpu, msr_info);
3425 }
3426
3427 return ret;
3428 }
3429
3430 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3431 {
3432 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3433 switch (reg) {
3434 case VCPU_REGS_RSP:
3435 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3436 break;
3437 case VCPU_REGS_RIP:
3438 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3439 break;
3440 case VCPU_EXREG_PDPTR:
3441 if (enable_ept)
3442 ept_save_pdptrs(vcpu);
3443 break;
3444 default:
3445 break;
3446 }
3447 }
3448
3449 static __init int cpu_has_kvm_support(void)
3450 {
3451 return cpu_has_vmx();
3452 }
3453
3454 static __init int vmx_disabled_by_bios(void)
3455 {
3456 u64 msr;
3457
3458 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3459 if (msr & FEATURE_CONTROL_LOCKED) {
3460 /* launched w/ TXT and VMX disabled */
3461 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3462 && tboot_enabled())
3463 return 1;
3464 /* launched w/o TXT and VMX only enabled w/ TXT */
3465 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3466 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3467 && !tboot_enabled()) {
3468 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3469 "activate TXT before enabling KVM\n");
3470 return 1;
3471 }
3472 /* launched w/o TXT and VMX disabled */
3473 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3474 && !tboot_enabled())
3475 return 1;
3476 }
3477
3478 return 0;
3479 }
3480
3481 static void kvm_cpu_vmxon(u64 addr)
3482 {
3483 cr4_set_bits(X86_CR4_VMXE);
3484 intel_pt_handle_vmx(1);
3485
3486 asm volatile (ASM_VMX_VMXON_RAX
3487 : : "a"(&addr), "m"(addr)
3488 : "memory", "cc");
3489 }
3490
3491 static int hardware_enable(void)
3492 {
3493 int cpu = raw_smp_processor_id();
3494 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3495 u64 old, test_bits;
3496
3497 if (cr4_read_shadow() & X86_CR4_VMXE)
3498 return -EBUSY;
3499
3500 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3501 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3502 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3503
3504 /*
3505 * Now we can enable the vmclear operation in kdump
3506 * since the loaded_vmcss_on_cpu list on this cpu
3507 * has been initialized.
3508 *
3509 * Though the cpu is not in VMX operation now, there
3510 * is no problem to enable the vmclear operation
3511 * for the loaded_vmcss_on_cpu list is empty!
3512 */
3513 crash_enable_local_vmclear(cpu);
3514
3515 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3516
3517 test_bits = FEATURE_CONTROL_LOCKED;
3518 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3519 if (tboot_enabled())
3520 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3521
3522 if ((old & test_bits) != test_bits) {
3523 /* enable and lock */
3524 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3525 }
3526 kvm_cpu_vmxon(phys_addr);
3527 ept_sync_global();
3528
3529 return 0;
3530 }
3531
3532 static void vmclear_local_loaded_vmcss(void)
3533 {
3534 int cpu = raw_smp_processor_id();
3535 struct loaded_vmcs *v, *n;
3536
3537 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3538 loaded_vmcss_on_cpu_link)
3539 __loaded_vmcs_clear(v);
3540 }
3541
3542
3543 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3544 * tricks.
3545 */
3546 static void kvm_cpu_vmxoff(void)
3547 {
3548 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3549
3550 intel_pt_handle_vmx(0);
3551 cr4_clear_bits(X86_CR4_VMXE);
3552 }
3553
3554 static void hardware_disable(void)
3555 {
3556 vmclear_local_loaded_vmcss();
3557 kvm_cpu_vmxoff();
3558 }
3559
3560 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3561 u32 msr, u32 *result)
3562 {
3563 u32 vmx_msr_low, vmx_msr_high;
3564 u32 ctl = ctl_min | ctl_opt;
3565
3566 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3567
3568 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3569 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3570
3571 /* Ensure minimum (required) set of control bits are supported. */
3572 if (ctl_min & ~ctl)
3573 return -EIO;
3574
3575 *result = ctl;
3576 return 0;
3577 }
3578
3579 static __init bool allow_1_setting(u32 msr, u32 ctl)
3580 {
3581 u32 vmx_msr_low, vmx_msr_high;
3582
3583 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3584 return vmx_msr_high & ctl;
3585 }
3586
3587 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3588 {
3589 u32 vmx_msr_low, vmx_msr_high;
3590 u32 min, opt, min2, opt2;
3591 u32 _pin_based_exec_control = 0;
3592 u32 _cpu_based_exec_control = 0;
3593 u32 _cpu_based_2nd_exec_control = 0;
3594 u32 _vmexit_control = 0;
3595 u32 _vmentry_control = 0;
3596
3597 min = CPU_BASED_HLT_EXITING |
3598 #ifdef CONFIG_X86_64
3599 CPU_BASED_CR8_LOAD_EXITING |
3600 CPU_BASED_CR8_STORE_EXITING |
3601 #endif
3602 CPU_BASED_CR3_LOAD_EXITING |
3603 CPU_BASED_CR3_STORE_EXITING |
3604 CPU_BASED_USE_IO_BITMAPS |
3605 CPU_BASED_MOV_DR_EXITING |
3606 CPU_BASED_USE_TSC_OFFSETING |
3607 CPU_BASED_INVLPG_EXITING |
3608 CPU_BASED_RDPMC_EXITING;
3609
3610 if (!kvm_mwait_in_guest())
3611 min |= CPU_BASED_MWAIT_EXITING |
3612 CPU_BASED_MONITOR_EXITING;
3613
3614 opt = CPU_BASED_TPR_SHADOW |
3615 CPU_BASED_USE_MSR_BITMAPS |
3616 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3617 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3618 &_cpu_based_exec_control) < 0)
3619 return -EIO;
3620 #ifdef CONFIG_X86_64
3621 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3622 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3623 ~CPU_BASED_CR8_STORE_EXITING;
3624 #endif
3625 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3626 min2 = 0;
3627 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3628 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3629 SECONDARY_EXEC_WBINVD_EXITING |
3630 SECONDARY_EXEC_ENABLE_VPID |
3631 SECONDARY_EXEC_ENABLE_EPT |
3632 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3633 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3634 SECONDARY_EXEC_RDTSCP |
3635 SECONDARY_EXEC_ENABLE_INVPCID |
3636 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3637 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3638 SECONDARY_EXEC_SHADOW_VMCS |
3639 SECONDARY_EXEC_XSAVES |
3640 SECONDARY_EXEC_ENABLE_PML |
3641 SECONDARY_EXEC_TSC_SCALING;
3642 if (adjust_vmx_controls(min2, opt2,
3643 MSR_IA32_VMX_PROCBASED_CTLS2,
3644 &_cpu_based_2nd_exec_control) < 0)
3645 return -EIO;
3646 }
3647 #ifndef CONFIG_X86_64
3648 if (!(_cpu_based_2nd_exec_control &
3649 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3650 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3651 #endif
3652
3653 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3654 _cpu_based_2nd_exec_control &= ~(
3655 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3656 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3657 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3658
3659 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3660 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3661 enabled */
3662 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3663 CPU_BASED_CR3_STORE_EXITING |
3664 CPU_BASED_INVLPG_EXITING);
3665 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3666 vmx_capability.ept, vmx_capability.vpid);
3667 }
3668
3669 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3670 #ifdef CONFIG_X86_64
3671 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3672 #endif
3673 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3674 VM_EXIT_CLEAR_BNDCFGS;
3675 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3676 &_vmexit_control) < 0)
3677 return -EIO;
3678
3679 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3680 PIN_BASED_VIRTUAL_NMIS;
3681 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3682 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3683 &_pin_based_exec_control) < 0)
3684 return -EIO;
3685
3686 if (cpu_has_broken_vmx_preemption_timer())
3687 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3688 if (!(_cpu_based_2nd_exec_control &
3689 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3690 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3691
3692 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3693 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3694 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3695 &_vmentry_control) < 0)
3696 return -EIO;
3697
3698 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3699
3700 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3701 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3702 return -EIO;
3703
3704 #ifdef CONFIG_X86_64
3705 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3706 if (vmx_msr_high & (1u<<16))
3707 return -EIO;
3708 #endif
3709
3710 /* Require Write-Back (WB) memory type for VMCS accesses. */
3711 if (((vmx_msr_high >> 18) & 15) != 6)
3712 return -EIO;
3713
3714 vmcs_conf->size = vmx_msr_high & 0x1fff;
3715 vmcs_conf->order = get_order(vmcs_conf->size);
3716 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3717 vmcs_conf->revision_id = vmx_msr_low;
3718
3719 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3720 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3721 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3722 vmcs_conf->vmexit_ctrl = _vmexit_control;
3723 vmcs_conf->vmentry_ctrl = _vmentry_control;
3724
3725 cpu_has_load_ia32_efer =
3726 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3727 VM_ENTRY_LOAD_IA32_EFER)
3728 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3729 VM_EXIT_LOAD_IA32_EFER);
3730
3731 cpu_has_load_perf_global_ctrl =
3732 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3733 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3734 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3735 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3736
3737 /*
3738 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3739 * but due to errata below it can't be used. Workaround is to use
3740 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3741 *
3742 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3743 *
3744 * AAK155 (model 26)
3745 * AAP115 (model 30)
3746 * AAT100 (model 37)
3747 * BC86,AAY89,BD102 (model 44)
3748 * BA97 (model 46)
3749 *
3750 */
3751 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3752 switch (boot_cpu_data.x86_model) {
3753 case 26:
3754 case 30:
3755 case 37:
3756 case 44:
3757 case 46:
3758 cpu_has_load_perf_global_ctrl = false;
3759 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3760 "does not work properly. Using workaround\n");
3761 break;
3762 default:
3763 break;
3764 }
3765 }
3766
3767 if (boot_cpu_has(X86_FEATURE_XSAVES))
3768 rdmsrl(MSR_IA32_XSS, host_xss);
3769
3770 return 0;
3771 }
3772
3773 static struct vmcs *alloc_vmcs_cpu(int cpu)
3774 {
3775 int node = cpu_to_node(cpu);
3776 struct page *pages;
3777 struct vmcs *vmcs;
3778
3779 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3780 if (!pages)
3781 return NULL;
3782 vmcs = page_address(pages);
3783 memset(vmcs, 0, vmcs_config.size);
3784 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3785 return vmcs;
3786 }
3787
3788 static struct vmcs *alloc_vmcs(void)
3789 {
3790 return alloc_vmcs_cpu(raw_smp_processor_id());
3791 }
3792
3793 static void free_vmcs(struct vmcs *vmcs)
3794 {
3795 free_pages((unsigned long)vmcs, vmcs_config.order);
3796 }
3797
3798 /*
3799 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3800 */
3801 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3802 {
3803 if (!loaded_vmcs->vmcs)
3804 return;
3805 loaded_vmcs_clear(loaded_vmcs);
3806 free_vmcs(loaded_vmcs->vmcs);
3807 loaded_vmcs->vmcs = NULL;
3808 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3809 }
3810
3811 static void free_kvm_area(void)
3812 {
3813 int cpu;
3814
3815 for_each_possible_cpu(cpu) {
3816 free_vmcs(per_cpu(vmxarea, cpu));
3817 per_cpu(vmxarea, cpu) = NULL;
3818 }
3819 }
3820
3821 enum vmcs_field_type {
3822 VMCS_FIELD_TYPE_U16 = 0,
3823 VMCS_FIELD_TYPE_U64 = 1,
3824 VMCS_FIELD_TYPE_U32 = 2,
3825 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3826 };
3827
3828 static inline int vmcs_field_type(unsigned long field)
3829 {
3830 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3831 return VMCS_FIELD_TYPE_U32;
3832 return (field >> 13) & 0x3 ;
3833 }
3834
3835 static inline int vmcs_field_readonly(unsigned long field)
3836 {
3837 return (((field >> 10) & 0x3) == 1);
3838 }
3839
3840 static void init_vmcs_shadow_fields(void)
3841 {
3842 int i, j;
3843
3844 /* No checks for read only fields yet */
3845
3846 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3847 switch (shadow_read_write_fields[i]) {
3848 case GUEST_BNDCFGS:
3849 if (!kvm_mpx_supported())
3850 continue;
3851 break;
3852 default:
3853 break;
3854 }
3855
3856 if (j < i)
3857 shadow_read_write_fields[j] =
3858 shadow_read_write_fields[i];
3859 j++;
3860 }
3861 max_shadow_read_write_fields = j;
3862
3863 /* shadowed fields guest access without vmexit */
3864 for (i = 0; i < max_shadow_read_write_fields; i++) {
3865 unsigned long field = shadow_read_write_fields[i];
3866
3867 clear_bit(field, vmx_vmwrite_bitmap);
3868 clear_bit(field, vmx_vmread_bitmap);
3869 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3870 clear_bit(field + 1, vmx_vmwrite_bitmap);
3871 clear_bit(field + 1, vmx_vmread_bitmap);
3872 }
3873 }
3874 for (i = 0; i < max_shadow_read_only_fields; i++) {
3875 unsigned long field = shadow_read_only_fields[i];
3876
3877 clear_bit(field, vmx_vmread_bitmap);
3878 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3879 clear_bit(field + 1, vmx_vmread_bitmap);
3880 }
3881 }
3882
3883 static __init int alloc_kvm_area(void)
3884 {
3885 int cpu;
3886
3887 for_each_possible_cpu(cpu) {
3888 struct vmcs *vmcs;
3889
3890 vmcs = alloc_vmcs_cpu(cpu);
3891 if (!vmcs) {
3892 free_kvm_area();
3893 return -ENOMEM;
3894 }
3895
3896 per_cpu(vmxarea, cpu) = vmcs;
3897 }
3898 return 0;
3899 }
3900
3901 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3902 struct kvm_segment *save)
3903 {
3904 if (!emulate_invalid_guest_state) {
3905 /*
3906 * CS and SS RPL should be equal during guest entry according
3907 * to VMX spec, but in reality it is not always so. Since vcpu
3908 * is in the middle of the transition from real mode to
3909 * protected mode it is safe to assume that RPL 0 is a good
3910 * default value.
3911 */
3912 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3913 save->selector &= ~SEGMENT_RPL_MASK;
3914 save->dpl = save->selector & SEGMENT_RPL_MASK;
3915 save->s = 1;
3916 }
3917 vmx_set_segment(vcpu, save, seg);
3918 }
3919
3920 static void enter_pmode(struct kvm_vcpu *vcpu)
3921 {
3922 unsigned long flags;
3923 struct vcpu_vmx *vmx = to_vmx(vcpu);
3924
3925 /*
3926 * Update real mode segment cache. It may be not up-to-date if sement
3927 * register was written while vcpu was in a guest mode.
3928 */
3929 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3930 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3931 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3932 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3933 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3934 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3935
3936 vmx->rmode.vm86_active = 0;
3937
3938 vmx_segment_cache_clear(vmx);
3939
3940 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3941
3942 flags = vmcs_readl(GUEST_RFLAGS);
3943 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3944 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3945 vmcs_writel(GUEST_RFLAGS, flags);
3946
3947 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3948 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3949
3950 update_exception_bitmap(vcpu);
3951
3952 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3953 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3954 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3955 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3956 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3957 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3958 }
3959
3960 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3961 {
3962 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3963 struct kvm_segment var = *save;
3964
3965 var.dpl = 0x3;
3966 if (seg == VCPU_SREG_CS)
3967 var.type = 0x3;
3968
3969 if (!emulate_invalid_guest_state) {
3970 var.selector = var.base >> 4;
3971 var.base = var.base & 0xffff0;
3972 var.limit = 0xffff;
3973 var.g = 0;
3974 var.db = 0;
3975 var.present = 1;
3976 var.s = 1;
3977 var.l = 0;
3978 var.unusable = 0;
3979 var.type = 0x3;
3980 var.avl = 0;
3981 if (save->base & 0xf)
3982 printk_once(KERN_WARNING "kvm: segment base is not "
3983 "paragraph aligned when entering "
3984 "protected mode (seg=%d)", seg);
3985 }
3986
3987 vmcs_write16(sf->selector, var.selector);
3988 vmcs_writel(sf->base, var.base);
3989 vmcs_write32(sf->limit, var.limit);
3990 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3991 }
3992
3993 static void enter_rmode(struct kvm_vcpu *vcpu)
3994 {
3995 unsigned long flags;
3996 struct vcpu_vmx *vmx = to_vmx(vcpu);
3997
3998 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3999 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4000 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4001 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4002 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4003 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4004 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4005
4006 vmx->rmode.vm86_active = 1;
4007
4008 /*
4009 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4010 * vcpu. Warn the user that an update is overdue.
4011 */
4012 if (!vcpu->kvm->arch.tss_addr)
4013 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4014 "called before entering vcpu\n");
4015
4016 vmx_segment_cache_clear(vmx);
4017
4018 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4019 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4020 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4021
4022 flags = vmcs_readl(GUEST_RFLAGS);
4023 vmx->rmode.save_rflags = flags;
4024
4025 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4026
4027 vmcs_writel(GUEST_RFLAGS, flags);
4028 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4029 update_exception_bitmap(vcpu);
4030
4031 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4032 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4033 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4034 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4035 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4036 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4037
4038 kvm_mmu_reset_context(vcpu);
4039 }
4040
4041 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4042 {
4043 struct vcpu_vmx *vmx = to_vmx(vcpu);
4044 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4045
4046 if (!msr)
4047 return;
4048
4049 /*
4050 * Force kernel_gs_base reloading before EFER changes, as control
4051 * of this msr depends on is_long_mode().
4052 */
4053 vmx_load_host_state(to_vmx(vcpu));
4054 vcpu->arch.efer = efer;
4055 if (efer & EFER_LMA) {
4056 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4057 msr->data = efer;
4058 } else {
4059 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4060
4061 msr->data = efer & ~EFER_LME;
4062 }
4063 setup_msrs(vmx);
4064 }
4065
4066 #ifdef CONFIG_X86_64
4067
4068 static void enter_lmode(struct kvm_vcpu *vcpu)
4069 {
4070 u32 guest_tr_ar;
4071
4072 vmx_segment_cache_clear(to_vmx(vcpu));
4073
4074 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4075 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4076 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4077 __func__);
4078 vmcs_write32(GUEST_TR_AR_BYTES,
4079 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4080 | VMX_AR_TYPE_BUSY_64_TSS);
4081 }
4082 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4083 }
4084
4085 static void exit_lmode(struct kvm_vcpu *vcpu)
4086 {
4087 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4088 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4089 }
4090
4091 #endif
4092
4093 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4094 {
4095 if (enable_ept) {
4096 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4097 return;
4098 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4099 } else {
4100 vpid_sync_context(vpid);
4101 }
4102 }
4103
4104 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4105 {
4106 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4107 }
4108
4109 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4110 {
4111 if (enable_ept)
4112 vmx_flush_tlb(vcpu);
4113 }
4114
4115 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4116 {
4117 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4118
4119 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4120 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4121 }
4122
4123 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4124 {
4125 if (enable_ept && is_paging(vcpu))
4126 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4127 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4128 }
4129
4130 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4131 {
4132 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4133
4134 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4135 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4136 }
4137
4138 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4139 {
4140 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4141
4142 if (!test_bit(VCPU_EXREG_PDPTR,
4143 (unsigned long *)&vcpu->arch.regs_dirty))
4144 return;
4145
4146 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4147 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4148 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4149 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4150 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4151 }
4152 }
4153
4154 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4155 {
4156 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4157
4158 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4159 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4160 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4161 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4162 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4163 }
4164
4165 __set_bit(VCPU_EXREG_PDPTR,
4166 (unsigned long *)&vcpu->arch.regs_avail);
4167 __set_bit(VCPU_EXREG_PDPTR,
4168 (unsigned long *)&vcpu->arch.regs_dirty);
4169 }
4170
4171 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4172 {
4173 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4174 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4175 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4176
4177 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4178 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4179 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4180 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4181
4182 return fixed_bits_valid(val, fixed0, fixed1);
4183 }
4184
4185 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4186 {
4187 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4188 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4189
4190 return fixed_bits_valid(val, fixed0, fixed1);
4191 }
4192
4193 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4194 {
4195 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4196 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4197
4198 return fixed_bits_valid(val, fixed0, fixed1);
4199 }
4200
4201 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4202 #define nested_guest_cr4_valid nested_cr4_valid
4203 #define nested_host_cr4_valid nested_cr4_valid
4204
4205 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4206
4207 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4208 unsigned long cr0,
4209 struct kvm_vcpu *vcpu)
4210 {
4211 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4212 vmx_decache_cr3(vcpu);
4213 if (!(cr0 & X86_CR0_PG)) {
4214 /* From paging/starting to nonpaging */
4215 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4216 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4217 (CPU_BASED_CR3_LOAD_EXITING |
4218 CPU_BASED_CR3_STORE_EXITING));
4219 vcpu->arch.cr0 = cr0;
4220 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4221 } else if (!is_paging(vcpu)) {
4222 /* From nonpaging to paging */
4223 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4224 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4225 ~(CPU_BASED_CR3_LOAD_EXITING |
4226 CPU_BASED_CR3_STORE_EXITING));
4227 vcpu->arch.cr0 = cr0;
4228 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4229 }
4230
4231 if (!(cr0 & X86_CR0_WP))
4232 *hw_cr0 &= ~X86_CR0_WP;
4233 }
4234
4235 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4236 {
4237 struct vcpu_vmx *vmx = to_vmx(vcpu);
4238 unsigned long hw_cr0;
4239
4240 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4241 if (enable_unrestricted_guest)
4242 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4243 else {
4244 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4245
4246 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4247 enter_pmode(vcpu);
4248
4249 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4250 enter_rmode(vcpu);
4251 }
4252
4253 #ifdef CONFIG_X86_64
4254 if (vcpu->arch.efer & EFER_LME) {
4255 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4256 enter_lmode(vcpu);
4257 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4258 exit_lmode(vcpu);
4259 }
4260 #endif
4261
4262 if (enable_ept)
4263 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4264
4265 vmcs_writel(CR0_READ_SHADOW, cr0);
4266 vmcs_writel(GUEST_CR0, hw_cr0);
4267 vcpu->arch.cr0 = cr0;
4268
4269 /* depends on vcpu->arch.cr0 to be set to a new value */
4270 vmx->emulation_required = emulation_required(vcpu);
4271 }
4272
4273 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4274 {
4275 u64 eptp;
4276
4277 /* TODO write the value reading from MSR */
4278 eptp = VMX_EPT_DEFAULT_MT |
4279 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4280 if (enable_ept_ad_bits &&
4281 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4282 eptp |= VMX_EPT_AD_ENABLE_BIT;
4283 eptp |= (root_hpa & PAGE_MASK);
4284
4285 return eptp;
4286 }
4287
4288 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4289 {
4290 unsigned long guest_cr3;
4291 u64 eptp;
4292
4293 guest_cr3 = cr3;
4294 if (enable_ept) {
4295 eptp = construct_eptp(vcpu, cr3);
4296 vmcs_write64(EPT_POINTER, eptp);
4297 if (is_paging(vcpu) || is_guest_mode(vcpu))
4298 guest_cr3 = kvm_read_cr3(vcpu);
4299 else
4300 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4301 ept_load_pdptrs(vcpu);
4302 }
4303
4304 vmx_flush_tlb(vcpu);
4305 vmcs_writel(GUEST_CR3, guest_cr3);
4306 }
4307
4308 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4309 {
4310 /*
4311 * Pass through host's Machine Check Enable value to hw_cr4, which
4312 * is in force while we are in guest mode. Do not let guests control
4313 * this bit, even if host CR4.MCE == 0.
4314 */
4315 unsigned long hw_cr4 =
4316 (cr4_read_shadow() & X86_CR4_MCE) |
4317 (cr4 & ~X86_CR4_MCE) |
4318 (to_vmx(vcpu)->rmode.vm86_active ?
4319 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4320
4321 if (cr4 & X86_CR4_VMXE) {
4322 /*
4323 * To use VMXON (and later other VMX instructions), a guest
4324 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4325 * So basically the check on whether to allow nested VMX
4326 * is here.
4327 */
4328 if (!nested_vmx_allowed(vcpu))
4329 return 1;
4330 }
4331
4332 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4333 return 1;
4334
4335 vcpu->arch.cr4 = cr4;
4336 if (enable_ept) {
4337 if (!is_paging(vcpu)) {
4338 hw_cr4 &= ~X86_CR4_PAE;
4339 hw_cr4 |= X86_CR4_PSE;
4340 } else if (!(cr4 & X86_CR4_PAE)) {
4341 hw_cr4 &= ~X86_CR4_PAE;
4342 }
4343 }
4344
4345 if (!enable_unrestricted_guest && !is_paging(vcpu))
4346 /*
4347 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4348 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4349 * to be manually disabled when guest switches to non-paging
4350 * mode.
4351 *
4352 * If !enable_unrestricted_guest, the CPU is always running
4353 * with CR0.PG=1 and CR4 needs to be modified.
4354 * If enable_unrestricted_guest, the CPU automatically
4355 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4356 */
4357 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4358
4359 vmcs_writel(CR4_READ_SHADOW, cr4);
4360 vmcs_writel(GUEST_CR4, hw_cr4);
4361 return 0;
4362 }
4363
4364 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4365 struct kvm_segment *var, int seg)
4366 {
4367 struct vcpu_vmx *vmx = to_vmx(vcpu);
4368 u32 ar;
4369
4370 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4371 *var = vmx->rmode.segs[seg];
4372 if (seg == VCPU_SREG_TR
4373 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4374 return;
4375 var->base = vmx_read_guest_seg_base(vmx, seg);
4376 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4377 return;
4378 }
4379 var->base = vmx_read_guest_seg_base(vmx, seg);
4380 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4381 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4382 ar = vmx_read_guest_seg_ar(vmx, seg);
4383 var->unusable = (ar >> 16) & 1;
4384 var->type = ar & 15;
4385 var->s = (ar >> 4) & 1;
4386 var->dpl = (ar >> 5) & 3;
4387 /*
4388 * Some userspaces do not preserve unusable property. Since usable
4389 * segment has to be present according to VMX spec we can use present
4390 * property to amend userspace bug by making unusable segment always
4391 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4392 * segment as unusable.
4393 */
4394 var->present = !var->unusable;
4395 var->avl = (ar >> 12) & 1;
4396 var->l = (ar >> 13) & 1;
4397 var->db = (ar >> 14) & 1;
4398 var->g = (ar >> 15) & 1;
4399 }
4400
4401 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4402 {
4403 struct kvm_segment s;
4404
4405 if (to_vmx(vcpu)->rmode.vm86_active) {
4406 vmx_get_segment(vcpu, &s, seg);
4407 return s.base;
4408 }
4409 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4410 }
4411
4412 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4413 {
4414 struct vcpu_vmx *vmx = to_vmx(vcpu);
4415
4416 if (unlikely(vmx->rmode.vm86_active))
4417 return 0;
4418 else {
4419 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4420 return VMX_AR_DPL(ar);
4421 }
4422 }
4423
4424 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4425 {
4426 u32 ar;
4427
4428 if (var->unusable || !var->present)
4429 ar = 1 << 16;
4430 else {
4431 ar = var->type & 15;
4432 ar |= (var->s & 1) << 4;
4433 ar |= (var->dpl & 3) << 5;
4434 ar |= (var->present & 1) << 7;
4435 ar |= (var->avl & 1) << 12;
4436 ar |= (var->l & 1) << 13;
4437 ar |= (var->db & 1) << 14;
4438 ar |= (var->g & 1) << 15;
4439 }
4440
4441 return ar;
4442 }
4443
4444 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4445 struct kvm_segment *var, int seg)
4446 {
4447 struct vcpu_vmx *vmx = to_vmx(vcpu);
4448 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4449
4450 vmx_segment_cache_clear(vmx);
4451
4452 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4453 vmx->rmode.segs[seg] = *var;
4454 if (seg == VCPU_SREG_TR)
4455 vmcs_write16(sf->selector, var->selector);
4456 else if (var->s)
4457 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4458 goto out;
4459 }
4460
4461 vmcs_writel(sf->base, var->base);
4462 vmcs_write32(sf->limit, var->limit);
4463 vmcs_write16(sf->selector, var->selector);
4464
4465 /*
4466 * Fix the "Accessed" bit in AR field of segment registers for older
4467 * qemu binaries.
4468 * IA32 arch specifies that at the time of processor reset the
4469 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4470 * is setting it to 0 in the userland code. This causes invalid guest
4471 * state vmexit when "unrestricted guest" mode is turned on.
4472 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4473 * tree. Newer qemu binaries with that qemu fix would not need this
4474 * kvm hack.
4475 */
4476 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4477 var->type |= 0x1; /* Accessed */
4478
4479 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4480
4481 out:
4482 vmx->emulation_required = emulation_required(vcpu);
4483 }
4484
4485 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4486 {
4487 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4488
4489 *db = (ar >> 14) & 1;
4490 *l = (ar >> 13) & 1;
4491 }
4492
4493 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4494 {
4495 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4496 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4497 }
4498
4499 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4500 {
4501 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4502 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4503 }
4504
4505 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4506 {
4507 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4508 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4509 }
4510
4511 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4512 {
4513 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4514 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4515 }
4516
4517 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4518 {
4519 struct kvm_segment var;
4520 u32 ar;
4521
4522 vmx_get_segment(vcpu, &var, seg);
4523 var.dpl = 0x3;
4524 if (seg == VCPU_SREG_CS)
4525 var.type = 0x3;
4526 ar = vmx_segment_access_rights(&var);
4527
4528 if (var.base != (var.selector << 4))
4529 return false;
4530 if (var.limit != 0xffff)
4531 return false;
4532 if (ar != 0xf3)
4533 return false;
4534
4535 return true;
4536 }
4537
4538 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4539 {
4540 struct kvm_segment cs;
4541 unsigned int cs_rpl;
4542
4543 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4544 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4545
4546 if (cs.unusable)
4547 return false;
4548 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4549 return false;
4550 if (!cs.s)
4551 return false;
4552 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4553 if (cs.dpl > cs_rpl)
4554 return false;
4555 } else {
4556 if (cs.dpl != cs_rpl)
4557 return false;
4558 }
4559 if (!cs.present)
4560 return false;
4561
4562 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4563 return true;
4564 }
4565
4566 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4567 {
4568 struct kvm_segment ss;
4569 unsigned int ss_rpl;
4570
4571 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4572 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4573
4574 if (ss.unusable)
4575 return true;
4576 if (ss.type != 3 && ss.type != 7)
4577 return false;
4578 if (!ss.s)
4579 return false;
4580 if (ss.dpl != ss_rpl) /* DPL != RPL */
4581 return false;
4582 if (!ss.present)
4583 return false;
4584
4585 return true;
4586 }
4587
4588 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4589 {
4590 struct kvm_segment var;
4591 unsigned int rpl;
4592
4593 vmx_get_segment(vcpu, &var, seg);
4594 rpl = var.selector & SEGMENT_RPL_MASK;
4595
4596 if (var.unusable)
4597 return true;
4598 if (!var.s)
4599 return false;
4600 if (!var.present)
4601 return false;
4602 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4603 if (var.dpl < rpl) /* DPL < RPL */
4604 return false;
4605 }
4606
4607 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4608 * rights flags
4609 */
4610 return true;
4611 }
4612
4613 static bool tr_valid(struct kvm_vcpu *vcpu)
4614 {
4615 struct kvm_segment tr;
4616
4617 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4618
4619 if (tr.unusable)
4620 return false;
4621 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4622 return false;
4623 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4624 return false;
4625 if (!tr.present)
4626 return false;
4627
4628 return true;
4629 }
4630
4631 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4632 {
4633 struct kvm_segment ldtr;
4634
4635 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4636
4637 if (ldtr.unusable)
4638 return true;
4639 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4640 return false;
4641 if (ldtr.type != 2)
4642 return false;
4643 if (!ldtr.present)
4644 return false;
4645
4646 return true;
4647 }
4648
4649 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4650 {
4651 struct kvm_segment cs, ss;
4652
4653 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4654 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4655
4656 return ((cs.selector & SEGMENT_RPL_MASK) ==
4657 (ss.selector & SEGMENT_RPL_MASK));
4658 }
4659
4660 /*
4661 * Check if guest state is valid. Returns true if valid, false if
4662 * not.
4663 * We assume that registers are always usable
4664 */
4665 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4666 {
4667 if (enable_unrestricted_guest)
4668 return true;
4669
4670 /* real mode guest state checks */
4671 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4672 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4673 return false;
4674 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4675 return false;
4676 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4677 return false;
4678 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4679 return false;
4680 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4681 return false;
4682 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4683 return false;
4684 } else {
4685 /* protected mode guest state checks */
4686 if (!cs_ss_rpl_check(vcpu))
4687 return false;
4688 if (!code_segment_valid(vcpu))
4689 return false;
4690 if (!stack_segment_valid(vcpu))
4691 return false;
4692 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4693 return false;
4694 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4695 return false;
4696 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4697 return false;
4698 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4699 return false;
4700 if (!tr_valid(vcpu))
4701 return false;
4702 if (!ldtr_valid(vcpu))
4703 return false;
4704 }
4705 /* TODO:
4706 * - Add checks on RIP
4707 * - Add checks on RFLAGS
4708 */
4709
4710 return true;
4711 }
4712
4713 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4714 {
4715 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4716 }
4717
4718 static int init_rmode_tss(struct kvm *kvm)
4719 {
4720 gfn_t fn;
4721 u16 data = 0;
4722 int idx, r;
4723
4724 idx = srcu_read_lock(&kvm->srcu);
4725 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4726 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4727 if (r < 0)
4728 goto out;
4729 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4730 r = kvm_write_guest_page(kvm, fn++, &data,
4731 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4732 if (r < 0)
4733 goto out;
4734 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4735 if (r < 0)
4736 goto out;
4737 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4738 if (r < 0)
4739 goto out;
4740 data = ~0;
4741 r = kvm_write_guest_page(kvm, fn, &data,
4742 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4743 sizeof(u8));
4744 out:
4745 srcu_read_unlock(&kvm->srcu, idx);
4746 return r;
4747 }
4748
4749 static int init_rmode_identity_map(struct kvm *kvm)
4750 {
4751 int i, idx, r = 0;
4752 kvm_pfn_t identity_map_pfn;
4753 u32 tmp;
4754
4755 if (!enable_ept)
4756 return 0;
4757
4758 /* Protect kvm->arch.ept_identity_pagetable_done. */
4759 mutex_lock(&kvm->slots_lock);
4760
4761 if (likely(kvm->arch.ept_identity_pagetable_done))
4762 goto out2;
4763
4764 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4765
4766 r = alloc_identity_pagetable(kvm);
4767 if (r < 0)
4768 goto out2;
4769
4770 idx = srcu_read_lock(&kvm->srcu);
4771 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4772 if (r < 0)
4773 goto out;
4774 /* Set up identity-mapping pagetable for EPT in real mode */
4775 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4776 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4777 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4778 r = kvm_write_guest_page(kvm, identity_map_pfn,
4779 &tmp, i * sizeof(tmp), sizeof(tmp));
4780 if (r < 0)
4781 goto out;
4782 }
4783 kvm->arch.ept_identity_pagetable_done = true;
4784
4785 out:
4786 srcu_read_unlock(&kvm->srcu, idx);
4787
4788 out2:
4789 mutex_unlock(&kvm->slots_lock);
4790 return r;
4791 }
4792
4793 static void seg_setup(int seg)
4794 {
4795 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4796 unsigned int ar;
4797
4798 vmcs_write16(sf->selector, 0);
4799 vmcs_writel(sf->base, 0);
4800 vmcs_write32(sf->limit, 0xffff);
4801 ar = 0x93;
4802 if (seg == VCPU_SREG_CS)
4803 ar |= 0x08; /* code segment */
4804
4805 vmcs_write32(sf->ar_bytes, ar);
4806 }
4807
4808 static int alloc_apic_access_page(struct kvm *kvm)
4809 {
4810 struct page *page;
4811 int r = 0;
4812
4813 mutex_lock(&kvm->slots_lock);
4814 if (kvm->arch.apic_access_page_done)
4815 goto out;
4816 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4817 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4818 if (r)
4819 goto out;
4820
4821 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4822 if (is_error_page(page)) {
4823 r = -EFAULT;
4824 goto out;
4825 }
4826
4827 /*
4828 * Do not pin the page in memory, so that memory hot-unplug
4829 * is able to migrate it.
4830 */
4831 put_page(page);
4832 kvm->arch.apic_access_page_done = true;
4833 out:
4834 mutex_unlock(&kvm->slots_lock);
4835 return r;
4836 }
4837
4838 static int alloc_identity_pagetable(struct kvm *kvm)
4839 {
4840 /* Called with kvm->slots_lock held. */
4841
4842 int r = 0;
4843
4844 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4845
4846 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4847 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4848
4849 return r;
4850 }
4851
4852 static int allocate_vpid(void)
4853 {
4854 int vpid;
4855
4856 if (!enable_vpid)
4857 return 0;
4858 spin_lock(&vmx_vpid_lock);
4859 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4860 if (vpid < VMX_NR_VPIDS)
4861 __set_bit(vpid, vmx_vpid_bitmap);
4862 else
4863 vpid = 0;
4864 spin_unlock(&vmx_vpid_lock);
4865 return vpid;
4866 }
4867
4868 static void free_vpid(int vpid)
4869 {
4870 if (!enable_vpid || vpid == 0)
4871 return;
4872 spin_lock(&vmx_vpid_lock);
4873 __clear_bit(vpid, vmx_vpid_bitmap);
4874 spin_unlock(&vmx_vpid_lock);
4875 }
4876
4877 #define MSR_TYPE_R 1
4878 #define MSR_TYPE_W 2
4879 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4880 u32 msr, int type)
4881 {
4882 int f = sizeof(unsigned long);
4883
4884 if (!cpu_has_vmx_msr_bitmap())
4885 return;
4886
4887 /*
4888 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4889 * have the write-low and read-high bitmap offsets the wrong way round.
4890 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4891 */
4892 if (msr <= 0x1fff) {
4893 if (type & MSR_TYPE_R)
4894 /* read-low */
4895 __clear_bit(msr, msr_bitmap + 0x000 / f);
4896
4897 if (type & MSR_TYPE_W)
4898 /* write-low */
4899 __clear_bit(msr, msr_bitmap + 0x800 / f);
4900
4901 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4902 msr &= 0x1fff;
4903 if (type & MSR_TYPE_R)
4904 /* read-high */
4905 __clear_bit(msr, msr_bitmap + 0x400 / f);
4906
4907 if (type & MSR_TYPE_W)
4908 /* write-high */
4909 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4910
4911 }
4912 }
4913
4914 /*
4915 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4916 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4917 */
4918 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4919 unsigned long *msr_bitmap_nested,
4920 u32 msr, int type)
4921 {
4922 int f = sizeof(unsigned long);
4923
4924 if (!cpu_has_vmx_msr_bitmap()) {
4925 WARN_ON(1);
4926 return;
4927 }
4928
4929 /*
4930 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4931 * have the write-low and read-high bitmap offsets the wrong way round.
4932 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4933 */
4934 if (msr <= 0x1fff) {
4935 if (type & MSR_TYPE_R &&
4936 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4937 /* read-low */
4938 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4939
4940 if (type & MSR_TYPE_W &&
4941 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4942 /* write-low */
4943 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4944
4945 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4946 msr &= 0x1fff;
4947 if (type & MSR_TYPE_R &&
4948 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4949 /* read-high */
4950 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4951
4952 if (type & MSR_TYPE_W &&
4953 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4954 /* write-high */
4955 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4956
4957 }
4958 }
4959
4960 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4961 {
4962 if (!longmode_only)
4963 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4964 msr, MSR_TYPE_R | MSR_TYPE_W);
4965 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4966 msr, MSR_TYPE_R | MSR_TYPE_W);
4967 }
4968
4969 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4970 {
4971 if (apicv_active) {
4972 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4973 msr, type);
4974 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4975 msr, type);
4976 } else {
4977 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4978 msr, type);
4979 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4980 msr, type);
4981 }
4982 }
4983
4984 static bool vmx_get_enable_apicv(void)
4985 {
4986 return enable_apicv;
4987 }
4988
4989 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
4990 {
4991 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4992 gfn_t gfn;
4993
4994 /*
4995 * Don't need to mark the APIC access page dirty; it is never
4996 * written to by the CPU during APIC virtualization.
4997 */
4998
4999 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5000 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5001 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5002 }
5003
5004 if (nested_cpu_has_posted_intr(vmcs12)) {
5005 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5006 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5007 }
5008 }
5009
5010
5011 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5012 {
5013 struct vcpu_vmx *vmx = to_vmx(vcpu);
5014 int max_irr;
5015 void *vapic_page;
5016 u16 status;
5017
5018 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5019 return;
5020
5021 vmx->nested.pi_pending = false;
5022 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5023 return;
5024
5025 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5026 if (max_irr != 256) {
5027 vapic_page = kmap(vmx->nested.virtual_apic_page);
5028 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5029 kunmap(vmx->nested.virtual_apic_page);
5030
5031 status = vmcs_read16(GUEST_INTR_STATUS);
5032 if ((u8)max_irr > ((u8)status & 0xff)) {
5033 status &= ~0xff;
5034 status |= (u8)max_irr;
5035 vmcs_write16(GUEST_INTR_STATUS, status);
5036 }
5037 }
5038
5039 nested_mark_vmcs12_pages_dirty(vcpu);
5040 }
5041
5042 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5043 bool nested)
5044 {
5045 #ifdef CONFIG_SMP
5046 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5047
5048 if (vcpu->mode == IN_GUEST_MODE) {
5049 /*
5050 * The vector of interrupt to be delivered to vcpu had
5051 * been set in PIR before this function.
5052 *
5053 * Following cases will be reached in this block, and
5054 * we always send a notification event in all cases as
5055 * explained below.
5056 *
5057 * Case 1: vcpu keeps in non-root mode. Sending a
5058 * notification event posts the interrupt to vcpu.
5059 *
5060 * Case 2: vcpu exits to root mode and is still
5061 * runnable. PIR will be synced to vIRR before the
5062 * next vcpu entry. Sending a notification event in
5063 * this case has no effect, as vcpu is not in root
5064 * mode.
5065 *
5066 * Case 3: vcpu exits to root mode and is blocked.
5067 * vcpu_block() has already synced PIR to vIRR and
5068 * never blocks vcpu if vIRR is not cleared. Therefore,
5069 * a blocked vcpu here does not wait for any requested
5070 * interrupts in PIR, and sending a notification event
5071 * which has no effect is safe here.
5072 */
5073
5074 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5075 return true;
5076 }
5077 #endif
5078 return false;
5079 }
5080
5081 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5082 int vector)
5083 {
5084 struct vcpu_vmx *vmx = to_vmx(vcpu);
5085
5086 if (is_guest_mode(vcpu) &&
5087 vector == vmx->nested.posted_intr_nv) {
5088 /* the PIR and ON have been set by L1. */
5089 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5090 /*
5091 * If a posted intr is not recognized by hardware,
5092 * we will accomplish it in the next vmentry.
5093 */
5094 vmx->nested.pi_pending = true;
5095 kvm_make_request(KVM_REQ_EVENT, vcpu);
5096 return 0;
5097 }
5098 return -1;
5099 }
5100 /*
5101 * Send interrupt to vcpu via posted interrupt way.
5102 * 1. If target vcpu is running(non-root mode), send posted interrupt
5103 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5104 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5105 * interrupt from PIR in next vmentry.
5106 */
5107 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5108 {
5109 struct vcpu_vmx *vmx = to_vmx(vcpu);
5110 int r;
5111
5112 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5113 if (!r)
5114 return;
5115
5116 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5117 return;
5118
5119 /* If a previous notification has sent the IPI, nothing to do. */
5120 if (pi_test_and_set_on(&vmx->pi_desc))
5121 return;
5122
5123 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5124 kvm_vcpu_kick(vcpu);
5125 }
5126
5127 /*
5128 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5129 * will not change in the lifetime of the guest.
5130 * Note that host-state that does change is set elsewhere. E.g., host-state
5131 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5132 */
5133 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5134 {
5135 u32 low32, high32;
5136 unsigned long tmpl;
5137 struct desc_ptr dt;
5138 unsigned long cr0, cr3, cr4;
5139
5140 cr0 = read_cr0();
5141 WARN_ON(cr0 & X86_CR0_TS);
5142 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5143
5144 /*
5145 * Save the most likely value for this task's CR3 in the VMCS.
5146 * We can't use __get_current_cr3_fast() because we're not atomic.
5147 */
5148 cr3 = __read_cr3();
5149 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5150 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5151
5152 /* Save the most likely value for this task's CR4 in the VMCS. */
5153 cr4 = cr4_read_shadow();
5154 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5155 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5156
5157 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5158 #ifdef CONFIG_X86_64
5159 /*
5160 * Load null selectors, so we can avoid reloading them in
5161 * __vmx_load_host_state(), in case userspace uses the null selectors
5162 * too (the expected case).
5163 */
5164 vmcs_write16(HOST_DS_SELECTOR, 0);
5165 vmcs_write16(HOST_ES_SELECTOR, 0);
5166 #else
5167 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5168 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5169 #endif
5170 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5171 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5172
5173 native_store_idt(&dt);
5174 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5175 vmx->host_idt_base = dt.address;
5176
5177 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5178
5179 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5180 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5181 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5182 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5183
5184 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5185 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5186 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5187 }
5188 }
5189
5190 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5191 {
5192 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5193 if (enable_ept)
5194 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5195 if (is_guest_mode(&vmx->vcpu))
5196 vmx->vcpu.arch.cr4_guest_owned_bits &=
5197 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5198 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5199 }
5200
5201 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5202 {
5203 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5204
5205 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5206 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5207 /* Enable the preemption timer dynamically */
5208 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5209 return pin_based_exec_ctrl;
5210 }
5211
5212 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5213 {
5214 struct vcpu_vmx *vmx = to_vmx(vcpu);
5215
5216 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5217 if (cpu_has_secondary_exec_ctrls()) {
5218 if (kvm_vcpu_apicv_active(vcpu))
5219 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5220 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5221 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5222 else
5223 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5224 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5225 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5226 }
5227
5228 if (cpu_has_vmx_msr_bitmap())
5229 vmx_set_msr_bitmap(vcpu);
5230 }
5231
5232 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5233 {
5234 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5235
5236 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5237 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5238
5239 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5240 exec_control &= ~CPU_BASED_TPR_SHADOW;
5241 #ifdef CONFIG_X86_64
5242 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5243 CPU_BASED_CR8_LOAD_EXITING;
5244 #endif
5245 }
5246 if (!enable_ept)
5247 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5248 CPU_BASED_CR3_LOAD_EXITING |
5249 CPU_BASED_INVLPG_EXITING;
5250 return exec_control;
5251 }
5252
5253 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5254 {
5255 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5256 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5257 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5258 if (vmx->vpid == 0)
5259 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5260 if (!enable_ept) {
5261 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5262 enable_unrestricted_guest = 0;
5263 /* Enable INVPCID for non-ept guests may cause performance regression. */
5264 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5265 }
5266 if (!enable_unrestricted_guest)
5267 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5268 if (!ple_gap)
5269 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5270 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5271 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5272 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5273 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5274 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5275 (handle_vmptrld).
5276 We can NOT enable shadow_vmcs here because we don't have yet
5277 a current VMCS12
5278 */
5279 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5280
5281 if (!enable_pml)
5282 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5283
5284 return exec_control;
5285 }
5286
5287 static void ept_set_mmio_spte_mask(void)
5288 {
5289 /*
5290 * EPT Misconfigurations can be generated if the value of bits 2:0
5291 * of an EPT paging-structure entry is 110b (write/execute).
5292 */
5293 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5294 VMX_EPT_MISCONFIG_WX_VALUE);
5295 }
5296
5297 #define VMX_XSS_EXIT_BITMAP 0
5298 /*
5299 * Sets up the vmcs for emulated real mode.
5300 */
5301 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5302 {
5303 #ifdef CONFIG_X86_64
5304 unsigned long a;
5305 #endif
5306 int i;
5307
5308 /* I/O */
5309 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5310 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5311
5312 if (enable_shadow_vmcs) {
5313 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5314 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5315 }
5316 if (cpu_has_vmx_msr_bitmap())
5317 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5318
5319 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5320
5321 /* Control */
5322 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5323 vmx->hv_deadline_tsc = -1;
5324
5325 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5326
5327 if (cpu_has_secondary_exec_ctrls()) {
5328 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5329 vmx_secondary_exec_control(vmx));
5330 }
5331
5332 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5333 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5334 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5335 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5336 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5337
5338 vmcs_write16(GUEST_INTR_STATUS, 0);
5339
5340 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5341 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5342 }
5343
5344 if (ple_gap) {
5345 vmcs_write32(PLE_GAP, ple_gap);
5346 vmx->ple_window = ple_window;
5347 vmx->ple_window_dirty = true;
5348 }
5349
5350 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5351 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5352 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5353
5354 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5355 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5356 vmx_set_constant_host_state(vmx);
5357 #ifdef CONFIG_X86_64
5358 rdmsrl(MSR_FS_BASE, a);
5359 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5360 rdmsrl(MSR_GS_BASE, a);
5361 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5362 #else
5363 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5364 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5365 #endif
5366
5367 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5368 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5369 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5370 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5371 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5372
5373 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5374 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5375
5376 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5377 u32 index = vmx_msr_index[i];
5378 u32 data_low, data_high;
5379 int j = vmx->nmsrs;
5380
5381 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5382 continue;
5383 if (wrmsr_safe(index, data_low, data_high) < 0)
5384 continue;
5385 vmx->guest_msrs[j].index = i;
5386 vmx->guest_msrs[j].data = 0;
5387 vmx->guest_msrs[j].mask = -1ull;
5388 ++vmx->nmsrs;
5389 }
5390
5391
5392 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5393
5394 /* 22.2.1, 20.8.1 */
5395 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5396
5397 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5398 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5399
5400 set_cr4_guest_host_mask(vmx);
5401
5402 if (vmx_xsaves_supported())
5403 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5404
5405 if (enable_pml) {
5406 ASSERT(vmx->pml_pg);
5407 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5408 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5409 }
5410
5411 return 0;
5412 }
5413
5414 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5415 {
5416 struct vcpu_vmx *vmx = to_vmx(vcpu);
5417 struct msr_data apic_base_msr;
5418 u64 cr0;
5419
5420 vmx->rmode.vm86_active = 0;
5421
5422 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5423 kvm_set_cr8(vcpu, 0);
5424
5425 if (!init_event) {
5426 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5427 MSR_IA32_APICBASE_ENABLE;
5428 if (kvm_vcpu_is_reset_bsp(vcpu))
5429 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5430 apic_base_msr.host_initiated = true;
5431 kvm_set_apic_base(vcpu, &apic_base_msr);
5432 }
5433
5434 vmx_segment_cache_clear(vmx);
5435
5436 seg_setup(VCPU_SREG_CS);
5437 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5438 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5439
5440 seg_setup(VCPU_SREG_DS);
5441 seg_setup(VCPU_SREG_ES);
5442 seg_setup(VCPU_SREG_FS);
5443 seg_setup(VCPU_SREG_GS);
5444 seg_setup(VCPU_SREG_SS);
5445
5446 vmcs_write16(GUEST_TR_SELECTOR, 0);
5447 vmcs_writel(GUEST_TR_BASE, 0);
5448 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5449 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5450
5451 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5452 vmcs_writel(GUEST_LDTR_BASE, 0);
5453 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5454 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5455
5456 if (!init_event) {
5457 vmcs_write32(GUEST_SYSENTER_CS, 0);
5458 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5459 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5460 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5461 }
5462
5463 vmcs_writel(GUEST_RFLAGS, 0x02);
5464 kvm_rip_write(vcpu, 0xfff0);
5465
5466 vmcs_writel(GUEST_GDTR_BASE, 0);
5467 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5468
5469 vmcs_writel(GUEST_IDTR_BASE, 0);
5470 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5471
5472 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5473 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5474 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5475
5476 setup_msrs(vmx);
5477
5478 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5479
5480 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5481 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5482 if (cpu_need_tpr_shadow(vcpu))
5483 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5484 __pa(vcpu->arch.apic->regs));
5485 vmcs_write32(TPR_THRESHOLD, 0);
5486 }
5487
5488 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5489
5490 if (kvm_vcpu_apicv_active(vcpu))
5491 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5492
5493 if (vmx->vpid != 0)
5494 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5495
5496 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5497 vmx->vcpu.arch.cr0 = cr0;
5498 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5499 vmx_set_cr4(vcpu, 0);
5500 vmx_set_efer(vcpu, 0);
5501
5502 update_exception_bitmap(vcpu);
5503
5504 vpid_sync_context(vmx->vpid);
5505 }
5506
5507 /*
5508 * In nested virtualization, check if L1 asked to exit on external interrupts.
5509 * For most existing hypervisors, this will always return true.
5510 */
5511 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5512 {
5513 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5514 PIN_BASED_EXT_INTR_MASK;
5515 }
5516
5517 /*
5518 * In nested virtualization, check if L1 has set
5519 * VM_EXIT_ACK_INTR_ON_EXIT
5520 */
5521 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5522 {
5523 return get_vmcs12(vcpu)->vm_exit_controls &
5524 VM_EXIT_ACK_INTR_ON_EXIT;
5525 }
5526
5527 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5528 {
5529 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5530 PIN_BASED_NMI_EXITING;
5531 }
5532
5533 static void enable_irq_window(struct kvm_vcpu *vcpu)
5534 {
5535 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5536 CPU_BASED_VIRTUAL_INTR_PENDING);
5537 }
5538
5539 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5540 {
5541 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5542 enable_irq_window(vcpu);
5543 return;
5544 }
5545
5546 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5547 CPU_BASED_VIRTUAL_NMI_PENDING);
5548 }
5549
5550 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5551 {
5552 struct vcpu_vmx *vmx = to_vmx(vcpu);
5553 uint32_t intr;
5554 int irq = vcpu->arch.interrupt.nr;
5555
5556 trace_kvm_inj_virq(irq);
5557
5558 ++vcpu->stat.irq_injections;
5559 if (vmx->rmode.vm86_active) {
5560 int inc_eip = 0;
5561 if (vcpu->arch.interrupt.soft)
5562 inc_eip = vcpu->arch.event_exit_inst_len;
5563 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5564 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5565 return;
5566 }
5567 intr = irq | INTR_INFO_VALID_MASK;
5568 if (vcpu->arch.interrupt.soft) {
5569 intr |= INTR_TYPE_SOFT_INTR;
5570 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5571 vmx->vcpu.arch.event_exit_inst_len);
5572 } else
5573 intr |= INTR_TYPE_EXT_INTR;
5574 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5575 }
5576
5577 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5578 {
5579 struct vcpu_vmx *vmx = to_vmx(vcpu);
5580
5581 ++vcpu->stat.nmi_injections;
5582 vmx->loaded_vmcs->nmi_known_unmasked = false;
5583
5584 if (vmx->rmode.vm86_active) {
5585 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5586 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5587 return;
5588 }
5589
5590 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5591 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5592 }
5593
5594 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5595 {
5596 struct vcpu_vmx *vmx = to_vmx(vcpu);
5597 bool masked;
5598
5599 if (vmx->loaded_vmcs->nmi_known_unmasked)
5600 return false;
5601 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5602 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5603 return masked;
5604 }
5605
5606 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5607 {
5608 struct vcpu_vmx *vmx = to_vmx(vcpu);
5609
5610 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5611 if (masked)
5612 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5613 GUEST_INTR_STATE_NMI);
5614 else
5615 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5616 GUEST_INTR_STATE_NMI);
5617 }
5618
5619 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5620 {
5621 if (to_vmx(vcpu)->nested.nested_run_pending)
5622 return 0;
5623
5624 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5625 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5626 | GUEST_INTR_STATE_NMI));
5627 }
5628
5629 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5630 {
5631 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5632 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5633 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5634 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5635 }
5636
5637 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5638 {
5639 int ret;
5640
5641 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5642 PAGE_SIZE * 3);
5643 if (ret)
5644 return ret;
5645 kvm->arch.tss_addr = addr;
5646 return init_rmode_tss(kvm);
5647 }
5648
5649 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5650 {
5651 switch (vec) {
5652 case BP_VECTOR:
5653 /*
5654 * Update instruction length as we may reinject the exception
5655 * from user space while in guest debugging mode.
5656 */
5657 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5658 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5659 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5660 return false;
5661 /* fall through */
5662 case DB_VECTOR:
5663 if (vcpu->guest_debug &
5664 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5665 return false;
5666 /* fall through */
5667 case DE_VECTOR:
5668 case OF_VECTOR:
5669 case BR_VECTOR:
5670 case UD_VECTOR:
5671 case DF_VECTOR:
5672 case SS_VECTOR:
5673 case GP_VECTOR:
5674 case MF_VECTOR:
5675 return true;
5676 break;
5677 }
5678 return false;
5679 }
5680
5681 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5682 int vec, u32 err_code)
5683 {
5684 /*
5685 * Instruction with address size override prefix opcode 0x67
5686 * Cause the #SS fault with 0 error code in VM86 mode.
5687 */
5688 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5689 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5690 if (vcpu->arch.halt_request) {
5691 vcpu->arch.halt_request = 0;
5692 return kvm_vcpu_halt(vcpu);
5693 }
5694 return 1;
5695 }
5696 return 0;
5697 }
5698
5699 /*
5700 * Forward all other exceptions that are valid in real mode.
5701 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5702 * the required debugging infrastructure rework.
5703 */
5704 kvm_queue_exception(vcpu, vec);
5705 return 1;
5706 }
5707
5708 /*
5709 * Trigger machine check on the host. We assume all the MSRs are already set up
5710 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5711 * We pass a fake environment to the machine check handler because we want
5712 * the guest to be always treated like user space, no matter what context
5713 * it used internally.
5714 */
5715 static void kvm_machine_check(void)
5716 {
5717 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5718 struct pt_regs regs = {
5719 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5720 .flags = X86_EFLAGS_IF,
5721 };
5722
5723 do_machine_check(&regs, 0);
5724 #endif
5725 }
5726
5727 static int handle_machine_check(struct kvm_vcpu *vcpu)
5728 {
5729 /* already handled by vcpu_run */
5730 return 1;
5731 }
5732
5733 static int handle_exception(struct kvm_vcpu *vcpu)
5734 {
5735 struct vcpu_vmx *vmx = to_vmx(vcpu);
5736 struct kvm_run *kvm_run = vcpu->run;
5737 u32 intr_info, ex_no, error_code;
5738 unsigned long cr2, rip, dr6;
5739 u32 vect_info;
5740 enum emulation_result er;
5741
5742 vect_info = vmx->idt_vectoring_info;
5743 intr_info = vmx->exit_intr_info;
5744
5745 if (is_machine_check(intr_info))
5746 return handle_machine_check(vcpu);
5747
5748 if (is_nmi(intr_info))
5749 return 1; /* already handled by vmx_vcpu_run() */
5750
5751 if (is_invalid_opcode(intr_info)) {
5752 if (is_guest_mode(vcpu)) {
5753 kvm_queue_exception(vcpu, UD_VECTOR);
5754 return 1;
5755 }
5756 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5757 if (er != EMULATE_DONE)
5758 kvm_queue_exception(vcpu, UD_VECTOR);
5759 return 1;
5760 }
5761
5762 error_code = 0;
5763 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5764 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5765
5766 /*
5767 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5768 * MMIO, it is better to report an internal error.
5769 * See the comments in vmx_handle_exit.
5770 */
5771 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5772 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5773 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5774 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5775 vcpu->run->internal.ndata = 3;
5776 vcpu->run->internal.data[0] = vect_info;
5777 vcpu->run->internal.data[1] = intr_info;
5778 vcpu->run->internal.data[2] = error_code;
5779 return 0;
5780 }
5781
5782 if (is_page_fault(intr_info)) {
5783 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5784 /* EPT won't cause page fault directly */
5785 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5786 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5787 true);
5788 }
5789
5790 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5791
5792 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5793 return handle_rmode_exception(vcpu, ex_no, error_code);
5794
5795 switch (ex_no) {
5796 case AC_VECTOR:
5797 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5798 return 1;
5799 case DB_VECTOR:
5800 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5801 if (!(vcpu->guest_debug &
5802 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5803 vcpu->arch.dr6 &= ~15;
5804 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5805 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5806 skip_emulated_instruction(vcpu);
5807
5808 kvm_queue_exception(vcpu, DB_VECTOR);
5809 return 1;
5810 }
5811 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5812 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5813 /* fall through */
5814 case BP_VECTOR:
5815 /*
5816 * Update instruction length as we may reinject #BP from
5817 * user space while in guest debugging mode. Reading it for
5818 * #DB as well causes no harm, it is not used in that case.
5819 */
5820 vmx->vcpu.arch.event_exit_inst_len =
5821 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5822 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5823 rip = kvm_rip_read(vcpu);
5824 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5825 kvm_run->debug.arch.exception = ex_no;
5826 break;
5827 default:
5828 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5829 kvm_run->ex.exception = ex_no;
5830 kvm_run->ex.error_code = error_code;
5831 break;
5832 }
5833 return 0;
5834 }
5835
5836 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5837 {
5838 ++vcpu->stat.irq_exits;
5839 return 1;
5840 }
5841
5842 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5843 {
5844 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5845 return 0;
5846 }
5847
5848 static int handle_io(struct kvm_vcpu *vcpu)
5849 {
5850 unsigned long exit_qualification;
5851 int size, in, string, ret;
5852 unsigned port;
5853
5854 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5855 string = (exit_qualification & 16) != 0;
5856 in = (exit_qualification & 8) != 0;
5857
5858 ++vcpu->stat.io_exits;
5859
5860 if (string || in)
5861 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5862
5863 port = exit_qualification >> 16;
5864 size = (exit_qualification & 7) + 1;
5865
5866 ret = kvm_skip_emulated_instruction(vcpu);
5867
5868 /*
5869 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5870 * KVM_EXIT_DEBUG here.
5871 */
5872 return kvm_fast_pio_out(vcpu, size, port) && ret;
5873 }
5874
5875 static void
5876 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5877 {
5878 /*
5879 * Patch in the VMCALL instruction:
5880 */
5881 hypercall[0] = 0x0f;
5882 hypercall[1] = 0x01;
5883 hypercall[2] = 0xc1;
5884 }
5885
5886 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5887 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5888 {
5889 if (is_guest_mode(vcpu)) {
5890 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5891 unsigned long orig_val = val;
5892
5893 /*
5894 * We get here when L2 changed cr0 in a way that did not change
5895 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5896 * but did change L0 shadowed bits. So we first calculate the
5897 * effective cr0 value that L1 would like to write into the
5898 * hardware. It consists of the L2-owned bits from the new
5899 * value combined with the L1-owned bits from L1's guest_cr0.
5900 */
5901 val = (val & ~vmcs12->cr0_guest_host_mask) |
5902 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5903
5904 if (!nested_guest_cr0_valid(vcpu, val))
5905 return 1;
5906
5907 if (kvm_set_cr0(vcpu, val))
5908 return 1;
5909 vmcs_writel(CR0_READ_SHADOW, orig_val);
5910 return 0;
5911 } else {
5912 if (to_vmx(vcpu)->nested.vmxon &&
5913 !nested_host_cr0_valid(vcpu, val))
5914 return 1;
5915
5916 return kvm_set_cr0(vcpu, val);
5917 }
5918 }
5919
5920 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5921 {
5922 if (is_guest_mode(vcpu)) {
5923 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5924 unsigned long orig_val = val;
5925
5926 /* analogously to handle_set_cr0 */
5927 val = (val & ~vmcs12->cr4_guest_host_mask) |
5928 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5929 if (kvm_set_cr4(vcpu, val))
5930 return 1;
5931 vmcs_writel(CR4_READ_SHADOW, orig_val);
5932 return 0;
5933 } else
5934 return kvm_set_cr4(vcpu, val);
5935 }
5936
5937 static int handle_cr(struct kvm_vcpu *vcpu)
5938 {
5939 unsigned long exit_qualification, val;
5940 int cr;
5941 int reg;
5942 int err;
5943 int ret;
5944
5945 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5946 cr = exit_qualification & 15;
5947 reg = (exit_qualification >> 8) & 15;
5948 switch ((exit_qualification >> 4) & 3) {
5949 case 0: /* mov to cr */
5950 val = kvm_register_readl(vcpu, reg);
5951 trace_kvm_cr_write(cr, val);
5952 switch (cr) {
5953 case 0:
5954 err = handle_set_cr0(vcpu, val);
5955 return kvm_complete_insn_gp(vcpu, err);
5956 case 3:
5957 err = kvm_set_cr3(vcpu, val);
5958 return kvm_complete_insn_gp(vcpu, err);
5959 case 4:
5960 err = handle_set_cr4(vcpu, val);
5961 return kvm_complete_insn_gp(vcpu, err);
5962 case 8: {
5963 u8 cr8_prev = kvm_get_cr8(vcpu);
5964 u8 cr8 = (u8)val;
5965 err = kvm_set_cr8(vcpu, cr8);
5966 ret = kvm_complete_insn_gp(vcpu, err);
5967 if (lapic_in_kernel(vcpu))
5968 return ret;
5969 if (cr8_prev <= cr8)
5970 return ret;
5971 /*
5972 * TODO: we might be squashing a
5973 * KVM_GUESTDBG_SINGLESTEP-triggered
5974 * KVM_EXIT_DEBUG here.
5975 */
5976 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5977 return 0;
5978 }
5979 }
5980 break;
5981 case 2: /* clts */
5982 WARN_ONCE(1, "Guest should always own CR0.TS");
5983 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5984 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5985 return kvm_skip_emulated_instruction(vcpu);
5986 case 1: /*mov from cr*/
5987 switch (cr) {
5988 case 3:
5989 val = kvm_read_cr3(vcpu);
5990 kvm_register_write(vcpu, reg, val);
5991 trace_kvm_cr_read(cr, val);
5992 return kvm_skip_emulated_instruction(vcpu);
5993 case 8:
5994 val = kvm_get_cr8(vcpu);
5995 kvm_register_write(vcpu, reg, val);
5996 trace_kvm_cr_read(cr, val);
5997 return kvm_skip_emulated_instruction(vcpu);
5998 }
5999 break;
6000 case 3: /* lmsw */
6001 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6002 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6003 kvm_lmsw(vcpu, val);
6004
6005 return kvm_skip_emulated_instruction(vcpu);
6006 default:
6007 break;
6008 }
6009 vcpu->run->exit_reason = 0;
6010 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6011 (int)(exit_qualification >> 4) & 3, cr);
6012 return 0;
6013 }
6014
6015 static int handle_dr(struct kvm_vcpu *vcpu)
6016 {
6017 unsigned long exit_qualification;
6018 int dr, dr7, reg;
6019
6020 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6021 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6022
6023 /* First, if DR does not exist, trigger UD */
6024 if (!kvm_require_dr(vcpu, dr))
6025 return 1;
6026
6027 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6028 if (!kvm_require_cpl(vcpu, 0))
6029 return 1;
6030 dr7 = vmcs_readl(GUEST_DR7);
6031 if (dr7 & DR7_GD) {
6032 /*
6033 * As the vm-exit takes precedence over the debug trap, we
6034 * need to emulate the latter, either for the host or the
6035 * guest debugging itself.
6036 */
6037 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6038 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6039 vcpu->run->debug.arch.dr7 = dr7;
6040 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6041 vcpu->run->debug.arch.exception = DB_VECTOR;
6042 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6043 return 0;
6044 } else {
6045 vcpu->arch.dr6 &= ~15;
6046 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6047 kvm_queue_exception(vcpu, DB_VECTOR);
6048 return 1;
6049 }
6050 }
6051
6052 if (vcpu->guest_debug == 0) {
6053 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6054 CPU_BASED_MOV_DR_EXITING);
6055
6056 /*
6057 * No more DR vmexits; force a reload of the debug registers
6058 * and reenter on this instruction. The next vmexit will
6059 * retrieve the full state of the debug registers.
6060 */
6061 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6062 return 1;
6063 }
6064
6065 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6066 if (exit_qualification & TYPE_MOV_FROM_DR) {
6067 unsigned long val;
6068
6069 if (kvm_get_dr(vcpu, dr, &val))
6070 return 1;
6071 kvm_register_write(vcpu, reg, val);
6072 } else
6073 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6074 return 1;
6075
6076 return kvm_skip_emulated_instruction(vcpu);
6077 }
6078
6079 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6080 {
6081 return vcpu->arch.dr6;
6082 }
6083
6084 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6085 {
6086 }
6087
6088 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6089 {
6090 get_debugreg(vcpu->arch.db[0], 0);
6091 get_debugreg(vcpu->arch.db[1], 1);
6092 get_debugreg(vcpu->arch.db[2], 2);
6093 get_debugreg(vcpu->arch.db[3], 3);
6094 get_debugreg(vcpu->arch.dr6, 6);
6095 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6096
6097 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6098 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6099 }
6100
6101 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6102 {
6103 vmcs_writel(GUEST_DR7, val);
6104 }
6105
6106 static int handle_cpuid(struct kvm_vcpu *vcpu)
6107 {
6108 return kvm_emulate_cpuid(vcpu);
6109 }
6110
6111 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6112 {
6113 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6114 struct msr_data msr_info;
6115
6116 msr_info.index = ecx;
6117 msr_info.host_initiated = false;
6118 if (vmx_get_msr(vcpu, &msr_info)) {
6119 trace_kvm_msr_read_ex(ecx);
6120 kvm_inject_gp(vcpu, 0);
6121 return 1;
6122 }
6123
6124 trace_kvm_msr_read(ecx, msr_info.data);
6125
6126 /* FIXME: handling of bits 32:63 of rax, rdx */
6127 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6128 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6129 return kvm_skip_emulated_instruction(vcpu);
6130 }
6131
6132 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6133 {
6134 struct msr_data msr;
6135 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6136 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6137 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6138
6139 msr.data = data;
6140 msr.index = ecx;
6141 msr.host_initiated = false;
6142 if (kvm_set_msr(vcpu, &msr) != 0) {
6143 trace_kvm_msr_write_ex(ecx, data);
6144 kvm_inject_gp(vcpu, 0);
6145 return 1;
6146 }
6147
6148 trace_kvm_msr_write(ecx, data);
6149 return kvm_skip_emulated_instruction(vcpu);
6150 }
6151
6152 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6153 {
6154 kvm_apic_update_ppr(vcpu);
6155 return 1;
6156 }
6157
6158 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6159 {
6160 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6161 CPU_BASED_VIRTUAL_INTR_PENDING);
6162
6163 kvm_make_request(KVM_REQ_EVENT, vcpu);
6164
6165 ++vcpu->stat.irq_window_exits;
6166 return 1;
6167 }
6168
6169 static int handle_halt(struct kvm_vcpu *vcpu)
6170 {
6171 return kvm_emulate_halt(vcpu);
6172 }
6173
6174 static int handle_vmcall(struct kvm_vcpu *vcpu)
6175 {
6176 return kvm_emulate_hypercall(vcpu);
6177 }
6178
6179 static int handle_invd(struct kvm_vcpu *vcpu)
6180 {
6181 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6182 }
6183
6184 static int handle_invlpg(struct kvm_vcpu *vcpu)
6185 {
6186 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6187
6188 kvm_mmu_invlpg(vcpu, exit_qualification);
6189 return kvm_skip_emulated_instruction(vcpu);
6190 }
6191
6192 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6193 {
6194 int err;
6195
6196 err = kvm_rdpmc(vcpu);
6197 return kvm_complete_insn_gp(vcpu, err);
6198 }
6199
6200 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6201 {
6202 return kvm_emulate_wbinvd(vcpu);
6203 }
6204
6205 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6206 {
6207 u64 new_bv = kvm_read_edx_eax(vcpu);
6208 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6209
6210 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6211 return kvm_skip_emulated_instruction(vcpu);
6212 return 1;
6213 }
6214
6215 static int handle_xsaves(struct kvm_vcpu *vcpu)
6216 {
6217 kvm_skip_emulated_instruction(vcpu);
6218 WARN(1, "this should never happen\n");
6219 return 1;
6220 }
6221
6222 static int handle_xrstors(struct kvm_vcpu *vcpu)
6223 {
6224 kvm_skip_emulated_instruction(vcpu);
6225 WARN(1, "this should never happen\n");
6226 return 1;
6227 }
6228
6229 static int handle_apic_access(struct kvm_vcpu *vcpu)
6230 {
6231 if (likely(fasteoi)) {
6232 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6233 int access_type, offset;
6234
6235 access_type = exit_qualification & APIC_ACCESS_TYPE;
6236 offset = exit_qualification & APIC_ACCESS_OFFSET;
6237 /*
6238 * Sane guest uses MOV to write EOI, with written value
6239 * not cared. So make a short-circuit here by avoiding
6240 * heavy instruction emulation.
6241 */
6242 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6243 (offset == APIC_EOI)) {
6244 kvm_lapic_set_eoi(vcpu);
6245 return kvm_skip_emulated_instruction(vcpu);
6246 }
6247 }
6248 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6249 }
6250
6251 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6252 {
6253 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6254 int vector = exit_qualification & 0xff;
6255
6256 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6257 kvm_apic_set_eoi_accelerated(vcpu, vector);
6258 return 1;
6259 }
6260
6261 static int handle_apic_write(struct kvm_vcpu *vcpu)
6262 {
6263 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6264 u32 offset = exit_qualification & 0xfff;
6265
6266 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6267 kvm_apic_write_nodecode(vcpu, offset);
6268 return 1;
6269 }
6270
6271 static int handle_task_switch(struct kvm_vcpu *vcpu)
6272 {
6273 struct vcpu_vmx *vmx = to_vmx(vcpu);
6274 unsigned long exit_qualification;
6275 bool has_error_code = false;
6276 u32 error_code = 0;
6277 u16 tss_selector;
6278 int reason, type, idt_v, idt_index;
6279
6280 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6281 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6282 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6283
6284 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6285
6286 reason = (u32)exit_qualification >> 30;
6287 if (reason == TASK_SWITCH_GATE && idt_v) {
6288 switch (type) {
6289 case INTR_TYPE_NMI_INTR:
6290 vcpu->arch.nmi_injected = false;
6291 vmx_set_nmi_mask(vcpu, true);
6292 break;
6293 case INTR_TYPE_EXT_INTR:
6294 case INTR_TYPE_SOFT_INTR:
6295 kvm_clear_interrupt_queue(vcpu);
6296 break;
6297 case INTR_TYPE_HARD_EXCEPTION:
6298 if (vmx->idt_vectoring_info &
6299 VECTORING_INFO_DELIVER_CODE_MASK) {
6300 has_error_code = true;
6301 error_code =
6302 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6303 }
6304 /* fall through */
6305 case INTR_TYPE_SOFT_EXCEPTION:
6306 kvm_clear_exception_queue(vcpu);
6307 break;
6308 default:
6309 break;
6310 }
6311 }
6312 tss_selector = exit_qualification;
6313
6314 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6315 type != INTR_TYPE_EXT_INTR &&
6316 type != INTR_TYPE_NMI_INTR))
6317 skip_emulated_instruction(vcpu);
6318
6319 if (kvm_task_switch(vcpu, tss_selector,
6320 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6321 has_error_code, error_code) == EMULATE_FAIL) {
6322 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6323 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6324 vcpu->run->internal.ndata = 0;
6325 return 0;
6326 }
6327
6328 /*
6329 * TODO: What about debug traps on tss switch?
6330 * Are we supposed to inject them and update dr6?
6331 */
6332
6333 return 1;
6334 }
6335
6336 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6337 {
6338 unsigned long exit_qualification;
6339 gpa_t gpa;
6340 u32 error_code;
6341
6342 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6343
6344 /*
6345 * EPT violation happened while executing iret from NMI,
6346 * "blocked by NMI" bit has to be set before next VM entry.
6347 * There are errata that may cause this bit to not be set:
6348 * AAK134, BY25.
6349 */
6350 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6351 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6352 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6353
6354 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6355 trace_kvm_page_fault(gpa, exit_qualification);
6356
6357 /* Is it a read fault? */
6358 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6359 ? PFERR_USER_MASK : 0;
6360 /* Is it a write fault? */
6361 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6362 ? PFERR_WRITE_MASK : 0;
6363 /* Is it a fetch fault? */
6364 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6365 ? PFERR_FETCH_MASK : 0;
6366 /* ept page table entry is present? */
6367 error_code |= (exit_qualification &
6368 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6369 EPT_VIOLATION_EXECUTABLE))
6370 ? PFERR_PRESENT_MASK : 0;
6371
6372 vcpu->arch.gpa_available = true;
6373 vcpu->arch.exit_qualification = exit_qualification;
6374
6375 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6376 }
6377
6378 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6379 {
6380 int ret;
6381 gpa_t gpa;
6382
6383 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6384 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6385 trace_kvm_fast_mmio(gpa);
6386 return kvm_skip_emulated_instruction(vcpu);
6387 }
6388
6389 ret = handle_mmio_page_fault(vcpu, gpa, true);
6390 vcpu->arch.gpa_available = true;
6391 if (likely(ret == RET_MMIO_PF_EMULATE))
6392 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6393 EMULATE_DONE;
6394
6395 if (unlikely(ret == RET_MMIO_PF_INVALID))
6396 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6397
6398 if (unlikely(ret == RET_MMIO_PF_RETRY))
6399 return 1;
6400
6401 /* It is the real ept misconfig */
6402 WARN_ON(1);
6403
6404 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6405 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6406
6407 return 0;
6408 }
6409
6410 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6411 {
6412 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6413 CPU_BASED_VIRTUAL_NMI_PENDING);
6414 ++vcpu->stat.nmi_window_exits;
6415 kvm_make_request(KVM_REQ_EVENT, vcpu);
6416
6417 return 1;
6418 }
6419
6420 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6421 {
6422 struct vcpu_vmx *vmx = to_vmx(vcpu);
6423 enum emulation_result err = EMULATE_DONE;
6424 int ret = 1;
6425 u32 cpu_exec_ctrl;
6426 bool intr_window_requested;
6427 unsigned count = 130;
6428
6429 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6430 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6431
6432 while (vmx->emulation_required && count-- != 0) {
6433 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6434 return handle_interrupt_window(&vmx->vcpu);
6435
6436 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6437 return 1;
6438
6439 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6440
6441 if (err == EMULATE_USER_EXIT) {
6442 ++vcpu->stat.mmio_exits;
6443 ret = 0;
6444 goto out;
6445 }
6446
6447 if (err != EMULATE_DONE) {
6448 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6449 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6450 vcpu->run->internal.ndata = 0;
6451 return 0;
6452 }
6453
6454 if (vcpu->arch.halt_request) {
6455 vcpu->arch.halt_request = 0;
6456 ret = kvm_vcpu_halt(vcpu);
6457 goto out;
6458 }
6459
6460 if (signal_pending(current))
6461 goto out;
6462 if (need_resched())
6463 schedule();
6464 }
6465
6466 out:
6467 return ret;
6468 }
6469
6470 static int __grow_ple_window(int val)
6471 {
6472 if (ple_window_grow < 1)
6473 return ple_window;
6474
6475 val = min(val, ple_window_actual_max);
6476
6477 if (ple_window_grow < ple_window)
6478 val *= ple_window_grow;
6479 else
6480 val += ple_window_grow;
6481
6482 return val;
6483 }
6484
6485 static int __shrink_ple_window(int val, int modifier, int minimum)
6486 {
6487 if (modifier < 1)
6488 return ple_window;
6489
6490 if (modifier < ple_window)
6491 val /= modifier;
6492 else
6493 val -= modifier;
6494
6495 return max(val, minimum);
6496 }
6497
6498 static void grow_ple_window(struct kvm_vcpu *vcpu)
6499 {
6500 struct vcpu_vmx *vmx = to_vmx(vcpu);
6501 int old = vmx->ple_window;
6502
6503 vmx->ple_window = __grow_ple_window(old);
6504
6505 if (vmx->ple_window != old)
6506 vmx->ple_window_dirty = true;
6507
6508 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6509 }
6510
6511 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6512 {
6513 struct vcpu_vmx *vmx = to_vmx(vcpu);
6514 int old = vmx->ple_window;
6515
6516 vmx->ple_window = __shrink_ple_window(old,
6517 ple_window_shrink, ple_window);
6518
6519 if (vmx->ple_window != old)
6520 vmx->ple_window_dirty = true;
6521
6522 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6523 }
6524
6525 /*
6526 * ple_window_actual_max is computed to be one grow_ple_window() below
6527 * ple_window_max. (See __grow_ple_window for the reason.)
6528 * This prevents overflows, because ple_window_max is int.
6529 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6530 * this process.
6531 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6532 */
6533 static void update_ple_window_actual_max(void)
6534 {
6535 ple_window_actual_max =
6536 __shrink_ple_window(max(ple_window_max, ple_window),
6537 ple_window_grow, INT_MIN);
6538 }
6539
6540 /*
6541 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6542 */
6543 static void wakeup_handler(void)
6544 {
6545 struct kvm_vcpu *vcpu;
6546 int cpu = smp_processor_id();
6547
6548 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6549 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6550 blocked_vcpu_list) {
6551 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6552
6553 if (pi_test_on(pi_desc) == 1)
6554 kvm_vcpu_kick(vcpu);
6555 }
6556 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6557 }
6558
6559 void vmx_enable_tdp(void)
6560 {
6561 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6562 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6563 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6564 0ull, VMX_EPT_EXECUTABLE_MASK,
6565 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6566 VMX_EPT_RWX_MASK);
6567
6568 ept_set_mmio_spte_mask();
6569 kvm_enable_tdp();
6570 }
6571
6572 static __init int hardware_setup(void)
6573 {
6574 int r = -ENOMEM, i, msr;
6575
6576 rdmsrl_safe(MSR_EFER, &host_efer);
6577
6578 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6579 kvm_define_shared_msr(i, vmx_msr_index[i]);
6580
6581 for (i = 0; i < VMX_BITMAP_NR; i++) {
6582 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6583 if (!vmx_bitmap[i])
6584 goto out;
6585 }
6586
6587 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6588 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6589 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6590
6591 /*
6592 * Allow direct access to the PC debug port (it is often used for I/O
6593 * delays, but the vmexits simply slow things down).
6594 */
6595 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6596 clear_bit(0x80, vmx_io_bitmap_a);
6597
6598 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6599
6600 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6601 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6602
6603 if (setup_vmcs_config(&vmcs_config) < 0) {
6604 r = -EIO;
6605 goto out;
6606 }
6607
6608 if (boot_cpu_has(X86_FEATURE_NX))
6609 kvm_enable_efer_bits(EFER_NX);
6610
6611 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6612 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6613 enable_vpid = 0;
6614
6615 if (!cpu_has_vmx_shadow_vmcs())
6616 enable_shadow_vmcs = 0;
6617 if (enable_shadow_vmcs)
6618 init_vmcs_shadow_fields();
6619
6620 if (!cpu_has_vmx_ept() ||
6621 !cpu_has_vmx_ept_4levels()) {
6622 enable_ept = 0;
6623 enable_unrestricted_guest = 0;
6624 enable_ept_ad_bits = 0;
6625 }
6626
6627 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6628 enable_ept_ad_bits = 0;
6629
6630 if (!cpu_has_vmx_unrestricted_guest())
6631 enable_unrestricted_guest = 0;
6632
6633 if (!cpu_has_vmx_flexpriority())
6634 flexpriority_enabled = 0;
6635
6636 /*
6637 * set_apic_access_page_addr() is used to reload apic access
6638 * page upon invalidation. No need to do anything if not
6639 * using the APIC_ACCESS_ADDR VMCS field.
6640 */
6641 if (!flexpriority_enabled)
6642 kvm_x86_ops->set_apic_access_page_addr = NULL;
6643
6644 if (!cpu_has_vmx_tpr_shadow())
6645 kvm_x86_ops->update_cr8_intercept = NULL;
6646
6647 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6648 kvm_disable_largepages();
6649
6650 if (!cpu_has_vmx_ple())
6651 ple_gap = 0;
6652
6653 if (!cpu_has_vmx_apicv()) {
6654 enable_apicv = 0;
6655 kvm_x86_ops->sync_pir_to_irr = NULL;
6656 }
6657
6658 if (cpu_has_vmx_tsc_scaling()) {
6659 kvm_has_tsc_control = true;
6660 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6661 kvm_tsc_scaling_ratio_frac_bits = 48;
6662 }
6663
6664 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6665 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6666 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6667 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6668 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6669 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6670
6671 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6672 vmx_msr_bitmap_legacy, PAGE_SIZE);
6673 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6674 vmx_msr_bitmap_longmode, PAGE_SIZE);
6675 memcpy(vmx_msr_bitmap_legacy_x2apic,
6676 vmx_msr_bitmap_legacy, PAGE_SIZE);
6677 memcpy(vmx_msr_bitmap_longmode_x2apic,
6678 vmx_msr_bitmap_longmode, PAGE_SIZE);
6679
6680 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6681
6682 for (msr = 0x800; msr <= 0x8ff; msr++) {
6683 if (msr == 0x839 /* TMCCT */)
6684 continue;
6685 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6686 }
6687
6688 /*
6689 * TPR reads and writes can be virtualized even if virtual interrupt
6690 * delivery is not in use.
6691 */
6692 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6693 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6694
6695 /* EOI */
6696 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6697 /* SELF-IPI */
6698 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6699
6700 if (enable_ept)
6701 vmx_enable_tdp();
6702 else
6703 kvm_disable_tdp();
6704
6705 update_ple_window_actual_max();
6706
6707 /*
6708 * Only enable PML when hardware supports PML feature, and both EPT
6709 * and EPT A/D bit features are enabled -- PML depends on them to work.
6710 */
6711 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6712 enable_pml = 0;
6713
6714 if (!enable_pml) {
6715 kvm_x86_ops->slot_enable_log_dirty = NULL;
6716 kvm_x86_ops->slot_disable_log_dirty = NULL;
6717 kvm_x86_ops->flush_log_dirty = NULL;
6718 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6719 }
6720
6721 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6722 u64 vmx_msr;
6723
6724 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6725 cpu_preemption_timer_multi =
6726 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6727 } else {
6728 kvm_x86_ops->set_hv_timer = NULL;
6729 kvm_x86_ops->cancel_hv_timer = NULL;
6730 }
6731
6732 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6733
6734 kvm_mce_cap_supported |= MCG_LMCE_P;
6735
6736 return alloc_kvm_area();
6737
6738 out:
6739 for (i = 0; i < VMX_BITMAP_NR; i++)
6740 free_page((unsigned long)vmx_bitmap[i]);
6741
6742 return r;
6743 }
6744
6745 static __exit void hardware_unsetup(void)
6746 {
6747 int i;
6748
6749 for (i = 0; i < VMX_BITMAP_NR; i++)
6750 free_page((unsigned long)vmx_bitmap[i]);
6751
6752 free_kvm_area();
6753 }
6754
6755 /*
6756 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6757 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6758 */
6759 static int handle_pause(struct kvm_vcpu *vcpu)
6760 {
6761 if (ple_gap)
6762 grow_ple_window(vcpu);
6763
6764 kvm_vcpu_on_spin(vcpu);
6765 return kvm_skip_emulated_instruction(vcpu);
6766 }
6767
6768 static int handle_nop(struct kvm_vcpu *vcpu)
6769 {
6770 return kvm_skip_emulated_instruction(vcpu);
6771 }
6772
6773 static int handle_mwait(struct kvm_vcpu *vcpu)
6774 {
6775 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6776 return handle_nop(vcpu);
6777 }
6778
6779 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6780 {
6781 return 1;
6782 }
6783
6784 static int handle_monitor(struct kvm_vcpu *vcpu)
6785 {
6786 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6787 return handle_nop(vcpu);
6788 }
6789
6790 /*
6791 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6792 * We could reuse a single VMCS for all the L2 guests, but we also want the
6793 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6794 * allows keeping them loaded on the processor, and in the future will allow
6795 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6796 * every entry if they never change.
6797 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6798 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6799 *
6800 * The following functions allocate and free a vmcs02 in this pool.
6801 */
6802
6803 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6804 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6805 {
6806 struct vmcs02_list *item;
6807 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6808 if (item->vmptr == vmx->nested.current_vmptr) {
6809 list_move(&item->list, &vmx->nested.vmcs02_pool);
6810 return &item->vmcs02;
6811 }
6812
6813 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6814 /* Recycle the least recently used VMCS. */
6815 item = list_last_entry(&vmx->nested.vmcs02_pool,
6816 struct vmcs02_list, list);
6817 item->vmptr = vmx->nested.current_vmptr;
6818 list_move(&item->list, &vmx->nested.vmcs02_pool);
6819 return &item->vmcs02;
6820 }
6821
6822 /* Create a new VMCS */
6823 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6824 if (!item)
6825 return NULL;
6826 item->vmcs02.vmcs = alloc_vmcs();
6827 item->vmcs02.shadow_vmcs = NULL;
6828 if (!item->vmcs02.vmcs) {
6829 kfree(item);
6830 return NULL;
6831 }
6832 loaded_vmcs_init(&item->vmcs02);
6833 item->vmptr = vmx->nested.current_vmptr;
6834 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6835 vmx->nested.vmcs02_num++;
6836 return &item->vmcs02;
6837 }
6838
6839 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6840 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6841 {
6842 struct vmcs02_list *item;
6843 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6844 if (item->vmptr == vmptr) {
6845 free_loaded_vmcs(&item->vmcs02);
6846 list_del(&item->list);
6847 kfree(item);
6848 vmx->nested.vmcs02_num--;
6849 return;
6850 }
6851 }
6852
6853 /*
6854 * Free all VMCSs saved for this vcpu, except the one pointed by
6855 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6856 * must be &vmx->vmcs01.
6857 */
6858 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6859 {
6860 struct vmcs02_list *item, *n;
6861
6862 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6863 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6864 /*
6865 * Something will leak if the above WARN triggers. Better than
6866 * a use-after-free.
6867 */
6868 if (vmx->loaded_vmcs == &item->vmcs02)
6869 continue;
6870
6871 free_loaded_vmcs(&item->vmcs02);
6872 list_del(&item->list);
6873 kfree(item);
6874 vmx->nested.vmcs02_num--;
6875 }
6876 }
6877
6878 /*
6879 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6880 * set the success or error code of an emulated VMX instruction, as specified
6881 * by Vol 2B, VMX Instruction Reference, "Conventions".
6882 */
6883 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6884 {
6885 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6886 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6887 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6888 }
6889
6890 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6891 {
6892 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6893 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6894 X86_EFLAGS_SF | X86_EFLAGS_OF))
6895 | X86_EFLAGS_CF);
6896 }
6897
6898 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6899 u32 vm_instruction_error)
6900 {
6901 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6902 /*
6903 * failValid writes the error number to the current VMCS, which
6904 * can't be done there isn't a current VMCS.
6905 */
6906 nested_vmx_failInvalid(vcpu);
6907 return;
6908 }
6909 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6910 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6911 X86_EFLAGS_SF | X86_EFLAGS_OF))
6912 | X86_EFLAGS_ZF);
6913 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6914 /*
6915 * We don't need to force a shadow sync because
6916 * VM_INSTRUCTION_ERROR is not shadowed
6917 */
6918 }
6919
6920 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6921 {
6922 /* TODO: not to reset guest simply here. */
6923 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6924 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6925 }
6926
6927 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6928 {
6929 struct vcpu_vmx *vmx =
6930 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6931
6932 vmx->nested.preemption_timer_expired = true;
6933 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6934 kvm_vcpu_kick(&vmx->vcpu);
6935
6936 return HRTIMER_NORESTART;
6937 }
6938
6939 /*
6940 * Decode the memory-address operand of a vmx instruction, as recorded on an
6941 * exit caused by such an instruction (run by a guest hypervisor).
6942 * On success, returns 0. When the operand is invalid, returns 1 and throws
6943 * #UD or #GP.
6944 */
6945 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6946 unsigned long exit_qualification,
6947 u32 vmx_instruction_info, bool wr, gva_t *ret)
6948 {
6949 gva_t off;
6950 bool exn;
6951 struct kvm_segment s;
6952
6953 /*
6954 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6955 * Execution", on an exit, vmx_instruction_info holds most of the
6956 * addressing components of the operand. Only the displacement part
6957 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6958 * For how an actual address is calculated from all these components,
6959 * refer to Vol. 1, "Operand Addressing".
6960 */
6961 int scaling = vmx_instruction_info & 3;
6962 int addr_size = (vmx_instruction_info >> 7) & 7;
6963 bool is_reg = vmx_instruction_info & (1u << 10);
6964 int seg_reg = (vmx_instruction_info >> 15) & 7;
6965 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6966 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6967 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6968 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6969
6970 if (is_reg) {
6971 kvm_queue_exception(vcpu, UD_VECTOR);
6972 return 1;
6973 }
6974
6975 /* Addr = segment_base + offset */
6976 /* offset = base + [index * scale] + displacement */
6977 off = exit_qualification; /* holds the displacement */
6978 if (base_is_valid)
6979 off += kvm_register_read(vcpu, base_reg);
6980 if (index_is_valid)
6981 off += kvm_register_read(vcpu, index_reg)<<scaling;
6982 vmx_get_segment(vcpu, &s, seg_reg);
6983 *ret = s.base + off;
6984
6985 if (addr_size == 1) /* 32 bit */
6986 *ret &= 0xffffffff;
6987
6988 /* Checks for #GP/#SS exceptions. */
6989 exn = false;
6990 if (is_long_mode(vcpu)) {
6991 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6992 * non-canonical form. This is the only check on the memory
6993 * destination for long mode!
6994 */
6995 exn = is_noncanonical_address(*ret);
6996 } else if (is_protmode(vcpu)) {
6997 /* Protected mode: apply checks for segment validity in the
6998 * following order:
6999 * - segment type check (#GP(0) may be thrown)
7000 * - usability check (#GP(0)/#SS(0))
7001 * - limit check (#GP(0)/#SS(0))
7002 */
7003 if (wr)
7004 /* #GP(0) if the destination operand is located in a
7005 * read-only data segment or any code segment.
7006 */
7007 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7008 else
7009 /* #GP(0) if the source operand is located in an
7010 * execute-only code segment
7011 */
7012 exn = ((s.type & 0xa) == 8);
7013 if (exn) {
7014 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7015 return 1;
7016 }
7017 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7018 */
7019 exn = (s.unusable != 0);
7020 /* Protected mode: #GP(0)/#SS(0) if the memory
7021 * operand is outside the segment limit.
7022 */
7023 exn = exn || (off + sizeof(u64) > s.limit);
7024 }
7025 if (exn) {
7026 kvm_queue_exception_e(vcpu,
7027 seg_reg == VCPU_SREG_SS ?
7028 SS_VECTOR : GP_VECTOR,
7029 0);
7030 return 1;
7031 }
7032
7033 return 0;
7034 }
7035
7036 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7037 {
7038 gva_t gva;
7039 struct x86_exception e;
7040
7041 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7042 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7043 return 1;
7044
7045 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7046 sizeof(*vmpointer), &e)) {
7047 kvm_inject_page_fault(vcpu, &e);
7048 return 1;
7049 }
7050
7051 return 0;
7052 }
7053
7054 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7055 {
7056 struct vcpu_vmx *vmx = to_vmx(vcpu);
7057 struct vmcs *shadow_vmcs;
7058
7059 if (cpu_has_vmx_msr_bitmap()) {
7060 vmx->nested.msr_bitmap =
7061 (unsigned long *)__get_free_page(GFP_KERNEL);
7062 if (!vmx->nested.msr_bitmap)
7063 goto out_msr_bitmap;
7064 }
7065
7066 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7067 if (!vmx->nested.cached_vmcs12)
7068 goto out_cached_vmcs12;
7069
7070 if (enable_shadow_vmcs) {
7071 shadow_vmcs = alloc_vmcs();
7072 if (!shadow_vmcs)
7073 goto out_shadow_vmcs;
7074 /* mark vmcs as shadow */
7075 shadow_vmcs->revision_id |= (1u << 31);
7076 /* init shadow vmcs */
7077 vmcs_clear(shadow_vmcs);
7078 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7079 }
7080
7081 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7082 vmx->nested.vmcs02_num = 0;
7083
7084 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7085 HRTIMER_MODE_REL_PINNED);
7086 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7087
7088 vmx->nested.vmxon = true;
7089 return 0;
7090
7091 out_shadow_vmcs:
7092 kfree(vmx->nested.cached_vmcs12);
7093
7094 out_cached_vmcs12:
7095 free_page((unsigned long)vmx->nested.msr_bitmap);
7096
7097 out_msr_bitmap:
7098 return -ENOMEM;
7099 }
7100
7101 /*
7102 * Emulate the VMXON instruction.
7103 * Currently, we just remember that VMX is active, and do not save or even
7104 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7105 * do not currently need to store anything in that guest-allocated memory
7106 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7107 * argument is different from the VMXON pointer (which the spec says they do).
7108 */
7109 static int handle_vmon(struct kvm_vcpu *vcpu)
7110 {
7111 int ret;
7112 gpa_t vmptr;
7113 struct page *page;
7114 struct vcpu_vmx *vmx = to_vmx(vcpu);
7115 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7116 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7117
7118 /*
7119 * The Intel VMX Instruction Reference lists a bunch of bits that are
7120 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7121 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7122 * Otherwise, we should fail with #UD. But most faulting conditions
7123 * have already been checked by hardware, prior to the VM-exit for
7124 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7125 * that bit set to 1 in non-root mode.
7126 */
7127 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7128 kvm_queue_exception(vcpu, UD_VECTOR);
7129 return 1;
7130 }
7131
7132 if (vmx->nested.vmxon) {
7133 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7134 return kvm_skip_emulated_instruction(vcpu);
7135 }
7136
7137 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7138 != VMXON_NEEDED_FEATURES) {
7139 kvm_inject_gp(vcpu, 0);
7140 return 1;
7141 }
7142
7143 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7144 return 1;
7145
7146 /*
7147 * SDM 3: 24.11.5
7148 * The first 4 bytes of VMXON region contain the supported
7149 * VMCS revision identifier
7150 *
7151 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7152 * which replaces physical address width with 32
7153 */
7154 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7155 nested_vmx_failInvalid(vcpu);
7156 return kvm_skip_emulated_instruction(vcpu);
7157 }
7158
7159 page = nested_get_page(vcpu, vmptr);
7160 if (page == NULL) {
7161 nested_vmx_failInvalid(vcpu);
7162 return kvm_skip_emulated_instruction(vcpu);
7163 }
7164 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7165 kunmap(page);
7166 nested_release_page_clean(page);
7167 nested_vmx_failInvalid(vcpu);
7168 return kvm_skip_emulated_instruction(vcpu);
7169 }
7170 kunmap(page);
7171 nested_release_page_clean(page);
7172
7173 vmx->nested.vmxon_ptr = vmptr;
7174 ret = enter_vmx_operation(vcpu);
7175 if (ret)
7176 return ret;
7177
7178 nested_vmx_succeed(vcpu);
7179 return kvm_skip_emulated_instruction(vcpu);
7180 }
7181
7182 /*
7183 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7184 * for running VMX instructions (except VMXON, whose prerequisites are
7185 * slightly different). It also specifies what exception to inject otherwise.
7186 * Note that many of these exceptions have priority over VM exits, so they
7187 * don't have to be checked again here.
7188 */
7189 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7190 {
7191 if (!to_vmx(vcpu)->nested.vmxon) {
7192 kvm_queue_exception(vcpu, UD_VECTOR);
7193 return 0;
7194 }
7195 return 1;
7196 }
7197
7198 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7199 {
7200 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7201 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7202 }
7203
7204 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7205 {
7206 if (vmx->nested.current_vmptr == -1ull)
7207 return;
7208
7209 if (enable_shadow_vmcs) {
7210 /* copy to memory all shadowed fields in case
7211 they were modified */
7212 copy_shadow_to_vmcs12(vmx);
7213 vmx->nested.sync_shadow_vmcs = false;
7214 vmx_disable_shadow_vmcs(vmx);
7215 }
7216 vmx->nested.posted_intr_nv = -1;
7217
7218 /* Flush VMCS12 to guest memory */
7219 kvm_vcpu_write_guest_page(&vmx->vcpu,
7220 vmx->nested.current_vmptr >> PAGE_SHIFT,
7221 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7222
7223 vmx->nested.current_vmptr = -1ull;
7224 }
7225
7226 /*
7227 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7228 * just stops using VMX.
7229 */
7230 static void free_nested(struct vcpu_vmx *vmx)
7231 {
7232 if (!vmx->nested.vmxon)
7233 return;
7234
7235 vmx->nested.vmxon = false;
7236 free_vpid(vmx->nested.vpid02);
7237 vmx->nested.posted_intr_nv = -1;
7238 vmx->nested.current_vmptr = -1ull;
7239 if (vmx->nested.msr_bitmap) {
7240 free_page((unsigned long)vmx->nested.msr_bitmap);
7241 vmx->nested.msr_bitmap = NULL;
7242 }
7243 if (enable_shadow_vmcs) {
7244 vmx_disable_shadow_vmcs(vmx);
7245 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7246 free_vmcs(vmx->vmcs01.shadow_vmcs);
7247 vmx->vmcs01.shadow_vmcs = NULL;
7248 }
7249 kfree(vmx->nested.cached_vmcs12);
7250 /* Unpin physical memory we referred to in current vmcs02 */
7251 if (vmx->nested.apic_access_page) {
7252 nested_release_page(vmx->nested.apic_access_page);
7253 vmx->nested.apic_access_page = NULL;
7254 }
7255 if (vmx->nested.virtual_apic_page) {
7256 nested_release_page(vmx->nested.virtual_apic_page);
7257 vmx->nested.virtual_apic_page = NULL;
7258 }
7259 if (vmx->nested.pi_desc_page) {
7260 kunmap(vmx->nested.pi_desc_page);
7261 nested_release_page(vmx->nested.pi_desc_page);
7262 vmx->nested.pi_desc_page = NULL;
7263 vmx->nested.pi_desc = NULL;
7264 }
7265
7266 nested_free_all_saved_vmcss(vmx);
7267 }
7268
7269 /* Emulate the VMXOFF instruction */
7270 static int handle_vmoff(struct kvm_vcpu *vcpu)
7271 {
7272 if (!nested_vmx_check_permission(vcpu))
7273 return 1;
7274 free_nested(to_vmx(vcpu));
7275 nested_vmx_succeed(vcpu);
7276 return kvm_skip_emulated_instruction(vcpu);
7277 }
7278
7279 /* Emulate the VMCLEAR instruction */
7280 static int handle_vmclear(struct kvm_vcpu *vcpu)
7281 {
7282 struct vcpu_vmx *vmx = to_vmx(vcpu);
7283 u32 zero = 0;
7284 gpa_t vmptr;
7285
7286 if (!nested_vmx_check_permission(vcpu))
7287 return 1;
7288
7289 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7290 return 1;
7291
7292 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7293 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7294 return kvm_skip_emulated_instruction(vcpu);
7295 }
7296
7297 if (vmptr == vmx->nested.vmxon_ptr) {
7298 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7299 return kvm_skip_emulated_instruction(vcpu);
7300 }
7301
7302 if (vmptr == vmx->nested.current_vmptr)
7303 nested_release_vmcs12(vmx);
7304
7305 kvm_vcpu_write_guest(vcpu,
7306 vmptr + offsetof(struct vmcs12, launch_state),
7307 &zero, sizeof(zero));
7308
7309 nested_free_vmcs02(vmx, vmptr);
7310
7311 nested_vmx_succeed(vcpu);
7312 return kvm_skip_emulated_instruction(vcpu);
7313 }
7314
7315 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7316
7317 /* Emulate the VMLAUNCH instruction */
7318 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7319 {
7320 return nested_vmx_run(vcpu, true);
7321 }
7322
7323 /* Emulate the VMRESUME instruction */
7324 static int handle_vmresume(struct kvm_vcpu *vcpu)
7325 {
7326
7327 return nested_vmx_run(vcpu, false);
7328 }
7329
7330 /*
7331 * Read a vmcs12 field. Since these can have varying lengths and we return
7332 * one type, we chose the biggest type (u64) and zero-extend the return value
7333 * to that size. Note that the caller, handle_vmread, might need to use only
7334 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7335 * 64-bit fields are to be returned).
7336 */
7337 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7338 unsigned long field, u64 *ret)
7339 {
7340 short offset = vmcs_field_to_offset(field);
7341 char *p;
7342
7343 if (offset < 0)
7344 return offset;
7345
7346 p = ((char *)(get_vmcs12(vcpu))) + offset;
7347
7348 switch (vmcs_field_type(field)) {
7349 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7350 *ret = *((natural_width *)p);
7351 return 0;
7352 case VMCS_FIELD_TYPE_U16:
7353 *ret = *((u16 *)p);
7354 return 0;
7355 case VMCS_FIELD_TYPE_U32:
7356 *ret = *((u32 *)p);
7357 return 0;
7358 case VMCS_FIELD_TYPE_U64:
7359 *ret = *((u64 *)p);
7360 return 0;
7361 default:
7362 WARN_ON(1);
7363 return -ENOENT;
7364 }
7365 }
7366
7367
7368 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7369 unsigned long field, u64 field_value){
7370 short offset = vmcs_field_to_offset(field);
7371 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7372 if (offset < 0)
7373 return offset;
7374
7375 switch (vmcs_field_type(field)) {
7376 case VMCS_FIELD_TYPE_U16:
7377 *(u16 *)p = field_value;
7378 return 0;
7379 case VMCS_FIELD_TYPE_U32:
7380 *(u32 *)p = field_value;
7381 return 0;
7382 case VMCS_FIELD_TYPE_U64:
7383 *(u64 *)p = field_value;
7384 return 0;
7385 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7386 *(natural_width *)p = field_value;
7387 return 0;
7388 default:
7389 WARN_ON(1);
7390 return -ENOENT;
7391 }
7392
7393 }
7394
7395 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7396 {
7397 int i;
7398 unsigned long field;
7399 u64 field_value;
7400 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7401 const unsigned long *fields = shadow_read_write_fields;
7402 const int num_fields = max_shadow_read_write_fields;
7403
7404 preempt_disable();
7405
7406 vmcs_load(shadow_vmcs);
7407
7408 for (i = 0; i < num_fields; i++) {
7409 field = fields[i];
7410 switch (vmcs_field_type(field)) {
7411 case VMCS_FIELD_TYPE_U16:
7412 field_value = vmcs_read16(field);
7413 break;
7414 case VMCS_FIELD_TYPE_U32:
7415 field_value = vmcs_read32(field);
7416 break;
7417 case VMCS_FIELD_TYPE_U64:
7418 field_value = vmcs_read64(field);
7419 break;
7420 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7421 field_value = vmcs_readl(field);
7422 break;
7423 default:
7424 WARN_ON(1);
7425 continue;
7426 }
7427 vmcs12_write_any(&vmx->vcpu, field, field_value);
7428 }
7429
7430 vmcs_clear(shadow_vmcs);
7431 vmcs_load(vmx->loaded_vmcs->vmcs);
7432
7433 preempt_enable();
7434 }
7435
7436 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7437 {
7438 const unsigned long *fields[] = {
7439 shadow_read_write_fields,
7440 shadow_read_only_fields
7441 };
7442 const int max_fields[] = {
7443 max_shadow_read_write_fields,
7444 max_shadow_read_only_fields
7445 };
7446 int i, q;
7447 unsigned long field;
7448 u64 field_value = 0;
7449 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7450
7451 vmcs_load(shadow_vmcs);
7452
7453 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7454 for (i = 0; i < max_fields[q]; i++) {
7455 field = fields[q][i];
7456 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7457
7458 switch (vmcs_field_type(field)) {
7459 case VMCS_FIELD_TYPE_U16:
7460 vmcs_write16(field, (u16)field_value);
7461 break;
7462 case VMCS_FIELD_TYPE_U32:
7463 vmcs_write32(field, (u32)field_value);
7464 break;
7465 case VMCS_FIELD_TYPE_U64:
7466 vmcs_write64(field, (u64)field_value);
7467 break;
7468 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7469 vmcs_writel(field, (long)field_value);
7470 break;
7471 default:
7472 WARN_ON(1);
7473 break;
7474 }
7475 }
7476 }
7477
7478 vmcs_clear(shadow_vmcs);
7479 vmcs_load(vmx->loaded_vmcs->vmcs);
7480 }
7481
7482 /*
7483 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7484 * used before) all generate the same failure when it is missing.
7485 */
7486 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7487 {
7488 struct vcpu_vmx *vmx = to_vmx(vcpu);
7489 if (vmx->nested.current_vmptr == -1ull) {
7490 nested_vmx_failInvalid(vcpu);
7491 return 0;
7492 }
7493 return 1;
7494 }
7495
7496 static int handle_vmread(struct kvm_vcpu *vcpu)
7497 {
7498 unsigned long field;
7499 u64 field_value;
7500 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7501 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7502 gva_t gva = 0;
7503
7504 if (!nested_vmx_check_permission(vcpu))
7505 return 1;
7506
7507 if (!nested_vmx_check_vmcs12(vcpu))
7508 return kvm_skip_emulated_instruction(vcpu);
7509
7510 /* Decode instruction info and find the field to read */
7511 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7512 /* Read the field, zero-extended to a u64 field_value */
7513 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7514 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7515 return kvm_skip_emulated_instruction(vcpu);
7516 }
7517 /*
7518 * Now copy part of this value to register or memory, as requested.
7519 * Note that the number of bits actually copied is 32 or 64 depending
7520 * on the guest's mode (32 or 64 bit), not on the given field's length.
7521 */
7522 if (vmx_instruction_info & (1u << 10)) {
7523 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7524 field_value);
7525 } else {
7526 if (get_vmx_mem_address(vcpu, exit_qualification,
7527 vmx_instruction_info, true, &gva))
7528 return 1;
7529 /* _system ok, as hardware has verified cpl=0 */
7530 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7531 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7532 }
7533
7534 nested_vmx_succeed(vcpu);
7535 return kvm_skip_emulated_instruction(vcpu);
7536 }
7537
7538
7539 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7540 {
7541 unsigned long field;
7542 gva_t gva;
7543 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7544 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7545 /* The value to write might be 32 or 64 bits, depending on L1's long
7546 * mode, and eventually we need to write that into a field of several
7547 * possible lengths. The code below first zero-extends the value to 64
7548 * bit (field_value), and then copies only the appropriate number of
7549 * bits into the vmcs12 field.
7550 */
7551 u64 field_value = 0;
7552 struct x86_exception e;
7553
7554 if (!nested_vmx_check_permission(vcpu))
7555 return 1;
7556
7557 if (!nested_vmx_check_vmcs12(vcpu))
7558 return kvm_skip_emulated_instruction(vcpu);
7559
7560 if (vmx_instruction_info & (1u << 10))
7561 field_value = kvm_register_readl(vcpu,
7562 (((vmx_instruction_info) >> 3) & 0xf));
7563 else {
7564 if (get_vmx_mem_address(vcpu, exit_qualification,
7565 vmx_instruction_info, false, &gva))
7566 return 1;
7567 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7568 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7569 kvm_inject_page_fault(vcpu, &e);
7570 return 1;
7571 }
7572 }
7573
7574
7575 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7576 if (vmcs_field_readonly(field)) {
7577 nested_vmx_failValid(vcpu,
7578 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7579 return kvm_skip_emulated_instruction(vcpu);
7580 }
7581
7582 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7583 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7584 return kvm_skip_emulated_instruction(vcpu);
7585 }
7586
7587 nested_vmx_succeed(vcpu);
7588 return kvm_skip_emulated_instruction(vcpu);
7589 }
7590
7591 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7592 {
7593 vmx->nested.current_vmptr = vmptr;
7594 if (enable_shadow_vmcs) {
7595 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7596 SECONDARY_EXEC_SHADOW_VMCS);
7597 vmcs_write64(VMCS_LINK_POINTER,
7598 __pa(vmx->vmcs01.shadow_vmcs));
7599 vmx->nested.sync_shadow_vmcs = true;
7600 }
7601 }
7602
7603 /* Emulate the VMPTRLD instruction */
7604 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7605 {
7606 struct vcpu_vmx *vmx = to_vmx(vcpu);
7607 gpa_t vmptr;
7608
7609 if (!nested_vmx_check_permission(vcpu))
7610 return 1;
7611
7612 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7613 return 1;
7614
7615 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7616 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7617 return kvm_skip_emulated_instruction(vcpu);
7618 }
7619
7620 if (vmptr == vmx->nested.vmxon_ptr) {
7621 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7622 return kvm_skip_emulated_instruction(vcpu);
7623 }
7624
7625 if (vmx->nested.current_vmptr != vmptr) {
7626 struct vmcs12 *new_vmcs12;
7627 struct page *page;
7628 page = nested_get_page(vcpu, vmptr);
7629 if (page == NULL) {
7630 nested_vmx_failInvalid(vcpu);
7631 return kvm_skip_emulated_instruction(vcpu);
7632 }
7633 new_vmcs12 = kmap(page);
7634 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7635 kunmap(page);
7636 nested_release_page_clean(page);
7637 nested_vmx_failValid(vcpu,
7638 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7639 return kvm_skip_emulated_instruction(vcpu);
7640 }
7641
7642 nested_release_vmcs12(vmx);
7643 /*
7644 * Load VMCS12 from guest memory since it is not already
7645 * cached.
7646 */
7647 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7648 kunmap(page);
7649 nested_release_page_clean(page);
7650
7651 set_current_vmptr(vmx, vmptr);
7652 }
7653
7654 nested_vmx_succeed(vcpu);
7655 return kvm_skip_emulated_instruction(vcpu);
7656 }
7657
7658 /* Emulate the VMPTRST instruction */
7659 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7660 {
7661 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7662 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7663 gva_t vmcs_gva;
7664 struct x86_exception e;
7665
7666 if (!nested_vmx_check_permission(vcpu))
7667 return 1;
7668
7669 if (get_vmx_mem_address(vcpu, exit_qualification,
7670 vmx_instruction_info, true, &vmcs_gva))
7671 return 1;
7672 /* ok to use *_system, as hardware has verified cpl=0 */
7673 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7674 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7675 sizeof(u64), &e)) {
7676 kvm_inject_page_fault(vcpu, &e);
7677 return 1;
7678 }
7679 nested_vmx_succeed(vcpu);
7680 return kvm_skip_emulated_instruction(vcpu);
7681 }
7682
7683 /* Emulate the INVEPT instruction */
7684 static int handle_invept(struct kvm_vcpu *vcpu)
7685 {
7686 struct vcpu_vmx *vmx = to_vmx(vcpu);
7687 u32 vmx_instruction_info, types;
7688 unsigned long type;
7689 gva_t gva;
7690 struct x86_exception e;
7691 struct {
7692 u64 eptp, gpa;
7693 } operand;
7694
7695 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7696 SECONDARY_EXEC_ENABLE_EPT) ||
7697 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7698 kvm_queue_exception(vcpu, UD_VECTOR);
7699 return 1;
7700 }
7701
7702 if (!nested_vmx_check_permission(vcpu))
7703 return 1;
7704
7705 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7706 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7707
7708 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7709
7710 if (type >= 32 || !(types & (1 << type))) {
7711 nested_vmx_failValid(vcpu,
7712 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7713 return kvm_skip_emulated_instruction(vcpu);
7714 }
7715
7716 /* According to the Intel VMX instruction reference, the memory
7717 * operand is read even if it isn't needed (e.g., for type==global)
7718 */
7719 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7720 vmx_instruction_info, false, &gva))
7721 return 1;
7722 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7723 sizeof(operand), &e)) {
7724 kvm_inject_page_fault(vcpu, &e);
7725 return 1;
7726 }
7727
7728 switch (type) {
7729 case VMX_EPT_EXTENT_GLOBAL:
7730 /*
7731 * TODO: track mappings and invalidate
7732 * single context requests appropriately
7733 */
7734 case VMX_EPT_EXTENT_CONTEXT:
7735 kvm_mmu_sync_roots(vcpu);
7736 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7737 nested_vmx_succeed(vcpu);
7738 break;
7739 default:
7740 BUG_ON(1);
7741 break;
7742 }
7743
7744 return kvm_skip_emulated_instruction(vcpu);
7745 }
7746
7747 static int handle_invvpid(struct kvm_vcpu *vcpu)
7748 {
7749 struct vcpu_vmx *vmx = to_vmx(vcpu);
7750 u32 vmx_instruction_info;
7751 unsigned long type, types;
7752 gva_t gva;
7753 struct x86_exception e;
7754 struct {
7755 u64 vpid;
7756 u64 gla;
7757 } operand;
7758
7759 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7760 SECONDARY_EXEC_ENABLE_VPID) ||
7761 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7762 kvm_queue_exception(vcpu, UD_VECTOR);
7763 return 1;
7764 }
7765
7766 if (!nested_vmx_check_permission(vcpu))
7767 return 1;
7768
7769 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7770 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7771
7772 types = (vmx->nested.nested_vmx_vpid_caps &
7773 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7774
7775 if (type >= 32 || !(types & (1 << type))) {
7776 nested_vmx_failValid(vcpu,
7777 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7778 return kvm_skip_emulated_instruction(vcpu);
7779 }
7780
7781 /* according to the intel vmx instruction reference, the memory
7782 * operand is read even if it isn't needed (e.g., for type==global)
7783 */
7784 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7785 vmx_instruction_info, false, &gva))
7786 return 1;
7787 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7788 sizeof(operand), &e)) {
7789 kvm_inject_page_fault(vcpu, &e);
7790 return 1;
7791 }
7792 if (operand.vpid >> 16) {
7793 nested_vmx_failValid(vcpu,
7794 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7795 return kvm_skip_emulated_instruction(vcpu);
7796 }
7797
7798 switch (type) {
7799 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7800 if (is_noncanonical_address(operand.gla)) {
7801 nested_vmx_failValid(vcpu,
7802 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7803 return kvm_skip_emulated_instruction(vcpu);
7804 }
7805 /* fall through */
7806 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7807 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7808 if (!operand.vpid) {
7809 nested_vmx_failValid(vcpu,
7810 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7811 return kvm_skip_emulated_instruction(vcpu);
7812 }
7813 break;
7814 case VMX_VPID_EXTENT_ALL_CONTEXT:
7815 break;
7816 default:
7817 WARN_ON_ONCE(1);
7818 return kvm_skip_emulated_instruction(vcpu);
7819 }
7820
7821 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7822 nested_vmx_succeed(vcpu);
7823
7824 return kvm_skip_emulated_instruction(vcpu);
7825 }
7826
7827 static int handle_pml_full(struct kvm_vcpu *vcpu)
7828 {
7829 unsigned long exit_qualification;
7830
7831 trace_kvm_pml_full(vcpu->vcpu_id);
7832
7833 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7834
7835 /*
7836 * PML buffer FULL happened while executing iret from NMI,
7837 * "blocked by NMI" bit has to be set before next VM entry.
7838 */
7839 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7840 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7841 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7842 GUEST_INTR_STATE_NMI);
7843
7844 /*
7845 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7846 * here.., and there's no userspace involvement needed for PML.
7847 */
7848 return 1;
7849 }
7850
7851 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7852 {
7853 kvm_lapic_expired_hv_timer(vcpu);
7854 return 1;
7855 }
7856
7857 /*
7858 * The exit handlers return 1 if the exit was handled fully and guest execution
7859 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7860 * to be done to userspace and return 0.
7861 */
7862 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7863 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7864 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7865 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7866 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7867 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7868 [EXIT_REASON_CR_ACCESS] = handle_cr,
7869 [EXIT_REASON_DR_ACCESS] = handle_dr,
7870 [EXIT_REASON_CPUID] = handle_cpuid,
7871 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7872 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7873 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7874 [EXIT_REASON_HLT] = handle_halt,
7875 [EXIT_REASON_INVD] = handle_invd,
7876 [EXIT_REASON_INVLPG] = handle_invlpg,
7877 [EXIT_REASON_RDPMC] = handle_rdpmc,
7878 [EXIT_REASON_VMCALL] = handle_vmcall,
7879 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7880 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7881 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7882 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7883 [EXIT_REASON_VMREAD] = handle_vmread,
7884 [EXIT_REASON_VMRESUME] = handle_vmresume,
7885 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7886 [EXIT_REASON_VMOFF] = handle_vmoff,
7887 [EXIT_REASON_VMON] = handle_vmon,
7888 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7889 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7890 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7891 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7892 [EXIT_REASON_WBINVD] = handle_wbinvd,
7893 [EXIT_REASON_XSETBV] = handle_xsetbv,
7894 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7895 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7896 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7897 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7898 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7899 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7900 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7901 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7902 [EXIT_REASON_INVEPT] = handle_invept,
7903 [EXIT_REASON_INVVPID] = handle_invvpid,
7904 [EXIT_REASON_XSAVES] = handle_xsaves,
7905 [EXIT_REASON_XRSTORS] = handle_xrstors,
7906 [EXIT_REASON_PML_FULL] = handle_pml_full,
7907 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7908 };
7909
7910 static const int kvm_vmx_max_exit_handlers =
7911 ARRAY_SIZE(kvm_vmx_exit_handlers);
7912
7913 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7914 struct vmcs12 *vmcs12)
7915 {
7916 unsigned long exit_qualification;
7917 gpa_t bitmap, last_bitmap;
7918 unsigned int port;
7919 int size;
7920 u8 b;
7921
7922 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7923 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7924
7925 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7926
7927 port = exit_qualification >> 16;
7928 size = (exit_qualification & 7) + 1;
7929
7930 last_bitmap = (gpa_t)-1;
7931 b = -1;
7932
7933 while (size > 0) {
7934 if (port < 0x8000)
7935 bitmap = vmcs12->io_bitmap_a;
7936 else if (port < 0x10000)
7937 bitmap = vmcs12->io_bitmap_b;
7938 else
7939 return true;
7940 bitmap += (port & 0x7fff) / 8;
7941
7942 if (last_bitmap != bitmap)
7943 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7944 return true;
7945 if (b & (1 << (port & 7)))
7946 return true;
7947
7948 port++;
7949 size--;
7950 last_bitmap = bitmap;
7951 }
7952
7953 return false;
7954 }
7955
7956 /*
7957 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7958 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7959 * disinterest in the current event (read or write a specific MSR) by using an
7960 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7961 */
7962 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7963 struct vmcs12 *vmcs12, u32 exit_reason)
7964 {
7965 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7966 gpa_t bitmap;
7967
7968 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7969 return true;
7970
7971 /*
7972 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7973 * for the four combinations of read/write and low/high MSR numbers.
7974 * First we need to figure out which of the four to use:
7975 */
7976 bitmap = vmcs12->msr_bitmap;
7977 if (exit_reason == EXIT_REASON_MSR_WRITE)
7978 bitmap += 2048;
7979 if (msr_index >= 0xc0000000) {
7980 msr_index -= 0xc0000000;
7981 bitmap += 1024;
7982 }
7983
7984 /* Then read the msr_index'th bit from this bitmap: */
7985 if (msr_index < 1024*8) {
7986 unsigned char b;
7987 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7988 return true;
7989 return 1 & (b >> (msr_index & 7));
7990 } else
7991 return true; /* let L1 handle the wrong parameter */
7992 }
7993
7994 /*
7995 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7996 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7997 * intercept (via guest_host_mask etc.) the current event.
7998 */
7999 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8000 struct vmcs12 *vmcs12)
8001 {
8002 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8003 int cr = exit_qualification & 15;
8004 int reg;
8005 unsigned long val;
8006
8007 switch ((exit_qualification >> 4) & 3) {
8008 case 0: /* mov to cr */
8009 reg = (exit_qualification >> 8) & 15;
8010 val = kvm_register_readl(vcpu, reg);
8011 switch (cr) {
8012 case 0:
8013 if (vmcs12->cr0_guest_host_mask &
8014 (val ^ vmcs12->cr0_read_shadow))
8015 return true;
8016 break;
8017 case 3:
8018 if ((vmcs12->cr3_target_count >= 1 &&
8019 vmcs12->cr3_target_value0 == val) ||
8020 (vmcs12->cr3_target_count >= 2 &&
8021 vmcs12->cr3_target_value1 == val) ||
8022 (vmcs12->cr3_target_count >= 3 &&
8023 vmcs12->cr3_target_value2 == val) ||
8024 (vmcs12->cr3_target_count >= 4 &&
8025 vmcs12->cr3_target_value3 == val))
8026 return false;
8027 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8028 return true;
8029 break;
8030 case 4:
8031 if (vmcs12->cr4_guest_host_mask &
8032 (vmcs12->cr4_read_shadow ^ val))
8033 return true;
8034 break;
8035 case 8:
8036 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8037 return true;
8038 break;
8039 }
8040 break;
8041 case 2: /* clts */
8042 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8043 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8044 return true;
8045 break;
8046 case 1: /* mov from cr */
8047 switch (cr) {
8048 case 3:
8049 if (vmcs12->cpu_based_vm_exec_control &
8050 CPU_BASED_CR3_STORE_EXITING)
8051 return true;
8052 break;
8053 case 8:
8054 if (vmcs12->cpu_based_vm_exec_control &
8055 CPU_BASED_CR8_STORE_EXITING)
8056 return true;
8057 break;
8058 }
8059 break;
8060 case 3: /* lmsw */
8061 /*
8062 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8063 * cr0. Other attempted changes are ignored, with no exit.
8064 */
8065 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8066 if (vmcs12->cr0_guest_host_mask & 0xe &
8067 (val ^ vmcs12->cr0_read_shadow))
8068 return true;
8069 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8070 !(vmcs12->cr0_read_shadow & 0x1) &&
8071 (val & 0x1))
8072 return true;
8073 break;
8074 }
8075 return false;
8076 }
8077
8078 /*
8079 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8080 * should handle it ourselves in L0 (and then continue L2). Only call this
8081 * when in is_guest_mode (L2).
8082 */
8083 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8084 {
8085 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8086 struct vcpu_vmx *vmx = to_vmx(vcpu);
8087 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8088
8089 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8090 vmcs_readl(EXIT_QUALIFICATION),
8091 vmx->idt_vectoring_info,
8092 intr_info,
8093 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8094 KVM_ISA_VMX);
8095
8096 /*
8097 * The host physical addresses of some pages of guest memory
8098 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8099 * may write to these pages via their host physical address while
8100 * L2 is running, bypassing any address-translation-based dirty
8101 * tracking (e.g. EPT write protection).
8102 *
8103 * Mark them dirty on every exit from L2 to prevent them from
8104 * getting out of sync with dirty tracking.
8105 */
8106 nested_mark_vmcs12_pages_dirty(vcpu);
8107
8108 if (vmx->nested.nested_run_pending)
8109 return false;
8110
8111 if (unlikely(vmx->fail)) {
8112 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8113 vmcs_read32(VM_INSTRUCTION_ERROR));
8114 return true;
8115 }
8116
8117 switch (exit_reason) {
8118 case EXIT_REASON_EXCEPTION_NMI:
8119 if (is_nmi(intr_info))
8120 return false;
8121 else if (is_page_fault(intr_info))
8122 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8123 else if (is_no_device(intr_info) &&
8124 !(vmcs12->guest_cr0 & X86_CR0_TS))
8125 return false;
8126 else if (is_debug(intr_info) &&
8127 vcpu->guest_debug &
8128 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8129 return false;
8130 else if (is_breakpoint(intr_info) &&
8131 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8132 return false;
8133 return vmcs12->exception_bitmap &
8134 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8135 case EXIT_REASON_EXTERNAL_INTERRUPT:
8136 return false;
8137 case EXIT_REASON_TRIPLE_FAULT:
8138 return true;
8139 case EXIT_REASON_PENDING_INTERRUPT:
8140 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8141 case EXIT_REASON_NMI_WINDOW:
8142 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8143 case EXIT_REASON_TASK_SWITCH:
8144 return true;
8145 case EXIT_REASON_CPUID:
8146 return true;
8147 case EXIT_REASON_HLT:
8148 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8149 case EXIT_REASON_INVD:
8150 return true;
8151 case EXIT_REASON_INVLPG:
8152 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8153 case EXIT_REASON_RDPMC:
8154 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8155 case EXIT_REASON_RDRAND:
8156 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8157 case EXIT_REASON_RDSEED:
8158 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8159 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8160 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8161 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8162 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8163 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8164 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8165 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8166 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8167 /*
8168 * VMX instructions trap unconditionally. This allows L1 to
8169 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8170 */
8171 return true;
8172 case EXIT_REASON_CR_ACCESS:
8173 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8174 case EXIT_REASON_DR_ACCESS:
8175 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8176 case EXIT_REASON_IO_INSTRUCTION:
8177 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8178 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8179 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8180 case EXIT_REASON_MSR_READ:
8181 case EXIT_REASON_MSR_WRITE:
8182 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8183 case EXIT_REASON_INVALID_STATE:
8184 return true;
8185 case EXIT_REASON_MWAIT_INSTRUCTION:
8186 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8187 case EXIT_REASON_MONITOR_TRAP_FLAG:
8188 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8189 case EXIT_REASON_MONITOR_INSTRUCTION:
8190 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8191 case EXIT_REASON_PAUSE_INSTRUCTION:
8192 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8193 nested_cpu_has2(vmcs12,
8194 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8195 case EXIT_REASON_MCE_DURING_VMENTRY:
8196 return false;
8197 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8198 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8199 case EXIT_REASON_APIC_ACCESS:
8200 return nested_cpu_has2(vmcs12,
8201 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8202 case EXIT_REASON_APIC_WRITE:
8203 case EXIT_REASON_EOI_INDUCED:
8204 /* apic_write and eoi_induced should exit unconditionally. */
8205 return true;
8206 case EXIT_REASON_EPT_VIOLATION:
8207 /*
8208 * L0 always deals with the EPT violation. If nested EPT is
8209 * used, and the nested mmu code discovers that the address is
8210 * missing in the guest EPT table (EPT12), the EPT violation
8211 * will be injected with nested_ept_inject_page_fault()
8212 */
8213 return false;
8214 case EXIT_REASON_EPT_MISCONFIG:
8215 /*
8216 * L2 never uses directly L1's EPT, but rather L0's own EPT
8217 * table (shadow on EPT) or a merged EPT table that L0 built
8218 * (EPT on EPT). So any problems with the structure of the
8219 * table is L0's fault.
8220 */
8221 return false;
8222 case EXIT_REASON_WBINVD:
8223 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8224 case EXIT_REASON_XSETBV:
8225 return true;
8226 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8227 /*
8228 * This should never happen, since it is not possible to
8229 * set XSS to a non-zero value---neither in L1 nor in L2.
8230 * If if it were, XSS would have to be checked against
8231 * the XSS exit bitmap in vmcs12.
8232 */
8233 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8234 case EXIT_REASON_PREEMPTION_TIMER:
8235 return false;
8236 case EXIT_REASON_PML_FULL:
8237 /* We emulate PML support to L1. */
8238 return false;
8239 default:
8240 return true;
8241 }
8242 }
8243
8244 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8245 {
8246 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8247
8248 /*
8249 * At this point, the exit interruption info in exit_intr_info
8250 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8251 * we need to query the in-kernel LAPIC.
8252 */
8253 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8254 if ((exit_intr_info &
8255 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8256 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8257 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8258 vmcs12->vm_exit_intr_error_code =
8259 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8260 }
8261
8262 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8263 vmcs_readl(EXIT_QUALIFICATION));
8264 return 1;
8265 }
8266
8267 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8268 {
8269 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8270 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8271 }
8272
8273 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8274 {
8275 if (vmx->pml_pg) {
8276 __free_page(vmx->pml_pg);
8277 vmx->pml_pg = NULL;
8278 }
8279 }
8280
8281 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8282 {
8283 struct vcpu_vmx *vmx = to_vmx(vcpu);
8284 u64 *pml_buf;
8285 u16 pml_idx;
8286
8287 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8288
8289 /* Do nothing if PML buffer is empty */
8290 if (pml_idx == (PML_ENTITY_NUM - 1))
8291 return;
8292
8293 /* PML index always points to next available PML buffer entity */
8294 if (pml_idx >= PML_ENTITY_NUM)
8295 pml_idx = 0;
8296 else
8297 pml_idx++;
8298
8299 pml_buf = page_address(vmx->pml_pg);
8300 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8301 u64 gpa;
8302
8303 gpa = pml_buf[pml_idx];
8304 WARN_ON(gpa & (PAGE_SIZE - 1));
8305 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8306 }
8307
8308 /* reset PML index */
8309 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8310 }
8311
8312 /*
8313 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8314 * Called before reporting dirty_bitmap to userspace.
8315 */
8316 static void kvm_flush_pml_buffers(struct kvm *kvm)
8317 {
8318 int i;
8319 struct kvm_vcpu *vcpu;
8320 /*
8321 * We only need to kick vcpu out of guest mode here, as PML buffer
8322 * is flushed at beginning of all VMEXITs, and it's obvious that only
8323 * vcpus running in guest are possible to have unflushed GPAs in PML
8324 * buffer.
8325 */
8326 kvm_for_each_vcpu(i, vcpu, kvm)
8327 kvm_vcpu_kick(vcpu);
8328 }
8329
8330 static void vmx_dump_sel(char *name, uint32_t sel)
8331 {
8332 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8333 name, vmcs_read16(sel),
8334 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8335 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8336 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8337 }
8338
8339 static void vmx_dump_dtsel(char *name, uint32_t limit)
8340 {
8341 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8342 name, vmcs_read32(limit),
8343 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8344 }
8345
8346 static void dump_vmcs(void)
8347 {
8348 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8349 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8350 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8351 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8352 u32 secondary_exec_control = 0;
8353 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8354 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8355 int i, n;
8356
8357 if (cpu_has_secondary_exec_ctrls())
8358 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8359
8360 pr_err("*** Guest State ***\n");
8361 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8362 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8363 vmcs_readl(CR0_GUEST_HOST_MASK));
8364 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8365 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8366 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8367 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8368 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8369 {
8370 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8371 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8372 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8373 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8374 }
8375 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8376 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8377 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8378 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8379 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8380 vmcs_readl(GUEST_SYSENTER_ESP),
8381 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8382 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8383 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8384 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8385 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8386 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8387 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8388 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8389 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8390 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8391 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8392 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8393 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8394 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8395 efer, vmcs_read64(GUEST_IA32_PAT));
8396 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8397 vmcs_read64(GUEST_IA32_DEBUGCTL),
8398 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8399 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8400 pr_err("PerfGlobCtl = 0x%016llx\n",
8401 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8402 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8403 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8404 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8405 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8406 vmcs_read32(GUEST_ACTIVITY_STATE));
8407 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8408 pr_err("InterruptStatus = %04x\n",
8409 vmcs_read16(GUEST_INTR_STATUS));
8410
8411 pr_err("*** Host State ***\n");
8412 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8413 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8414 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8415 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8416 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8417 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8418 vmcs_read16(HOST_TR_SELECTOR));
8419 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8420 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8421 vmcs_readl(HOST_TR_BASE));
8422 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8423 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8424 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8425 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8426 vmcs_readl(HOST_CR4));
8427 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8428 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8429 vmcs_read32(HOST_IA32_SYSENTER_CS),
8430 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8431 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8432 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8433 vmcs_read64(HOST_IA32_EFER),
8434 vmcs_read64(HOST_IA32_PAT));
8435 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8436 pr_err("PerfGlobCtl = 0x%016llx\n",
8437 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8438
8439 pr_err("*** Control State ***\n");
8440 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8441 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8442 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8443 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8444 vmcs_read32(EXCEPTION_BITMAP),
8445 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8446 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8447 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8448 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8449 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8450 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8451 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8452 vmcs_read32(VM_EXIT_INTR_INFO),
8453 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8454 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8455 pr_err(" reason=%08x qualification=%016lx\n",
8456 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8457 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8458 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8459 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8460 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8461 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8462 pr_err("TSC Multiplier = 0x%016llx\n",
8463 vmcs_read64(TSC_MULTIPLIER));
8464 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8465 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8466 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8467 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8468 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8469 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8470 n = vmcs_read32(CR3_TARGET_COUNT);
8471 for (i = 0; i + 1 < n; i += 4)
8472 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8473 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8474 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8475 if (i < n)
8476 pr_err("CR3 target%u=%016lx\n",
8477 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8478 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8479 pr_err("PLE Gap=%08x Window=%08x\n",
8480 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8481 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8482 pr_err("Virtual processor ID = 0x%04x\n",
8483 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8484 }
8485
8486 /*
8487 * The guest has exited. See if we can fix it or if we need userspace
8488 * assistance.
8489 */
8490 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8491 {
8492 struct vcpu_vmx *vmx = to_vmx(vcpu);
8493 u32 exit_reason = vmx->exit_reason;
8494 u32 vectoring_info = vmx->idt_vectoring_info;
8495
8496 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8497 vcpu->arch.gpa_available = false;
8498
8499 /*
8500 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8501 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8502 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8503 * mode as if vcpus is in root mode, the PML buffer must has been
8504 * flushed already.
8505 */
8506 if (enable_pml)
8507 vmx_flush_pml_buffer(vcpu);
8508
8509 /* If guest state is invalid, start emulating */
8510 if (vmx->emulation_required)
8511 return handle_invalid_guest_state(vcpu);
8512
8513 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8514 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8515
8516 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8517 dump_vmcs();
8518 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8519 vcpu->run->fail_entry.hardware_entry_failure_reason
8520 = exit_reason;
8521 return 0;
8522 }
8523
8524 if (unlikely(vmx->fail)) {
8525 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8526 vcpu->run->fail_entry.hardware_entry_failure_reason
8527 = vmcs_read32(VM_INSTRUCTION_ERROR);
8528 return 0;
8529 }
8530
8531 /*
8532 * Note:
8533 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8534 * delivery event since it indicates guest is accessing MMIO.
8535 * The vm-exit can be triggered again after return to guest that
8536 * will cause infinite loop.
8537 */
8538 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8539 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8540 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8541 exit_reason != EXIT_REASON_PML_FULL &&
8542 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8543 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8544 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8545 vcpu->run->internal.ndata = 3;
8546 vcpu->run->internal.data[0] = vectoring_info;
8547 vcpu->run->internal.data[1] = exit_reason;
8548 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8549 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8550 vcpu->run->internal.ndata++;
8551 vcpu->run->internal.data[3] =
8552 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8553 }
8554 return 0;
8555 }
8556
8557 if (exit_reason < kvm_vmx_max_exit_handlers
8558 && kvm_vmx_exit_handlers[exit_reason])
8559 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8560 else {
8561 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8562 exit_reason);
8563 kvm_queue_exception(vcpu, UD_VECTOR);
8564 return 1;
8565 }
8566 }
8567
8568 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8569 {
8570 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8571
8572 if (is_guest_mode(vcpu) &&
8573 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8574 return;
8575
8576 if (irr == -1 || tpr < irr) {
8577 vmcs_write32(TPR_THRESHOLD, 0);
8578 return;
8579 }
8580
8581 vmcs_write32(TPR_THRESHOLD, irr);
8582 }
8583
8584 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8585 {
8586 u32 sec_exec_control;
8587
8588 /* Postpone execution until vmcs01 is the current VMCS. */
8589 if (is_guest_mode(vcpu)) {
8590 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8591 return;
8592 }
8593
8594 if (!cpu_has_vmx_virtualize_x2apic_mode())
8595 return;
8596
8597 if (!cpu_need_tpr_shadow(vcpu))
8598 return;
8599
8600 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8601
8602 if (set) {
8603 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8604 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8605 } else {
8606 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8607 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8608 vmx_flush_tlb_ept_only(vcpu);
8609 }
8610 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8611
8612 vmx_set_msr_bitmap(vcpu);
8613 }
8614
8615 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8616 {
8617 struct vcpu_vmx *vmx = to_vmx(vcpu);
8618
8619 /*
8620 * Currently we do not handle the nested case where L2 has an
8621 * APIC access page of its own; that page is still pinned.
8622 * Hence, we skip the case where the VCPU is in guest mode _and_
8623 * L1 prepared an APIC access page for L2.
8624 *
8625 * For the case where L1 and L2 share the same APIC access page
8626 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8627 * in the vmcs12), this function will only update either the vmcs01
8628 * or the vmcs02. If the former, the vmcs02 will be updated by
8629 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8630 * the next L2->L1 exit.
8631 */
8632 if (!is_guest_mode(vcpu) ||
8633 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8634 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8635 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8636 vmx_flush_tlb_ept_only(vcpu);
8637 }
8638 }
8639
8640 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8641 {
8642 u16 status;
8643 u8 old;
8644
8645 if (max_isr == -1)
8646 max_isr = 0;
8647
8648 status = vmcs_read16(GUEST_INTR_STATUS);
8649 old = status >> 8;
8650 if (max_isr != old) {
8651 status &= 0xff;
8652 status |= max_isr << 8;
8653 vmcs_write16(GUEST_INTR_STATUS, status);
8654 }
8655 }
8656
8657 static void vmx_set_rvi(int vector)
8658 {
8659 u16 status;
8660 u8 old;
8661
8662 if (vector == -1)
8663 vector = 0;
8664
8665 status = vmcs_read16(GUEST_INTR_STATUS);
8666 old = (u8)status & 0xff;
8667 if ((u8)vector != old) {
8668 status &= ~0xff;
8669 status |= (u8)vector;
8670 vmcs_write16(GUEST_INTR_STATUS, status);
8671 }
8672 }
8673
8674 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8675 {
8676 if (!is_guest_mode(vcpu)) {
8677 vmx_set_rvi(max_irr);
8678 return;
8679 }
8680
8681 if (max_irr == -1)
8682 return;
8683
8684 /*
8685 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8686 * handles it.
8687 */
8688 if (nested_exit_on_intr(vcpu))
8689 return;
8690
8691 /*
8692 * Else, fall back to pre-APICv interrupt injection since L2
8693 * is run without virtual interrupt delivery.
8694 */
8695 if (!kvm_event_needs_reinjection(vcpu) &&
8696 vmx_interrupt_allowed(vcpu)) {
8697 kvm_queue_interrupt(vcpu, max_irr, false);
8698 vmx_inject_irq(vcpu);
8699 }
8700 }
8701
8702 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8703 {
8704 struct vcpu_vmx *vmx = to_vmx(vcpu);
8705 int max_irr;
8706
8707 WARN_ON(!vcpu->arch.apicv_active);
8708 if (pi_test_on(&vmx->pi_desc)) {
8709 pi_clear_on(&vmx->pi_desc);
8710 /*
8711 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8712 * But on x86 this is just a compiler barrier anyway.
8713 */
8714 smp_mb__after_atomic();
8715 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8716 } else {
8717 max_irr = kvm_lapic_find_highest_irr(vcpu);
8718 }
8719 vmx_hwapic_irr_update(vcpu, max_irr);
8720 return max_irr;
8721 }
8722
8723 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8724 {
8725 if (!kvm_vcpu_apicv_active(vcpu))
8726 return;
8727
8728 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8729 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8730 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8731 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8732 }
8733
8734 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8735 {
8736 struct vcpu_vmx *vmx = to_vmx(vcpu);
8737
8738 pi_clear_on(&vmx->pi_desc);
8739 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8740 }
8741
8742 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8743 {
8744 u32 exit_intr_info = 0;
8745 u16 basic_exit_reason = (u16)vmx->exit_reason;
8746
8747 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8748 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
8749 return;
8750
8751 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8752 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8753 vmx->exit_intr_info = exit_intr_info;
8754
8755 /* if exit due to PF check for async PF */
8756 if (is_page_fault(exit_intr_info))
8757 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8758
8759 /* Handle machine checks before interrupts are enabled */
8760 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8761 is_machine_check(exit_intr_info))
8762 kvm_machine_check();
8763
8764 /* We need to handle NMIs before interrupts are enabled */
8765 if (is_nmi(exit_intr_info)) {
8766 kvm_before_handle_nmi(&vmx->vcpu);
8767 asm("int $2");
8768 kvm_after_handle_nmi(&vmx->vcpu);
8769 }
8770 }
8771
8772 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8773 {
8774 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8775 register void *__sp asm(_ASM_SP);
8776
8777 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8778 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8779 unsigned int vector;
8780 unsigned long entry;
8781 gate_desc *desc;
8782 struct vcpu_vmx *vmx = to_vmx(vcpu);
8783 #ifdef CONFIG_X86_64
8784 unsigned long tmp;
8785 #endif
8786
8787 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8788 desc = (gate_desc *)vmx->host_idt_base + vector;
8789 entry = gate_offset(*desc);
8790 asm volatile(
8791 #ifdef CONFIG_X86_64
8792 "mov %%" _ASM_SP ", %[sp]\n\t"
8793 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8794 "push $%c[ss]\n\t"
8795 "push %[sp]\n\t"
8796 #endif
8797 "pushf\n\t"
8798 __ASM_SIZE(push) " $%c[cs]\n\t"
8799 "call *%[entry]\n\t"
8800 :
8801 #ifdef CONFIG_X86_64
8802 [sp]"=&r"(tmp),
8803 #endif
8804 "+r"(__sp)
8805 :
8806 [entry]"r"(entry),
8807 [ss]"i"(__KERNEL_DS),
8808 [cs]"i"(__KERNEL_CS)
8809 );
8810 }
8811 }
8812 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8813
8814 static bool vmx_has_high_real_mode_segbase(void)
8815 {
8816 return enable_unrestricted_guest || emulate_invalid_guest_state;
8817 }
8818
8819 static bool vmx_mpx_supported(void)
8820 {
8821 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8822 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8823 }
8824
8825 static bool vmx_xsaves_supported(void)
8826 {
8827 return vmcs_config.cpu_based_2nd_exec_ctrl &
8828 SECONDARY_EXEC_XSAVES;
8829 }
8830
8831 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8832 {
8833 u32 exit_intr_info;
8834 bool unblock_nmi;
8835 u8 vector;
8836 bool idtv_info_valid;
8837
8838 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8839
8840 if (vmx->loaded_vmcs->nmi_known_unmasked)
8841 return;
8842 /*
8843 * Can't use vmx->exit_intr_info since we're not sure what
8844 * the exit reason is.
8845 */
8846 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8847 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8848 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8849 /*
8850 * SDM 3: 27.7.1.2 (September 2008)
8851 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8852 * a guest IRET fault.
8853 * SDM 3: 23.2.2 (September 2008)
8854 * Bit 12 is undefined in any of the following cases:
8855 * If the VM exit sets the valid bit in the IDT-vectoring
8856 * information field.
8857 * If the VM exit is due to a double fault.
8858 */
8859 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8860 vector != DF_VECTOR && !idtv_info_valid)
8861 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8862 GUEST_INTR_STATE_NMI);
8863 else
8864 vmx->loaded_vmcs->nmi_known_unmasked =
8865 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8866 & GUEST_INTR_STATE_NMI);
8867 }
8868
8869 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8870 u32 idt_vectoring_info,
8871 int instr_len_field,
8872 int error_code_field)
8873 {
8874 u8 vector;
8875 int type;
8876 bool idtv_info_valid;
8877
8878 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8879
8880 vcpu->arch.nmi_injected = false;
8881 kvm_clear_exception_queue(vcpu);
8882 kvm_clear_interrupt_queue(vcpu);
8883
8884 if (!idtv_info_valid)
8885 return;
8886
8887 kvm_make_request(KVM_REQ_EVENT, vcpu);
8888
8889 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8890 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8891
8892 switch (type) {
8893 case INTR_TYPE_NMI_INTR:
8894 vcpu->arch.nmi_injected = true;
8895 /*
8896 * SDM 3: 27.7.1.2 (September 2008)
8897 * Clear bit "block by NMI" before VM entry if a NMI
8898 * delivery faulted.
8899 */
8900 vmx_set_nmi_mask(vcpu, false);
8901 break;
8902 case INTR_TYPE_SOFT_EXCEPTION:
8903 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8904 /* fall through */
8905 case INTR_TYPE_HARD_EXCEPTION:
8906 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8907 u32 err = vmcs_read32(error_code_field);
8908 kvm_requeue_exception_e(vcpu, vector, err);
8909 } else
8910 kvm_requeue_exception(vcpu, vector);
8911 break;
8912 case INTR_TYPE_SOFT_INTR:
8913 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8914 /* fall through */
8915 case INTR_TYPE_EXT_INTR:
8916 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8917 break;
8918 default:
8919 break;
8920 }
8921 }
8922
8923 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8924 {
8925 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8926 VM_EXIT_INSTRUCTION_LEN,
8927 IDT_VECTORING_ERROR_CODE);
8928 }
8929
8930 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8931 {
8932 __vmx_complete_interrupts(vcpu,
8933 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8934 VM_ENTRY_INSTRUCTION_LEN,
8935 VM_ENTRY_EXCEPTION_ERROR_CODE);
8936
8937 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8938 }
8939
8940 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8941 {
8942 int i, nr_msrs;
8943 struct perf_guest_switch_msr *msrs;
8944
8945 msrs = perf_guest_get_msrs(&nr_msrs);
8946
8947 if (!msrs)
8948 return;
8949
8950 for (i = 0; i < nr_msrs; i++)
8951 if (msrs[i].host == msrs[i].guest)
8952 clear_atomic_switch_msr(vmx, msrs[i].msr);
8953 else
8954 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8955 msrs[i].host);
8956 }
8957
8958 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8959 {
8960 struct vcpu_vmx *vmx = to_vmx(vcpu);
8961 u64 tscl;
8962 u32 delta_tsc;
8963
8964 if (vmx->hv_deadline_tsc == -1)
8965 return;
8966
8967 tscl = rdtsc();
8968 if (vmx->hv_deadline_tsc > tscl)
8969 /* sure to be 32 bit only because checked on set_hv_timer */
8970 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8971 cpu_preemption_timer_multi);
8972 else
8973 delta_tsc = 0;
8974
8975 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8976 }
8977
8978 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8979 {
8980 struct vcpu_vmx *vmx = to_vmx(vcpu);
8981 unsigned long debugctlmsr, cr3, cr4;
8982
8983 /* Don't enter VMX if guest state is invalid, let the exit handler
8984 start emulation until we arrive back to a valid state */
8985 if (vmx->emulation_required)
8986 return;
8987
8988 if (vmx->ple_window_dirty) {
8989 vmx->ple_window_dirty = false;
8990 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8991 }
8992
8993 if (vmx->nested.sync_shadow_vmcs) {
8994 copy_vmcs12_to_shadow(vmx);
8995 vmx->nested.sync_shadow_vmcs = false;
8996 }
8997
8998 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8999 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9000 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9001 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9002
9003 cr3 = __get_current_cr3_fast();
9004 if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9005 vmcs_writel(HOST_CR3, cr3);
9006 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9007 }
9008
9009 cr4 = cr4_read_shadow();
9010 if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9011 vmcs_writel(HOST_CR4, cr4);
9012 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9013 }
9014
9015 /* When single-stepping over STI and MOV SS, we must clear the
9016 * corresponding interruptibility bits in the guest state. Otherwise
9017 * vmentry fails as it then expects bit 14 (BS) in pending debug
9018 * exceptions being set, but that's not correct for the guest debugging
9019 * case. */
9020 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9021 vmx_set_interrupt_shadow(vcpu, 0);
9022
9023 if (static_cpu_has(X86_FEATURE_PKU) &&
9024 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9025 vcpu->arch.pkru != vmx->host_pkru)
9026 __write_pkru(vcpu->arch.pkru);
9027
9028 atomic_switch_perf_msrs(vmx);
9029 debugctlmsr = get_debugctlmsr();
9030
9031 vmx_arm_hv_timer(vcpu);
9032
9033 vmx->__launched = vmx->loaded_vmcs->launched;
9034 asm(
9035 /* Store host registers */
9036 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9037 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9038 "push %%" _ASM_CX " \n\t"
9039 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9040 "je 1f \n\t"
9041 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9042 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9043 "1: \n\t"
9044 /* Reload cr2 if changed */
9045 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9046 "mov %%cr2, %%" _ASM_DX " \n\t"
9047 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9048 "je 2f \n\t"
9049 "mov %%" _ASM_AX", %%cr2 \n\t"
9050 "2: \n\t"
9051 /* Check if vmlaunch of vmresume is needed */
9052 "cmpl $0, %c[launched](%0) \n\t"
9053 /* Load guest registers. Don't clobber flags. */
9054 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9055 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9056 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9057 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9058 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9059 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9060 #ifdef CONFIG_X86_64
9061 "mov %c[r8](%0), %%r8 \n\t"
9062 "mov %c[r9](%0), %%r9 \n\t"
9063 "mov %c[r10](%0), %%r10 \n\t"
9064 "mov %c[r11](%0), %%r11 \n\t"
9065 "mov %c[r12](%0), %%r12 \n\t"
9066 "mov %c[r13](%0), %%r13 \n\t"
9067 "mov %c[r14](%0), %%r14 \n\t"
9068 "mov %c[r15](%0), %%r15 \n\t"
9069 #endif
9070 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9071
9072 /* Enter guest mode */
9073 "jne 1f \n\t"
9074 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9075 "jmp 2f \n\t"
9076 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9077 "2: "
9078 /* Save guest registers, load host registers, keep flags */
9079 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9080 "pop %0 \n\t"
9081 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9082 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9083 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9084 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9085 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9086 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9087 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9088 #ifdef CONFIG_X86_64
9089 "mov %%r8, %c[r8](%0) \n\t"
9090 "mov %%r9, %c[r9](%0) \n\t"
9091 "mov %%r10, %c[r10](%0) \n\t"
9092 "mov %%r11, %c[r11](%0) \n\t"
9093 "mov %%r12, %c[r12](%0) \n\t"
9094 "mov %%r13, %c[r13](%0) \n\t"
9095 "mov %%r14, %c[r14](%0) \n\t"
9096 "mov %%r15, %c[r15](%0) \n\t"
9097 #endif
9098 "mov %%cr2, %%" _ASM_AX " \n\t"
9099 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9100
9101 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
9102 "setbe %c[fail](%0) \n\t"
9103 ".pushsection .rodata \n\t"
9104 ".global vmx_return \n\t"
9105 "vmx_return: " _ASM_PTR " 2b \n\t"
9106 ".popsection"
9107 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9108 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9109 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9110 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9111 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9112 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9113 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9114 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9115 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9116 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9117 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9118 #ifdef CONFIG_X86_64
9119 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9120 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9121 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9122 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9123 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9124 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9125 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9126 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9127 #endif
9128 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9129 [wordsize]"i"(sizeof(ulong))
9130 : "cc", "memory"
9131 #ifdef CONFIG_X86_64
9132 , "rax", "rbx", "rdi", "rsi"
9133 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9134 #else
9135 , "eax", "ebx", "edi", "esi"
9136 #endif
9137 );
9138
9139 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9140 if (debugctlmsr)
9141 update_debugctlmsr(debugctlmsr);
9142
9143 #ifndef CONFIG_X86_64
9144 /*
9145 * The sysexit path does not restore ds/es, so we must set them to
9146 * a reasonable value ourselves.
9147 *
9148 * We can't defer this to vmx_load_host_state() since that function
9149 * may be executed in interrupt context, which saves and restore segments
9150 * around it, nullifying its effect.
9151 */
9152 loadsegment(ds, __USER_DS);
9153 loadsegment(es, __USER_DS);
9154 #endif
9155
9156 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9157 | (1 << VCPU_EXREG_RFLAGS)
9158 | (1 << VCPU_EXREG_PDPTR)
9159 | (1 << VCPU_EXREG_SEGMENTS)
9160 | (1 << VCPU_EXREG_CR3));
9161 vcpu->arch.regs_dirty = 0;
9162
9163 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9164
9165 vmx->loaded_vmcs->launched = 1;
9166
9167 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9168
9169 /*
9170 * eager fpu is enabled if PKEY is supported and CR4 is switched
9171 * back on host, so it is safe to read guest PKRU from current
9172 * XSAVE.
9173 */
9174 if (static_cpu_has(X86_FEATURE_PKU) &&
9175 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9176 vcpu->arch.pkru = __read_pkru();
9177 if (vcpu->arch.pkru != vmx->host_pkru)
9178 __write_pkru(vmx->host_pkru);
9179 }
9180
9181 /*
9182 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9183 * we did not inject a still-pending event to L1 now because of
9184 * nested_run_pending, we need to re-enable this bit.
9185 */
9186 if (vmx->nested.nested_run_pending)
9187 kvm_make_request(KVM_REQ_EVENT, vcpu);
9188
9189 vmx->nested.nested_run_pending = 0;
9190
9191 vmx_complete_atomic_exit(vmx);
9192 vmx_recover_nmi_blocking(vmx);
9193 vmx_complete_interrupts(vmx);
9194 }
9195 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9196
9197 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9198 {
9199 struct vcpu_vmx *vmx = to_vmx(vcpu);
9200 int cpu;
9201
9202 if (vmx->loaded_vmcs == vmcs)
9203 return;
9204
9205 cpu = get_cpu();
9206 vmx->loaded_vmcs = vmcs;
9207 vmx_vcpu_put(vcpu);
9208 vmx_vcpu_load(vcpu, cpu);
9209 vcpu->cpu = cpu;
9210 put_cpu();
9211 }
9212
9213 /*
9214 * Ensure that the current vmcs of the logical processor is the
9215 * vmcs01 of the vcpu before calling free_nested().
9216 */
9217 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9218 {
9219 struct vcpu_vmx *vmx = to_vmx(vcpu);
9220 int r;
9221
9222 r = vcpu_load(vcpu);
9223 BUG_ON(r);
9224 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9225 free_nested(vmx);
9226 vcpu_put(vcpu);
9227 }
9228
9229 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9230 {
9231 struct vcpu_vmx *vmx = to_vmx(vcpu);
9232
9233 if (enable_pml)
9234 vmx_destroy_pml_buffer(vmx);
9235 free_vpid(vmx->vpid);
9236 leave_guest_mode(vcpu);
9237 vmx_free_vcpu_nested(vcpu);
9238 free_loaded_vmcs(vmx->loaded_vmcs);
9239 kfree(vmx->guest_msrs);
9240 kvm_vcpu_uninit(vcpu);
9241 kmem_cache_free(kvm_vcpu_cache, vmx);
9242 }
9243
9244 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9245 {
9246 int err;
9247 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9248 int cpu;
9249
9250 if (!vmx)
9251 return ERR_PTR(-ENOMEM);
9252
9253 vmx->vpid = allocate_vpid();
9254
9255 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9256 if (err)
9257 goto free_vcpu;
9258
9259 err = -ENOMEM;
9260
9261 /*
9262 * If PML is turned on, failure on enabling PML just results in failure
9263 * of creating the vcpu, therefore we can simplify PML logic (by
9264 * avoiding dealing with cases, such as enabling PML partially on vcpus
9265 * for the guest, etc.
9266 */
9267 if (enable_pml) {
9268 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9269 if (!vmx->pml_pg)
9270 goto uninit_vcpu;
9271 }
9272
9273 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9274 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9275 > PAGE_SIZE);
9276
9277 if (!vmx->guest_msrs)
9278 goto free_pml;
9279
9280 vmx->loaded_vmcs = &vmx->vmcs01;
9281 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9282 vmx->loaded_vmcs->shadow_vmcs = NULL;
9283 if (!vmx->loaded_vmcs->vmcs)
9284 goto free_msrs;
9285 loaded_vmcs_init(vmx->loaded_vmcs);
9286
9287 cpu = get_cpu();
9288 vmx_vcpu_load(&vmx->vcpu, cpu);
9289 vmx->vcpu.cpu = cpu;
9290 err = vmx_vcpu_setup(vmx);
9291 vmx_vcpu_put(&vmx->vcpu);
9292 put_cpu();
9293 if (err)
9294 goto free_vmcs;
9295 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9296 err = alloc_apic_access_page(kvm);
9297 if (err)
9298 goto free_vmcs;
9299 }
9300
9301 if (enable_ept) {
9302 if (!kvm->arch.ept_identity_map_addr)
9303 kvm->arch.ept_identity_map_addr =
9304 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9305 err = init_rmode_identity_map(kvm);
9306 if (err)
9307 goto free_vmcs;
9308 }
9309
9310 if (nested) {
9311 nested_vmx_setup_ctls_msrs(vmx);
9312 vmx->nested.vpid02 = allocate_vpid();
9313 }
9314
9315 vmx->nested.posted_intr_nv = -1;
9316 vmx->nested.current_vmptr = -1ull;
9317
9318 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9319
9320 /*
9321 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9322 * or POSTED_INTR_WAKEUP_VECTOR.
9323 */
9324 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9325 vmx->pi_desc.sn = 1;
9326
9327 return &vmx->vcpu;
9328
9329 free_vmcs:
9330 free_vpid(vmx->nested.vpid02);
9331 free_loaded_vmcs(vmx->loaded_vmcs);
9332 free_msrs:
9333 kfree(vmx->guest_msrs);
9334 free_pml:
9335 vmx_destroy_pml_buffer(vmx);
9336 uninit_vcpu:
9337 kvm_vcpu_uninit(&vmx->vcpu);
9338 free_vcpu:
9339 free_vpid(vmx->vpid);
9340 kmem_cache_free(kvm_vcpu_cache, vmx);
9341 return ERR_PTR(err);
9342 }
9343
9344 static void __init vmx_check_processor_compat(void *rtn)
9345 {
9346 struct vmcs_config vmcs_conf;
9347
9348 *(int *)rtn = 0;
9349 if (setup_vmcs_config(&vmcs_conf) < 0)
9350 *(int *)rtn = -EIO;
9351 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9352 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9353 smp_processor_id());
9354 *(int *)rtn = -EIO;
9355 }
9356 }
9357
9358 static int get_ept_level(void)
9359 {
9360 return VMX_EPT_DEFAULT_GAW + 1;
9361 }
9362
9363 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9364 {
9365 u8 cache;
9366 u64 ipat = 0;
9367
9368 /* For VT-d and EPT combination
9369 * 1. MMIO: always map as UC
9370 * 2. EPT with VT-d:
9371 * a. VT-d without snooping control feature: can't guarantee the
9372 * result, try to trust guest.
9373 * b. VT-d with snooping control feature: snooping control feature of
9374 * VT-d engine can guarantee the cache correctness. Just set it
9375 * to WB to keep consistent with host. So the same as item 3.
9376 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9377 * consistent with host MTRR
9378 */
9379 if (is_mmio) {
9380 cache = MTRR_TYPE_UNCACHABLE;
9381 goto exit;
9382 }
9383
9384 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9385 ipat = VMX_EPT_IPAT_BIT;
9386 cache = MTRR_TYPE_WRBACK;
9387 goto exit;
9388 }
9389
9390 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9391 ipat = VMX_EPT_IPAT_BIT;
9392 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9393 cache = MTRR_TYPE_WRBACK;
9394 else
9395 cache = MTRR_TYPE_UNCACHABLE;
9396 goto exit;
9397 }
9398
9399 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9400
9401 exit:
9402 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9403 }
9404
9405 static int vmx_get_lpage_level(void)
9406 {
9407 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9408 return PT_DIRECTORY_LEVEL;
9409 else
9410 /* For shadow and EPT supported 1GB page */
9411 return PT_PDPE_LEVEL;
9412 }
9413
9414 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9415 {
9416 /*
9417 * These bits in the secondary execution controls field
9418 * are dynamic, the others are mostly based on the hypervisor
9419 * architecture and the guest's CPUID. Do not touch the
9420 * dynamic bits.
9421 */
9422 u32 mask =
9423 SECONDARY_EXEC_SHADOW_VMCS |
9424 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9425 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9426
9427 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9428
9429 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9430 (new_ctl & ~mask) | (cur_ctl & mask));
9431 }
9432
9433 /*
9434 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9435 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9436 */
9437 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9438 {
9439 struct vcpu_vmx *vmx = to_vmx(vcpu);
9440 struct kvm_cpuid_entry2 *entry;
9441
9442 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9443 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9444
9445 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9446 if (entry && (entry->_reg & (_cpuid_mask))) \
9447 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9448 } while (0)
9449
9450 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9451 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9452 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9453 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9454 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9455 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9456 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9457 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9458 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9459 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9460 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9461 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9462 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9463 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9464 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9465
9466 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9467 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9468 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9469 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9470 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9471 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9472 cr4_fixed1_update(bit(11), ecx, bit(2));
9473
9474 #undef cr4_fixed1_update
9475 }
9476
9477 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9478 {
9479 struct kvm_cpuid_entry2 *best;
9480 struct vcpu_vmx *vmx = to_vmx(vcpu);
9481 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9482
9483 if (vmx_rdtscp_supported()) {
9484 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9485 if (!rdtscp_enabled)
9486 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9487
9488 if (nested) {
9489 if (rdtscp_enabled)
9490 vmx->nested.nested_vmx_secondary_ctls_high |=
9491 SECONDARY_EXEC_RDTSCP;
9492 else
9493 vmx->nested.nested_vmx_secondary_ctls_high &=
9494 ~SECONDARY_EXEC_RDTSCP;
9495 }
9496 }
9497
9498 /* Exposing INVPCID only when PCID is exposed */
9499 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9500 if (vmx_invpcid_supported() &&
9501 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9502 !guest_cpuid_has_pcid(vcpu))) {
9503 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9504
9505 if (best)
9506 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9507 }
9508
9509 if (cpu_has_secondary_exec_ctrls())
9510 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9511
9512 if (nested_vmx_allowed(vcpu))
9513 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9514 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9515 else
9516 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9517 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9518
9519 if (nested_vmx_allowed(vcpu))
9520 nested_vmx_cr_fixed1_bits_update(vcpu);
9521 }
9522
9523 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9524 {
9525 if (func == 1 && nested)
9526 entry->ecx |= bit(X86_FEATURE_VMX);
9527 }
9528
9529 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9530 struct x86_exception *fault)
9531 {
9532 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9533 struct vcpu_vmx *vmx = to_vmx(vcpu);
9534 u32 exit_reason;
9535 unsigned long exit_qualification = vcpu->arch.exit_qualification;
9536
9537 if (vmx->nested.pml_full) {
9538 exit_reason = EXIT_REASON_PML_FULL;
9539 vmx->nested.pml_full = false;
9540 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9541 } else if (fault->error_code & PFERR_RSVD_MASK)
9542 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9543 else
9544 exit_reason = EXIT_REASON_EPT_VIOLATION;
9545
9546 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9547 vmcs12->guest_physical_address = fault->address;
9548 }
9549
9550 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9551 {
9552 return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9553 }
9554
9555 /* Callbacks for nested_ept_init_mmu_context: */
9556
9557 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9558 {
9559 /* return the page table to be shadowed - in our case, EPT12 */
9560 return get_vmcs12(vcpu)->ept_pointer;
9561 }
9562
9563 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9564 {
9565 bool wants_ad;
9566
9567 WARN_ON(mmu_is_nested(vcpu));
9568 wants_ad = nested_ept_ad_enabled(vcpu);
9569 if (wants_ad && !enable_ept_ad_bits)
9570 return 1;
9571
9572 kvm_mmu_unload(vcpu);
9573 kvm_init_shadow_ept_mmu(vcpu,
9574 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9575 VMX_EPT_EXECUTE_ONLY_BIT,
9576 wants_ad);
9577 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9578 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9579 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9580
9581 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9582 return 0;
9583 }
9584
9585 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9586 {
9587 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9588 }
9589
9590 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9591 u16 error_code)
9592 {
9593 bool inequality, bit;
9594
9595 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9596 inequality =
9597 (error_code & vmcs12->page_fault_error_code_mask) !=
9598 vmcs12->page_fault_error_code_match;
9599 return inequality ^ bit;
9600 }
9601
9602 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9603 struct x86_exception *fault)
9604 {
9605 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9606
9607 WARN_ON(!is_guest_mode(vcpu));
9608
9609 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) {
9610 vmcs12->vm_exit_intr_error_code = fault->error_code;
9611 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9612 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9613 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9614 fault->address);
9615 } else {
9616 kvm_inject_page_fault(vcpu, fault);
9617 }
9618 }
9619
9620 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9621 struct vmcs12 *vmcs12);
9622
9623 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9624 struct vmcs12 *vmcs12)
9625 {
9626 struct vcpu_vmx *vmx = to_vmx(vcpu);
9627 u64 hpa;
9628
9629 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9630 /*
9631 * Translate L1 physical address to host physical
9632 * address for vmcs02. Keep the page pinned, so this
9633 * physical address remains valid. We keep a reference
9634 * to it so we can release it later.
9635 */
9636 if (vmx->nested.apic_access_page) /* shouldn't happen */
9637 nested_release_page(vmx->nested.apic_access_page);
9638 vmx->nested.apic_access_page =
9639 nested_get_page(vcpu, vmcs12->apic_access_addr);
9640 /*
9641 * If translation failed, no matter: This feature asks
9642 * to exit when accessing the given address, and if it
9643 * can never be accessed, this feature won't do
9644 * anything anyway.
9645 */
9646 if (vmx->nested.apic_access_page) {
9647 hpa = page_to_phys(vmx->nested.apic_access_page);
9648 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9649 } else {
9650 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9651 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9652 }
9653 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9654 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9655 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9656 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9657 kvm_vcpu_reload_apic_access_page(vcpu);
9658 }
9659
9660 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9661 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9662 nested_release_page(vmx->nested.virtual_apic_page);
9663 vmx->nested.virtual_apic_page =
9664 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9665
9666 /*
9667 * If translation failed, VM entry will fail because
9668 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9669 * Failing the vm entry is _not_ what the processor
9670 * does but it's basically the only possibility we
9671 * have. We could still enter the guest if CR8 load
9672 * exits are enabled, CR8 store exits are enabled, and
9673 * virtualize APIC access is disabled; in this case
9674 * the processor would never use the TPR shadow and we
9675 * could simply clear the bit from the execution
9676 * control. But such a configuration is useless, so
9677 * let's keep the code simple.
9678 */
9679 if (vmx->nested.virtual_apic_page) {
9680 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9681 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9682 }
9683 }
9684
9685 if (nested_cpu_has_posted_intr(vmcs12)) {
9686 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9687 kunmap(vmx->nested.pi_desc_page);
9688 nested_release_page(vmx->nested.pi_desc_page);
9689 }
9690 vmx->nested.pi_desc_page =
9691 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9692 vmx->nested.pi_desc =
9693 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9694 if (!vmx->nested.pi_desc) {
9695 nested_release_page_clean(vmx->nested.pi_desc_page);
9696 return;
9697 }
9698 vmx->nested.pi_desc =
9699 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9700 (unsigned long)(vmcs12->posted_intr_desc_addr &
9701 (PAGE_SIZE - 1)));
9702 vmcs_write64(POSTED_INTR_DESC_ADDR,
9703 page_to_phys(vmx->nested.pi_desc_page) +
9704 (unsigned long)(vmcs12->posted_intr_desc_addr &
9705 (PAGE_SIZE - 1)));
9706 }
9707 if (cpu_has_vmx_msr_bitmap() &&
9708 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9709 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9710 ;
9711 else
9712 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9713 CPU_BASED_USE_MSR_BITMAPS);
9714 }
9715
9716 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9717 {
9718 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9719 struct vcpu_vmx *vmx = to_vmx(vcpu);
9720
9721 if (vcpu->arch.virtual_tsc_khz == 0)
9722 return;
9723
9724 /* Make sure short timeouts reliably trigger an immediate vmexit.
9725 * hrtimer_start does not guarantee this. */
9726 if (preemption_timeout <= 1) {
9727 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9728 return;
9729 }
9730
9731 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9732 preemption_timeout *= 1000000;
9733 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9734 hrtimer_start(&vmx->nested.preemption_timer,
9735 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9736 }
9737
9738 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9739 struct vmcs12 *vmcs12)
9740 {
9741 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9742 return 0;
9743
9744 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9745 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9746 return -EINVAL;
9747
9748 return 0;
9749 }
9750
9751 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9752 struct vmcs12 *vmcs12)
9753 {
9754 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9755 return 0;
9756
9757 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
9758 return -EINVAL;
9759
9760 return 0;
9761 }
9762
9763 /*
9764 * Merge L0's and L1's MSR bitmap, return false to indicate that
9765 * we do not use the hardware.
9766 */
9767 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9768 struct vmcs12 *vmcs12)
9769 {
9770 int msr;
9771 struct page *page;
9772 unsigned long *msr_bitmap_l1;
9773 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9774
9775 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9776 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9777 return false;
9778
9779 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9780 if (!page)
9781 return false;
9782 msr_bitmap_l1 = (unsigned long *)kmap(page);
9783
9784 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9785
9786 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9787 if (nested_cpu_has_apic_reg_virt(vmcs12))
9788 for (msr = 0x800; msr <= 0x8ff; msr++)
9789 nested_vmx_disable_intercept_for_msr(
9790 msr_bitmap_l1, msr_bitmap_l0,
9791 msr, MSR_TYPE_R);
9792
9793 nested_vmx_disable_intercept_for_msr(
9794 msr_bitmap_l1, msr_bitmap_l0,
9795 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9796 MSR_TYPE_R | MSR_TYPE_W);
9797
9798 if (nested_cpu_has_vid(vmcs12)) {
9799 nested_vmx_disable_intercept_for_msr(
9800 msr_bitmap_l1, msr_bitmap_l0,
9801 APIC_BASE_MSR + (APIC_EOI >> 4),
9802 MSR_TYPE_W);
9803 nested_vmx_disable_intercept_for_msr(
9804 msr_bitmap_l1, msr_bitmap_l0,
9805 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9806 MSR_TYPE_W);
9807 }
9808 }
9809 kunmap(page);
9810 nested_release_page_clean(page);
9811
9812 return true;
9813 }
9814
9815 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9816 struct vmcs12 *vmcs12)
9817 {
9818 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9819 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9820 !nested_cpu_has_vid(vmcs12) &&
9821 !nested_cpu_has_posted_intr(vmcs12))
9822 return 0;
9823
9824 /*
9825 * If virtualize x2apic mode is enabled,
9826 * virtualize apic access must be disabled.
9827 */
9828 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9829 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9830 return -EINVAL;
9831
9832 /*
9833 * If virtual interrupt delivery is enabled,
9834 * we must exit on external interrupts.
9835 */
9836 if (nested_cpu_has_vid(vmcs12) &&
9837 !nested_exit_on_intr(vcpu))
9838 return -EINVAL;
9839
9840 /*
9841 * bits 15:8 should be zero in posted_intr_nv,
9842 * the descriptor address has been already checked
9843 * in nested_get_vmcs12_pages.
9844 */
9845 if (nested_cpu_has_posted_intr(vmcs12) &&
9846 (!nested_cpu_has_vid(vmcs12) ||
9847 !nested_exit_intr_ack_set(vcpu) ||
9848 vmcs12->posted_intr_nv & 0xff00))
9849 return -EINVAL;
9850
9851 /* tpr shadow is needed by all apicv features. */
9852 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9853 return -EINVAL;
9854
9855 return 0;
9856 }
9857
9858 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9859 unsigned long count_field,
9860 unsigned long addr_field)
9861 {
9862 int maxphyaddr;
9863 u64 count, addr;
9864
9865 if (vmcs12_read_any(vcpu, count_field, &count) ||
9866 vmcs12_read_any(vcpu, addr_field, &addr)) {
9867 WARN_ON(1);
9868 return -EINVAL;
9869 }
9870 if (count == 0)
9871 return 0;
9872 maxphyaddr = cpuid_maxphyaddr(vcpu);
9873 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9874 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9875 pr_debug_ratelimited(
9876 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9877 addr_field, maxphyaddr, count, addr);
9878 return -EINVAL;
9879 }
9880 return 0;
9881 }
9882
9883 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9884 struct vmcs12 *vmcs12)
9885 {
9886 if (vmcs12->vm_exit_msr_load_count == 0 &&
9887 vmcs12->vm_exit_msr_store_count == 0 &&
9888 vmcs12->vm_entry_msr_load_count == 0)
9889 return 0; /* Fast path */
9890 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9891 VM_EXIT_MSR_LOAD_ADDR) ||
9892 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9893 VM_EXIT_MSR_STORE_ADDR) ||
9894 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9895 VM_ENTRY_MSR_LOAD_ADDR))
9896 return -EINVAL;
9897 return 0;
9898 }
9899
9900 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9901 struct vmcs12 *vmcs12)
9902 {
9903 u64 address = vmcs12->pml_address;
9904 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9905
9906 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9907 if (!nested_cpu_has_ept(vmcs12) ||
9908 !IS_ALIGNED(address, 4096) ||
9909 address >> maxphyaddr)
9910 return -EINVAL;
9911 }
9912
9913 return 0;
9914 }
9915
9916 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9917 struct vmx_msr_entry *e)
9918 {
9919 /* x2APIC MSR accesses are not allowed */
9920 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9921 return -EINVAL;
9922 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9923 e->index == MSR_IA32_UCODE_REV)
9924 return -EINVAL;
9925 if (e->reserved != 0)
9926 return -EINVAL;
9927 return 0;
9928 }
9929
9930 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9931 struct vmx_msr_entry *e)
9932 {
9933 if (e->index == MSR_FS_BASE ||
9934 e->index == MSR_GS_BASE ||
9935 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9936 nested_vmx_msr_check_common(vcpu, e))
9937 return -EINVAL;
9938 return 0;
9939 }
9940
9941 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9942 struct vmx_msr_entry *e)
9943 {
9944 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9945 nested_vmx_msr_check_common(vcpu, e))
9946 return -EINVAL;
9947 return 0;
9948 }
9949
9950 /*
9951 * Load guest's/host's msr at nested entry/exit.
9952 * return 0 for success, entry index for failure.
9953 */
9954 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9955 {
9956 u32 i;
9957 struct vmx_msr_entry e;
9958 struct msr_data msr;
9959
9960 msr.host_initiated = false;
9961 for (i = 0; i < count; i++) {
9962 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9963 &e, sizeof(e))) {
9964 pr_debug_ratelimited(
9965 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9966 __func__, i, gpa + i * sizeof(e));
9967 goto fail;
9968 }
9969 if (nested_vmx_load_msr_check(vcpu, &e)) {
9970 pr_debug_ratelimited(
9971 "%s check failed (%u, 0x%x, 0x%x)\n",
9972 __func__, i, e.index, e.reserved);
9973 goto fail;
9974 }
9975 msr.index = e.index;
9976 msr.data = e.value;
9977 if (kvm_set_msr(vcpu, &msr)) {
9978 pr_debug_ratelimited(
9979 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9980 __func__, i, e.index, e.value);
9981 goto fail;
9982 }
9983 }
9984 return 0;
9985 fail:
9986 return i + 1;
9987 }
9988
9989 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9990 {
9991 u32 i;
9992 struct vmx_msr_entry e;
9993
9994 for (i = 0; i < count; i++) {
9995 struct msr_data msr_info;
9996 if (kvm_vcpu_read_guest(vcpu,
9997 gpa + i * sizeof(e),
9998 &e, 2 * sizeof(u32))) {
9999 pr_debug_ratelimited(
10000 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10001 __func__, i, gpa + i * sizeof(e));
10002 return -EINVAL;
10003 }
10004 if (nested_vmx_store_msr_check(vcpu, &e)) {
10005 pr_debug_ratelimited(
10006 "%s check failed (%u, 0x%x, 0x%x)\n",
10007 __func__, i, e.index, e.reserved);
10008 return -EINVAL;
10009 }
10010 msr_info.host_initiated = false;
10011 msr_info.index = e.index;
10012 if (kvm_get_msr(vcpu, &msr_info)) {
10013 pr_debug_ratelimited(
10014 "%s cannot read MSR (%u, 0x%x)\n",
10015 __func__, i, e.index);
10016 return -EINVAL;
10017 }
10018 if (kvm_vcpu_write_guest(vcpu,
10019 gpa + i * sizeof(e) +
10020 offsetof(struct vmx_msr_entry, value),
10021 &msr_info.data, sizeof(msr_info.data))) {
10022 pr_debug_ratelimited(
10023 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10024 __func__, i, e.index, msr_info.data);
10025 return -EINVAL;
10026 }
10027 }
10028 return 0;
10029 }
10030
10031 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10032 {
10033 unsigned long invalid_mask;
10034
10035 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10036 return (val & invalid_mask) == 0;
10037 }
10038
10039 /*
10040 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10041 * emulating VM entry into a guest with EPT enabled.
10042 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10043 * is assigned to entry_failure_code on failure.
10044 */
10045 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10046 u32 *entry_failure_code)
10047 {
10048 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10049 if (!nested_cr3_valid(vcpu, cr3)) {
10050 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10051 return 1;
10052 }
10053
10054 /*
10055 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10056 * must not be dereferenced.
10057 */
10058 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10059 !nested_ept) {
10060 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10061 *entry_failure_code = ENTRY_FAIL_PDPTE;
10062 return 1;
10063 }
10064 }
10065
10066 vcpu->arch.cr3 = cr3;
10067 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10068 }
10069
10070 kvm_mmu_reset_context(vcpu);
10071 return 0;
10072 }
10073
10074 /*
10075 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10076 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10077 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10078 * guest in a way that will both be appropriate to L1's requests, and our
10079 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10080 * function also has additional necessary side-effects, like setting various
10081 * vcpu->arch fields.
10082 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10083 * is assigned to entry_failure_code on failure.
10084 */
10085 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10086 bool from_vmentry, u32 *entry_failure_code)
10087 {
10088 struct vcpu_vmx *vmx = to_vmx(vcpu);
10089 u32 exec_control, vmcs12_exec_ctrl;
10090
10091 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10092 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10093 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10094 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10095 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10096 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10097 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10098 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10099 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10100 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10101 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10102 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10103 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10104 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10105 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10106 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10107 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10108 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10109 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10110 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10111 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10112 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10113 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10114 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10115 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10116 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10117 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10118 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10119 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10120 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10121 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10122 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10123 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10124 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10125 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10126 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10127
10128 if (from_vmentry &&
10129 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10130 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10131 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10132 } else {
10133 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10134 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10135 }
10136 if (from_vmentry) {
10137 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10138 vmcs12->vm_entry_intr_info_field);
10139 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10140 vmcs12->vm_entry_exception_error_code);
10141 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10142 vmcs12->vm_entry_instruction_len);
10143 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10144 vmcs12->guest_interruptibility_info);
10145 vmx->loaded_vmcs->nmi_known_unmasked =
10146 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10147 } else {
10148 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10149 }
10150 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10151 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10152 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10153 vmcs12->guest_pending_dbg_exceptions);
10154 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10155 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10156
10157 if (nested_cpu_has_xsaves(vmcs12))
10158 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10159 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10160
10161 exec_control = vmcs12->pin_based_vm_exec_control;
10162
10163 /* Preemption timer setting is only taken from vmcs01. */
10164 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10165 exec_control |= vmcs_config.pin_based_exec_ctrl;
10166 if (vmx->hv_deadline_tsc == -1)
10167 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10168
10169 /* Posted interrupts setting is only taken from vmcs12. */
10170 if (nested_cpu_has_posted_intr(vmcs12)) {
10171 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10172 vmx->nested.pi_pending = false;
10173 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10174 } else {
10175 exec_control &= ~PIN_BASED_POSTED_INTR;
10176 }
10177
10178 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10179
10180 vmx->nested.preemption_timer_expired = false;
10181 if (nested_cpu_has_preemption_timer(vmcs12))
10182 vmx_start_preemption_timer(vcpu);
10183
10184 /*
10185 * Whether page-faults are trapped is determined by a combination of
10186 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10187 * If enable_ept, L0 doesn't care about page faults and we should
10188 * set all of these to L1's desires. However, if !enable_ept, L0 does
10189 * care about (at least some) page faults, and because it is not easy
10190 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10191 * to exit on each and every L2 page fault. This is done by setting
10192 * MASK=MATCH=0 and (see below) EB.PF=1.
10193 * Note that below we don't need special code to set EB.PF beyond the
10194 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10195 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10196 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10197 */
10198 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10199 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10200 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10201 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10202
10203 if (cpu_has_secondary_exec_ctrls()) {
10204 exec_control = vmx_secondary_exec_control(vmx);
10205
10206 /* Take the following fields only from vmcs12 */
10207 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10208 SECONDARY_EXEC_RDTSCP |
10209 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10210 SECONDARY_EXEC_APIC_REGISTER_VIRT);
10211 if (nested_cpu_has(vmcs12,
10212 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10213 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10214 ~SECONDARY_EXEC_ENABLE_PML;
10215 exec_control |= vmcs12_exec_ctrl;
10216 }
10217
10218 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10219 vmcs_write64(EOI_EXIT_BITMAP0,
10220 vmcs12->eoi_exit_bitmap0);
10221 vmcs_write64(EOI_EXIT_BITMAP1,
10222 vmcs12->eoi_exit_bitmap1);
10223 vmcs_write64(EOI_EXIT_BITMAP2,
10224 vmcs12->eoi_exit_bitmap2);
10225 vmcs_write64(EOI_EXIT_BITMAP3,
10226 vmcs12->eoi_exit_bitmap3);
10227 vmcs_write16(GUEST_INTR_STATUS,
10228 vmcs12->guest_intr_status);
10229 }
10230
10231 /*
10232 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10233 * nested_get_vmcs12_pages will either fix it up or
10234 * remove the VM execution control.
10235 */
10236 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10237 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10238
10239 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10240 }
10241
10242
10243 /*
10244 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10245 * Some constant fields are set here by vmx_set_constant_host_state().
10246 * Other fields are different per CPU, and will be set later when
10247 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10248 */
10249 vmx_set_constant_host_state(vmx);
10250
10251 /*
10252 * Set the MSR load/store lists to match L0's settings.
10253 */
10254 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10255 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10256 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10257 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10258 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10259
10260 /*
10261 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10262 * entry, but only if the current (host) sp changed from the value
10263 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10264 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10265 * here we just force the write to happen on entry.
10266 */
10267 vmx->host_rsp = 0;
10268
10269 exec_control = vmx_exec_control(vmx); /* L0's desires */
10270 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10271 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10272 exec_control &= ~CPU_BASED_TPR_SHADOW;
10273 exec_control |= vmcs12->cpu_based_vm_exec_control;
10274
10275 /*
10276 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10277 * nested_get_vmcs12_pages can't fix it up, the illegal value
10278 * will result in a VM entry failure.
10279 */
10280 if (exec_control & CPU_BASED_TPR_SHADOW) {
10281 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10282 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10283 } else {
10284 #ifdef CONFIG_X86_64
10285 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10286 CPU_BASED_CR8_STORE_EXITING;
10287 #endif
10288 }
10289
10290 /*
10291 * Merging of IO bitmap not currently supported.
10292 * Rather, exit every time.
10293 */
10294 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10295 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10296
10297 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10298
10299 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10300 * bitwise-or of what L1 wants to trap for L2, and what we want to
10301 * trap. Note that CR0.TS also needs updating - we do this later.
10302 */
10303 update_exception_bitmap(vcpu);
10304 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10305 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10306
10307 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10308 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10309 * bits are further modified by vmx_set_efer() below.
10310 */
10311 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10312
10313 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10314 * emulated by vmx_set_efer(), below.
10315 */
10316 vm_entry_controls_init(vmx,
10317 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10318 ~VM_ENTRY_IA32E_MODE) |
10319 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10320
10321 if (from_vmentry &&
10322 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10323 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10324 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10325 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10326 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10327 }
10328
10329 set_cr4_guest_host_mask(vmx);
10330
10331 if (from_vmentry &&
10332 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10333 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10334
10335 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10336 vmcs_write64(TSC_OFFSET,
10337 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10338 else
10339 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10340 if (kvm_has_tsc_control)
10341 decache_tsc_multiplier(vmx);
10342
10343 if (enable_vpid) {
10344 /*
10345 * There is no direct mapping between vpid02 and vpid12, the
10346 * vpid02 is per-vCPU for L0 and reused while the value of
10347 * vpid12 is changed w/ one invvpid during nested vmentry.
10348 * The vpid12 is allocated by L1 for L2, so it will not
10349 * influence global bitmap(for vpid01 and vpid02 allocation)
10350 * even if spawn a lot of nested vCPUs.
10351 */
10352 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10353 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10354 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10355 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10356 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10357 }
10358 } else {
10359 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10360 vmx_flush_tlb(vcpu);
10361 }
10362
10363 }
10364
10365 if (enable_pml) {
10366 /*
10367 * Conceptually we want to copy the PML address and index from
10368 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10369 * since we always flush the log on each vmexit, this happens
10370 * to be equivalent to simply resetting the fields in vmcs02.
10371 */
10372 ASSERT(vmx->pml_pg);
10373 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10374 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10375 }
10376
10377 if (nested_cpu_has_ept(vmcs12)) {
10378 if (nested_ept_init_mmu_context(vcpu)) {
10379 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10380 return 1;
10381 }
10382 } else if (nested_cpu_has2(vmcs12,
10383 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10384 vmx_flush_tlb_ept_only(vcpu);
10385 }
10386
10387 /*
10388 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10389 * bits which we consider mandatory enabled.
10390 * The CR0_READ_SHADOW is what L2 should have expected to read given
10391 * the specifications by L1; It's not enough to take
10392 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10393 * have more bits than L1 expected.
10394 */
10395 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10396 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10397
10398 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10399 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10400
10401 if (from_vmentry &&
10402 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10403 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10404 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10405 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10406 else
10407 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10408 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10409 vmx_set_efer(vcpu, vcpu->arch.efer);
10410
10411 /* Shadow page tables on either EPT or shadow page tables. */
10412 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10413 entry_failure_code))
10414 return 1;
10415
10416 if (!enable_ept)
10417 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10418
10419 /*
10420 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10421 */
10422 if (enable_ept) {
10423 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10424 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10425 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10426 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10427 }
10428
10429 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10430 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10431 return 0;
10432 }
10433
10434 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10435 {
10436 struct vcpu_vmx *vmx = to_vmx(vcpu);
10437
10438 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10439 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10440 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10441
10442 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10443 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10444
10445 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10446 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10447
10448 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10449 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10450
10451 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10452 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10453
10454 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10455 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10456
10457 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10458 vmx->nested.nested_vmx_procbased_ctls_low,
10459 vmx->nested.nested_vmx_procbased_ctls_high) ||
10460 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10461 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10462 vmx->nested.nested_vmx_secondary_ctls_low,
10463 vmx->nested.nested_vmx_secondary_ctls_high)) ||
10464 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10465 vmx->nested.nested_vmx_pinbased_ctls_low,
10466 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10467 !vmx_control_verify(vmcs12->vm_exit_controls,
10468 vmx->nested.nested_vmx_exit_ctls_low,
10469 vmx->nested.nested_vmx_exit_ctls_high) ||
10470 !vmx_control_verify(vmcs12->vm_entry_controls,
10471 vmx->nested.nested_vmx_entry_ctls_low,
10472 vmx->nested.nested_vmx_entry_ctls_high))
10473 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10474
10475 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10476 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10477
10478 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10479 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10480 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10481 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10482
10483 return 0;
10484 }
10485
10486 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10487 u32 *exit_qual)
10488 {
10489 bool ia32e;
10490
10491 *exit_qual = ENTRY_FAIL_DEFAULT;
10492
10493 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10494 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10495 return 1;
10496
10497 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10498 vmcs12->vmcs_link_pointer != -1ull) {
10499 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10500 return 1;
10501 }
10502
10503 /*
10504 * If the load IA32_EFER VM-entry control is 1, the following checks
10505 * are performed on the field for the IA32_EFER MSR:
10506 * - Bits reserved in the IA32_EFER MSR must be 0.
10507 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10508 * the IA-32e mode guest VM-exit control. It must also be identical
10509 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10510 * CR0.PG) is 1.
10511 */
10512 if (to_vmx(vcpu)->nested.nested_run_pending &&
10513 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10514 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10515 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10516 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10517 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10518 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10519 return 1;
10520 }
10521
10522 /*
10523 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10524 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10525 * the values of the LMA and LME bits in the field must each be that of
10526 * the host address-space size VM-exit control.
10527 */
10528 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10529 ia32e = (vmcs12->vm_exit_controls &
10530 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10531 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10532 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10533 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10534 return 1;
10535 }
10536
10537 return 0;
10538 }
10539
10540 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10541 {
10542 struct vcpu_vmx *vmx = to_vmx(vcpu);
10543 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10544 struct loaded_vmcs *vmcs02;
10545 u32 msr_entry_idx;
10546 u32 exit_qual;
10547
10548 vmcs02 = nested_get_current_vmcs02(vmx);
10549 if (!vmcs02)
10550 return -ENOMEM;
10551
10552 enter_guest_mode(vcpu);
10553
10554 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10555 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10556
10557 vmx_switch_vmcs(vcpu, vmcs02);
10558 vmx_segment_cache_clear(vmx);
10559
10560 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10561 leave_guest_mode(vcpu);
10562 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10563 nested_vmx_entry_failure(vcpu, vmcs12,
10564 EXIT_REASON_INVALID_STATE, exit_qual);
10565 return 1;
10566 }
10567
10568 nested_get_vmcs12_pages(vcpu, vmcs12);
10569
10570 msr_entry_idx = nested_vmx_load_msr(vcpu,
10571 vmcs12->vm_entry_msr_load_addr,
10572 vmcs12->vm_entry_msr_load_count);
10573 if (msr_entry_idx) {
10574 leave_guest_mode(vcpu);
10575 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10576 nested_vmx_entry_failure(vcpu, vmcs12,
10577 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10578 return 1;
10579 }
10580
10581 /*
10582 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10583 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10584 * returned as far as L1 is concerned. It will only return (and set
10585 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10586 */
10587 return 0;
10588 }
10589
10590 /*
10591 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10592 * for running an L2 nested guest.
10593 */
10594 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10595 {
10596 struct vmcs12 *vmcs12;
10597 struct vcpu_vmx *vmx = to_vmx(vcpu);
10598 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10599 u32 exit_qual;
10600 int ret;
10601
10602 if (!nested_vmx_check_permission(vcpu))
10603 return 1;
10604
10605 if (!nested_vmx_check_vmcs12(vcpu))
10606 goto out;
10607
10608 vmcs12 = get_vmcs12(vcpu);
10609
10610 if (enable_shadow_vmcs)
10611 copy_shadow_to_vmcs12(vmx);
10612
10613 /*
10614 * The nested entry process starts with enforcing various prerequisites
10615 * on vmcs12 as required by the Intel SDM, and act appropriately when
10616 * they fail: As the SDM explains, some conditions should cause the
10617 * instruction to fail, while others will cause the instruction to seem
10618 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10619 * To speed up the normal (success) code path, we should avoid checking
10620 * for misconfigurations which will anyway be caught by the processor
10621 * when using the merged vmcs02.
10622 */
10623 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10624 nested_vmx_failValid(vcpu,
10625 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10626 goto out;
10627 }
10628
10629 if (vmcs12->launch_state == launch) {
10630 nested_vmx_failValid(vcpu,
10631 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10632 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10633 goto out;
10634 }
10635
10636 ret = check_vmentry_prereqs(vcpu, vmcs12);
10637 if (ret) {
10638 nested_vmx_failValid(vcpu, ret);
10639 goto out;
10640 }
10641
10642 /*
10643 * After this point, the trap flag no longer triggers a singlestep trap
10644 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10645 * This is not 100% correct; for performance reasons, we delegate most
10646 * of the checks on host state to the processor. If those fail,
10647 * the singlestep trap is missed.
10648 */
10649 skip_emulated_instruction(vcpu);
10650
10651 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10652 if (ret) {
10653 nested_vmx_entry_failure(vcpu, vmcs12,
10654 EXIT_REASON_INVALID_STATE, exit_qual);
10655 return 1;
10656 }
10657
10658 /*
10659 * We're finally done with prerequisite checking, and can start with
10660 * the nested entry.
10661 */
10662
10663 ret = enter_vmx_non_root_mode(vcpu, true);
10664 if (ret)
10665 return ret;
10666
10667 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10668 return kvm_vcpu_halt(vcpu);
10669
10670 vmx->nested.nested_run_pending = 1;
10671
10672 return 1;
10673
10674 out:
10675 return kvm_skip_emulated_instruction(vcpu);
10676 }
10677
10678 /*
10679 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10680 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10681 * This function returns the new value we should put in vmcs12.guest_cr0.
10682 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10683 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10684 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10685 * didn't trap the bit, because if L1 did, so would L0).
10686 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10687 * been modified by L2, and L1 knows it. So just leave the old value of
10688 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10689 * isn't relevant, because if L0 traps this bit it can set it to anything.
10690 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10691 * changed these bits, and therefore they need to be updated, but L0
10692 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10693 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10694 */
10695 static inline unsigned long
10696 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10697 {
10698 return
10699 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10700 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10701 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10702 vcpu->arch.cr0_guest_owned_bits));
10703 }
10704
10705 static inline unsigned long
10706 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10707 {
10708 return
10709 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10710 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10711 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10712 vcpu->arch.cr4_guest_owned_bits));
10713 }
10714
10715 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10716 struct vmcs12 *vmcs12)
10717 {
10718 u32 idt_vectoring;
10719 unsigned int nr;
10720
10721 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10722 nr = vcpu->arch.exception.nr;
10723 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10724
10725 if (kvm_exception_is_soft(nr)) {
10726 vmcs12->vm_exit_instruction_len =
10727 vcpu->arch.event_exit_inst_len;
10728 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10729 } else
10730 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10731
10732 if (vcpu->arch.exception.has_error_code) {
10733 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10734 vmcs12->idt_vectoring_error_code =
10735 vcpu->arch.exception.error_code;
10736 }
10737
10738 vmcs12->idt_vectoring_info_field = idt_vectoring;
10739 } else if (vcpu->arch.nmi_injected) {
10740 vmcs12->idt_vectoring_info_field =
10741 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10742 } else if (vcpu->arch.interrupt.pending) {
10743 nr = vcpu->arch.interrupt.nr;
10744 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10745
10746 if (vcpu->arch.interrupt.soft) {
10747 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10748 vmcs12->vm_entry_instruction_len =
10749 vcpu->arch.event_exit_inst_len;
10750 } else
10751 idt_vectoring |= INTR_TYPE_EXT_INTR;
10752
10753 vmcs12->idt_vectoring_info_field = idt_vectoring;
10754 }
10755 }
10756
10757 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10758 {
10759 struct vcpu_vmx *vmx = to_vmx(vcpu);
10760
10761 if (vcpu->arch.exception.pending ||
10762 vcpu->arch.nmi_injected ||
10763 vcpu->arch.interrupt.pending)
10764 return -EBUSY;
10765
10766 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10767 vmx->nested.preemption_timer_expired) {
10768 if (vmx->nested.nested_run_pending)
10769 return -EBUSY;
10770 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10771 return 0;
10772 }
10773
10774 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10775 if (vmx->nested.nested_run_pending)
10776 return -EBUSY;
10777 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10778 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10779 INTR_INFO_VALID_MASK, 0);
10780 /*
10781 * The NMI-triggered VM exit counts as injection:
10782 * clear this one and block further NMIs.
10783 */
10784 vcpu->arch.nmi_pending = 0;
10785 vmx_set_nmi_mask(vcpu, true);
10786 return 0;
10787 }
10788
10789 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10790 nested_exit_on_intr(vcpu)) {
10791 if (vmx->nested.nested_run_pending)
10792 return -EBUSY;
10793 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10794 return 0;
10795 }
10796
10797 vmx_complete_nested_posted_interrupt(vcpu);
10798 return 0;
10799 }
10800
10801 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10802 {
10803 ktime_t remaining =
10804 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10805 u64 value;
10806
10807 if (ktime_to_ns(remaining) <= 0)
10808 return 0;
10809
10810 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10811 do_div(value, 1000000);
10812 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10813 }
10814
10815 /*
10816 * Update the guest state fields of vmcs12 to reflect changes that
10817 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10818 * VM-entry controls is also updated, since this is really a guest
10819 * state bit.)
10820 */
10821 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10822 {
10823 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10824 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10825
10826 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10827 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10828 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10829
10830 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10831 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10832 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10833 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10834 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10835 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10836 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10837 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10838 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10839 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10840 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10841 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10842 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10843 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10844 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10845 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10846 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10847 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10848 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10849 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10850 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10851 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10852 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10853 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10854 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10855 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10856 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10857 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10858 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10859 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10860 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10861 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10862 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10863 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10864 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10865 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10866
10867 vmcs12->guest_interruptibility_info =
10868 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10869 vmcs12->guest_pending_dbg_exceptions =
10870 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10871 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10872 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10873 else
10874 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10875
10876 if (nested_cpu_has_preemption_timer(vmcs12)) {
10877 if (vmcs12->vm_exit_controls &
10878 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10879 vmcs12->vmx_preemption_timer_value =
10880 vmx_get_preemption_timer_value(vcpu);
10881 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10882 }
10883
10884 /*
10885 * In some cases (usually, nested EPT), L2 is allowed to change its
10886 * own CR3 without exiting. If it has changed it, we must keep it.
10887 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10888 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10889 *
10890 * Additionally, restore L2's PDPTR to vmcs12.
10891 */
10892 if (enable_ept) {
10893 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10894 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10895 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10896 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10897 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10898 }
10899
10900 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10901
10902 if (nested_cpu_has_vid(vmcs12))
10903 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10904
10905 vmcs12->vm_entry_controls =
10906 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10907 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10908
10909 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10910 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10911 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10912 }
10913
10914 /* TODO: These cannot have changed unless we have MSR bitmaps and
10915 * the relevant bit asks not to trap the change */
10916 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10917 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10918 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10919 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10920 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10921 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10922 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10923 if (kvm_mpx_supported())
10924 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10925 }
10926
10927 /*
10928 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10929 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10930 * and this function updates it to reflect the changes to the guest state while
10931 * L2 was running (and perhaps made some exits which were handled directly by L0
10932 * without going back to L1), and to reflect the exit reason.
10933 * Note that we do not have to copy here all VMCS fields, just those that
10934 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10935 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10936 * which already writes to vmcs12 directly.
10937 */
10938 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10939 u32 exit_reason, u32 exit_intr_info,
10940 unsigned long exit_qualification)
10941 {
10942 /* update guest state fields: */
10943 sync_vmcs12(vcpu, vmcs12);
10944
10945 /* update exit information fields: */
10946
10947 vmcs12->vm_exit_reason = exit_reason;
10948 vmcs12->exit_qualification = exit_qualification;
10949 vmcs12->vm_exit_intr_info = exit_intr_info;
10950
10951 vmcs12->idt_vectoring_info_field = 0;
10952 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10953 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10954
10955 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10956 vmcs12->launch_state = 1;
10957
10958 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10959 * instead of reading the real value. */
10960 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10961
10962 /*
10963 * Transfer the event that L0 or L1 may wanted to inject into
10964 * L2 to IDT_VECTORING_INFO_FIELD.
10965 */
10966 vmcs12_save_pending_event(vcpu, vmcs12);
10967 }
10968
10969 /*
10970 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10971 * preserved above and would only end up incorrectly in L1.
10972 */
10973 vcpu->arch.nmi_injected = false;
10974 kvm_clear_exception_queue(vcpu);
10975 kvm_clear_interrupt_queue(vcpu);
10976 }
10977
10978 /*
10979 * A part of what we need to when the nested L2 guest exits and we want to
10980 * run its L1 parent, is to reset L1's guest state to the host state specified
10981 * in vmcs12.
10982 * This function is to be called not only on normal nested exit, but also on
10983 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10984 * Failures During or After Loading Guest State").
10985 * This function should be called when the active VMCS is L1's (vmcs01).
10986 */
10987 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10988 struct vmcs12 *vmcs12)
10989 {
10990 struct kvm_segment seg;
10991 u32 entry_failure_code;
10992
10993 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10994 vcpu->arch.efer = vmcs12->host_ia32_efer;
10995 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10996 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10997 else
10998 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10999 vmx_set_efer(vcpu, vcpu->arch.efer);
11000
11001 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11002 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11003 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11004 /*
11005 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11006 * actually changed, because vmx_set_cr0 refers to efer set above.
11007 *
11008 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11009 * (KVM doesn't change it);
11010 */
11011 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11012 vmx_set_cr0(vcpu, vmcs12->host_cr0);
11013
11014 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11015 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11016 vmx_set_cr4(vcpu, vmcs12->host_cr4);
11017
11018 nested_ept_uninit_mmu_context(vcpu);
11019
11020 /*
11021 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11022 * couldn't have changed.
11023 */
11024 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11025 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11026
11027 if (!enable_ept)
11028 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11029
11030 if (enable_vpid) {
11031 /*
11032 * Trivially support vpid by letting L2s share their parent
11033 * L1's vpid. TODO: move to a more elaborate solution, giving
11034 * each L2 its own vpid and exposing the vpid feature to L1.
11035 */
11036 vmx_flush_tlb(vcpu);
11037 }
11038 /* Restore posted intr vector. */
11039 if (nested_cpu_has_posted_intr(vmcs12))
11040 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11041
11042 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11043 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11044 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11045 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11046 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11047
11048 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11049 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11050 vmcs_write64(GUEST_BNDCFGS, 0);
11051
11052 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11053 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11054 vcpu->arch.pat = vmcs12->host_ia32_pat;
11055 }
11056 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11057 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11058 vmcs12->host_ia32_perf_global_ctrl);
11059
11060 /* Set L1 segment info according to Intel SDM
11061 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11062 seg = (struct kvm_segment) {
11063 .base = 0,
11064 .limit = 0xFFFFFFFF,
11065 .selector = vmcs12->host_cs_selector,
11066 .type = 11,
11067 .present = 1,
11068 .s = 1,
11069 .g = 1
11070 };
11071 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11072 seg.l = 1;
11073 else
11074 seg.db = 1;
11075 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11076 seg = (struct kvm_segment) {
11077 .base = 0,
11078 .limit = 0xFFFFFFFF,
11079 .type = 3,
11080 .present = 1,
11081 .s = 1,
11082 .db = 1,
11083 .g = 1
11084 };
11085 seg.selector = vmcs12->host_ds_selector;
11086 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11087 seg.selector = vmcs12->host_es_selector;
11088 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11089 seg.selector = vmcs12->host_ss_selector;
11090 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11091 seg.selector = vmcs12->host_fs_selector;
11092 seg.base = vmcs12->host_fs_base;
11093 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11094 seg.selector = vmcs12->host_gs_selector;
11095 seg.base = vmcs12->host_gs_base;
11096 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11097 seg = (struct kvm_segment) {
11098 .base = vmcs12->host_tr_base,
11099 .limit = 0x67,
11100 .selector = vmcs12->host_tr_selector,
11101 .type = 11,
11102 .present = 1
11103 };
11104 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11105
11106 kvm_set_dr(vcpu, 7, 0x400);
11107 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11108
11109 if (cpu_has_vmx_msr_bitmap())
11110 vmx_set_msr_bitmap(vcpu);
11111
11112 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11113 vmcs12->vm_exit_msr_load_count))
11114 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11115 }
11116
11117 /*
11118 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11119 * and modify vmcs12 to make it see what it would expect to see there if
11120 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11121 */
11122 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11123 u32 exit_intr_info,
11124 unsigned long exit_qualification)
11125 {
11126 struct vcpu_vmx *vmx = to_vmx(vcpu);
11127 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11128 u32 vm_inst_error = 0;
11129
11130 /* trying to cancel vmlaunch/vmresume is a bug */
11131 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11132
11133 leave_guest_mode(vcpu);
11134 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11135 exit_qualification);
11136
11137 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11138 vmcs12->vm_exit_msr_store_count))
11139 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11140
11141 if (unlikely(vmx->fail))
11142 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11143
11144 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11145
11146 /*
11147 * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11148 * the VM-exit interrupt information (valid interrupt) is always set to
11149 * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11150 * kvm_cpu_has_interrupt(). See the commit message for details.
11151 */
11152 if (nested_exit_intr_ack_set(vcpu) &&
11153 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11154 kvm_cpu_has_interrupt(vcpu)) {
11155 int irq = kvm_cpu_get_interrupt(vcpu);
11156 WARN_ON(irq < 0);
11157 vmcs12->vm_exit_intr_info = irq |
11158 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11159 }
11160
11161 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11162 vmcs12->exit_qualification,
11163 vmcs12->idt_vectoring_info_field,
11164 vmcs12->vm_exit_intr_info,
11165 vmcs12->vm_exit_intr_error_code,
11166 KVM_ISA_VMX);
11167
11168 vm_entry_controls_reset_shadow(vmx);
11169 vm_exit_controls_reset_shadow(vmx);
11170 vmx_segment_cache_clear(vmx);
11171
11172 /* if no vmcs02 cache requested, remove the one we used */
11173 if (VMCS02_POOL_SIZE == 0)
11174 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11175
11176 load_vmcs12_host_state(vcpu, vmcs12);
11177
11178 /* Update any VMCS fields that might have changed while L2 ran */
11179 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11180 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11181 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11182 if (vmx->hv_deadline_tsc == -1)
11183 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11184 PIN_BASED_VMX_PREEMPTION_TIMER);
11185 else
11186 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11187 PIN_BASED_VMX_PREEMPTION_TIMER);
11188 if (kvm_has_tsc_control)
11189 decache_tsc_multiplier(vmx);
11190
11191 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11192 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11193 vmx_set_virtual_x2apic_mode(vcpu,
11194 vcpu->arch.apic_base & X2APIC_ENABLE);
11195 } else if (!nested_cpu_has_ept(vmcs12) &&
11196 nested_cpu_has2(vmcs12,
11197 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11198 vmx_flush_tlb_ept_only(vcpu);
11199 }
11200
11201 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11202 vmx->host_rsp = 0;
11203
11204 /* Unpin physical memory we referred to in vmcs02 */
11205 if (vmx->nested.apic_access_page) {
11206 nested_release_page(vmx->nested.apic_access_page);
11207 vmx->nested.apic_access_page = NULL;
11208 }
11209 if (vmx->nested.virtual_apic_page) {
11210 nested_release_page(vmx->nested.virtual_apic_page);
11211 vmx->nested.virtual_apic_page = NULL;
11212 }
11213 if (vmx->nested.pi_desc_page) {
11214 kunmap(vmx->nested.pi_desc_page);
11215 nested_release_page(vmx->nested.pi_desc_page);
11216 vmx->nested.pi_desc_page = NULL;
11217 vmx->nested.pi_desc = NULL;
11218 }
11219
11220 /*
11221 * We are now running in L2, mmu_notifier will force to reload the
11222 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11223 */
11224 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11225
11226 /*
11227 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11228 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11229 * success or failure flag accordingly.
11230 */
11231 if (unlikely(vmx->fail)) {
11232 vmx->fail = 0;
11233 nested_vmx_failValid(vcpu, vm_inst_error);
11234 } else
11235 nested_vmx_succeed(vcpu);
11236 if (enable_shadow_vmcs)
11237 vmx->nested.sync_shadow_vmcs = true;
11238
11239 /* in case we halted in L2 */
11240 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11241 }
11242
11243 /*
11244 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11245 */
11246 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11247 {
11248 if (is_guest_mode(vcpu)) {
11249 to_vmx(vcpu)->nested.nested_run_pending = 0;
11250 nested_vmx_vmexit(vcpu, -1, 0, 0);
11251 }
11252 free_nested(to_vmx(vcpu));
11253 }
11254
11255 /*
11256 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11257 * 23.7 "VM-entry failures during or after loading guest state" (this also
11258 * lists the acceptable exit-reason and exit-qualification parameters).
11259 * It should only be called before L2 actually succeeded to run, and when
11260 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11261 */
11262 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11263 struct vmcs12 *vmcs12,
11264 u32 reason, unsigned long qualification)
11265 {
11266 load_vmcs12_host_state(vcpu, vmcs12);
11267 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11268 vmcs12->exit_qualification = qualification;
11269 nested_vmx_succeed(vcpu);
11270 if (enable_shadow_vmcs)
11271 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11272 }
11273
11274 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11275 struct x86_instruction_info *info,
11276 enum x86_intercept_stage stage)
11277 {
11278 return X86EMUL_CONTINUE;
11279 }
11280
11281 #ifdef CONFIG_X86_64
11282 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11283 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11284 u64 divisor, u64 *result)
11285 {
11286 u64 low = a << shift, high = a >> (64 - shift);
11287
11288 /* To avoid the overflow on divq */
11289 if (high >= divisor)
11290 return 1;
11291
11292 /* Low hold the result, high hold rem which is discarded */
11293 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11294 "rm" (divisor), "0" (low), "1" (high));
11295 *result = low;
11296
11297 return 0;
11298 }
11299
11300 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11301 {
11302 struct vcpu_vmx *vmx = to_vmx(vcpu);
11303 u64 tscl = rdtsc();
11304 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11305 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11306
11307 /* Convert to host delta tsc if tsc scaling is enabled */
11308 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11309 u64_shl_div_u64(delta_tsc,
11310 kvm_tsc_scaling_ratio_frac_bits,
11311 vcpu->arch.tsc_scaling_ratio,
11312 &delta_tsc))
11313 return -ERANGE;
11314
11315 /*
11316 * If the delta tsc can't fit in the 32 bit after the multi shift,
11317 * we can't use the preemption timer.
11318 * It's possible that it fits on later vmentries, but checking
11319 * on every vmentry is costly so we just use an hrtimer.
11320 */
11321 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11322 return -ERANGE;
11323
11324 vmx->hv_deadline_tsc = tscl + delta_tsc;
11325 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11326 PIN_BASED_VMX_PREEMPTION_TIMER);
11327
11328 return delta_tsc == 0;
11329 }
11330
11331 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11332 {
11333 struct vcpu_vmx *vmx = to_vmx(vcpu);
11334 vmx->hv_deadline_tsc = -1;
11335 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11336 PIN_BASED_VMX_PREEMPTION_TIMER);
11337 }
11338 #endif
11339
11340 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11341 {
11342 if (ple_gap)
11343 shrink_ple_window(vcpu);
11344 }
11345
11346 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11347 struct kvm_memory_slot *slot)
11348 {
11349 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11350 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11351 }
11352
11353 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11354 struct kvm_memory_slot *slot)
11355 {
11356 kvm_mmu_slot_set_dirty(kvm, slot);
11357 }
11358
11359 static void vmx_flush_log_dirty(struct kvm *kvm)
11360 {
11361 kvm_flush_pml_buffers(kvm);
11362 }
11363
11364 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11365 {
11366 struct vmcs12 *vmcs12;
11367 struct vcpu_vmx *vmx = to_vmx(vcpu);
11368 gpa_t gpa;
11369 struct page *page = NULL;
11370 u64 *pml_address;
11371
11372 if (is_guest_mode(vcpu)) {
11373 WARN_ON_ONCE(vmx->nested.pml_full);
11374
11375 /*
11376 * Check if PML is enabled for the nested guest.
11377 * Whether eptp bit 6 is set is already checked
11378 * as part of A/D emulation.
11379 */
11380 vmcs12 = get_vmcs12(vcpu);
11381 if (!nested_cpu_has_pml(vmcs12))
11382 return 0;
11383
11384 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11385 vmx->nested.pml_full = true;
11386 return 1;
11387 }
11388
11389 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11390
11391 page = nested_get_page(vcpu, vmcs12->pml_address);
11392 if (!page)
11393 return 0;
11394
11395 pml_address = kmap(page);
11396 pml_address[vmcs12->guest_pml_index--] = gpa;
11397 kunmap(page);
11398 nested_release_page_clean(page);
11399 }
11400
11401 return 0;
11402 }
11403
11404 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11405 struct kvm_memory_slot *memslot,
11406 gfn_t offset, unsigned long mask)
11407 {
11408 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11409 }
11410
11411 static void __pi_post_block(struct kvm_vcpu *vcpu)
11412 {
11413 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11414 struct pi_desc old, new;
11415 unsigned int dest;
11416
11417 do {
11418 old.control = new.control = pi_desc->control;
11419 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
11420 "Wakeup handler not enabled while the VCPU is blocked\n");
11421
11422 dest = cpu_physical_id(vcpu->cpu);
11423
11424 if (x2apic_enabled())
11425 new.ndst = dest;
11426 else
11427 new.ndst = (dest << 8) & 0xFF00;
11428
11429 /* set 'NV' to 'notification vector' */
11430 new.nv = POSTED_INTR_VECTOR;
11431 } while (cmpxchg64(&pi_desc->control, old.control,
11432 new.control) != old.control);
11433
11434 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
11435 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11436 list_del(&vcpu->blocked_vcpu_list);
11437 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11438 vcpu->pre_pcpu = -1;
11439 }
11440 }
11441
11442 /*
11443 * This routine does the following things for vCPU which is going
11444 * to be blocked if VT-d PI is enabled.
11445 * - Store the vCPU to the wakeup list, so when interrupts happen
11446 * we can find the right vCPU to wake up.
11447 * - Change the Posted-interrupt descriptor as below:
11448 * 'NDST' <-- vcpu->pre_pcpu
11449 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11450 * - If 'ON' is set during this process, which means at least one
11451 * interrupt is posted for this vCPU, we cannot block it, in
11452 * this case, return 1, otherwise, return 0.
11453 *
11454 */
11455 static int pi_pre_block(struct kvm_vcpu *vcpu)
11456 {
11457 unsigned int dest;
11458 struct pi_desc old, new;
11459 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11460
11461 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11462 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11463 !kvm_vcpu_apicv_active(vcpu))
11464 return 0;
11465
11466 WARN_ON(irqs_disabled());
11467 local_irq_disable();
11468 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
11469 vcpu->pre_pcpu = vcpu->cpu;
11470 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11471 list_add_tail(&vcpu->blocked_vcpu_list,
11472 &per_cpu(blocked_vcpu_on_cpu,
11473 vcpu->pre_pcpu));
11474 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11475 }
11476
11477 do {
11478 old.control = new.control = pi_desc->control;
11479
11480 WARN((pi_desc->sn == 1),
11481 "Warning: SN field of posted-interrupts "
11482 "is set before blocking\n");
11483
11484 /*
11485 * Since vCPU can be preempted during this process,
11486 * vcpu->cpu could be different with pre_pcpu, we
11487 * need to set pre_pcpu as the destination of wakeup
11488 * notification event, then we can find the right vCPU
11489 * to wakeup in wakeup handler if interrupts happen
11490 * when the vCPU is in blocked state.
11491 */
11492 dest = cpu_physical_id(vcpu->pre_pcpu);
11493
11494 if (x2apic_enabled())
11495 new.ndst = dest;
11496 else
11497 new.ndst = (dest << 8) & 0xFF00;
11498
11499 /* set 'NV' to 'wakeup vector' */
11500 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11501 } while (cmpxchg64(&pi_desc->control, old.control,
11502 new.control) != old.control);
11503
11504 /* We should not block the vCPU if an interrupt is posted for it. */
11505 if (pi_test_on(pi_desc) == 1)
11506 __pi_post_block(vcpu);
11507
11508 local_irq_enable();
11509 return (vcpu->pre_pcpu == -1);
11510 }
11511
11512 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11513 {
11514 if (pi_pre_block(vcpu))
11515 return 1;
11516
11517 if (kvm_lapic_hv_timer_in_use(vcpu))
11518 kvm_lapic_switch_to_sw_timer(vcpu);
11519
11520 return 0;
11521 }
11522
11523 static void pi_post_block(struct kvm_vcpu *vcpu)
11524 {
11525 if (vcpu->pre_pcpu == -1)
11526 return;
11527
11528 WARN_ON(irqs_disabled());
11529 local_irq_disable();
11530 __pi_post_block(vcpu);
11531 local_irq_enable();
11532 }
11533
11534 static void vmx_post_block(struct kvm_vcpu *vcpu)
11535 {
11536 if (kvm_x86_ops->set_hv_timer)
11537 kvm_lapic_switch_to_hv_timer(vcpu);
11538
11539 pi_post_block(vcpu);
11540 }
11541
11542 /*
11543 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11544 *
11545 * @kvm: kvm
11546 * @host_irq: host irq of the interrupt
11547 * @guest_irq: gsi of the interrupt
11548 * @set: set or unset PI
11549 * returns 0 on success, < 0 on failure
11550 */
11551 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11552 uint32_t guest_irq, bool set)
11553 {
11554 struct kvm_kernel_irq_routing_entry *e;
11555 struct kvm_irq_routing_table *irq_rt;
11556 struct kvm_lapic_irq irq;
11557 struct kvm_vcpu *vcpu;
11558 struct vcpu_data vcpu_info;
11559 int idx, ret = 0;
11560
11561 if (!kvm_arch_has_assigned_device(kvm) ||
11562 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11563 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11564 return 0;
11565
11566 idx = srcu_read_lock(&kvm->irq_srcu);
11567 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11568 if (guest_irq >= irq_rt->nr_rt_entries ||
11569 hlist_empty(&irq_rt->map[guest_irq])) {
11570 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11571 guest_irq, irq_rt->nr_rt_entries);
11572 goto out;
11573 }
11574
11575 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11576 if (e->type != KVM_IRQ_ROUTING_MSI)
11577 continue;
11578 /*
11579 * VT-d PI cannot support posting multicast/broadcast
11580 * interrupts to a vCPU, we still use interrupt remapping
11581 * for these kind of interrupts.
11582 *
11583 * For lowest-priority interrupts, we only support
11584 * those with single CPU as the destination, e.g. user
11585 * configures the interrupts via /proc/irq or uses
11586 * irqbalance to make the interrupts single-CPU.
11587 *
11588 * We will support full lowest-priority interrupt later.
11589 */
11590
11591 kvm_set_msi_irq(kvm, e, &irq);
11592 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11593 /*
11594 * Make sure the IRTE is in remapped mode if
11595 * we don't handle it in posted mode.
11596 */
11597 ret = irq_set_vcpu_affinity(host_irq, NULL);
11598 if (ret < 0) {
11599 printk(KERN_INFO
11600 "failed to back to remapped mode, irq: %u\n",
11601 host_irq);
11602 goto out;
11603 }
11604
11605 continue;
11606 }
11607
11608 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11609 vcpu_info.vector = irq.vector;
11610
11611 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11612 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11613
11614 if (set)
11615 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11616 else
11617 ret = irq_set_vcpu_affinity(host_irq, NULL);
11618
11619 if (ret < 0) {
11620 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11621 __func__);
11622 goto out;
11623 }
11624 }
11625
11626 ret = 0;
11627 out:
11628 srcu_read_unlock(&kvm->irq_srcu, idx);
11629 return ret;
11630 }
11631
11632 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11633 {
11634 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11635 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11636 FEATURE_CONTROL_LMCE;
11637 else
11638 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11639 ~FEATURE_CONTROL_LMCE;
11640 }
11641
11642 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11643 .cpu_has_kvm_support = cpu_has_kvm_support,
11644 .disabled_by_bios = vmx_disabled_by_bios,
11645 .hardware_setup = hardware_setup,
11646 .hardware_unsetup = hardware_unsetup,
11647 .check_processor_compatibility = vmx_check_processor_compat,
11648 .hardware_enable = hardware_enable,
11649 .hardware_disable = hardware_disable,
11650 .cpu_has_accelerated_tpr = report_flexpriority,
11651 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11652
11653 .vcpu_create = vmx_create_vcpu,
11654 .vcpu_free = vmx_free_vcpu,
11655 .vcpu_reset = vmx_vcpu_reset,
11656
11657 .prepare_guest_switch = vmx_save_host_state,
11658 .vcpu_load = vmx_vcpu_load,
11659 .vcpu_put = vmx_vcpu_put,
11660
11661 .update_bp_intercept = update_exception_bitmap,
11662 .get_msr = vmx_get_msr,
11663 .set_msr = vmx_set_msr,
11664 .get_segment_base = vmx_get_segment_base,
11665 .get_segment = vmx_get_segment,
11666 .set_segment = vmx_set_segment,
11667 .get_cpl = vmx_get_cpl,
11668 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11669 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11670 .decache_cr3 = vmx_decache_cr3,
11671 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11672 .set_cr0 = vmx_set_cr0,
11673 .set_cr3 = vmx_set_cr3,
11674 .set_cr4 = vmx_set_cr4,
11675 .set_efer = vmx_set_efer,
11676 .get_idt = vmx_get_idt,
11677 .set_idt = vmx_set_idt,
11678 .get_gdt = vmx_get_gdt,
11679 .set_gdt = vmx_set_gdt,
11680 .get_dr6 = vmx_get_dr6,
11681 .set_dr6 = vmx_set_dr6,
11682 .set_dr7 = vmx_set_dr7,
11683 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11684 .cache_reg = vmx_cache_reg,
11685 .get_rflags = vmx_get_rflags,
11686 .set_rflags = vmx_set_rflags,
11687
11688 .tlb_flush = vmx_flush_tlb,
11689
11690 .run = vmx_vcpu_run,
11691 .handle_exit = vmx_handle_exit,
11692 .skip_emulated_instruction = skip_emulated_instruction,
11693 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11694 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11695 .patch_hypercall = vmx_patch_hypercall,
11696 .set_irq = vmx_inject_irq,
11697 .set_nmi = vmx_inject_nmi,
11698 .queue_exception = vmx_queue_exception,
11699 .cancel_injection = vmx_cancel_injection,
11700 .interrupt_allowed = vmx_interrupt_allowed,
11701 .nmi_allowed = vmx_nmi_allowed,
11702 .get_nmi_mask = vmx_get_nmi_mask,
11703 .set_nmi_mask = vmx_set_nmi_mask,
11704 .enable_nmi_window = enable_nmi_window,
11705 .enable_irq_window = enable_irq_window,
11706 .update_cr8_intercept = update_cr8_intercept,
11707 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11708 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11709 .get_enable_apicv = vmx_get_enable_apicv,
11710 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11711 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11712 .apicv_post_state_restore = vmx_apicv_post_state_restore,
11713 .hwapic_irr_update = vmx_hwapic_irr_update,
11714 .hwapic_isr_update = vmx_hwapic_isr_update,
11715 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11716 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11717
11718 .set_tss_addr = vmx_set_tss_addr,
11719 .get_tdp_level = get_ept_level,
11720 .get_mt_mask = vmx_get_mt_mask,
11721
11722 .get_exit_info = vmx_get_exit_info,
11723
11724 .get_lpage_level = vmx_get_lpage_level,
11725
11726 .cpuid_update = vmx_cpuid_update,
11727
11728 .rdtscp_supported = vmx_rdtscp_supported,
11729 .invpcid_supported = vmx_invpcid_supported,
11730
11731 .set_supported_cpuid = vmx_set_supported_cpuid,
11732
11733 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11734
11735 .write_tsc_offset = vmx_write_tsc_offset,
11736
11737 .set_tdp_cr3 = vmx_set_cr3,
11738
11739 .check_intercept = vmx_check_intercept,
11740 .handle_external_intr = vmx_handle_external_intr,
11741 .mpx_supported = vmx_mpx_supported,
11742 .xsaves_supported = vmx_xsaves_supported,
11743
11744 .check_nested_events = vmx_check_nested_events,
11745
11746 .sched_in = vmx_sched_in,
11747
11748 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11749 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11750 .flush_log_dirty = vmx_flush_log_dirty,
11751 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11752 .write_log_dirty = vmx_write_pml_buffer,
11753
11754 .pre_block = vmx_pre_block,
11755 .post_block = vmx_post_block,
11756
11757 .pmu_ops = &intel_pmu_ops,
11758
11759 .update_pi_irte = vmx_update_pi_irte,
11760
11761 #ifdef CONFIG_X86_64
11762 .set_hv_timer = vmx_set_hv_timer,
11763 .cancel_hv_timer = vmx_cancel_hv_timer,
11764 #endif
11765
11766 .setup_mce = vmx_setup_mce,
11767 };
11768
11769 static int __init vmx_init(void)
11770 {
11771 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11772 __alignof__(struct vcpu_vmx), THIS_MODULE);
11773 if (r)
11774 return r;
11775
11776 #ifdef CONFIG_KEXEC_CORE
11777 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11778 crash_vmclear_local_loaded_vmcss);
11779 #endif
11780
11781 return 0;
11782 }
11783
11784 static void __exit vmx_exit(void)
11785 {
11786 #ifdef CONFIG_KEXEC_CORE
11787 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11788 synchronize_rcu();
11789 #endif
11790
11791 kvm_exit();
11792 }
11793
11794 module_init(vmx_init)
11795 module_exit(vmx_exit)
Linux with added FPC-III support