Linux 4.13.16
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blob272320eb328c9bc8c2d0cf839a097a30ca27491f
1 /*
2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
58 #include <trace/events/kvm.h>
60 #include <asm/debugreg.h>
61 #include <asm/msr.h>
62 #include <asm/desc.h>
63 #include <asm/mce.h>
64 #include <linux/kernel_stat.h>
65 #include <asm/fpu/internal.h> /* Ugh! */
66 #include <asm/pvclock.h>
67 #include <asm/div64.h>
68 #include <asm/irq_remapping.h>
70 #define CREATE_TRACE_POINTS
71 #include "trace.h"
73 #define MAX_IO_MSRS 256
74 #define KVM_MAX_MCE_BANKS 32
75 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78 #define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81 /* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
85 #ifdef CONFIG_X86_64
86 static
87 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
88 #else
89 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
90 #endif
92 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
99 static void process_nmi(struct kvm_vcpu *vcpu);
100 static void enter_smm(struct kvm_vcpu *vcpu);
101 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
104 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106 static bool __read_mostly ignore_msrs = 0;
107 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109 unsigned int min_timer_period_us = 500;
110 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112 static bool __read_mostly kvmclock_periodic_sync = true;
113 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115 bool __read_mostly kvm_has_tsc_control;
116 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
117 u32 __read_mostly kvm_max_guest_tsc_khz;
118 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
119 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121 u64 __read_mostly kvm_max_tsc_scaling_ratio;
122 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
123 u64 __read_mostly kvm_default_tsc_scaling_ratio;
124 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
126 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
127 static u32 __read_mostly tsc_tolerance_ppm = 250;
128 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
131 unsigned int __read_mostly lapic_timer_advance_ns = 0;
132 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134 static bool __read_mostly vector_hashing = true;
135 module_param(vector_hashing, bool, S_IRUGO);
137 #define KVM_NR_SHARED_MSRS 16
139 struct kvm_shared_msrs_global {
140 int nr;
141 u32 msrs[KVM_NR_SHARED_MSRS];
144 struct kvm_shared_msrs {
145 struct user_return_notifier urn;
146 bool registered;
147 struct kvm_shared_msr_values {
148 u64 host;
149 u64 curr;
150 } values[KVM_NR_SHARED_MSRS];
153 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
154 static struct kvm_shared_msrs __percpu *shared_msrs;
156 struct kvm_stats_debugfs_item debugfs_entries[] = {
157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
167 { "halt_exits", VCPU_STAT(halt_exits) },
168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
172 { "hypercalls", VCPU_STAT(hypercalls) },
173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
180 { "irq_injections", VCPU_STAT(irq_injections) },
181 { "nmi_injections", VCPU_STAT(nmi_injections) },
182 { "req_event", VCPU_STAT(req_event) },
183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
190 { "mmu_unsync", VM_STAT(mmu_unsync) },
191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
192 { "largepages", VM_STAT(lpages) },
193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
195 { NULL }
198 u64 __read_mostly host_xcr0;
200 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
202 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
209 static void kvm_on_user_return(struct user_return_notifier *urn)
211 unsigned slot;
212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
214 struct kvm_shared_msr_values *values;
215 unsigned long flags;
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
226 local_irq_restore(flags);
227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
236 static void shared_msr_update(unsigned slot, u32 msr)
238 u64 value;
239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
253 void kvm_define_shared_msr(unsigned slot, u32 msr)
255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
256 shared_msrs_global.msrs[slot] = msr;
257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
260 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262 static void kvm_shared_msr_cpu_online(void)
264 unsigned i;
266 for (i = 0; i < shared_msrs_global.nr; ++i)
267 shared_msr_update(i, shared_msrs_global.msrs[i]);
270 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
274 int err;
276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
277 return 0;
278 smsr->values[slot].curr = value;
279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
288 return 0;
290 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292 static void drop_user_return_notifiers(void)
294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
301 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303 return vcpu->arch.apic_base;
305 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
314 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
316 if (!msr_info->host_initiated &&
317 ((msr_info->data & reserved_bits) != 0 ||
318 new_state == X2APIC_ENABLE ||
319 (new_state == MSR_IA32_APICBASE_ENABLE &&
320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
328 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330 asmlinkage __visible void kvm_spurious_fault(void)
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
335 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337 #define EXCPT_BENIGN 0
338 #define EXCPT_CONTRIBUTORY 1
339 #define EXCPT_PF 2
341 static int exception_class(int vector)
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
355 return EXCPT_BENIGN;
358 #define EXCPT_FAULT 0
359 #define EXCPT_TRAP 1
360 #define EXCPT_ABORT 2
361 #define EXCPT_INTERRUPT 3
363 static int exception_type(int vector)
365 unsigned int mask;
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
370 mask = 1 << vector;
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
383 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
387 u32 prev_nr;
388 int class1, class2;
390 kvm_make_request(KVM_REQ_EVENT, vcpu);
392 if (!vcpu->arch.exception.pending) {
393 queue:
394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
400 vcpu->arch.exception.reinject = reinject;
401 return;
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
409 return;
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
427 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
429 kvm_multiple_exception(vcpu, nr, false, 0, false);
431 EXPORT_SYMBOL_GPL(kvm_queue_exception);
433 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
437 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
439 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
444 return kvm_skip_emulated_instruction(vcpu);
446 return 1;
448 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
450 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
452 ++vcpu->stat.pf_guest;
453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
457 else
458 vcpu->arch.cr2 = fault->address;
459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
461 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
463 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
467 else
468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
470 return fault->nested_page_fault;
473 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
478 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
480 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
484 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
486 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
490 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
496 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
499 return true;
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
501 return false;
503 EXPORT_SYMBOL_GPL(kvm_require_cpl);
505 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
508 return true;
510 kvm_queue_exception(vcpu, UD_VECTOR);
511 return false;
513 EXPORT_SYMBOL_GPL(kvm_require_dr);
516 * This function will be used to read from the physical memory of the currently
517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
518 * can read from guest physical or from the guest's guest physical memory.
520 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
522 u32 access)
524 struct x86_exception exception;
525 gfn_t real_gfn;
526 gpa_t ngpa;
528 ngpa = gfn_to_gpa(ngfn);
529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
530 if (real_gfn == UNMAPPED_GVA)
531 return -EFAULT;
533 real_gfn = gpa_to_gfn(real_gfn);
535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
537 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
539 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
540 void *data, int offset, int len, u32 access)
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
547 * Load the pae pdptrs. Return true is they are all valid.
549 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
553 int i;
554 int ret;
555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
560 if (ret < 0) {
561 ret = 0;
562 goto out;
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
565 if ((pdpte[i] & PT_PRESENT_MASK) &&
566 (pdpte[i] &
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
568 ret = 0;
569 goto out;
572 ret = 1;
574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
579 out:
581 return ret;
583 EXPORT_SYMBOL_GPL(load_pdptrs);
585 bool pdptrs_changed(struct kvm_vcpu *vcpu)
587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
588 bool changed = true;
589 int offset;
590 gfn_t gfn;
591 int r;
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
594 return false;
596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
598 return true;
600 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
604 if (r < 0)
605 goto out;
606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
607 out:
609 return changed;
611 EXPORT_SYMBOL_GPL(pdptrs_changed);
613 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
618 cr0 |= X86_CR0_ET;
620 #ifdef CONFIG_X86_64
621 if (cr0 & 0xffffffff00000000UL)
622 return 1;
623 #endif
625 cr0 &= ~CR0_RESERVED_BITS;
627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
628 return 1;
630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
631 return 1;
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
634 #ifdef CONFIG_X86_64
635 if ((vcpu->arch.efer & EFER_LME)) {
636 int cs_db, cs_l;
638 if (!is_pae(vcpu))
639 return 1;
640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
641 if (cs_l)
642 return 1;
643 } else
644 #endif
645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
646 kvm_read_cr3(vcpu)))
647 return 1;
650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
651 return 1;
653 kvm_x86_ops->set_cr0(vcpu, cr0);
655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
656 kvm_clear_async_pf_completion_queue(vcpu);
657 kvm_async_pf_hash_reset(vcpu);
660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
668 return 0;
670 EXPORT_SYMBOL_GPL(kvm_set_cr0);
672 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
676 EXPORT_SYMBOL_GPL(kvm_lmsw);
678 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
688 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
697 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
699 u64 xcr0 = xcr;
700 u64 old_xcr0 = vcpu->arch.xcr0;
701 u64 valid_bits;
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
705 return 1;
706 if (!(xcr0 & XFEATURE_MASK_FP))
707 return 1;
708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
709 return 1;
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
717 if (xcr0 & ~valid_bits)
718 return 1;
720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
722 return 1;
724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
726 return 1;
727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
728 return 1;
730 vcpu->arch.xcr0 = xcr0;
732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
733 kvm_update_cpuid(vcpu);
734 return 0;
737 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
741 kvm_inject_gp(vcpu, 0);
742 return 1;
744 return 0;
746 EXPORT_SYMBOL_GPL(kvm_set_xcr);
748 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
754 if (cr4 & CR4_RESERVED_BITS)
755 return 1;
757 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
758 return 1;
760 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
761 return 1;
763 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
764 return 1;
766 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
767 return 1;
769 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
770 return 1;
772 if (is_long_mode(vcpu)) {
773 if (!(cr4 & X86_CR4_PAE))
774 return 1;
775 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
776 && ((cr4 ^ old_cr4) & pdptr_bits)
777 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
778 kvm_read_cr3(vcpu)))
779 return 1;
781 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
782 if (!guest_cpuid_has_pcid(vcpu))
783 return 1;
785 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
786 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
787 return 1;
790 if (kvm_x86_ops->set_cr4(vcpu, cr4))
791 return 1;
793 if (((cr4 ^ old_cr4) & pdptr_bits) ||
794 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
795 kvm_mmu_reset_context(vcpu);
797 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
798 kvm_update_cpuid(vcpu);
800 return 0;
802 EXPORT_SYMBOL_GPL(kvm_set_cr4);
804 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
806 #ifdef CONFIG_X86_64
807 cr3 &= ~CR3_PCID_INVD;
808 #endif
810 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
811 kvm_mmu_sync_roots(vcpu);
812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
813 return 0;
816 if (is_long_mode(vcpu)) {
817 if (cr3 & CR3_L_MODE_RESERVED_BITS)
818 return 1;
819 } else if (is_pae(vcpu) && is_paging(vcpu) &&
820 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
821 return 1;
823 vcpu->arch.cr3 = cr3;
824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
825 kvm_mmu_new_cr3(vcpu);
826 return 0;
828 EXPORT_SYMBOL_GPL(kvm_set_cr3);
830 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
832 if (cr8 & CR8_RESERVED_BITS)
833 return 1;
834 if (lapic_in_kernel(vcpu))
835 kvm_lapic_set_tpr(vcpu, cr8);
836 else
837 vcpu->arch.cr8 = cr8;
838 return 0;
840 EXPORT_SYMBOL_GPL(kvm_set_cr8);
842 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
844 if (lapic_in_kernel(vcpu))
845 return kvm_lapic_get_cr8(vcpu);
846 else
847 return vcpu->arch.cr8;
849 EXPORT_SYMBOL_GPL(kvm_get_cr8);
851 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
853 int i;
855 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
856 for (i = 0; i < KVM_NR_DB_REGS; i++)
857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
862 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
868 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
870 unsigned long dr7;
872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
873 dr7 = vcpu->arch.guest_debug_dr7;
874 else
875 dr7 = vcpu->arch.dr7;
876 kvm_x86_ops->set_dr7(vcpu, dr7);
877 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
878 if (dr7 & DR7_BP_EN_MASK)
879 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
882 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
884 u64 fixed = DR6_FIXED_1;
886 if (!guest_cpuid_has_rtm(vcpu))
887 fixed |= DR6_RTM;
888 return fixed;
891 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
893 switch (dr) {
894 case 0 ... 3:
895 vcpu->arch.db[dr] = val;
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 vcpu->arch.eff_db[dr] = val;
898 break;
899 case 4:
900 /* fall through */
901 case 6:
902 if (val & 0xffffffff00000000ULL)
903 return -1; /* #GP */
904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
905 kvm_update_dr6(vcpu);
906 break;
907 case 5:
908 /* fall through */
909 default: /* 7 */
910 if (val & 0xffffffff00000000ULL)
911 return -1; /* #GP */
912 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
913 kvm_update_dr7(vcpu);
914 break;
917 return 0;
920 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
922 if (__kvm_set_dr(vcpu, dr, val)) {
923 kvm_inject_gp(vcpu, 0);
924 return 1;
926 return 0;
928 EXPORT_SYMBOL_GPL(kvm_set_dr);
930 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
932 switch (dr) {
933 case 0 ... 3:
934 *val = vcpu->arch.db[dr];
935 break;
936 case 4:
937 /* fall through */
938 case 6:
939 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
940 *val = vcpu->arch.dr6;
941 else
942 *val = kvm_x86_ops->get_dr6(vcpu);
943 break;
944 case 5:
945 /* fall through */
946 default: /* 7 */
947 *val = vcpu->arch.dr7;
948 break;
950 return 0;
952 EXPORT_SYMBOL_GPL(kvm_get_dr);
954 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
956 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
957 u64 data;
958 int err;
960 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
961 if (err)
962 return err;
963 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
964 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
965 return err;
967 EXPORT_SYMBOL_GPL(kvm_rdpmc);
970 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
971 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
973 * This list is modified at module load time to reflect the
974 * capabilities of the host cpu. This capabilities test skips MSRs that are
975 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
976 * may depend on host virtualization features rather than host cpu features.
979 static u32 msrs_to_save[] = {
980 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
981 MSR_STAR,
982 #ifdef CONFIG_X86_64
983 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
984 #endif
985 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
986 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
989 static unsigned num_msrs_to_save;
991 static u32 emulated_msrs[] = {
992 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
993 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
994 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
995 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
996 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
997 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
998 HV_X64_MSR_RESET,
999 HV_X64_MSR_VP_INDEX,
1000 HV_X64_MSR_VP_RUNTIME,
1001 HV_X64_MSR_SCONTROL,
1002 HV_X64_MSR_STIMER0_CONFIG,
1003 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1004 MSR_KVM_PV_EOI_EN,
1006 MSR_IA32_TSC_ADJUST,
1007 MSR_IA32_TSCDEADLINE,
1008 MSR_IA32_MISC_ENABLE,
1009 MSR_IA32_MCG_STATUS,
1010 MSR_IA32_MCG_CTL,
1011 MSR_IA32_MCG_EXT_CTL,
1012 MSR_IA32_SMBASE,
1013 MSR_PLATFORM_INFO,
1014 MSR_MISC_FEATURES_ENABLES,
1017 static unsigned num_emulated_msrs;
1019 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1021 if (efer & efer_reserved_bits)
1022 return false;
1024 if (efer & EFER_FFXSR) {
1025 struct kvm_cpuid_entry2 *feat;
1027 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1028 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1029 return false;
1032 if (efer & EFER_SVME) {
1033 struct kvm_cpuid_entry2 *feat;
1035 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1036 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1037 return false;
1040 return true;
1042 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1044 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1046 u64 old_efer = vcpu->arch.efer;
1048 if (!kvm_valid_efer(vcpu, efer))
1049 return 1;
1051 if (is_paging(vcpu)
1052 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1053 return 1;
1055 efer &= ~EFER_LMA;
1056 efer |= vcpu->arch.efer & EFER_LMA;
1058 kvm_x86_ops->set_efer(vcpu, efer);
1060 /* Update reserved bits */
1061 if ((efer ^ old_efer) & EFER_NX)
1062 kvm_mmu_reset_context(vcpu);
1064 return 0;
1067 void kvm_enable_efer_bits(u64 mask)
1069 efer_reserved_bits &= ~mask;
1071 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1074 * Writes msr value into into the appropriate "register".
1075 * Returns 0 on success, non-0 otherwise.
1076 * Assumes vcpu_load() was already called.
1078 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1080 switch (msr->index) {
1081 case MSR_FS_BASE:
1082 case MSR_GS_BASE:
1083 case MSR_KERNEL_GS_BASE:
1084 case MSR_CSTAR:
1085 case MSR_LSTAR:
1086 if (is_noncanonical_address(msr->data))
1087 return 1;
1088 break;
1089 case MSR_IA32_SYSENTER_EIP:
1090 case MSR_IA32_SYSENTER_ESP:
1092 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1093 * non-canonical address is written on Intel but not on
1094 * AMD (which ignores the top 32-bits, because it does
1095 * not implement 64-bit SYSENTER).
1097 * 64-bit code should hence be able to write a non-canonical
1098 * value on AMD. Making the address canonical ensures that
1099 * vmentry does not fail on Intel after writing a non-canonical
1100 * value, and that something deterministic happens if the guest
1101 * invokes 64-bit SYSENTER.
1103 msr->data = get_canonical(msr->data);
1105 return kvm_x86_ops->set_msr(vcpu, msr);
1107 EXPORT_SYMBOL_GPL(kvm_set_msr);
1110 * Adapt set_msr() to msr_io()'s calling convention
1112 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1114 struct msr_data msr;
1115 int r;
1117 msr.index = index;
1118 msr.host_initiated = true;
1119 r = kvm_get_msr(vcpu, &msr);
1120 if (r)
1121 return r;
1123 *data = msr.data;
1124 return 0;
1127 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1129 struct msr_data msr;
1131 msr.data = *data;
1132 msr.index = index;
1133 msr.host_initiated = true;
1134 return kvm_set_msr(vcpu, &msr);
1137 #ifdef CONFIG_X86_64
1138 struct pvclock_gtod_data {
1139 seqcount_t seq;
1141 struct { /* extract of a clocksource struct */
1142 int vclock_mode;
1143 u64 cycle_last;
1144 u64 mask;
1145 u32 mult;
1146 u32 shift;
1147 } clock;
1149 u64 boot_ns;
1150 u64 nsec_base;
1151 u64 wall_time_sec;
1154 static struct pvclock_gtod_data pvclock_gtod_data;
1156 static void update_pvclock_gtod(struct timekeeper *tk)
1158 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1159 u64 boot_ns;
1161 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1163 write_seqcount_begin(&vdata->seq);
1165 /* copy pvclock gtod data */
1166 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1167 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1168 vdata->clock.mask = tk->tkr_mono.mask;
1169 vdata->clock.mult = tk->tkr_mono.mult;
1170 vdata->clock.shift = tk->tkr_mono.shift;
1172 vdata->boot_ns = boot_ns;
1173 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1175 vdata->wall_time_sec = tk->xtime_sec;
1177 write_seqcount_end(&vdata->seq);
1179 #endif
1181 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1184 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1185 * vcpu_enter_guest. This function is only called from
1186 * the physical CPU that is running vcpu.
1188 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1191 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1193 int version;
1194 int r;
1195 struct pvclock_wall_clock wc;
1196 struct timespec64 boot;
1198 if (!wall_clock)
1199 return;
1201 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1202 if (r)
1203 return;
1205 if (version & 1)
1206 ++version; /* first time write, random junk */
1208 ++version;
1210 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1211 return;
1214 * The guest calculates current wall clock time by adding
1215 * system time (updated by kvm_guest_time_update below) to the
1216 * wall clock specified here. guest system time equals host
1217 * system time for us, thus we must fill in host boot time here.
1219 getboottime64(&boot);
1221 if (kvm->arch.kvmclock_offset) {
1222 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1223 boot = timespec64_sub(boot, ts);
1225 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1226 wc.nsec = boot.tv_nsec;
1227 wc.version = version;
1229 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1231 version++;
1232 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1235 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1237 do_shl32_div32(dividend, divisor);
1238 return dividend;
1241 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1242 s8 *pshift, u32 *pmultiplier)
1244 uint64_t scaled64;
1245 int32_t shift = 0;
1246 uint64_t tps64;
1247 uint32_t tps32;
1249 tps64 = base_hz;
1250 scaled64 = scaled_hz;
1251 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1252 tps64 >>= 1;
1253 shift--;
1256 tps32 = (uint32_t)tps64;
1257 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1258 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1259 scaled64 >>= 1;
1260 else
1261 tps32 <<= 1;
1262 shift++;
1265 *pshift = shift;
1266 *pmultiplier = div_frac(scaled64, tps32);
1268 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1269 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1272 #ifdef CONFIG_X86_64
1273 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1274 #endif
1276 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1277 static unsigned long max_tsc_khz;
1279 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1281 u64 v = (u64)khz * (1000000 + ppm);
1282 do_div(v, 1000000);
1283 return v;
1286 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1288 u64 ratio;
1290 /* Guest TSC same frequency as host TSC? */
1291 if (!scale) {
1292 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1293 return 0;
1296 /* TSC scaling supported? */
1297 if (!kvm_has_tsc_control) {
1298 if (user_tsc_khz > tsc_khz) {
1299 vcpu->arch.tsc_catchup = 1;
1300 vcpu->arch.tsc_always_catchup = 1;
1301 return 0;
1302 } else {
1303 WARN(1, "user requested TSC rate below hardware speed\n");
1304 return -1;
1308 /* TSC scaling required - calculate ratio */
1309 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1310 user_tsc_khz, tsc_khz);
1312 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1313 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1314 user_tsc_khz);
1315 return -1;
1318 vcpu->arch.tsc_scaling_ratio = ratio;
1319 return 0;
1322 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1324 u32 thresh_lo, thresh_hi;
1325 int use_scaling = 0;
1327 /* tsc_khz can be zero if TSC calibration fails */
1328 if (user_tsc_khz == 0) {
1329 /* set tsc_scaling_ratio to a safe value */
1330 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1331 return -1;
1334 /* Compute a scale to convert nanoseconds in TSC cycles */
1335 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1336 &vcpu->arch.virtual_tsc_shift,
1337 &vcpu->arch.virtual_tsc_mult);
1338 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1341 * Compute the variation in TSC rate which is acceptable
1342 * within the range of tolerance and decide if the
1343 * rate being applied is within that bounds of the hardware
1344 * rate. If so, no scaling or compensation need be done.
1346 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1347 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1348 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1349 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1350 use_scaling = 1;
1352 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1355 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1357 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1358 vcpu->arch.virtual_tsc_mult,
1359 vcpu->arch.virtual_tsc_shift);
1360 tsc += vcpu->arch.this_tsc_write;
1361 return tsc;
1364 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1366 #ifdef CONFIG_X86_64
1367 bool vcpus_matched;
1368 struct kvm_arch *ka = &vcpu->kvm->arch;
1369 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1371 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1372 atomic_read(&vcpu->kvm->online_vcpus));
1375 * Once the masterclock is enabled, always perform request in
1376 * order to update it.
1378 * In order to enable masterclock, the host clocksource must be TSC
1379 * and the vcpus need to have matched TSCs. When that happens,
1380 * perform request to enable masterclock.
1382 if (ka->use_master_clock ||
1383 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1384 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1386 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1387 atomic_read(&vcpu->kvm->online_vcpus),
1388 ka->use_master_clock, gtod->clock.vclock_mode);
1389 #endif
1392 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1394 u64 curr_offset = vcpu->arch.tsc_offset;
1395 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1399 * Multiply tsc by a fixed point number represented by ratio.
1401 * The most significant 64-N bits (mult) of ratio represent the
1402 * integral part of the fixed point number; the remaining N bits
1403 * (frac) represent the fractional part, ie. ratio represents a fixed
1404 * point number (mult + frac * 2^(-N)).
1406 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1408 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1410 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1413 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1415 u64 _tsc = tsc;
1416 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1418 if (ratio != kvm_default_tsc_scaling_ratio)
1419 _tsc = __scale_tsc(ratio, tsc);
1421 return _tsc;
1423 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1425 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1427 u64 tsc;
1429 tsc = kvm_scale_tsc(vcpu, rdtsc());
1431 return target_tsc - tsc;
1434 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1436 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1438 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1440 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1442 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1443 vcpu->arch.tsc_offset = offset;
1446 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1448 struct kvm *kvm = vcpu->kvm;
1449 u64 offset, ns, elapsed;
1450 unsigned long flags;
1451 bool matched;
1452 bool already_matched;
1453 u64 data = msr->data;
1454 bool synchronizing = false;
1456 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1457 offset = kvm_compute_tsc_offset(vcpu, data);
1458 ns = ktime_get_boot_ns();
1459 elapsed = ns - kvm->arch.last_tsc_nsec;
1461 if (vcpu->arch.virtual_tsc_khz) {
1462 if (data == 0 && msr->host_initiated) {
1464 * detection of vcpu initialization -- need to sync
1465 * with other vCPUs. This particularly helps to keep
1466 * kvm_clock stable after CPU hotplug
1468 synchronizing = true;
1469 } else {
1470 u64 tsc_exp = kvm->arch.last_tsc_write +
1471 nsec_to_cycles(vcpu, elapsed);
1472 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1474 * Special case: TSC write with a small delta (1 second)
1475 * of virtual cycle time against real time is
1476 * interpreted as an attempt to synchronize the CPU.
1478 synchronizing = data < tsc_exp + tsc_hz &&
1479 data + tsc_hz > tsc_exp;
1484 * For a reliable TSC, we can match TSC offsets, and for an unstable
1485 * TSC, we add elapsed time in this computation. We could let the
1486 * compensation code attempt to catch up if we fall behind, but
1487 * it's better to try to match offsets from the beginning.
1489 if (synchronizing &&
1490 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1491 if (!check_tsc_unstable()) {
1492 offset = kvm->arch.cur_tsc_offset;
1493 pr_debug("kvm: matched tsc offset for %llu\n", data);
1494 } else {
1495 u64 delta = nsec_to_cycles(vcpu, elapsed);
1496 data += delta;
1497 offset = kvm_compute_tsc_offset(vcpu, data);
1498 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1500 matched = true;
1501 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1502 } else {
1504 * We split periods of matched TSC writes into generations.
1505 * For each generation, we track the original measured
1506 * nanosecond time, offset, and write, so if TSCs are in
1507 * sync, we can match exact offset, and if not, we can match
1508 * exact software computation in compute_guest_tsc()
1510 * These values are tracked in kvm->arch.cur_xxx variables.
1512 kvm->arch.cur_tsc_generation++;
1513 kvm->arch.cur_tsc_nsec = ns;
1514 kvm->arch.cur_tsc_write = data;
1515 kvm->arch.cur_tsc_offset = offset;
1516 matched = false;
1517 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1518 kvm->arch.cur_tsc_generation, data);
1522 * We also track th most recent recorded KHZ, write and time to
1523 * allow the matching interval to be extended at each write.
1525 kvm->arch.last_tsc_nsec = ns;
1526 kvm->arch.last_tsc_write = data;
1527 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1529 vcpu->arch.last_guest_tsc = data;
1531 /* Keep track of which generation this VCPU has synchronized to */
1532 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1533 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1534 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1536 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1537 update_ia32_tsc_adjust_msr(vcpu, offset);
1538 kvm_vcpu_write_tsc_offset(vcpu, offset);
1539 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1541 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1542 if (!matched) {
1543 kvm->arch.nr_vcpus_matched_tsc = 0;
1544 } else if (!already_matched) {
1545 kvm->arch.nr_vcpus_matched_tsc++;
1548 kvm_track_tsc_matching(vcpu);
1549 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1552 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1554 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1555 s64 adjustment)
1557 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1560 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1562 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1563 WARN_ON(adjustment < 0);
1564 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1565 adjust_tsc_offset_guest(vcpu, adjustment);
1568 #ifdef CONFIG_X86_64
1570 static u64 read_tsc(void)
1572 u64 ret = (u64)rdtsc_ordered();
1573 u64 last = pvclock_gtod_data.clock.cycle_last;
1575 if (likely(ret >= last))
1576 return ret;
1579 * GCC likes to generate cmov here, but this branch is extremely
1580 * predictable (it's just a function of time and the likely is
1581 * very likely) and there's a data dependence, so force GCC
1582 * to generate a branch instead. I don't barrier() because
1583 * we don't actually need a barrier, and if this function
1584 * ever gets inlined it will generate worse code.
1586 asm volatile ("");
1587 return last;
1590 static inline u64 vgettsc(u64 *cycle_now)
1592 long v;
1593 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1595 *cycle_now = read_tsc();
1597 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1598 return v * gtod->clock.mult;
1601 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1603 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1604 unsigned long seq;
1605 int mode;
1606 u64 ns;
1608 do {
1609 seq = read_seqcount_begin(&gtod->seq);
1610 mode = gtod->clock.vclock_mode;
1611 ns = gtod->nsec_base;
1612 ns += vgettsc(cycle_now);
1613 ns >>= gtod->clock.shift;
1614 ns += gtod->boot_ns;
1615 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1616 *t = ns;
1618 return mode;
1621 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1623 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1624 unsigned long seq;
1625 int mode;
1626 u64 ns;
1628 do {
1629 seq = read_seqcount_begin(&gtod->seq);
1630 mode = gtod->clock.vclock_mode;
1631 ts->tv_sec = gtod->wall_time_sec;
1632 ns = gtod->nsec_base;
1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
1635 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1637 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1638 ts->tv_nsec = ns;
1640 return mode;
1643 /* returns true if host is using tsc clocksource */
1644 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1646 /* checked again under seqlock below */
1647 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1648 return false;
1650 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1653 /* returns true if host is using tsc clocksource */
1654 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1655 u64 *cycle_now)
1657 /* checked again under seqlock below */
1658 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1659 return false;
1661 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1663 #endif
1667 * Assuming a stable TSC across physical CPUS, and a stable TSC
1668 * across virtual CPUs, the following condition is possible.
1669 * Each numbered line represents an event visible to both
1670 * CPUs at the next numbered event.
1672 * "timespecX" represents host monotonic time. "tscX" represents
1673 * RDTSC value.
1675 * VCPU0 on CPU0 | VCPU1 on CPU1
1677 * 1. read timespec0,tsc0
1678 * 2. | timespec1 = timespec0 + N
1679 * | tsc1 = tsc0 + M
1680 * 3. transition to guest | transition to guest
1681 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1682 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1683 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1685 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1687 * - ret0 < ret1
1688 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1689 * ...
1690 * - 0 < N - M => M < N
1692 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1693 * always the case (the difference between two distinct xtime instances
1694 * might be smaller then the difference between corresponding TSC reads,
1695 * when updating guest vcpus pvclock areas).
1697 * To avoid that problem, do not allow visibility of distinct
1698 * system_timestamp/tsc_timestamp values simultaneously: use a master
1699 * copy of host monotonic time values. Update that master copy
1700 * in lockstep.
1702 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1706 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1708 #ifdef CONFIG_X86_64
1709 struct kvm_arch *ka = &kvm->arch;
1710 int vclock_mode;
1711 bool host_tsc_clocksource, vcpus_matched;
1713 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1714 atomic_read(&kvm->online_vcpus));
1717 * If the host uses TSC clock, then passthrough TSC as stable
1718 * to the guest.
1720 host_tsc_clocksource = kvm_get_time_and_clockread(
1721 &ka->master_kernel_ns,
1722 &ka->master_cycle_now);
1724 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1725 && !ka->backwards_tsc_observed
1726 && !ka->boot_vcpu_runs_old_kvmclock;
1728 if (ka->use_master_clock)
1729 atomic_set(&kvm_guest_has_master_clock, 1);
1731 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1732 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1733 vcpus_matched);
1734 #endif
1737 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1739 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1742 static void kvm_gen_update_masterclock(struct kvm *kvm)
1744 #ifdef CONFIG_X86_64
1745 int i;
1746 struct kvm_vcpu *vcpu;
1747 struct kvm_arch *ka = &kvm->arch;
1749 spin_lock(&ka->pvclock_gtod_sync_lock);
1750 kvm_make_mclock_inprogress_request(kvm);
1751 /* no guest entries from this point */
1752 pvclock_update_vm_gtod_copy(kvm);
1754 kvm_for_each_vcpu(i, vcpu, kvm)
1755 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1757 /* guest entries allowed */
1758 kvm_for_each_vcpu(i, vcpu, kvm)
1759 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1761 spin_unlock(&ka->pvclock_gtod_sync_lock);
1762 #endif
1765 u64 get_kvmclock_ns(struct kvm *kvm)
1767 struct kvm_arch *ka = &kvm->arch;
1768 struct pvclock_vcpu_time_info hv_clock;
1769 u64 ret;
1771 spin_lock(&ka->pvclock_gtod_sync_lock);
1772 if (!ka->use_master_clock) {
1773 spin_unlock(&ka->pvclock_gtod_sync_lock);
1774 return ktime_get_boot_ns() + ka->kvmclock_offset;
1777 hv_clock.tsc_timestamp = ka->master_cycle_now;
1778 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1779 spin_unlock(&ka->pvclock_gtod_sync_lock);
1781 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1782 get_cpu();
1784 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1785 &hv_clock.tsc_shift,
1786 &hv_clock.tsc_to_system_mul);
1787 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1789 put_cpu();
1791 return ret;
1794 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1796 struct kvm_vcpu_arch *vcpu = &v->arch;
1797 struct pvclock_vcpu_time_info guest_hv_clock;
1799 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1800 &guest_hv_clock, sizeof(guest_hv_clock))))
1801 return;
1803 /* This VCPU is paused, but it's legal for a guest to read another
1804 * VCPU's kvmclock, so we really have to follow the specification where
1805 * it says that version is odd if data is being modified, and even after
1806 * it is consistent.
1808 * Version field updates must be kept separate. This is because
1809 * kvm_write_guest_cached might use a "rep movs" instruction, and
1810 * writes within a string instruction are weakly ordered. So there
1811 * are three writes overall.
1813 * As a small optimization, only write the version field in the first
1814 * and third write. The vcpu->pv_time cache is still valid, because the
1815 * version field is the first in the struct.
1817 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1819 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1820 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1821 &vcpu->hv_clock,
1822 sizeof(vcpu->hv_clock.version));
1824 smp_wmb();
1826 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1827 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1829 if (vcpu->pvclock_set_guest_stopped_request) {
1830 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1831 vcpu->pvclock_set_guest_stopped_request = false;
1834 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock));
1840 smp_wmb();
1842 vcpu->hv_clock.version++;
1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock.version));
1848 static int kvm_guest_time_update(struct kvm_vcpu *v)
1850 unsigned long flags, tgt_tsc_khz;
1851 struct kvm_vcpu_arch *vcpu = &v->arch;
1852 struct kvm_arch *ka = &v->kvm->arch;
1853 s64 kernel_ns;
1854 u64 tsc_timestamp, host_tsc;
1855 u8 pvclock_flags;
1856 bool use_master_clock;
1858 kernel_ns = 0;
1859 host_tsc = 0;
1862 * If the host uses TSC clock, then passthrough TSC as stable
1863 * to the guest.
1865 spin_lock(&ka->pvclock_gtod_sync_lock);
1866 use_master_clock = ka->use_master_clock;
1867 if (use_master_clock) {
1868 host_tsc = ka->master_cycle_now;
1869 kernel_ns = ka->master_kernel_ns;
1871 spin_unlock(&ka->pvclock_gtod_sync_lock);
1873 /* Keep irq disabled to prevent changes to the clock */
1874 local_irq_save(flags);
1875 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1876 if (unlikely(tgt_tsc_khz == 0)) {
1877 local_irq_restore(flags);
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1879 return 1;
1881 if (!use_master_clock) {
1882 host_tsc = rdtsc();
1883 kernel_ns = ktime_get_boot_ns();
1886 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1889 * We may have to catch up the TSC to match elapsed wall clock
1890 * time for two reasons, even if kvmclock is used.
1891 * 1) CPU could have been running below the maximum TSC rate
1892 * 2) Broken TSC compensation resets the base at each VCPU
1893 * entry to avoid unknown leaps of TSC even when running
1894 * again on the same CPU. This may cause apparent elapsed
1895 * time to disappear, and the guest to stand still or run
1896 * very slowly.
1898 if (vcpu->tsc_catchup) {
1899 u64 tsc = compute_guest_tsc(v, kernel_ns);
1900 if (tsc > tsc_timestamp) {
1901 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1902 tsc_timestamp = tsc;
1906 local_irq_restore(flags);
1908 /* With all the info we got, fill in the values */
1910 if (kvm_has_tsc_control)
1911 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1913 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1914 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1915 &vcpu->hv_clock.tsc_shift,
1916 &vcpu->hv_clock.tsc_to_system_mul);
1917 vcpu->hw_tsc_khz = tgt_tsc_khz;
1920 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1921 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1922 vcpu->last_guest_tsc = tsc_timestamp;
1924 /* If the host uses TSC clocksource, then it is stable */
1925 pvclock_flags = 0;
1926 if (use_master_clock)
1927 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1929 vcpu->hv_clock.flags = pvclock_flags;
1931 if (vcpu->pv_time_enabled)
1932 kvm_setup_pvclock_page(v);
1933 if (v == kvm_get_vcpu(v->kvm, 0))
1934 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1935 return 0;
1939 * kvmclock updates which are isolated to a given vcpu, such as
1940 * vcpu->cpu migration, should not allow system_timestamp from
1941 * the rest of the vcpus to remain static. Otherwise ntp frequency
1942 * correction applies to one vcpu's system_timestamp but not
1943 * the others.
1945 * So in those cases, request a kvmclock update for all vcpus.
1946 * We need to rate-limit these requests though, as they can
1947 * considerably slow guests that have a large number of vcpus.
1948 * The time for a remote vcpu to update its kvmclock is bound
1949 * by the delay we use to rate-limit the updates.
1952 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1954 static void kvmclock_update_fn(struct work_struct *work)
1956 int i;
1957 struct delayed_work *dwork = to_delayed_work(work);
1958 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1959 kvmclock_update_work);
1960 struct kvm *kvm = container_of(ka, struct kvm, arch);
1961 struct kvm_vcpu *vcpu;
1963 kvm_for_each_vcpu(i, vcpu, kvm) {
1964 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1965 kvm_vcpu_kick(vcpu);
1969 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1971 struct kvm *kvm = v->kvm;
1973 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1974 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1975 KVMCLOCK_UPDATE_DELAY);
1978 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1980 static void kvmclock_sync_fn(struct work_struct *work)
1982 struct delayed_work *dwork = to_delayed_work(work);
1983 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1984 kvmclock_sync_work);
1985 struct kvm *kvm = container_of(ka, struct kvm, arch);
1987 if (!kvmclock_periodic_sync)
1988 return;
1990 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1991 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1992 KVMCLOCK_SYNC_PERIOD);
1995 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1997 u64 mcg_cap = vcpu->arch.mcg_cap;
1998 unsigned bank_num = mcg_cap & 0xff;
2000 switch (msr) {
2001 case MSR_IA32_MCG_STATUS:
2002 vcpu->arch.mcg_status = data;
2003 break;
2004 case MSR_IA32_MCG_CTL:
2005 if (!(mcg_cap & MCG_CTL_P))
2006 return 1;
2007 if (data != 0 && data != ~(u64)0)
2008 return -1;
2009 vcpu->arch.mcg_ctl = data;
2010 break;
2011 default:
2012 if (msr >= MSR_IA32_MC0_CTL &&
2013 msr < MSR_IA32_MCx_CTL(bank_num)) {
2014 u32 offset = msr - MSR_IA32_MC0_CTL;
2015 /* only 0 or all 1s can be written to IA32_MCi_CTL
2016 * some Linux kernels though clear bit 10 in bank 4 to
2017 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2018 * this to avoid an uncatched #GP in the guest
2020 if ((offset & 0x3) == 0 &&
2021 data != 0 && (data | (1 << 10)) != ~(u64)0)
2022 return -1;
2023 vcpu->arch.mce_banks[offset] = data;
2024 break;
2026 return 1;
2028 return 0;
2031 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2033 struct kvm *kvm = vcpu->kvm;
2034 int lm = is_long_mode(vcpu);
2035 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2036 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2037 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2038 : kvm->arch.xen_hvm_config.blob_size_32;
2039 u32 page_num = data & ~PAGE_MASK;
2040 u64 page_addr = data & PAGE_MASK;
2041 u8 *page;
2042 int r;
2044 r = -E2BIG;
2045 if (page_num >= blob_size)
2046 goto out;
2047 r = -ENOMEM;
2048 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2049 if (IS_ERR(page)) {
2050 r = PTR_ERR(page);
2051 goto out;
2053 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2054 goto out_free;
2055 r = 0;
2056 out_free:
2057 kfree(page);
2058 out:
2059 return r;
2062 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2064 gpa_t gpa = data & ~0x3f;
2066 /* Bits 3:5 are reserved, Should be zero */
2067 if (data & 0x38)
2068 return 1;
2070 vcpu->arch.apf.msr_val = data;
2072 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2073 kvm_clear_async_pf_completion_queue(vcpu);
2074 kvm_async_pf_hash_reset(vcpu);
2075 return 0;
2078 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2079 sizeof(u32)))
2080 return 1;
2082 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2083 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2084 kvm_async_pf_wakeup_all(vcpu);
2085 return 0;
2088 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2090 vcpu->arch.pv_time_enabled = false;
2093 static void record_steal_time(struct kvm_vcpu *vcpu)
2095 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2096 return;
2098 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2099 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2100 return;
2102 vcpu->arch.st.steal.preempted = 0;
2104 if (vcpu->arch.st.steal.version & 1)
2105 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2107 vcpu->arch.st.steal.version += 1;
2109 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2110 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2112 smp_wmb();
2114 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2115 vcpu->arch.st.last_steal;
2116 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2118 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2119 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2121 smp_wmb();
2123 vcpu->arch.st.steal.version += 1;
2125 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2126 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2129 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2131 bool pr = false;
2132 u32 msr = msr_info->index;
2133 u64 data = msr_info->data;
2135 switch (msr) {
2136 case MSR_AMD64_NB_CFG:
2137 case MSR_IA32_UCODE_REV:
2138 case MSR_IA32_UCODE_WRITE:
2139 case MSR_VM_HSAVE_PA:
2140 case MSR_AMD64_PATCH_LOADER:
2141 case MSR_AMD64_BU_CFG2:
2142 case MSR_AMD64_DC_CFG:
2143 break;
2145 case MSR_EFER:
2146 return set_efer(vcpu, data);
2147 case MSR_K7_HWCR:
2148 data &= ~(u64)0x40; /* ignore flush filter disable */
2149 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2150 data &= ~(u64)0x8; /* ignore TLB cache disable */
2151 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2152 if (data != 0) {
2153 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2154 data);
2155 return 1;
2157 break;
2158 case MSR_FAM10H_MMIO_CONF_BASE:
2159 if (data != 0) {
2160 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2161 "0x%llx\n", data);
2162 return 1;
2164 break;
2165 case MSR_IA32_DEBUGCTLMSR:
2166 if (!data) {
2167 /* We support the non-activated case already */
2168 break;
2169 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2170 /* Values other than LBR and BTF are vendor-specific,
2171 thus reserved and should throw a #GP */
2172 return 1;
2174 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2175 __func__, data);
2176 break;
2177 case 0x200 ... 0x2ff:
2178 return kvm_mtrr_set_msr(vcpu, msr, data);
2179 case MSR_IA32_APICBASE:
2180 return kvm_set_apic_base(vcpu, msr_info);
2181 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2182 return kvm_x2apic_msr_write(vcpu, msr, data);
2183 case MSR_IA32_TSCDEADLINE:
2184 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2185 break;
2186 case MSR_IA32_TSC_ADJUST:
2187 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2188 if (!msr_info->host_initiated) {
2189 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2190 adjust_tsc_offset_guest(vcpu, adj);
2192 vcpu->arch.ia32_tsc_adjust_msr = data;
2194 break;
2195 case MSR_IA32_MISC_ENABLE:
2196 vcpu->arch.ia32_misc_enable_msr = data;
2197 break;
2198 case MSR_IA32_SMBASE:
2199 if (!msr_info->host_initiated)
2200 return 1;
2201 vcpu->arch.smbase = data;
2202 break;
2203 case MSR_KVM_WALL_CLOCK_NEW:
2204 case MSR_KVM_WALL_CLOCK:
2205 vcpu->kvm->arch.wall_clock = data;
2206 kvm_write_wall_clock(vcpu->kvm, data);
2207 break;
2208 case MSR_KVM_SYSTEM_TIME_NEW:
2209 case MSR_KVM_SYSTEM_TIME: {
2210 struct kvm_arch *ka = &vcpu->kvm->arch;
2212 kvmclock_reset(vcpu);
2214 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2215 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2217 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2218 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2220 ka->boot_vcpu_runs_old_kvmclock = tmp;
2223 vcpu->arch.time = data;
2224 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2226 /* we verify if the enable bit is set... */
2227 if (!(data & 1))
2228 break;
2230 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2231 &vcpu->arch.pv_time, data & ~1ULL,
2232 sizeof(struct pvclock_vcpu_time_info)))
2233 vcpu->arch.pv_time_enabled = false;
2234 else
2235 vcpu->arch.pv_time_enabled = true;
2237 break;
2239 case MSR_KVM_ASYNC_PF_EN:
2240 if (kvm_pv_enable_async_pf(vcpu, data))
2241 return 1;
2242 break;
2243 case MSR_KVM_STEAL_TIME:
2245 if (unlikely(!sched_info_on()))
2246 return 1;
2248 if (data & KVM_STEAL_RESERVED_MASK)
2249 return 1;
2251 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2252 data & KVM_STEAL_VALID_BITS,
2253 sizeof(struct kvm_steal_time)))
2254 return 1;
2256 vcpu->arch.st.msr_val = data;
2258 if (!(data & KVM_MSR_ENABLED))
2259 break;
2261 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2263 break;
2264 case MSR_KVM_PV_EOI_EN:
2265 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2266 return 1;
2267 break;
2269 case MSR_IA32_MCG_CTL:
2270 case MSR_IA32_MCG_STATUS:
2271 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2272 return set_msr_mce(vcpu, msr, data);
2274 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2275 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2276 pr = true; /* fall through */
2277 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2278 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2279 if (kvm_pmu_is_valid_msr(vcpu, msr))
2280 return kvm_pmu_set_msr(vcpu, msr_info);
2282 if (pr || data != 0)
2283 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2284 "0x%x data 0x%llx\n", msr, data);
2285 break;
2286 case MSR_K7_CLK_CTL:
2288 * Ignore all writes to this no longer documented MSR.
2289 * Writes are only relevant for old K7 processors,
2290 * all pre-dating SVM, but a recommended workaround from
2291 * AMD for these chips. It is possible to specify the
2292 * affected processor models on the command line, hence
2293 * the need to ignore the workaround.
2295 break;
2296 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2297 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2298 case HV_X64_MSR_CRASH_CTL:
2299 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2300 return kvm_hv_set_msr_common(vcpu, msr, data,
2301 msr_info->host_initiated);
2302 case MSR_IA32_BBL_CR_CTL3:
2303 /* Drop writes to this legacy MSR -- see rdmsr
2304 * counterpart for further detail.
2306 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2307 break;
2308 case MSR_AMD64_OSVW_ID_LENGTH:
2309 if (!guest_cpuid_has_osvw(vcpu))
2310 return 1;
2311 vcpu->arch.osvw.length = data;
2312 break;
2313 case MSR_AMD64_OSVW_STATUS:
2314 if (!guest_cpuid_has_osvw(vcpu))
2315 return 1;
2316 vcpu->arch.osvw.status = data;
2317 break;
2318 case MSR_PLATFORM_INFO:
2319 if (!msr_info->host_initiated ||
2320 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2321 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2322 cpuid_fault_enabled(vcpu)))
2323 return 1;
2324 vcpu->arch.msr_platform_info = data;
2325 break;
2326 case MSR_MISC_FEATURES_ENABLES:
2327 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2328 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2329 !supports_cpuid_fault(vcpu)))
2330 return 1;
2331 vcpu->arch.msr_misc_features_enables = data;
2332 break;
2333 default:
2334 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2335 return xen_hvm_config(vcpu, data);
2336 if (kvm_pmu_is_valid_msr(vcpu, msr))
2337 return kvm_pmu_set_msr(vcpu, msr_info);
2338 if (!ignore_msrs) {
2339 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2340 msr, data);
2341 return 1;
2342 } else {
2343 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2344 msr, data);
2345 break;
2348 return 0;
2350 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2354 * Reads an msr value (of 'msr_index') into 'pdata'.
2355 * Returns 0 on success, non-0 otherwise.
2356 * Assumes vcpu_load() was already called.
2358 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2360 return kvm_x86_ops->get_msr(vcpu, msr);
2362 EXPORT_SYMBOL_GPL(kvm_get_msr);
2364 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2366 u64 data;
2367 u64 mcg_cap = vcpu->arch.mcg_cap;
2368 unsigned bank_num = mcg_cap & 0xff;
2370 switch (msr) {
2371 case MSR_IA32_P5_MC_ADDR:
2372 case MSR_IA32_P5_MC_TYPE:
2373 data = 0;
2374 break;
2375 case MSR_IA32_MCG_CAP:
2376 data = vcpu->arch.mcg_cap;
2377 break;
2378 case MSR_IA32_MCG_CTL:
2379 if (!(mcg_cap & MCG_CTL_P))
2380 return 1;
2381 data = vcpu->arch.mcg_ctl;
2382 break;
2383 case MSR_IA32_MCG_STATUS:
2384 data = vcpu->arch.mcg_status;
2385 break;
2386 default:
2387 if (msr >= MSR_IA32_MC0_CTL &&
2388 msr < MSR_IA32_MCx_CTL(bank_num)) {
2389 u32 offset = msr - MSR_IA32_MC0_CTL;
2390 data = vcpu->arch.mce_banks[offset];
2391 break;
2393 return 1;
2395 *pdata = data;
2396 return 0;
2399 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2401 switch (msr_info->index) {
2402 case MSR_IA32_PLATFORM_ID:
2403 case MSR_IA32_EBL_CR_POWERON:
2404 case MSR_IA32_DEBUGCTLMSR:
2405 case MSR_IA32_LASTBRANCHFROMIP:
2406 case MSR_IA32_LASTBRANCHTOIP:
2407 case MSR_IA32_LASTINTFROMIP:
2408 case MSR_IA32_LASTINTTOIP:
2409 case MSR_K8_SYSCFG:
2410 case MSR_K8_TSEG_ADDR:
2411 case MSR_K8_TSEG_MASK:
2412 case MSR_K7_HWCR:
2413 case MSR_VM_HSAVE_PA:
2414 case MSR_K8_INT_PENDING_MSG:
2415 case MSR_AMD64_NB_CFG:
2416 case MSR_FAM10H_MMIO_CONF_BASE:
2417 case MSR_AMD64_BU_CFG2:
2418 case MSR_IA32_PERF_CTL:
2419 case MSR_AMD64_DC_CFG:
2420 msr_info->data = 0;
2421 break;
2422 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2423 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2424 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2425 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2426 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2427 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2428 msr_info->data = 0;
2429 break;
2430 case MSR_IA32_UCODE_REV:
2431 msr_info->data = 0x100000000ULL;
2432 break;
2433 case MSR_MTRRcap:
2434 case 0x200 ... 0x2ff:
2435 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2436 case 0xcd: /* fsb frequency */
2437 msr_info->data = 3;
2438 break;
2440 * MSR_EBC_FREQUENCY_ID
2441 * Conservative value valid for even the basic CPU models.
2442 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2443 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2444 * and 266MHz for model 3, or 4. Set Core Clock
2445 * Frequency to System Bus Frequency Ratio to 1 (bits
2446 * 31:24) even though these are only valid for CPU
2447 * models > 2, however guests may end up dividing or
2448 * multiplying by zero otherwise.
2450 case MSR_EBC_FREQUENCY_ID:
2451 msr_info->data = 1 << 24;
2452 break;
2453 case MSR_IA32_APICBASE:
2454 msr_info->data = kvm_get_apic_base(vcpu);
2455 break;
2456 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2457 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2458 break;
2459 case MSR_IA32_TSCDEADLINE:
2460 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2461 break;
2462 case MSR_IA32_TSC_ADJUST:
2463 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2464 break;
2465 case MSR_IA32_MISC_ENABLE:
2466 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2467 break;
2468 case MSR_IA32_SMBASE:
2469 if (!msr_info->host_initiated)
2470 return 1;
2471 msr_info->data = vcpu->arch.smbase;
2472 break;
2473 case MSR_IA32_PERF_STATUS:
2474 /* TSC increment by tick */
2475 msr_info->data = 1000ULL;
2476 /* CPU multiplier */
2477 msr_info->data |= (((uint64_t)4ULL) << 40);
2478 break;
2479 case MSR_EFER:
2480 msr_info->data = vcpu->arch.efer;
2481 break;
2482 case MSR_KVM_WALL_CLOCK:
2483 case MSR_KVM_WALL_CLOCK_NEW:
2484 msr_info->data = vcpu->kvm->arch.wall_clock;
2485 break;
2486 case MSR_KVM_SYSTEM_TIME:
2487 case MSR_KVM_SYSTEM_TIME_NEW:
2488 msr_info->data = vcpu->arch.time;
2489 break;
2490 case MSR_KVM_ASYNC_PF_EN:
2491 msr_info->data = vcpu->arch.apf.msr_val;
2492 break;
2493 case MSR_KVM_STEAL_TIME:
2494 msr_info->data = vcpu->arch.st.msr_val;
2495 break;
2496 case MSR_KVM_PV_EOI_EN:
2497 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2498 break;
2499 case MSR_IA32_P5_MC_ADDR:
2500 case MSR_IA32_P5_MC_TYPE:
2501 case MSR_IA32_MCG_CAP:
2502 case MSR_IA32_MCG_CTL:
2503 case MSR_IA32_MCG_STATUS:
2504 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2505 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2506 case MSR_K7_CLK_CTL:
2508 * Provide expected ramp-up count for K7. All other
2509 * are set to zero, indicating minimum divisors for
2510 * every field.
2512 * This prevents guest kernels on AMD host with CPU
2513 * type 6, model 8 and higher from exploding due to
2514 * the rdmsr failing.
2516 msr_info->data = 0x20000000;
2517 break;
2518 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2519 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2520 case HV_X64_MSR_CRASH_CTL:
2521 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2522 return kvm_hv_get_msr_common(vcpu,
2523 msr_info->index, &msr_info->data);
2524 break;
2525 case MSR_IA32_BBL_CR_CTL3:
2526 /* This legacy MSR exists but isn't fully documented in current
2527 * silicon. It is however accessed by winxp in very narrow
2528 * scenarios where it sets bit #19, itself documented as
2529 * a "reserved" bit. Best effort attempt to source coherent
2530 * read data here should the balance of the register be
2531 * interpreted by the guest:
2533 * L2 cache control register 3: 64GB range, 256KB size,
2534 * enabled, latency 0x1, configured
2536 msr_info->data = 0xbe702111;
2537 break;
2538 case MSR_AMD64_OSVW_ID_LENGTH:
2539 if (!guest_cpuid_has_osvw(vcpu))
2540 return 1;
2541 msr_info->data = vcpu->arch.osvw.length;
2542 break;
2543 case MSR_AMD64_OSVW_STATUS:
2544 if (!guest_cpuid_has_osvw(vcpu))
2545 return 1;
2546 msr_info->data = vcpu->arch.osvw.status;
2547 break;
2548 case MSR_PLATFORM_INFO:
2549 msr_info->data = vcpu->arch.msr_platform_info;
2550 break;
2551 case MSR_MISC_FEATURES_ENABLES:
2552 msr_info->data = vcpu->arch.msr_misc_features_enables;
2553 break;
2554 default:
2555 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2556 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2557 if (!ignore_msrs) {
2558 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2559 msr_info->index);
2560 return 1;
2561 } else {
2562 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2563 msr_info->data = 0;
2565 break;
2567 return 0;
2569 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2572 * Read or write a bunch of msrs. All parameters are kernel addresses.
2574 * @return number of msrs set successfully.
2576 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2577 struct kvm_msr_entry *entries,
2578 int (*do_msr)(struct kvm_vcpu *vcpu,
2579 unsigned index, u64 *data))
2581 int i, idx;
2583 idx = srcu_read_lock(&vcpu->kvm->srcu);
2584 for (i = 0; i < msrs->nmsrs; ++i)
2585 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2586 break;
2587 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2589 return i;
2593 * Read or write a bunch of msrs. Parameters are user addresses.
2595 * @return number of msrs set successfully.
2597 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2598 int (*do_msr)(struct kvm_vcpu *vcpu,
2599 unsigned index, u64 *data),
2600 int writeback)
2602 struct kvm_msrs msrs;
2603 struct kvm_msr_entry *entries;
2604 int r, n;
2605 unsigned size;
2607 r = -EFAULT;
2608 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2609 goto out;
2611 r = -E2BIG;
2612 if (msrs.nmsrs >= MAX_IO_MSRS)
2613 goto out;
2615 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2616 entries = memdup_user(user_msrs->entries, size);
2617 if (IS_ERR(entries)) {
2618 r = PTR_ERR(entries);
2619 goto out;
2622 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2623 if (r < 0)
2624 goto out_free;
2626 r = -EFAULT;
2627 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2628 goto out_free;
2630 r = n;
2632 out_free:
2633 kfree(entries);
2634 out:
2635 return r;
2638 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2640 int r;
2642 switch (ext) {
2643 case KVM_CAP_IRQCHIP:
2644 case KVM_CAP_HLT:
2645 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2646 case KVM_CAP_SET_TSS_ADDR:
2647 case KVM_CAP_EXT_CPUID:
2648 case KVM_CAP_EXT_EMUL_CPUID:
2649 case KVM_CAP_CLOCKSOURCE:
2650 case KVM_CAP_PIT:
2651 case KVM_CAP_NOP_IO_DELAY:
2652 case KVM_CAP_MP_STATE:
2653 case KVM_CAP_SYNC_MMU:
2654 case KVM_CAP_USER_NMI:
2655 case KVM_CAP_REINJECT_CONTROL:
2656 case KVM_CAP_IRQ_INJECT_STATUS:
2657 case KVM_CAP_IOEVENTFD:
2658 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2659 case KVM_CAP_PIT2:
2660 case KVM_CAP_PIT_STATE2:
2661 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2662 case KVM_CAP_XEN_HVM:
2663 case KVM_CAP_VCPU_EVENTS:
2664 case KVM_CAP_HYPERV:
2665 case KVM_CAP_HYPERV_VAPIC:
2666 case KVM_CAP_HYPERV_SPIN:
2667 case KVM_CAP_HYPERV_SYNIC:
2668 case KVM_CAP_HYPERV_SYNIC2:
2669 case KVM_CAP_HYPERV_VP_INDEX:
2670 case KVM_CAP_PCI_SEGMENT:
2671 case KVM_CAP_DEBUGREGS:
2672 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2673 case KVM_CAP_XSAVE:
2674 case KVM_CAP_ASYNC_PF:
2675 case KVM_CAP_GET_TSC_KHZ:
2676 case KVM_CAP_KVMCLOCK_CTRL:
2677 case KVM_CAP_READONLY_MEM:
2678 case KVM_CAP_HYPERV_TIME:
2679 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2680 case KVM_CAP_TSC_DEADLINE_TIMER:
2681 case KVM_CAP_ENABLE_CAP_VM:
2682 case KVM_CAP_DISABLE_QUIRKS:
2683 case KVM_CAP_SET_BOOT_CPU_ID:
2684 case KVM_CAP_SPLIT_IRQCHIP:
2685 case KVM_CAP_IMMEDIATE_EXIT:
2686 r = 1;
2687 break;
2688 case KVM_CAP_ADJUST_CLOCK:
2689 r = KVM_CLOCK_TSC_STABLE;
2690 break;
2691 case KVM_CAP_X86_GUEST_MWAIT:
2692 r = kvm_mwait_in_guest();
2693 break;
2694 case KVM_CAP_X86_SMM:
2695 /* SMBASE is usually relocated above 1M on modern chipsets,
2696 * and SMM handlers might indeed rely on 4G segment limits,
2697 * so do not report SMM to be available if real mode is
2698 * emulated via vm86 mode. Still, do not go to great lengths
2699 * to avoid userspace's usage of the feature, because it is a
2700 * fringe case that is not enabled except via specific settings
2701 * of the module parameters.
2703 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2704 break;
2705 case KVM_CAP_VAPIC:
2706 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2707 break;
2708 case KVM_CAP_NR_VCPUS:
2709 r = KVM_SOFT_MAX_VCPUS;
2710 break;
2711 case KVM_CAP_MAX_VCPUS:
2712 r = KVM_MAX_VCPUS;
2713 break;
2714 case KVM_CAP_NR_MEMSLOTS:
2715 r = KVM_USER_MEM_SLOTS;
2716 break;
2717 case KVM_CAP_PV_MMU: /* obsolete */
2718 r = 0;
2719 break;
2720 case KVM_CAP_MCE:
2721 r = KVM_MAX_MCE_BANKS;
2722 break;
2723 case KVM_CAP_XCRS:
2724 r = boot_cpu_has(X86_FEATURE_XSAVE);
2725 break;
2726 case KVM_CAP_TSC_CONTROL:
2727 r = kvm_has_tsc_control;
2728 break;
2729 case KVM_CAP_X2APIC_API:
2730 r = KVM_X2APIC_API_VALID_FLAGS;
2731 break;
2732 default:
2733 r = 0;
2734 break;
2736 return r;
2740 long kvm_arch_dev_ioctl(struct file *filp,
2741 unsigned int ioctl, unsigned long arg)
2743 void __user *argp = (void __user *)arg;
2744 long r;
2746 switch (ioctl) {
2747 case KVM_GET_MSR_INDEX_LIST: {
2748 struct kvm_msr_list __user *user_msr_list = argp;
2749 struct kvm_msr_list msr_list;
2750 unsigned n;
2752 r = -EFAULT;
2753 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2754 goto out;
2755 n = msr_list.nmsrs;
2756 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2757 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2758 goto out;
2759 r = -E2BIG;
2760 if (n < msr_list.nmsrs)
2761 goto out;
2762 r = -EFAULT;
2763 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2764 num_msrs_to_save * sizeof(u32)))
2765 goto out;
2766 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2767 &emulated_msrs,
2768 num_emulated_msrs * sizeof(u32)))
2769 goto out;
2770 r = 0;
2771 break;
2773 case KVM_GET_SUPPORTED_CPUID:
2774 case KVM_GET_EMULATED_CPUID: {
2775 struct kvm_cpuid2 __user *cpuid_arg = argp;
2776 struct kvm_cpuid2 cpuid;
2778 r = -EFAULT;
2779 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2780 goto out;
2782 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2783 ioctl);
2784 if (r)
2785 goto out;
2787 r = -EFAULT;
2788 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2789 goto out;
2790 r = 0;
2791 break;
2793 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2794 r = -EFAULT;
2795 if (copy_to_user(argp, &kvm_mce_cap_supported,
2796 sizeof(kvm_mce_cap_supported)))
2797 goto out;
2798 r = 0;
2799 break;
2801 default:
2802 r = -EINVAL;
2804 out:
2805 return r;
2808 static void wbinvd_ipi(void *garbage)
2810 wbinvd();
2813 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2815 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2818 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2820 /* Address WBINVD may be executed by guest */
2821 if (need_emulate_wbinvd(vcpu)) {
2822 if (kvm_x86_ops->has_wbinvd_exit())
2823 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2824 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2825 smp_call_function_single(vcpu->cpu,
2826 wbinvd_ipi, NULL, 1);
2829 kvm_x86_ops->vcpu_load(vcpu, cpu);
2831 /* Apply any externally detected TSC adjustments (due to suspend) */
2832 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2833 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2834 vcpu->arch.tsc_offset_adjustment = 0;
2835 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2838 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2839 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2840 rdtsc() - vcpu->arch.last_host_tsc;
2841 if (tsc_delta < 0)
2842 mark_tsc_unstable("KVM discovered backwards TSC");
2844 if (check_tsc_unstable()) {
2845 u64 offset = kvm_compute_tsc_offset(vcpu,
2846 vcpu->arch.last_guest_tsc);
2847 kvm_vcpu_write_tsc_offset(vcpu, offset);
2848 vcpu->arch.tsc_catchup = 1;
2851 if (kvm_lapic_hv_timer_in_use(vcpu))
2852 kvm_lapic_restart_hv_timer(vcpu);
2855 * On a host with synchronized TSC, there is no need to update
2856 * kvmclock on vcpu->cpu migration
2858 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2859 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2860 if (vcpu->cpu != cpu)
2861 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
2862 vcpu->cpu = cpu;
2865 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2868 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2870 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2871 return;
2873 vcpu->arch.st.steal.preempted = 1;
2875 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2876 &vcpu->arch.st.steal.preempted,
2877 offsetof(struct kvm_steal_time, preempted),
2878 sizeof(vcpu->arch.st.steal.preempted));
2881 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2883 int idx;
2885 * Disable page faults because we're in atomic context here.
2886 * kvm_write_guest_offset_cached() would call might_fault()
2887 * that relies on pagefault_disable() to tell if there's a
2888 * bug. NOTE: the write to guest memory may not go through if
2889 * during postcopy live migration or if there's heavy guest
2890 * paging.
2892 pagefault_disable();
2894 * kvm_memslots() will be called by
2895 * kvm_write_guest_offset_cached() so take the srcu lock.
2897 idx = srcu_read_lock(&vcpu->kvm->srcu);
2898 kvm_steal_time_set_preempted(vcpu);
2899 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2900 pagefault_enable();
2901 kvm_x86_ops->vcpu_put(vcpu);
2902 kvm_put_guest_fpu(vcpu);
2903 vcpu->arch.last_host_tsc = rdtsc();
2906 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2907 struct kvm_lapic_state *s)
2909 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
2910 kvm_x86_ops->sync_pir_to_irr(vcpu);
2912 return kvm_apic_get_state(vcpu, s);
2915 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2916 struct kvm_lapic_state *s)
2918 int r;
2920 r = kvm_apic_set_state(vcpu, s);
2921 if (r)
2922 return r;
2923 update_cr8_intercept(vcpu);
2925 return 0;
2928 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2930 return (!lapic_in_kernel(vcpu) ||
2931 kvm_apic_accept_pic_intr(vcpu));
2935 * if userspace requested an interrupt window, check that the
2936 * interrupt window is open.
2938 * No need to exit to userspace if we already have an interrupt queued.
2940 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2942 return kvm_arch_interrupt_allowed(vcpu) &&
2943 !kvm_cpu_has_interrupt(vcpu) &&
2944 !kvm_event_needs_reinjection(vcpu) &&
2945 kvm_cpu_accept_dm_intr(vcpu);
2948 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2949 struct kvm_interrupt *irq)
2951 if (irq->irq >= KVM_NR_INTERRUPTS)
2952 return -EINVAL;
2954 if (!irqchip_in_kernel(vcpu->kvm)) {
2955 kvm_queue_interrupt(vcpu, irq->irq, false);
2956 kvm_make_request(KVM_REQ_EVENT, vcpu);
2957 return 0;
2961 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2962 * fail for in-kernel 8259.
2964 if (pic_in_kernel(vcpu->kvm))
2965 return -ENXIO;
2967 if (vcpu->arch.pending_external_vector != -1)
2968 return -EEXIST;
2970 vcpu->arch.pending_external_vector = irq->irq;
2971 kvm_make_request(KVM_REQ_EVENT, vcpu);
2972 return 0;
2975 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2977 kvm_inject_nmi(vcpu);
2979 return 0;
2982 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2984 kvm_make_request(KVM_REQ_SMI, vcpu);
2986 return 0;
2989 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2990 struct kvm_tpr_access_ctl *tac)
2992 if (tac->flags)
2993 return -EINVAL;
2994 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2995 return 0;
2998 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2999 u64 mcg_cap)
3001 int r;
3002 unsigned bank_num = mcg_cap & 0xff, bank;
3004 r = -EINVAL;
3005 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3006 goto out;
3007 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3008 goto out;
3009 r = 0;
3010 vcpu->arch.mcg_cap = mcg_cap;
3011 /* Init IA32_MCG_CTL to all 1s */
3012 if (mcg_cap & MCG_CTL_P)
3013 vcpu->arch.mcg_ctl = ~(u64)0;
3014 /* Init IA32_MCi_CTL to all 1s */
3015 for (bank = 0; bank < bank_num; bank++)
3016 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3018 if (kvm_x86_ops->setup_mce)
3019 kvm_x86_ops->setup_mce(vcpu);
3020 out:
3021 return r;
3024 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3025 struct kvm_x86_mce *mce)
3027 u64 mcg_cap = vcpu->arch.mcg_cap;
3028 unsigned bank_num = mcg_cap & 0xff;
3029 u64 *banks = vcpu->arch.mce_banks;
3031 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3032 return -EINVAL;
3034 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3035 * reporting is disabled
3037 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3038 vcpu->arch.mcg_ctl != ~(u64)0)
3039 return 0;
3040 banks += 4 * mce->bank;
3042 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3043 * reporting is disabled for the bank
3045 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3046 return 0;
3047 if (mce->status & MCI_STATUS_UC) {
3048 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3049 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3050 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3051 return 0;
3053 if (banks[1] & MCI_STATUS_VAL)
3054 mce->status |= MCI_STATUS_OVER;
3055 banks[2] = mce->addr;
3056 banks[3] = mce->misc;
3057 vcpu->arch.mcg_status = mce->mcg_status;
3058 banks[1] = mce->status;
3059 kvm_queue_exception(vcpu, MC_VECTOR);
3060 } else if (!(banks[1] & MCI_STATUS_VAL)
3061 || !(banks[1] & MCI_STATUS_UC)) {
3062 if (banks[1] & MCI_STATUS_VAL)
3063 mce->status |= MCI_STATUS_OVER;
3064 banks[2] = mce->addr;
3065 banks[3] = mce->misc;
3066 banks[1] = mce->status;
3067 } else
3068 banks[1] |= MCI_STATUS_OVER;
3069 return 0;
3072 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3073 struct kvm_vcpu_events *events)
3075 process_nmi(vcpu);
3076 events->exception.injected =
3077 vcpu->arch.exception.pending &&
3078 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3079 events->exception.nr = vcpu->arch.exception.nr;
3080 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3081 events->exception.pad = 0;
3082 events->exception.error_code = vcpu->arch.exception.error_code;
3084 events->interrupt.injected =
3085 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3086 events->interrupt.nr = vcpu->arch.interrupt.nr;
3087 events->interrupt.soft = 0;
3088 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3090 events->nmi.injected = vcpu->arch.nmi_injected;
3091 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3092 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3093 events->nmi.pad = 0;
3095 events->sipi_vector = 0; /* never valid when reporting to user space */
3097 events->smi.smm = is_smm(vcpu);
3098 events->smi.pending = vcpu->arch.smi_pending;
3099 events->smi.smm_inside_nmi =
3100 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3101 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3103 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3104 | KVM_VCPUEVENT_VALID_SHADOW
3105 | KVM_VCPUEVENT_VALID_SMM);
3106 memset(&events->reserved, 0, sizeof(events->reserved));
3109 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3111 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3112 struct kvm_vcpu_events *events)
3114 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3115 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3116 | KVM_VCPUEVENT_VALID_SHADOW
3117 | KVM_VCPUEVENT_VALID_SMM))
3118 return -EINVAL;
3120 if (events->exception.injected &&
3121 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3122 is_guest_mode(vcpu)))
3123 return -EINVAL;
3125 /* INITs are latched while in SMM */
3126 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3127 (events->smi.smm || events->smi.pending) &&
3128 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3129 return -EINVAL;
3131 process_nmi(vcpu);
3132 vcpu->arch.exception.pending = events->exception.injected;
3133 vcpu->arch.exception.nr = events->exception.nr;
3134 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3135 vcpu->arch.exception.error_code = events->exception.error_code;
3137 vcpu->arch.interrupt.pending = events->interrupt.injected;
3138 vcpu->arch.interrupt.nr = events->interrupt.nr;
3139 vcpu->arch.interrupt.soft = events->interrupt.soft;
3140 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3141 kvm_x86_ops->set_interrupt_shadow(vcpu,
3142 events->interrupt.shadow);
3144 vcpu->arch.nmi_injected = events->nmi.injected;
3145 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3146 vcpu->arch.nmi_pending = events->nmi.pending;
3147 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3149 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3150 lapic_in_kernel(vcpu))
3151 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3153 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3154 u32 hflags = vcpu->arch.hflags;
3155 if (events->smi.smm)
3156 hflags |= HF_SMM_MASK;
3157 else
3158 hflags &= ~HF_SMM_MASK;
3159 kvm_set_hflags(vcpu, hflags);
3161 vcpu->arch.smi_pending = events->smi.pending;
3163 if (events->smi.smm) {
3164 if (events->smi.smm_inside_nmi)
3165 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3166 else
3167 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3168 if (lapic_in_kernel(vcpu)) {
3169 if (events->smi.latched_init)
3170 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3171 else
3172 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3177 kvm_make_request(KVM_REQ_EVENT, vcpu);
3179 return 0;
3182 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3183 struct kvm_debugregs *dbgregs)
3185 unsigned long val;
3187 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3188 kvm_get_dr(vcpu, 6, &val);
3189 dbgregs->dr6 = val;
3190 dbgregs->dr7 = vcpu->arch.dr7;
3191 dbgregs->flags = 0;
3192 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3195 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3196 struct kvm_debugregs *dbgregs)
3198 if (dbgregs->flags)
3199 return -EINVAL;
3201 if (dbgregs->dr6 & ~0xffffffffull)
3202 return -EINVAL;
3203 if (dbgregs->dr7 & ~0xffffffffull)
3204 return -EINVAL;
3206 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3207 kvm_update_dr0123(vcpu);
3208 vcpu->arch.dr6 = dbgregs->dr6;
3209 kvm_update_dr6(vcpu);
3210 vcpu->arch.dr7 = dbgregs->dr7;
3211 kvm_update_dr7(vcpu);
3213 return 0;
3216 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3218 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3220 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3221 u64 xstate_bv = xsave->header.xfeatures;
3222 u64 valid;
3225 * Copy legacy XSAVE area, to avoid complications with CPUID
3226 * leaves 0 and 1 in the loop below.
3228 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3230 /* Set XSTATE_BV */
3231 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3232 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3235 * Copy each region from the possibly compacted offset to the
3236 * non-compacted offset.
3238 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3239 while (valid) {
3240 u64 feature = valid & -valid;
3241 int index = fls64(feature) - 1;
3242 void *src = get_xsave_addr(xsave, feature);
3244 if (src) {
3245 u32 size, offset, ecx, edx;
3246 cpuid_count(XSTATE_CPUID, index,
3247 &size, &offset, &ecx, &edx);
3248 if (feature == XFEATURE_MASK_PKRU)
3249 memcpy(dest + offset, &vcpu->arch.pkru,
3250 sizeof(vcpu->arch.pkru));
3251 else
3252 memcpy(dest + offset, src, size);
3256 valid -= feature;
3260 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3262 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3263 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3264 u64 valid;
3267 * Copy legacy XSAVE area, to avoid complications with CPUID
3268 * leaves 0 and 1 in the loop below.
3270 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3272 /* Set XSTATE_BV and possibly XCOMP_BV. */
3273 xsave->header.xfeatures = xstate_bv;
3274 if (boot_cpu_has(X86_FEATURE_XSAVES))
3275 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3278 * Copy each region from the non-compacted offset to the
3279 * possibly compacted offset.
3281 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3282 while (valid) {
3283 u64 feature = valid & -valid;
3284 int index = fls64(feature) - 1;
3285 void *dest = get_xsave_addr(xsave, feature);
3287 if (dest) {
3288 u32 size, offset, ecx, edx;
3289 cpuid_count(XSTATE_CPUID, index,
3290 &size, &offset, &ecx, &edx);
3291 if (feature == XFEATURE_MASK_PKRU)
3292 memcpy(&vcpu->arch.pkru, src + offset,
3293 sizeof(vcpu->arch.pkru));
3294 else
3295 memcpy(dest, src + offset, size);
3298 valid -= feature;
3302 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3303 struct kvm_xsave *guest_xsave)
3305 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3306 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3307 fill_xsave((u8 *) guest_xsave->region, vcpu);
3308 } else {
3309 memcpy(guest_xsave->region,
3310 &vcpu->arch.guest_fpu.state.fxsave,
3311 sizeof(struct fxregs_state));
3312 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3313 XFEATURE_MASK_FPSSE;
3317 #define XSAVE_MXCSR_OFFSET 24
3319 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3320 struct kvm_xsave *guest_xsave)
3322 u64 xstate_bv =
3323 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3324 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3326 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3328 * Here we allow setting states that are not present in
3329 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3330 * with old userspace.
3332 if (xstate_bv & ~kvm_supported_xcr0() ||
3333 mxcsr & ~mxcsr_feature_mask)
3334 return -EINVAL;
3335 load_xsave(vcpu, (u8 *)guest_xsave->region);
3336 } else {
3337 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3338 mxcsr & ~mxcsr_feature_mask)
3339 return -EINVAL;
3340 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3341 guest_xsave->region, sizeof(struct fxregs_state));
3343 return 0;
3346 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3347 struct kvm_xcrs *guest_xcrs)
3349 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3350 guest_xcrs->nr_xcrs = 0;
3351 return;
3354 guest_xcrs->nr_xcrs = 1;
3355 guest_xcrs->flags = 0;
3356 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3357 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3360 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3361 struct kvm_xcrs *guest_xcrs)
3363 int i, r = 0;
3365 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3366 return -EINVAL;
3368 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3369 return -EINVAL;
3371 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3372 /* Only support XCR0 currently */
3373 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3374 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3375 guest_xcrs->xcrs[i].value);
3376 break;
3378 if (r)
3379 r = -EINVAL;
3380 return r;
3384 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3385 * stopped by the hypervisor. This function will be called from the host only.
3386 * EINVAL is returned when the host attempts to set the flag for a guest that
3387 * does not support pv clocks.
3389 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3391 if (!vcpu->arch.pv_time_enabled)
3392 return -EINVAL;
3393 vcpu->arch.pvclock_set_guest_stopped_request = true;
3394 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3395 return 0;
3398 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3399 struct kvm_enable_cap *cap)
3401 if (cap->flags)
3402 return -EINVAL;
3404 switch (cap->cap) {
3405 case KVM_CAP_HYPERV_SYNIC2:
3406 if (cap->args[0])
3407 return -EINVAL;
3408 case KVM_CAP_HYPERV_SYNIC:
3409 if (!irqchip_in_kernel(vcpu->kvm))
3410 return -EINVAL;
3411 return kvm_hv_activate_synic(vcpu, cap->cap ==
3412 KVM_CAP_HYPERV_SYNIC2);
3413 default:
3414 return -EINVAL;
3418 long kvm_arch_vcpu_ioctl(struct file *filp,
3419 unsigned int ioctl, unsigned long arg)
3421 struct kvm_vcpu *vcpu = filp->private_data;
3422 void __user *argp = (void __user *)arg;
3423 int r;
3424 union {
3425 struct kvm_lapic_state *lapic;
3426 struct kvm_xsave *xsave;
3427 struct kvm_xcrs *xcrs;
3428 void *buffer;
3429 } u;
3431 u.buffer = NULL;
3432 switch (ioctl) {
3433 case KVM_GET_LAPIC: {
3434 r = -EINVAL;
3435 if (!lapic_in_kernel(vcpu))
3436 goto out;
3437 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3439 r = -ENOMEM;
3440 if (!u.lapic)
3441 goto out;
3442 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3443 if (r)
3444 goto out;
3445 r = -EFAULT;
3446 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3447 goto out;
3448 r = 0;
3449 break;
3451 case KVM_SET_LAPIC: {
3452 r = -EINVAL;
3453 if (!lapic_in_kernel(vcpu))
3454 goto out;
3455 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3456 if (IS_ERR(u.lapic))
3457 return PTR_ERR(u.lapic);
3459 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3460 break;
3462 case KVM_INTERRUPT: {
3463 struct kvm_interrupt irq;
3465 r = -EFAULT;
3466 if (copy_from_user(&irq, argp, sizeof irq))
3467 goto out;
3468 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3469 break;
3471 case KVM_NMI: {
3472 r = kvm_vcpu_ioctl_nmi(vcpu);
3473 break;
3475 case KVM_SMI: {
3476 r = kvm_vcpu_ioctl_smi(vcpu);
3477 break;
3479 case KVM_SET_CPUID: {
3480 struct kvm_cpuid __user *cpuid_arg = argp;
3481 struct kvm_cpuid cpuid;
3483 r = -EFAULT;
3484 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3485 goto out;
3486 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3487 break;
3489 case KVM_SET_CPUID2: {
3490 struct kvm_cpuid2 __user *cpuid_arg = argp;
3491 struct kvm_cpuid2 cpuid;
3493 r = -EFAULT;
3494 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3495 goto out;
3496 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3497 cpuid_arg->entries);
3498 break;
3500 case KVM_GET_CPUID2: {
3501 struct kvm_cpuid2 __user *cpuid_arg = argp;
3502 struct kvm_cpuid2 cpuid;
3504 r = -EFAULT;
3505 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3506 goto out;
3507 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3508 cpuid_arg->entries);
3509 if (r)
3510 goto out;
3511 r = -EFAULT;
3512 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3513 goto out;
3514 r = 0;
3515 break;
3517 case KVM_GET_MSRS:
3518 r = msr_io(vcpu, argp, do_get_msr, 1);
3519 break;
3520 case KVM_SET_MSRS:
3521 r = msr_io(vcpu, argp, do_set_msr, 0);
3522 break;
3523 case KVM_TPR_ACCESS_REPORTING: {
3524 struct kvm_tpr_access_ctl tac;
3526 r = -EFAULT;
3527 if (copy_from_user(&tac, argp, sizeof tac))
3528 goto out;
3529 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3530 if (r)
3531 goto out;
3532 r = -EFAULT;
3533 if (copy_to_user(argp, &tac, sizeof tac))
3534 goto out;
3535 r = 0;
3536 break;
3538 case KVM_SET_VAPIC_ADDR: {
3539 struct kvm_vapic_addr va;
3540 int idx;
3542 r = -EINVAL;
3543 if (!lapic_in_kernel(vcpu))
3544 goto out;
3545 r = -EFAULT;
3546 if (copy_from_user(&va, argp, sizeof va))
3547 goto out;
3548 idx = srcu_read_lock(&vcpu->kvm->srcu);
3549 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3550 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3551 break;
3553 case KVM_X86_SETUP_MCE: {
3554 u64 mcg_cap;
3556 r = -EFAULT;
3557 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3558 goto out;
3559 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3560 break;
3562 case KVM_X86_SET_MCE: {
3563 struct kvm_x86_mce mce;
3565 r = -EFAULT;
3566 if (copy_from_user(&mce, argp, sizeof mce))
3567 goto out;
3568 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3569 break;
3571 case KVM_GET_VCPU_EVENTS: {
3572 struct kvm_vcpu_events events;
3574 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3576 r = -EFAULT;
3577 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3578 break;
3579 r = 0;
3580 break;
3582 case KVM_SET_VCPU_EVENTS: {
3583 struct kvm_vcpu_events events;
3585 r = -EFAULT;
3586 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3587 break;
3589 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3590 break;
3592 case KVM_GET_DEBUGREGS: {
3593 struct kvm_debugregs dbgregs;
3595 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3597 r = -EFAULT;
3598 if (copy_to_user(argp, &dbgregs,
3599 sizeof(struct kvm_debugregs)))
3600 break;
3601 r = 0;
3602 break;
3604 case KVM_SET_DEBUGREGS: {
3605 struct kvm_debugregs dbgregs;
3607 r = -EFAULT;
3608 if (copy_from_user(&dbgregs, argp,
3609 sizeof(struct kvm_debugregs)))
3610 break;
3612 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3613 break;
3615 case KVM_GET_XSAVE: {
3616 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3617 r = -ENOMEM;
3618 if (!u.xsave)
3619 break;
3621 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3623 r = -EFAULT;
3624 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3625 break;
3626 r = 0;
3627 break;
3629 case KVM_SET_XSAVE: {
3630 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3631 if (IS_ERR(u.xsave))
3632 return PTR_ERR(u.xsave);
3634 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3635 break;
3637 case KVM_GET_XCRS: {
3638 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3639 r = -ENOMEM;
3640 if (!u.xcrs)
3641 break;
3643 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3645 r = -EFAULT;
3646 if (copy_to_user(argp, u.xcrs,
3647 sizeof(struct kvm_xcrs)))
3648 break;
3649 r = 0;
3650 break;
3652 case KVM_SET_XCRS: {
3653 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3654 if (IS_ERR(u.xcrs))
3655 return PTR_ERR(u.xcrs);
3657 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3658 break;
3660 case KVM_SET_TSC_KHZ: {
3661 u32 user_tsc_khz;
3663 r = -EINVAL;
3664 user_tsc_khz = (u32)arg;
3666 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3667 goto out;
3669 if (user_tsc_khz == 0)
3670 user_tsc_khz = tsc_khz;
3672 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3673 r = 0;
3675 goto out;
3677 case KVM_GET_TSC_KHZ: {
3678 r = vcpu->arch.virtual_tsc_khz;
3679 goto out;
3681 case KVM_KVMCLOCK_CTRL: {
3682 r = kvm_set_guest_paused(vcpu);
3683 goto out;
3685 case KVM_ENABLE_CAP: {
3686 struct kvm_enable_cap cap;
3688 r = -EFAULT;
3689 if (copy_from_user(&cap, argp, sizeof(cap)))
3690 goto out;
3691 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3692 break;
3694 default:
3695 r = -EINVAL;
3697 out:
3698 kfree(u.buffer);
3699 return r;
3702 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3704 return VM_FAULT_SIGBUS;
3707 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3709 int ret;
3711 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3712 return -EINVAL;
3713 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3714 return ret;
3717 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3718 u64 ident_addr)
3720 kvm->arch.ept_identity_map_addr = ident_addr;
3721 return 0;
3724 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3725 u32 kvm_nr_mmu_pages)
3727 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3728 return -EINVAL;
3730 mutex_lock(&kvm->slots_lock);
3732 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3733 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3735 mutex_unlock(&kvm->slots_lock);
3736 return 0;
3739 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3741 return kvm->arch.n_max_mmu_pages;
3744 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3746 struct kvm_pic *pic = kvm->arch.vpic;
3747 int r;
3749 r = 0;
3750 switch (chip->chip_id) {
3751 case KVM_IRQCHIP_PIC_MASTER:
3752 memcpy(&chip->chip.pic, &pic->pics[0],
3753 sizeof(struct kvm_pic_state));
3754 break;
3755 case KVM_IRQCHIP_PIC_SLAVE:
3756 memcpy(&chip->chip.pic, &pic->pics[1],
3757 sizeof(struct kvm_pic_state));
3758 break;
3759 case KVM_IRQCHIP_IOAPIC:
3760 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3761 break;
3762 default:
3763 r = -EINVAL;
3764 break;
3766 return r;
3769 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3771 struct kvm_pic *pic = kvm->arch.vpic;
3772 int r;
3774 r = 0;
3775 switch (chip->chip_id) {
3776 case KVM_IRQCHIP_PIC_MASTER:
3777 spin_lock(&pic->lock);
3778 memcpy(&pic->pics[0], &chip->chip.pic,
3779 sizeof(struct kvm_pic_state));
3780 spin_unlock(&pic->lock);
3781 break;
3782 case KVM_IRQCHIP_PIC_SLAVE:
3783 spin_lock(&pic->lock);
3784 memcpy(&pic->pics[1], &chip->chip.pic,
3785 sizeof(struct kvm_pic_state));
3786 spin_unlock(&pic->lock);
3787 break;
3788 case KVM_IRQCHIP_IOAPIC:
3789 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3790 break;
3791 default:
3792 r = -EINVAL;
3793 break;
3795 kvm_pic_update_irq(pic);
3796 return r;
3799 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3801 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3803 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3805 mutex_lock(&kps->lock);
3806 memcpy(ps, &kps->channels, sizeof(*ps));
3807 mutex_unlock(&kps->lock);
3808 return 0;
3811 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3813 int i;
3814 struct kvm_pit *pit = kvm->arch.vpit;
3816 mutex_lock(&pit->pit_state.lock);
3817 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3818 for (i = 0; i < 3; i++)
3819 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3820 mutex_unlock(&pit->pit_state.lock);
3821 return 0;
3824 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3826 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3827 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3828 sizeof(ps->channels));
3829 ps->flags = kvm->arch.vpit->pit_state.flags;
3830 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3831 memset(&ps->reserved, 0, sizeof(ps->reserved));
3832 return 0;
3835 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3837 int start = 0;
3838 int i;
3839 u32 prev_legacy, cur_legacy;
3840 struct kvm_pit *pit = kvm->arch.vpit;
3842 mutex_lock(&pit->pit_state.lock);
3843 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3844 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3845 if (!prev_legacy && cur_legacy)
3846 start = 1;
3847 memcpy(&pit->pit_state.channels, &ps->channels,
3848 sizeof(pit->pit_state.channels));
3849 pit->pit_state.flags = ps->flags;
3850 for (i = 0; i < 3; i++)
3851 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3852 start && i == 0);
3853 mutex_unlock(&pit->pit_state.lock);
3854 return 0;
3857 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3858 struct kvm_reinject_control *control)
3860 struct kvm_pit *pit = kvm->arch.vpit;
3862 if (!pit)
3863 return -ENXIO;
3865 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3866 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3867 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3869 mutex_lock(&pit->pit_state.lock);
3870 kvm_pit_set_reinject(pit, control->pit_reinject);
3871 mutex_unlock(&pit->pit_state.lock);
3873 return 0;
3877 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3878 * @kvm: kvm instance
3879 * @log: slot id and address to which we copy the log
3881 * Steps 1-4 below provide general overview of dirty page logging. See
3882 * kvm_get_dirty_log_protect() function description for additional details.
3884 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3885 * always flush the TLB (step 4) even if previous step failed and the dirty
3886 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3887 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3888 * writes will be marked dirty for next log read.
3890 * 1. Take a snapshot of the bit and clear it if needed.
3891 * 2. Write protect the corresponding page.
3892 * 3. Copy the snapshot to the userspace.
3893 * 4. Flush TLB's if needed.
3895 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3897 bool is_dirty = false;
3898 int r;
3900 mutex_lock(&kvm->slots_lock);
3903 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3905 if (kvm_x86_ops->flush_log_dirty)
3906 kvm_x86_ops->flush_log_dirty(kvm);
3908 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3911 * All the TLBs can be flushed out of mmu lock, see the comments in
3912 * kvm_mmu_slot_remove_write_access().
3914 lockdep_assert_held(&kvm->slots_lock);
3915 if (is_dirty)
3916 kvm_flush_remote_tlbs(kvm);
3918 mutex_unlock(&kvm->slots_lock);
3919 return r;
3922 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3923 bool line_status)
3925 if (!irqchip_in_kernel(kvm))
3926 return -ENXIO;
3928 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3929 irq_event->irq, irq_event->level,
3930 line_status);
3931 return 0;
3934 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3935 struct kvm_enable_cap *cap)
3937 int r;
3939 if (cap->flags)
3940 return -EINVAL;
3942 switch (cap->cap) {
3943 case KVM_CAP_DISABLE_QUIRKS:
3944 kvm->arch.disabled_quirks = cap->args[0];
3945 r = 0;
3946 break;
3947 case KVM_CAP_SPLIT_IRQCHIP: {
3948 mutex_lock(&kvm->lock);
3949 r = -EINVAL;
3950 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3951 goto split_irqchip_unlock;
3952 r = -EEXIST;
3953 if (irqchip_in_kernel(kvm))
3954 goto split_irqchip_unlock;
3955 if (kvm->created_vcpus)
3956 goto split_irqchip_unlock;
3957 r = kvm_setup_empty_irq_routing(kvm);
3958 if (r)
3959 goto split_irqchip_unlock;
3960 /* Pairs with irqchip_in_kernel. */
3961 smp_wmb();
3962 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
3963 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3964 r = 0;
3965 split_irqchip_unlock:
3966 mutex_unlock(&kvm->lock);
3967 break;
3969 case KVM_CAP_X2APIC_API:
3970 r = -EINVAL;
3971 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3972 break;
3974 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3975 kvm->arch.x2apic_format = true;
3976 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3977 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3979 r = 0;
3980 break;
3981 default:
3982 r = -EINVAL;
3983 break;
3985 return r;
3988 long kvm_arch_vm_ioctl(struct file *filp,
3989 unsigned int ioctl, unsigned long arg)
3991 struct kvm *kvm = filp->private_data;
3992 void __user *argp = (void __user *)arg;
3993 int r = -ENOTTY;
3995 * This union makes it completely explicit to gcc-3.x
3996 * that these two variables' stack usage should be
3997 * combined, not added together.
3999 union {
4000 struct kvm_pit_state ps;
4001 struct kvm_pit_state2 ps2;
4002 struct kvm_pit_config pit_config;
4003 } u;
4005 switch (ioctl) {
4006 case KVM_SET_TSS_ADDR:
4007 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4008 break;
4009 case KVM_SET_IDENTITY_MAP_ADDR: {
4010 u64 ident_addr;
4012 r = -EFAULT;
4013 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4014 goto out;
4015 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4016 break;
4018 case KVM_SET_NR_MMU_PAGES:
4019 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4020 break;
4021 case KVM_GET_NR_MMU_PAGES:
4022 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4023 break;
4024 case KVM_CREATE_IRQCHIP: {
4025 mutex_lock(&kvm->lock);
4027 r = -EEXIST;
4028 if (irqchip_in_kernel(kvm))
4029 goto create_irqchip_unlock;
4031 r = -EINVAL;
4032 if (kvm->created_vcpus)
4033 goto create_irqchip_unlock;
4035 r = kvm_pic_init(kvm);
4036 if (r)
4037 goto create_irqchip_unlock;
4039 r = kvm_ioapic_init(kvm);
4040 if (r) {
4041 kvm_pic_destroy(kvm);
4042 goto create_irqchip_unlock;
4045 r = kvm_setup_default_irq_routing(kvm);
4046 if (r) {
4047 kvm_ioapic_destroy(kvm);
4048 kvm_pic_destroy(kvm);
4049 goto create_irqchip_unlock;
4051 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4052 smp_wmb();
4053 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4054 create_irqchip_unlock:
4055 mutex_unlock(&kvm->lock);
4056 break;
4058 case KVM_CREATE_PIT:
4059 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4060 goto create_pit;
4061 case KVM_CREATE_PIT2:
4062 r = -EFAULT;
4063 if (copy_from_user(&u.pit_config, argp,
4064 sizeof(struct kvm_pit_config)))
4065 goto out;
4066 create_pit:
4067 mutex_lock(&kvm->lock);
4068 r = -EEXIST;
4069 if (kvm->arch.vpit)
4070 goto create_pit_unlock;
4071 r = -ENOMEM;
4072 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4073 if (kvm->arch.vpit)
4074 r = 0;
4075 create_pit_unlock:
4076 mutex_unlock(&kvm->lock);
4077 break;
4078 case KVM_GET_IRQCHIP: {
4079 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4080 struct kvm_irqchip *chip;
4082 chip = memdup_user(argp, sizeof(*chip));
4083 if (IS_ERR(chip)) {
4084 r = PTR_ERR(chip);
4085 goto out;
4088 r = -ENXIO;
4089 if (!irqchip_kernel(kvm))
4090 goto get_irqchip_out;
4091 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4092 if (r)
4093 goto get_irqchip_out;
4094 r = -EFAULT;
4095 if (copy_to_user(argp, chip, sizeof *chip))
4096 goto get_irqchip_out;
4097 r = 0;
4098 get_irqchip_out:
4099 kfree(chip);
4100 break;
4102 case KVM_SET_IRQCHIP: {
4103 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4104 struct kvm_irqchip *chip;
4106 chip = memdup_user(argp, sizeof(*chip));
4107 if (IS_ERR(chip)) {
4108 r = PTR_ERR(chip);
4109 goto out;
4112 r = -ENXIO;
4113 if (!irqchip_kernel(kvm))
4114 goto set_irqchip_out;
4115 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4116 if (r)
4117 goto set_irqchip_out;
4118 r = 0;
4119 set_irqchip_out:
4120 kfree(chip);
4121 break;
4123 case KVM_GET_PIT: {
4124 r = -EFAULT;
4125 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4126 goto out;
4127 r = -ENXIO;
4128 if (!kvm->arch.vpit)
4129 goto out;
4130 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4131 if (r)
4132 goto out;
4133 r = -EFAULT;
4134 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4135 goto out;
4136 r = 0;
4137 break;
4139 case KVM_SET_PIT: {
4140 r = -EFAULT;
4141 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4142 goto out;
4143 r = -ENXIO;
4144 if (!kvm->arch.vpit)
4145 goto out;
4146 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4147 break;
4149 case KVM_GET_PIT2: {
4150 r = -ENXIO;
4151 if (!kvm->arch.vpit)
4152 goto out;
4153 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4154 if (r)
4155 goto out;
4156 r = -EFAULT;
4157 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4158 goto out;
4159 r = 0;
4160 break;
4162 case KVM_SET_PIT2: {
4163 r = -EFAULT;
4164 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4165 goto out;
4166 r = -ENXIO;
4167 if (!kvm->arch.vpit)
4168 goto out;
4169 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4170 break;
4172 case KVM_REINJECT_CONTROL: {
4173 struct kvm_reinject_control control;
4174 r = -EFAULT;
4175 if (copy_from_user(&control, argp, sizeof(control)))
4176 goto out;
4177 r = kvm_vm_ioctl_reinject(kvm, &control);
4178 break;
4180 case KVM_SET_BOOT_CPU_ID:
4181 r = 0;
4182 mutex_lock(&kvm->lock);
4183 if (kvm->created_vcpus)
4184 r = -EBUSY;
4185 else
4186 kvm->arch.bsp_vcpu_id = arg;
4187 mutex_unlock(&kvm->lock);
4188 break;
4189 case KVM_XEN_HVM_CONFIG: {
4190 r = -EFAULT;
4191 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4192 sizeof(struct kvm_xen_hvm_config)))
4193 goto out;
4194 r = -EINVAL;
4195 if (kvm->arch.xen_hvm_config.flags)
4196 goto out;
4197 r = 0;
4198 break;
4200 case KVM_SET_CLOCK: {
4201 struct kvm_clock_data user_ns;
4202 u64 now_ns;
4204 r = -EFAULT;
4205 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4206 goto out;
4208 r = -EINVAL;
4209 if (user_ns.flags)
4210 goto out;
4212 r = 0;
4214 * TODO: userspace has to take care of races with VCPU_RUN, so
4215 * kvm_gen_update_masterclock() can be cut down to locked
4216 * pvclock_update_vm_gtod_copy().
4218 kvm_gen_update_masterclock(kvm);
4219 now_ns = get_kvmclock_ns(kvm);
4220 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4221 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4222 break;
4224 case KVM_GET_CLOCK: {
4225 struct kvm_clock_data user_ns;
4226 u64 now_ns;
4228 now_ns = get_kvmclock_ns(kvm);
4229 user_ns.clock = now_ns;
4230 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4231 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4233 r = -EFAULT;
4234 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4235 goto out;
4236 r = 0;
4237 break;
4239 case KVM_ENABLE_CAP: {
4240 struct kvm_enable_cap cap;
4242 r = -EFAULT;
4243 if (copy_from_user(&cap, argp, sizeof(cap)))
4244 goto out;
4245 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4246 break;
4248 default:
4249 r = -ENOTTY;
4251 out:
4252 return r;
4255 static void kvm_init_msr_list(void)
4257 u32 dummy[2];
4258 unsigned i, j;
4260 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4261 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4262 continue;
4265 * Even MSRs that are valid in the host may not be exposed
4266 * to the guests in some cases.
4268 switch (msrs_to_save[i]) {
4269 case MSR_IA32_BNDCFGS:
4270 if (!kvm_x86_ops->mpx_supported())
4271 continue;
4272 break;
4273 case MSR_TSC_AUX:
4274 if (!kvm_x86_ops->rdtscp_supported())
4275 continue;
4276 break;
4277 default:
4278 break;
4281 if (j < i)
4282 msrs_to_save[j] = msrs_to_save[i];
4283 j++;
4285 num_msrs_to_save = j;
4287 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4288 switch (emulated_msrs[i]) {
4289 case MSR_IA32_SMBASE:
4290 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4291 continue;
4292 break;
4293 default:
4294 break;
4297 if (j < i)
4298 emulated_msrs[j] = emulated_msrs[i];
4299 j++;
4301 num_emulated_msrs = j;
4304 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4305 const void *v)
4307 int handled = 0;
4308 int n;
4310 do {
4311 n = min(len, 8);
4312 if (!(lapic_in_kernel(vcpu) &&
4313 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4314 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4315 break;
4316 handled += n;
4317 addr += n;
4318 len -= n;
4319 v += n;
4320 } while (len);
4322 return handled;
4325 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4327 int handled = 0;
4328 int n;
4330 do {
4331 n = min(len, 8);
4332 if (!(lapic_in_kernel(vcpu) &&
4333 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4334 addr, n, v))
4335 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4336 break;
4337 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4338 handled += n;
4339 addr += n;
4340 len -= n;
4341 v += n;
4342 } while (len);
4344 return handled;
4347 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4348 struct kvm_segment *var, int seg)
4350 kvm_x86_ops->set_segment(vcpu, var, seg);
4353 void kvm_get_segment(struct kvm_vcpu *vcpu,
4354 struct kvm_segment *var, int seg)
4356 kvm_x86_ops->get_segment(vcpu, var, seg);
4359 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4360 struct x86_exception *exception)
4362 gpa_t t_gpa;
4364 BUG_ON(!mmu_is_nested(vcpu));
4366 /* NPT walks are always user-walks */
4367 access |= PFERR_USER_MASK;
4368 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4370 return t_gpa;
4373 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4374 struct x86_exception *exception)
4376 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4377 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4380 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4381 struct x86_exception *exception)
4383 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4384 access |= PFERR_FETCH_MASK;
4385 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4388 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4389 struct x86_exception *exception)
4391 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4392 access |= PFERR_WRITE_MASK;
4393 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4396 /* uses this to access any guest's mapped memory without checking CPL */
4397 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4398 struct x86_exception *exception)
4400 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4403 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4404 struct kvm_vcpu *vcpu, u32 access,
4405 struct x86_exception *exception)
4407 void *data = val;
4408 int r = X86EMUL_CONTINUE;
4410 while (bytes) {
4411 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4412 exception);
4413 unsigned offset = addr & (PAGE_SIZE-1);
4414 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4415 int ret;
4417 if (gpa == UNMAPPED_GVA)
4418 return X86EMUL_PROPAGATE_FAULT;
4419 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4420 offset, toread);
4421 if (ret < 0) {
4422 r = X86EMUL_IO_NEEDED;
4423 goto out;
4426 bytes -= toread;
4427 data += toread;
4428 addr += toread;
4430 out:
4431 return r;
4434 /* used for instruction fetching */
4435 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4436 gva_t addr, void *val, unsigned int bytes,
4437 struct x86_exception *exception)
4439 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4440 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4441 unsigned offset;
4442 int ret;
4444 /* Inline kvm_read_guest_virt_helper for speed. */
4445 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4446 exception);
4447 if (unlikely(gpa == UNMAPPED_GVA))
4448 return X86EMUL_PROPAGATE_FAULT;
4450 offset = addr & (PAGE_SIZE-1);
4451 if (WARN_ON(offset + bytes > PAGE_SIZE))
4452 bytes = (unsigned)PAGE_SIZE - offset;
4453 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4454 offset, bytes);
4455 if (unlikely(ret < 0))
4456 return X86EMUL_IO_NEEDED;
4458 return X86EMUL_CONTINUE;
4461 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4462 gva_t addr, void *val, unsigned int bytes,
4463 struct x86_exception *exception)
4465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4466 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4468 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4469 exception);
4471 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4473 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4474 gva_t addr, void *val, unsigned int bytes,
4475 struct x86_exception *exception)
4477 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4478 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4481 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4482 unsigned long addr, void *val, unsigned int bytes)
4484 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4485 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4487 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4490 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4491 gva_t addr, void *val,
4492 unsigned int bytes,
4493 struct x86_exception *exception)
4495 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4496 void *data = val;
4497 int r = X86EMUL_CONTINUE;
4499 while (bytes) {
4500 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4501 PFERR_WRITE_MASK,
4502 exception);
4503 unsigned offset = addr & (PAGE_SIZE-1);
4504 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4505 int ret;
4507 if (gpa == UNMAPPED_GVA)
4508 return X86EMUL_PROPAGATE_FAULT;
4509 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4510 if (ret < 0) {
4511 r = X86EMUL_IO_NEEDED;
4512 goto out;
4515 bytes -= towrite;
4516 data += towrite;
4517 addr += towrite;
4519 out:
4520 return r;
4522 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4524 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4525 gpa_t gpa, bool write)
4527 /* For APIC access vmexit */
4528 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4529 return 1;
4531 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4532 trace_vcpu_match_mmio(gva, gpa, write, true);
4533 return 1;
4536 return 0;
4539 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4540 gpa_t *gpa, struct x86_exception *exception,
4541 bool write)
4543 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4544 | (write ? PFERR_WRITE_MASK : 0);
4547 * currently PKRU is only applied to ept enabled guest so
4548 * there is no pkey in EPT page table for L1 guest or EPT
4549 * shadow page table for L2 guest.
4551 if (vcpu_match_mmio_gva(vcpu, gva)
4552 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4553 vcpu->arch.access, 0, access)) {
4554 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4555 (gva & (PAGE_SIZE - 1));
4556 trace_vcpu_match_mmio(gva, *gpa, write, false);
4557 return 1;
4560 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4562 if (*gpa == UNMAPPED_GVA)
4563 return -1;
4565 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4568 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4569 const void *val, int bytes)
4571 int ret;
4573 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4574 if (ret < 0)
4575 return 0;
4576 kvm_page_track_write(vcpu, gpa, val, bytes);
4577 return 1;
4580 struct read_write_emulator_ops {
4581 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4582 int bytes);
4583 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4584 void *val, int bytes);
4585 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4586 int bytes, void *val);
4587 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4588 void *val, int bytes);
4589 bool write;
4592 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4594 if (vcpu->mmio_read_completed) {
4595 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4596 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4597 vcpu->mmio_read_completed = 0;
4598 return 1;
4601 return 0;
4604 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4605 void *val, int bytes)
4607 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4610 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4611 void *val, int bytes)
4613 return emulator_write_phys(vcpu, gpa, val, bytes);
4616 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4618 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4619 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4622 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4623 void *val, int bytes)
4625 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4626 return X86EMUL_IO_NEEDED;
4629 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4630 void *val, int bytes)
4632 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4634 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4635 return X86EMUL_CONTINUE;
4638 static const struct read_write_emulator_ops read_emultor = {
4639 .read_write_prepare = read_prepare,
4640 .read_write_emulate = read_emulate,
4641 .read_write_mmio = vcpu_mmio_read,
4642 .read_write_exit_mmio = read_exit_mmio,
4645 static const struct read_write_emulator_ops write_emultor = {
4646 .read_write_emulate = write_emulate,
4647 .read_write_mmio = write_mmio,
4648 .read_write_exit_mmio = write_exit_mmio,
4649 .write = true,
4652 static int emulator_read_write_onepage(unsigned long addr, void *val,
4653 unsigned int bytes,
4654 struct x86_exception *exception,
4655 struct kvm_vcpu *vcpu,
4656 const struct read_write_emulator_ops *ops)
4658 gpa_t gpa;
4659 int handled, ret;
4660 bool write = ops->write;
4661 struct kvm_mmio_fragment *frag;
4662 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4665 * If the exit was due to a NPF we may already have a GPA.
4666 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4667 * Note, this cannot be used on string operations since string
4668 * operation using rep will only have the initial GPA from the NPF
4669 * occurred.
4671 if (vcpu->arch.gpa_available &&
4672 emulator_can_use_gpa(ctxt) &&
4673 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4674 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4675 gpa = exception->address;
4676 goto mmio;
4679 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4681 if (ret < 0)
4682 return X86EMUL_PROPAGATE_FAULT;
4684 /* For APIC access vmexit */
4685 if (ret)
4686 goto mmio;
4688 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4689 return X86EMUL_CONTINUE;
4691 mmio:
4693 * Is this MMIO handled locally?
4695 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4696 if (handled == bytes)
4697 return X86EMUL_CONTINUE;
4699 gpa += handled;
4700 bytes -= handled;
4701 val += handled;
4703 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4704 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4705 frag->gpa = gpa;
4706 frag->data = val;
4707 frag->len = bytes;
4708 return X86EMUL_CONTINUE;
4711 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4712 unsigned long addr,
4713 void *val, unsigned int bytes,
4714 struct x86_exception *exception,
4715 const struct read_write_emulator_ops *ops)
4717 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4718 gpa_t gpa;
4719 int rc;
4721 if (ops->read_write_prepare &&
4722 ops->read_write_prepare(vcpu, val, bytes))
4723 return X86EMUL_CONTINUE;
4725 vcpu->mmio_nr_fragments = 0;
4727 /* Crossing a page boundary? */
4728 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4729 int now;
4731 now = -addr & ~PAGE_MASK;
4732 rc = emulator_read_write_onepage(addr, val, now, exception,
4733 vcpu, ops);
4735 if (rc != X86EMUL_CONTINUE)
4736 return rc;
4737 addr += now;
4738 if (ctxt->mode != X86EMUL_MODE_PROT64)
4739 addr = (u32)addr;
4740 val += now;
4741 bytes -= now;
4744 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4745 vcpu, ops);
4746 if (rc != X86EMUL_CONTINUE)
4747 return rc;
4749 if (!vcpu->mmio_nr_fragments)
4750 return rc;
4752 gpa = vcpu->mmio_fragments[0].gpa;
4754 vcpu->mmio_needed = 1;
4755 vcpu->mmio_cur_fragment = 0;
4757 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4758 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4759 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4760 vcpu->run->mmio.phys_addr = gpa;
4762 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4765 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4766 unsigned long addr,
4767 void *val,
4768 unsigned int bytes,
4769 struct x86_exception *exception)
4771 return emulator_read_write(ctxt, addr, val, bytes,
4772 exception, &read_emultor);
4775 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4776 unsigned long addr,
4777 const void *val,
4778 unsigned int bytes,
4779 struct x86_exception *exception)
4781 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4782 exception, &write_emultor);
4785 #define CMPXCHG_TYPE(t, ptr, old, new) \
4786 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4788 #ifdef CONFIG_X86_64
4789 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4790 #else
4791 # define CMPXCHG64(ptr, old, new) \
4792 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4793 #endif
4795 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4796 unsigned long addr,
4797 const void *old,
4798 const void *new,
4799 unsigned int bytes,
4800 struct x86_exception *exception)
4802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4803 gpa_t gpa;
4804 struct page *page;
4805 char *kaddr;
4806 bool exchanged;
4808 /* guests cmpxchg8b have to be emulated atomically */
4809 if (bytes > 8 || (bytes & (bytes - 1)))
4810 goto emul_write;
4812 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4814 if (gpa == UNMAPPED_GVA ||
4815 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4816 goto emul_write;
4818 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4819 goto emul_write;
4821 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4822 if (is_error_page(page))
4823 goto emul_write;
4825 kaddr = kmap_atomic(page);
4826 kaddr += offset_in_page(gpa);
4827 switch (bytes) {
4828 case 1:
4829 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4830 break;
4831 case 2:
4832 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4833 break;
4834 case 4:
4835 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4836 break;
4837 case 8:
4838 exchanged = CMPXCHG64(kaddr, old, new);
4839 break;
4840 default:
4841 BUG();
4843 kunmap_atomic(kaddr);
4844 kvm_release_page_dirty(page);
4846 if (!exchanged)
4847 return X86EMUL_CMPXCHG_FAILED;
4849 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4850 kvm_page_track_write(vcpu, gpa, new, bytes);
4852 return X86EMUL_CONTINUE;
4854 emul_write:
4855 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4857 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4860 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4862 int r = 0, i;
4864 for (i = 0; i < vcpu->arch.pio.count; i++) {
4865 if (vcpu->arch.pio.in)
4866 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4867 vcpu->arch.pio.size, pd);
4868 else
4869 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4870 vcpu->arch.pio.port, vcpu->arch.pio.size,
4871 pd);
4872 if (r)
4873 break;
4874 pd += vcpu->arch.pio.size;
4876 return r;
4879 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4880 unsigned short port, void *val,
4881 unsigned int count, bool in)
4883 vcpu->arch.pio.port = port;
4884 vcpu->arch.pio.in = in;
4885 vcpu->arch.pio.count = count;
4886 vcpu->arch.pio.size = size;
4888 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4889 vcpu->arch.pio.count = 0;
4890 return 1;
4893 vcpu->run->exit_reason = KVM_EXIT_IO;
4894 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4895 vcpu->run->io.size = size;
4896 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4897 vcpu->run->io.count = count;
4898 vcpu->run->io.port = port;
4900 return 0;
4903 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4904 int size, unsigned short port, void *val,
4905 unsigned int count)
4907 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4908 int ret;
4910 if (vcpu->arch.pio.count)
4911 goto data_avail;
4913 memset(vcpu->arch.pio_data, 0, size * count);
4915 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4916 if (ret) {
4917 data_avail:
4918 memcpy(val, vcpu->arch.pio_data, size * count);
4919 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4920 vcpu->arch.pio.count = 0;
4921 return 1;
4924 return 0;
4927 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4928 int size, unsigned short port,
4929 const void *val, unsigned int count)
4931 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4933 memcpy(vcpu->arch.pio_data, val, size * count);
4934 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4935 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4938 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4940 return kvm_x86_ops->get_segment_base(vcpu, seg);
4943 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4945 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4948 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4950 if (!need_emulate_wbinvd(vcpu))
4951 return X86EMUL_CONTINUE;
4953 if (kvm_x86_ops->has_wbinvd_exit()) {
4954 int cpu = get_cpu();
4956 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4957 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4958 wbinvd_ipi, NULL, 1);
4959 put_cpu();
4960 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4961 } else
4962 wbinvd();
4963 return X86EMUL_CONTINUE;
4966 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4968 kvm_emulate_wbinvd_noskip(vcpu);
4969 return kvm_skip_emulated_instruction(vcpu);
4971 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4975 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4977 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4980 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4981 unsigned long *dest)
4983 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4986 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4987 unsigned long value)
4990 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4993 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4995 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4998 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5001 unsigned long value;
5003 switch (cr) {
5004 case 0:
5005 value = kvm_read_cr0(vcpu);
5006 break;
5007 case 2:
5008 value = vcpu->arch.cr2;
5009 break;
5010 case 3:
5011 value = kvm_read_cr3(vcpu);
5012 break;
5013 case 4:
5014 value = kvm_read_cr4(vcpu);
5015 break;
5016 case 8:
5017 value = kvm_get_cr8(vcpu);
5018 break;
5019 default:
5020 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5021 return 0;
5024 return value;
5027 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5029 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5030 int res = 0;
5032 switch (cr) {
5033 case 0:
5034 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5035 break;
5036 case 2:
5037 vcpu->arch.cr2 = val;
5038 break;
5039 case 3:
5040 res = kvm_set_cr3(vcpu, val);
5041 break;
5042 case 4:
5043 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5044 break;
5045 case 8:
5046 res = kvm_set_cr8(vcpu, val);
5047 break;
5048 default:
5049 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5050 res = -1;
5053 return res;
5056 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5058 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5061 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5063 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5066 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5068 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5071 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5073 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5076 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5078 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5081 static unsigned long emulator_get_cached_segment_base(
5082 struct x86_emulate_ctxt *ctxt, int seg)
5084 return get_segment_base(emul_to_vcpu(ctxt), seg);
5087 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5088 struct desc_struct *desc, u32 *base3,
5089 int seg)
5091 struct kvm_segment var;
5093 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5094 *selector = var.selector;
5096 if (var.unusable) {
5097 memset(desc, 0, sizeof(*desc));
5098 if (base3)
5099 *base3 = 0;
5100 return false;
5103 if (var.g)
5104 var.limit >>= 12;
5105 set_desc_limit(desc, var.limit);
5106 set_desc_base(desc, (unsigned long)var.base);
5107 #ifdef CONFIG_X86_64
5108 if (base3)
5109 *base3 = var.base >> 32;
5110 #endif
5111 desc->type = var.type;
5112 desc->s = var.s;
5113 desc->dpl = var.dpl;
5114 desc->p = var.present;
5115 desc->avl = var.avl;
5116 desc->l = var.l;
5117 desc->d = var.db;
5118 desc->g = var.g;
5120 return true;
5123 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5124 struct desc_struct *desc, u32 base3,
5125 int seg)
5127 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5128 struct kvm_segment var;
5130 var.selector = selector;
5131 var.base = get_desc_base(desc);
5132 #ifdef CONFIG_X86_64
5133 var.base |= ((u64)base3) << 32;
5134 #endif
5135 var.limit = get_desc_limit(desc);
5136 if (desc->g)
5137 var.limit = (var.limit << 12) | 0xfff;
5138 var.type = desc->type;
5139 var.dpl = desc->dpl;
5140 var.db = desc->d;
5141 var.s = desc->s;
5142 var.l = desc->l;
5143 var.g = desc->g;
5144 var.avl = desc->avl;
5145 var.present = desc->p;
5146 var.unusable = !var.present;
5147 var.padding = 0;
5149 kvm_set_segment(vcpu, &var, seg);
5150 return;
5153 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5154 u32 msr_index, u64 *pdata)
5156 struct msr_data msr;
5157 int r;
5159 msr.index = msr_index;
5160 msr.host_initiated = false;
5161 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5162 if (r)
5163 return r;
5165 *pdata = msr.data;
5166 return 0;
5169 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5170 u32 msr_index, u64 data)
5172 struct msr_data msr;
5174 msr.data = data;
5175 msr.index = msr_index;
5176 msr.host_initiated = false;
5177 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5180 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5182 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5184 return vcpu->arch.smbase;
5187 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5189 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5191 vcpu->arch.smbase = smbase;
5194 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5195 u32 pmc)
5197 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5200 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5201 u32 pmc, u64 *pdata)
5203 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5206 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5208 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5211 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5213 preempt_disable();
5214 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5217 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5219 preempt_enable();
5222 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5223 struct x86_instruction_info *info,
5224 enum x86_intercept_stage stage)
5226 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5229 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5230 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5232 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5235 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5237 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5240 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5242 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5245 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5247 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5250 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5252 return emul_to_vcpu(ctxt)->arch.hflags;
5255 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5257 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5260 static const struct x86_emulate_ops emulate_ops = {
5261 .read_gpr = emulator_read_gpr,
5262 .write_gpr = emulator_write_gpr,
5263 .read_std = kvm_read_guest_virt_system,
5264 .write_std = kvm_write_guest_virt_system,
5265 .read_phys = kvm_read_guest_phys_system,
5266 .fetch = kvm_fetch_guest_virt,
5267 .read_emulated = emulator_read_emulated,
5268 .write_emulated = emulator_write_emulated,
5269 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5270 .invlpg = emulator_invlpg,
5271 .pio_in_emulated = emulator_pio_in_emulated,
5272 .pio_out_emulated = emulator_pio_out_emulated,
5273 .get_segment = emulator_get_segment,
5274 .set_segment = emulator_set_segment,
5275 .get_cached_segment_base = emulator_get_cached_segment_base,
5276 .get_gdt = emulator_get_gdt,
5277 .get_idt = emulator_get_idt,
5278 .set_gdt = emulator_set_gdt,
5279 .set_idt = emulator_set_idt,
5280 .get_cr = emulator_get_cr,
5281 .set_cr = emulator_set_cr,
5282 .cpl = emulator_get_cpl,
5283 .get_dr = emulator_get_dr,
5284 .set_dr = emulator_set_dr,
5285 .get_smbase = emulator_get_smbase,
5286 .set_smbase = emulator_set_smbase,
5287 .set_msr = emulator_set_msr,
5288 .get_msr = emulator_get_msr,
5289 .check_pmc = emulator_check_pmc,
5290 .read_pmc = emulator_read_pmc,
5291 .halt = emulator_halt,
5292 .wbinvd = emulator_wbinvd,
5293 .fix_hypercall = emulator_fix_hypercall,
5294 .get_fpu = emulator_get_fpu,
5295 .put_fpu = emulator_put_fpu,
5296 .intercept = emulator_intercept,
5297 .get_cpuid = emulator_get_cpuid,
5298 .set_nmi_mask = emulator_set_nmi_mask,
5299 .get_hflags = emulator_get_hflags,
5300 .set_hflags = emulator_set_hflags,
5303 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5305 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5307 * an sti; sti; sequence only disable interrupts for the first
5308 * instruction. So, if the last instruction, be it emulated or
5309 * not, left the system with the INT_STI flag enabled, it
5310 * means that the last instruction is an sti. We should not
5311 * leave the flag on in this case. The same goes for mov ss
5313 if (int_shadow & mask)
5314 mask = 0;
5315 if (unlikely(int_shadow || mask)) {
5316 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5317 if (!mask)
5318 kvm_make_request(KVM_REQ_EVENT, vcpu);
5322 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5324 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5325 if (ctxt->exception.vector == PF_VECTOR)
5326 return kvm_propagate_fault(vcpu, &ctxt->exception);
5328 if (ctxt->exception.error_code_valid)
5329 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5330 ctxt->exception.error_code);
5331 else
5332 kvm_queue_exception(vcpu, ctxt->exception.vector);
5333 return false;
5336 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5338 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5339 int cs_db, cs_l;
5341 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5343 ctxt->eflags = kvm_get_rflags(vcpu);
5344 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5346 ctxt->eip = kvm_rip_read(vcpu);
5347 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5348 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5349 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5350 cs_db ? X86EMUL_MODE_PROT32 :
5351 X86EMUL_MODE_PROT16;
5352 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5353 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5354 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5356 init_decode_cache(ctxt);
5357 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5360 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5362 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5363 int ret;
5365 init_emulate_ctxt(vcpu);
5367 ctxt->op_bytes = 2;
5368 ctxt->ad_bytes = 2;
5369 ctxt->_eip = ctxt->eip + inc_eip;
5370 ret = emulate_int_real(ctxt, irq);
5372 if (ret != X86EMUL_CONTINUE)
5373 return EMULATE_FAIL;
5375 ctxt->eip = ctxt->_eip;
5376 kvm_rip_write(vcpu, ctxt->eip);
5377 kvm_set_rflags(vcpu, ctxt->eflags);
5379 if (irq == NMI_VECTOR)
5380 vcpu->arch.nmi_pending = 0;
5381 else
5382 vcpu->arch.interrupt.pending = false;
5384 return EMULATE_DONE;
5386 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5388 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5390 int r = EMULATE_DONE;
5392 ++vcpu->stat.insn_emulation_fail;
5393 trace_kvm_emulate_insn_failed(vcpu);
5394 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5395 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5396 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5397 vcpu->run->internal.ndata = 0;
5398 r = EMULATE_FAIL;
5400 kvm_queue_exception(vcpu, UD_VECTOR);
5402 return r;
5405 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5406 bool write_fault_to_shadow_pgtable,
5407 int emulation_type)
5409 gpa_t gpa = cr2;
5410 kvm_pfn_t pfn;
5412 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5413 return false;
5415 if (!vcpu->arch.mmu.direct_map) {
5417 * Write permission should be allowed since only
5418 * write access need to be emulated.
5420 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5423 * If the mapping is invalid in guest, let cpu retry
5424 * it to generate fault.
5426 if (gpa == UNMAPPED_GVA)
5427 return true;
5431 * Do not retry the unhandleable instruction if it faults on the
5432 * readonly host memory, otherwise it will goto a infinite loop:
5433 * retry instruction -> write #PF -> emulation fail -> retry
5434 * instruction -> ...
5436 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5439 * If the instruction failed on the error pfn, it can not be fixed,
5440 * report the error to userspace.
5442 if (is_error_noslot_pfn(pfn))
5443 return false;
5445 kvm_release_pfn_clean(pfn);
5447 /* The instructions are well-emulated on direct mmu. */
5448 if (vcpu->arch.mmu.direct_map) {
5449 unsigned int indirect_shadow_pages;
5451 spin_lock(&vcpu->kvm->mmu_lock);
5452 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5453 spin_unlock(&vcpu->kvm->mmu_lock);
5455 if (indirect_shadow_pages)
5456 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5458 return true;
5462 * if emulation was due to access to shadowed page table
5463 * and it failed try to unshadow page and re-enter the
5464 * guest to let CPU execute the instruction.
5466 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5469 * If the access faults on its page table, it can not
5470 * be fixed by unprotecting shadow page and it should
5471 * be reported to userspace.
5473 return !write_fault_to_shadow_pgtable;
5476 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5477 unsigned long cr2, int emulation_type)
5479 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5480 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5482 last_retry_eip = vcpu->arch.last_retry_eip;
5483 last_retry_addr = vcpu->arch.last_retry_addr;
5486 * If the emulation is caused by #PF and it is non-page_table
5487 * writing instruction, it means the VM-EXIT is caused by shadow
5488 * page protected, we can zap the shadow page and retry this
5489 * instruction directly.
5491 * Note: if the guest uses a non-page-table modifying instruction
5492 * on the PDE that points to the instruction, then we will unmap
5493 * the instruction and go to an infinite loop. So, we cache the
5494 * last retried eip and the last fault address, if we meet the eip
5495 * and the address again, we can break out of the potential infinite
5496 * loop.
5498 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5500 if (!(emulation_type & EMULTYPE_RETRY))
5501 return false;
5503 if (x86_page_table_writing_insn(ctxt))
5504 return false;
5506 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5507 return false;
5509 vcpu->arch.last_retry_eip = ctxt->eip;
5510 vcpu->arch.last_retry_addr = cr2;
5512 if (!vcpu->arch.mmu.direct_map)
5513 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5515 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5517 return true;
5520 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5521 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5523 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5525 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5526 /* This is a good place to trace that we are exiting SMM. */
5527 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5529 /* Process a latched INIT or SMI, if any. */
5530 kvm_make_request(KVM_REQ_EVENT, vcpu);
5533 kvm_mmu_reset_context(vcpu);
5536 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5538 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5540 vcpu->arch.hflags = emul_flags;
5542 if (changed & HF_SMM_MASK)
5543 kvm_smm_changed(vcpu);
5546 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5547 unsigned long *db)
5549 u32 dr6 = 0;
5550 int i;
5551 u32 enable, rwlen;
5553 enable = dr7;
5554 rwlen = dr7 >> 16;
5555 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5556 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5557 dr6 |= (1 << i);
5558 return dr6;
5561 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5563 struct kvm_run *kvm_run = vcpu->run;
5565 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5566 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5567 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5568 kvm_run->debug.arch.exception = DB_VECTOR;
5569 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5570 *r = EMULATE_USER_EXIT;
5571 } else {
5573 * "Certain debug exceptions may clear bit 0-3. The
5574 * remaining contents of the DR6 register are never
5575 * cleared by the processor".
5577 vcpu->arch.dr6 &= ~15;
5578 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5579 kvm_queue_exception(vcpu, DB_VECTOR);
5583 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5585 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5586 int r = EMULATE_DONE;
5588 kvm_x86_ops->skip_emulated_instruction(vcpu);
5591 * rflags is the old, "raw" value of the flags. The new value has
5592 * not been saved yet.
5594 * This is correct even for TF set by the guest, because "the
5595 * processor will not generate this exception after the instruction
5596 * that sets the TF flag".
5598 if (unlikely(rflags & X86_EFLAGS_TF))
5599 kvm_vcpu_do_singlestep(vcpu, &r);
5600 return r == EMULATE_DONE;
5602 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5604 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5606 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5607 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5608 struct kvm_run *kvm_run = vcpu->run;
5609 unsigned long eip = kvm_get_linear_rip(vcpu);
5610 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5611 vcpu->arch.guest_debug_dr7,
5612 vcpu->arch.eff_db);
5614 if (dr6 != 0) {
5615 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5616 kvm_run->debug.arch.pc = eip;
5617 kvm_run->debug.arch.exception = DB_VECTOR;
5618 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5619 *r = EMULATE_USER_EXIT;
5620 return true;
5624 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5625 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5626 unsigned long eip = kvm_get_linear_rip(vcpu);
5627 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5628 vcpu->arch.dr7,
5629 vcpu->arch.db);
5631 if (dr6 != 0) {
5632 vcpu->arch.dr6 &= ~15;
5633 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5634 kvm_queue_exception(vcpu, DB_VECTOR);
5635 *r = EMULATE_DONE;
5636 return true;
5640 return false;
5643 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5644 unsigned long cr2,
5645 int emulation_type,
5646 void *insn,
5647 int insn_len)
5649 int r;
5650 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5651 bool writeback = true;
5652 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5655 * Clear write_fault_to_shadow_pgtable here to ensure it is
5656 * never reused.
5658 vcpu->arch.write_fault_to_shadow_pgtable = false;
5659 kvm_clear_exception_queue(vcpu);
5661 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5662 init_emulate_ctxt(vcpu);
5665 * We will reenter on the same instruction since
5666 * we do not set complete_userspace_io. This does not
5667 * handle watchpoints yet, those would be handled in
5668 * the emulate_ops.
5670 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5671 return r;
5673 ctxt->interruptibility = 0;
5674 ctxt->have_exception = false;
5675 ctxt->exception.vector = -1;
5676 ctxt->perm_ok = false;
5678 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5680 r = x86_decode_insn(ctxt, insn, insn_len);
5682 trace_kvm_emulate_insn_start(vcpu);
5683 ++vcpu->stat.insn_emulation;
5684 if (r != EMULATION_OK) {
5685 if (emulation_type & EMULTYPE_TRAP_UD)
5686 return EMULATE_FAIL;
5687 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5688 emulation_type))
5689 return EMULATE_DONE;
5690 if (emulation_type & EMULTYPE_SKIP)
5691 return EMULATE_FAIL;
5692 return handle_emulation_failure(vcpu);
5696 if (emulation_type & EMULTYPE_SKIP) {
5697 kvm_rip_write(vcpu, ctxt->_eip);
5698 if (ctxt->eflags & X86_EFLAGS_RF)
5699 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5700 return EMULATE_DONE;
5703 if (retry_instruction(ctxt, cr2, emulation_type))
5704 return EMULATE_DONE;
5706 /* this is needed for vmware backdoor interface to work since it
5707 changes registers values during IO operation */
5708 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5709 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5710 emulator_invalidate_register_cache(ctxt);
5713 restart:
5714 /* Save the faulting GPA (cr2) in the address field */
5715 ctxt->exception.address = cr2;
5717 r = x86_emulate_insn(ctxt);
5719 if (r == EMULATION_INTERCEPTED)
5720 return EMULATE_DONE;
5722 if (r == EMULATION_FAILED) {
5723 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5724 emulation_type))
5725 return EMULATE_DONE;
5727 return handle_emulation_failure(vcpu);
5730 if (ctxt->have_exception) {
5731 r = EMULATE_DONE;
5732 if (inject_emulated_exception(vcpu))
5733 return r;
5734 } else if (vcpu->arch.pio.count) {
5735 if (!vcpu->arch.pio.in) {
5736 /* FIXME: return into emulator if single-stepping. */
5737 vcpu->arch.pio.count = 0;
5738 } else {
5739 writeback = false;
5740 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5742 r = EMULATE_USER_EXIT;
5743 } else if (vcpu->mmio_needed) {
5744 if (!vcpu->mmio_is_write)
5745 writeback = false;
5746 r = EMULATE_USER_EXIT;
5747 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5748 } else if (r == EMULATION_RESTART)
5749 goto restart;
5750 else
5751 r = EMULATE_DONE;
5753 if (writeback) {
5754 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5755 toggle_interruptibility(vcpu, ctxt->interruptibility);
5756 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5757 kvm_rip_write(vcpu, ctxt->eip);
5758 if (r == EMULATE_DONE &&
5759 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5760 kvm_vcpu_do_singlestep(vcpu, &r);
5761 if (!ctxt->have_exception ||
5762 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5763 __kvm_set_rflags(vcpu, ctxt->eflags);
5766 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5767 * do nothing, and it will be requested again as soon as
5768 * the shadow expires. But we still need to check here,
5769 * because POPF has no interrupt shadow.
5771 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5772 kvm_make_request(KVM_REQ_EVENT, vcpu);
5773 } else
5774 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5776 return r;
5778 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5780 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5782 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5783 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5784 size, port, &val, 1);
5785 /* do not return to emulator after return from userspace */
5786 vcpu->arch.pio.count = 0;
5787 return ret;
5789 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5791 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5793 unsigned long val;
5795 /* We should only ever be called with arch.pio.count equal to 1 */
5796 BUG_ON(vcpu->arch.pio.count != 1);
5798 /* For size less than 4 we merge, else we zero extend */
5799 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5800 : 0;
5803 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5804 * the copy and tracing
5806 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5807 vcpu->arch.pio.port, &val, 1);
5808 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5810 return 1;
5813 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5815 unsigned long val;
5816 int ret;
5818 /* For size less than 4 we merge, else we zero extend */
5819 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5821 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5822 &val, 1);
5823 if (ret) {
5824 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5825 return ret;
5828 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5830 return 0;
5832 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5834 static int kvmclock_cpu_down_prep(unsigned int cpu)
5836 __this_cpu_write(cpu_tsc_khz, 0);
5837 return 0;
5840 static void tsc_khz_changed(void *data)
5842 struct cpufreq_freqs *freq = data;
5843 unsigned long khz = 0;
5845 if (data)
5846 khz = freq->new;
5847 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5848 khz = cpufreq_quick_get(raw_smp_processor_id());
5849 if (!khz)
5850 khz = tsc_khz;
5851 __this_cpu_write(cpu_tsc_khz, khz);
5854 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5855 void *data)
5857 struct cpufreq_freqs *freq = data;
5858 struct kvm *kvm;
5859 struct kvm_vcpu *vcpu;
5860 int i, send_ipi = 0;
5863 * We allow guests to temporarily run on slowing clocks,
5864 * provided we notify them after, or to run on accelerating
5865 * clocks, provided we notify them before. Thus time never
5866 * goes backwards.
5868 * However, we have a problem. We can't atomically update
5869 * the frequency of a given CPU from this function; it is
5870 * merely a notifier, which can be called from any CPU.
5871 * Changing the TSC frequency at arbitrary points in time
5872 * requires a recomputation of local variables related to
5873 * the TSC for each VCPU. We must flag these local variables
5874 * to be updated and be sure the update takes place with the
5875 * new frequency before any guests proceed.
5877 * Unfortunately, the combination of hotplug CPU and frequency
5878 * change creates an intractable locking scenario; the order
5879 * of when these callouts happen is undefined with respect to
5880 * CPU hotplug, and they can race with each other. As such,
5881 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5882 * undefined; you can actually have a CPU frequency change take
5883 * place in between the computation of X and the setting of the
5884 * variable. To protect against this problem, all updates of
5885 * the per_cpu tsc_khz variable are done in an interrupt
5886 * protected IPI, and all callers wishing to update the value
5887 * must wait for a synchronous IPI to complete (which is trivial
5888 * if the caller is on the CPU already). This establishes the
5889 * necessary total order on variable updates.
5891 * Note that because a guest time update may take place
5892 * anytime after the setting of the VCPU's request bit, the
5893 * correct TSC value must be set before the request. However,
5894 * to ensure the update actually makes it to any guest which
5895 * starts running in hardware virtualization between the set
5896 * and the acquisition of the spinlock, we must also ping the
5897 * CPU after setting the request bit.
5901 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5902 return 0;
5903 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5904 return 0;
5906 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5908 spin_lock(&kvm_lock);
5909 list_for_each_entry(kvm, &vm_list, vm_list) {
5910 kvm_for_each_vcpu(i, vcpu, kvm) {
5911 if (vcpu->cpu != freq->cpu)
5912 continue;
5913 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5914 if (vcpu->cpu != smp_processor_id())
5915 send_ipi = 1;
5918 spin_unlock(&kvm_lock);
5920 if (freq->old < freq->new && send_ipi) {
5922 * We upscale the frequency. Must make the guest
5923 * doesn't see old kvmclock values while running with
5924 * the new frequency, otherwise we risk the guest sees
5925 * time go backwards.
5927 * In case we update the frequency for another cpu
5928 * (which might be in guest context) send an interrupt
5929 * to kick the cpu out of guest context. Next time
5930 * guest context is entered kvmclock will be updated,
5931 * so the guest will not see stale values.
5933 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5935 return 0;
5938 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5939 .notifier_call = kvmclock_cpufreq_notifier
5942 static int kvmclock_cpu_online(unsigned int cpu)
5944 tsc_khz_changed(NULL);
5945 return 0;
5948 static void kvm_timer_init(void)
5950 max_tsc_khz = tsc_khz;
5952 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5953 #ifdef CONFIG_CPU_FREQ
5954 struct cpufreq_policy policy;
5955 int cpu;
5957 memset(&policy, 0, sizeof(policy));
5958 cpu = get_cpu();
5959 cpufreq_get_policy(&policy, cpu);
5960 if (policy.cpuinfo.max_freq)
5961 max_tsc_khz = policy.cpuinfo.max_freq;
5962 put_cpu();
5963 #endif
5964 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5965 CPUFREQ_TRANSITION_NOTIFIER);
5967 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5969 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
5970 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5973 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5975 int kvm_is_in_guest(void)
5977 return __this_cpu_read(current_vcpu) != NULL;
5980 static int kvm_is_user_mode(void)
5982 int user_mode = 3;
5984 if (__this_cpu_read(current_vcpu))
5985 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5987 return user_mode != 0;
5990 static unsigned long kvm_get_guest_ip(void)
5992 unsigned long ip = 0;
5994 if (__this_cpu_read(current_vcpu))
5995 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5997 return ip;
6000 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6001 .is_in_guest = kvm_is_in_guest,
6002 .is_user_mode = kvm_is_user_mode,
6003 .get_guest_ip = kvm_get_guest_ip,
6006 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6008 __this_cpu_write(current_vcpu, vcpu);
6010 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6012 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6014 __this_cpu_write(current_vcpu, NULL);
6016 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6018 static void kvm_set_mmio_spte_mask(void)
6020 u64 mask;
6021 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6024 * Set the reserved bits and the present bit of an paging-structure
6025 * entry to generate page fault with PFER.RSV = 1.
6027 /* Mask the reserved physical address bits. */
6028 mask = rsvd_bits(maxphyaddr, 51);
6030 /* Set the present bit. */
6031 mask |= 1ull;
6033 #ifdef CONFIG_X86_64
6035 * If reserved bit is not supported, clear the present bit to disable
6036 * mmio page fault.
6038 if (maxphyaddr == 52)
6039 mask &= ~1ull;
6040 #endif
6042 kvm_mmu_set_mmio_spte_mask(mask, mask);
6045 #ifdef CONFIG_X86_64
6046 static void pvclock_gtod_update_fn(struct work_struct *work)
6048 struct kvm *kvm;
6050 struct kvm_vcpu *vcpu;
6051 int i;
6053 spin_lock(&kvm_lock);
6054 list_for_each_entry(kvm, &vm_list, vm_list)
6055 kvm_for_each_vcpu(i, vcpu, kvm)
6056 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6057 atomic_set(&kvm_guest_has_master_clock, 0);
6058 spin_unlock(&kvm_lock);
6061 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6064 * Notification about pvclock gtod data update.
6066 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6067 void *priv)
6069 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6070 struct timekeeper *tk = priv;
6072 update_pvclock_gtod(tk);
6074 /* disable master clock if host does not trust, or does not
6075 * use, TSC clocksource
6077 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6078 atomic_read(&kvm_guest_has_master_clock) != 0)
6079 queue_work(system_long_wq, &pvclock_gtod_work);
6081 return 0;
6084 static struct notifier_block pvclock_gtod_notifier = {
6085 .notifier_call = pvclock_gtod_notify,
6087 #endif
6089 int kvm_arch_init(void *opaque)
6091 int r;
6092 struct kvm_x86_ops *ops = opaque;
6094 if (kvm_x86_ops) {
6095 printk(KERN_ERR "kvm: already loaded the other module\n");
6096 r = -EEXIST;
6097 goto out;
6100 if (!ops->cpu_has_kvm_support()) {
6101 printk(KERN_ERR "kvm: no hardware support\n");
6102 r = -EOPNOTSUPP;
6103 goto out;
6105 if (ops->disabled_by_bios()) {
6106 printk(KERN_ERR "kvm: disabled by bios\n");
6107 r = -EOPNOTSUPP;
6108 goto out;
6111 r = -ENOMEM;
6112 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6113 if (!shared_msrs) {
6114 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6115 goto out;
6118 r = kvm_mmu_module_init();
6119 if (r)
6120 goto out_free_percpu;
6122 kvm_set_mmio_spte_mask();
6124 kvm_x86_ops = ops;
6126 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6127 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6128 PT_PRESENT_MASK, 0);
6129 kvm_timer_init();
6131 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6133 if (boot_cpu_has(X86_FEATURE_XSAVE))
6134 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6136 kvm_lapic_init();
6137 #ifdef CONFIG_X86_64
6138 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6139 #endif
6141 return 0;
6143 out_free_percpu:
6144 free_percpu(shared_msrs);
6145 out:
6146 return r;
6149 void kvm_arch_exit(void)
6151 kvm_lapic_exit();
6152 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6154 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6155 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6156 CPUFREQ_TRANSITION_NOTIFIER);
6157 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6158 #ifdef CONFIG_X86_64
6159 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6160 #endif
6161 kvm_x86_ops = NULL;
6162 kvm_mmu_module_exit();
6163 free_percpu(shared_msrs);
6166 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6168 ++vcpu->stat.halt_exits;
6169 if (lapic_in_kernel(vcpu)) {
6170 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6171 return 1;
6172 } else {
6173 vcpu->run->exit_reason = KVM_EXIT_HLT;
6174 return 0;
6177 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6179 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6181 int ret = kvm_skip_emulated_instruction(vcpu);
6183 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6184 * KVM_EXIT_DEBUG here.
6186 return kvm_vcpu_halt(vcpu) && ret;
6188 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6190 #ifdef CONFIG_X86_64
6191 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6192 unsigned long clock_type)
6194 struct kvm_clock_pairing clock_pairing;
6195 struct timespec ts;
6196 u64 cycle;
6197 int ret;
6199 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6200 return -KVM_EOPNOTSUPP;
6202 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6203 return -KVM_EOPNOTSUPP;
6205 clock_pairing.sec = ts.tv_sec;
6206 clock_pairing.nsec = ts.tv_nsec;
6207 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6208 clock_pairing.flags = 0;
6210 ret = 0;
6211 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6212 sizeof(struct kvm_clock_pairing)))
6213 ret = -KVM_EFAULT;
6215 return ret;
6217 #endif
6220 * kvm_pv_kick_cpu_op: Kick a vcpu.
6222 * @apicid - apicid of vcpu to be kicked.
6224 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6226 struct kvm_lapic_irq lapic_irq;
6228 lapic_irq.shorthand = 0;
6229 lapic_irq.dest_mode = 0;
6230 lapic_irq.level = 0;
6231 lapic_irq.dest_id = apicid;
6232 lapic_irq.msi_redir_hint = false;
6234 lapic_irq.delivery_mode = APIC_DM_REMRD;
6235 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6238 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6240 vcpu->arch.apicv_active = false;
6241 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6244 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6246 unsigned long nr, a0, a1, a2, a3, ret;
6247 int op_64_bit, r;
6249 r = kvm_skip_emulated_instruction(vcpu);
6251 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6252 return kvm_hv_hypercall(vcpu);
6254 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6255 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6256 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6257 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6258 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6260 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6262 op_64_bit = is_64_bit_mode(vcpu);
6263 if (!op_64_bit) {
6264 nr &= 0xFFFFFFFF;
6265 a0 &= 0xFFFFFFFF;
6266 a1 &= 0xFFFFFFFF;
6267 a2 &= 0xFFFFFFFF;
6268 a3 &= 0xFFFFFFFF;
6271 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6272 ret = -KVM_EPERM;
6273 goto out;
6276 switch (nr) {
6277 case KVM_HC_VAPIC_POLL_IRQ:
6278 ret = 0;
6279 break;
6280 case KVM_HC_KICK_CPU:
6281 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6282 ret = 0;
6283 break;
6284 #ifdef CONFIG_X86_64
6285 case KVM_HC_CLOCK_PAIRING:
6286 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6287 break;
6288 #endif
6289 default:
6290 ret = -KVM_ENOSYS;
6291 break;
6293 out:
6294 if (!op_64_bit)
6295 ret = (u32)ret;
6296 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6297 ++vcpu->stat.hypercalls;
6298 return r;
6300 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6302 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6305 char instruction[3];
6306 unsigned long rip = kvm_rip_read(vcpu);
6308 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6310 return emulator_write_emulated(ctxt, rip, instruction, 3,
6311 &ctxt->exception);
6314 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6316 return vcpu->run->request_interrupt_window &&
6317 likely(!pic_in_kernel(vcpu->kvm));
6320 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6322 struct kvm_run *kvm_run = vcpu->run;
6324 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6325 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6326 kvm_run->cr8 = kvm_get_cr8(vcpu);
6327 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6328 kvm_run->ready_for_interrupt_injection =
6329 pic_in_kernel(vcpu->kvm) ||
6330 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6333 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6335 int max_irr, tpr;
6337 if (!kvm_x86_ops->update_cr8_intercept)
6338 return;
6340 if (!lapic_in_kernel(vcpu))
6341 return;
6343 if (vcpu->arch.apicv_active)
6344 return;
6346 if (!vcpu->arch.apic->vapic_addr)
6347 max_irr = kvm_lapic_find_highest_irr(vcpu);
6348 else
6349 max_irr = -1;
6351 if (max_irr != -1)
6352 max_irr >>= 4;
6354 tpr = kvm_lapic_get_cr8(vcpu);
6356 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6359 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6361 int r;
6363 /* try to reinject previous events if any */
6364 if (vcpu->arch.exception.pending) {
6365 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6366 vcpu->arch.exception.has_error_code,
6367 vcpu->arch.exception.error_code);
6369 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6370 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6371 X86_EFLAGS_RF);
6373 if (vcpu->arch.exception.nr == DB_VECTOR &&
6374 (vcpu->arch.dr7 & DR7_GD)) {
6375 vcpu->arch.dr7 &= ~DR7_GD;
6376 kvm_update_dr7(vcpu);
6379 kvm_x86_ops->queue_exception(vcpu);
6380 return 0;
6383 if (vcpu->arch.nmi_injected) {
6384 kvm_x86_ops->set_nmi(vcpu);
6385 return 0;
6388 if (vcpu->arch.interrupt.pending) {
6389 kvm_x86_ops->set_irq(vcpu);
6390 return 0;
6393 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6394 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6395 if (r != 0)
6396 return r;
6399 /* try to inject new event if pending */
6400 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6401 vcpu->arch.smi_pending = false;
6402 enter_smm(vcpu);
6403 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6404 --vcpu->arch.nmi_pending;
6405 vcpu->arch.nmi_injected = true;
6406 kvm_x86_ops->set_nmi(vcpu);
6407 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6409 * Because interrupts can be injected asynchronously, we are
6410 * calling check_nested_events again here to avoid a race condition.
6411 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6412 * proposal and current concerns. Perhaps we should be setting
6413 * KVM_REQ_EVENT only on certain events and not unconditionally?
6415 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6416 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6417 if (r != 0)
6418 return r;
6420 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6421 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6422 false);
6423 kvm_x86_ops->set_irq(vcpu);
6427 return 0;
6430 static void process_nmi(struct kvm_vcpu *vcpu)
6432 unsigned limit = 2;
6435 * x86 is limited to one NMI running, and one NMI pending after it.
6436 * If an NMI is already in progress, limit further NMIs to just one.
6437 * Otherwise, allow two (and we'll inject the first one immediately).
6439 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6440 limit = 1;
6442 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6443 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6444 kvm_make_request(KVM_REQ_EVENT, vcpu);
6447 #define put_smstate(type, buf, offset, val) \
6448 *(type *)((buf) + (offset) - 0x7e00) = val
6450 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6452 u32 flags = 0;
6453 flags |= seg->g << 23;
6454 flags |= seg->db << 22;
6455 flags |= seg->l << 21;
6456 flags |= seg->avl << 20;
6457 flags |= seg->present << 15;
6458 flags |= seg->dpl << 13;
6459 flags |= seg->s << 12;
6460 flags |= seg->type << 8;
6461 return flags;
6464 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6466 struct kvm_segment seg;
6467 int offset;
6469 kvm_get_segment(vcpu, &seg, n);
6470 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6472 if (n < 3)
6473 offset = 0x7f84 + n * 12;
6474 else
6475 offset = 0x7f2c + (n - 3) * 12;
6477 put_smstate(u32, buf, offset + 8, seg.base);
6478 put_smstate(u32, buf, offset + 4, seg.limit);
6479 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6482 #ifdef CONFIG_X86_64
6483 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6485 struct kvm_segment seg;
6486 int offset;
6487 u16 flags;
6489 kvm_get_segment(vcpu, &seg, n);
6490 offset = 0x7e00 + n * 16;
6492 flags = enter_smm_get_segment_flags(&seg) >> 8;
6493 put_smstate(u16, buf, offset, seg.selector);
6494 put_smstate(u16, buf, offset + 2, flags);
6495 put_smstate(u32, buf, offset + 4, seg.limit);
6496 put_smstate(u64, buf, offset + 8, seg.base);
6498 #endif
6500 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6502 struct desc_ptr dt;
6503 struct kvm_segment seg;
6504 unsigned long val;
6505 int i;
6507 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6508 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6509 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6510 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6512 for (i = 0; i < 8; i++)
6513 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6515 kvm_get_dr(vcpu, 6, &val);
6516 put_smstate(u32, buf, 0x7fcc, (u32)val);
6517 kvm_get_dr(vcpu, 7, &val);
6518 put_smstate(u32, buf, 0x7fc8, (u32)val);
6520 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6521 put_smstate(u32, buf, 0x7fc4, seg.selector);
6522 put_smstate(u32, buf, 0x7f64, seg.base);
6523 put_smstate(u32, buf, 0x7f60, seg.limit);
6524 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6526 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6527 put_smstate(u32, buf, 0x7fc0, seg.selector);
6528 put_smstate(u32, buf, 0x7f80, seg.base);
6529 put_smstate(u32, buf, 0x7f7c, seg.limit);
6530 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6532 kvm_x86_ops->get_gdt(vcpu, &dt);
6533 put_smstate(u32, buf, 0x7f74, dt.address);
6534 put_smstate(u32, buf, 0x7f70, dt.size);
6536 kvm_x86_ops->get_idt(vcpu, &dt);
6537 put_smstate(u32, buf, 0x7f58, dt.address);
6538 put_smstate(u32, buf, 0x7f54, dt.size);
6540 for (i = 0; i < 6; i++)
6541 enter_smm_save_seg_32(vcpu, buf, i);
6543 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6545 /* revision id */
6546 put_smstate(u32, buf, 0x7efc, 0x00020000);
6547 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6550 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6552 #ifdef CONFIG_X86_64
6553 struct desc_ptr dt;
6554 struct kvm_segment seg;
6555 unsigned long val;
6556 int i;
6558 for (i = 0; i < 16; i++)
6559 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6561 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6562 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6564 kvm_get_dr(vcpu, 6, &val);
6565 put_smstate(u64, buf, 0x7f68, val);
6566 kvm_get_dr(vcpu, 7, &val);
6567 put_smstate(u64, buf, 0x7f60, val);
6569 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6570 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6571 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6573 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6575 /* revision id */
6576 put_smstate(u32, buf, 0x7efc, 0x00020064);
6578 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6580 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6581 put_smstate(u16, buf, 0x7e90, seg.selector);
6582 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6583 put_smstate(u32, buf, 0x7e94, seg.limit);
6584 put_smstate(u64, buf, 0x7e98, seg.base);
6586 kvm_x86_ops->get_idt(vcpu, &dt);
6587 put_smstate(u32, buf, 0x7e84, dt.size);
6588 put_smstate(u64, buf, 0x7e88, dt.address);
6590 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6591 put_smstate(u16, buf, 0x7e70, seg.selector);
6592 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6593 put_smstate(u32, buf, 0x7e74, seg.limit);
6594 put_smstate(u64, buf, 0x7e78, seg.base);
6596 kvm_x86_ops->get_gdt(vcpu, &dt);
6597 put_smstate(u32, buf, 0x7e64, dt.size);
6598 put_smstate(u64, buf, 0x7e68, dt.address);
6600 for (i = 0; i < 6; i++)
6601 enter_smm_save_seg_64(vcpu, buf, i);
6602 #else
6603 WARN_ON_ONCE(1);
6604 #endif
6607 static void enter_smm(struct kvm_vcpu *vcpu)
6609 struct kvm_segment cs, ds;
6610 struct desc_ptr dt;
6611 char buf[512];
6612 u32 cr0;
6614 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6615 vcpu->arch.hflags |= HF_SMM_MASK;
6616 memset(buf, 0, 512);
6617 if (guest_cpuid_has_longmode(vcpu))
6618 enter_smm_save_state_64(vcpu, buf);
6619 else
6620 enter_smm_save_state_32(vcpu, buf);
6622 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6624 if (kvm_x86_ops->get_nmi_mask(vcpu))
6625 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6626 else
6627 kvm_x86_ops->set_nmi_mask(vcpu, true);
6629 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6630 kvm_rip_write(vcpu, 0x8000);
6632 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6633 kvm_x86_ops->set_cr0(vcpu, cr0);
6634 vcpu->arch.cr0 = cr0;
6636 kvm_x86_ops->set_cr4(vcpu, 0);
6638 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6639 dt.address = dt.size = 0;
6640 kvm_x86_ops->set_idt(vcpu, &dt);
6642 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6644 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6645 cs.base = vcpu->arch.smbase;
6647 ds.selector = 0;
6648 ds.base = 0;
6650 cs.limit = ds.limit = 0xffffffff;
6651 cs.type = ds.type = 0x3;
6652 cs.dpl = ds.dpl = 0;
6653 cs.db = ds.db = 0;
6654 cs.s = ds.s = 1;
6655 cs.l = ds.l = 0;
6656 cs.g = ds.g = 1;
6657 cs.avl = ds.avl = 0;
6658 cs.present = ds.present = 1;
6659 cs.unusable = ds.unusable = 0;
6660 cs.padding = ds.padding = 0;
6662 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6663 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6664 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6665 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6666 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6667 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6669 if (guest_cpuid_has_longmode(vcpu))
6670 kvm_x86_ops->set_efer(vcpu, 0);
6672 kvm_update_cpuid(vcpu);
6673 kvm_mmu_reset_context(vcpu);
6676 static void process_smi(struct kvm_vcpu *vcpu)
6678 vcpu->arch.smi_pending = true;
6679 kvm_make_request(KVM_REQ_EVENT, vcpu);
6682 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6684 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6687 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6689 u64 eoi_exit_bitmap[4];
6691 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6692 return;
6694 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6696 if (irqchip_split(vcpu->kvm))
6697 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6698 else {
6699 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6700 kvm_x86_ops->sync_pir_to_irr(vcpu);
6701 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6703 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6704 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6705 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6708 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6710 ++vcpu->stat.tlb_flush;
6711 kvm_x86_ops->tlb_flush(vcpu);
6714 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6716 struct page *page = NULL;
6718 if (!lapic_in_kernel(vcpu))
6719 return;
6721 if (!kvm_x86_ops->set_apic_access_page_addr)
6722 return;
6724 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6725 if (is_error_page(page))
6726 return;
6727 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6730 * Do not pin apic access page in memory, the MMU notifier
6731 * will call us again if it is migrated or swapped out.
6733 put_page(page);
6735 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6738 * Returns 1 to let vcpu_run() continue the guest execution loop without
6739 * exiting to the userspace. Otherwise, the value will be returned to the
6740 * userspace.
6742 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6744 int r;
6745 bool req_int_win =
6746 dm_request_for_irq_injection(vcpu) &&
6747 kvm_cpu_accept_dm_intr(vcpu);
6749 bool req_immediate_exit = false;
6751 if (kvm_request_pending(vcpu)) {
6752 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6753 kvm_mmu_unload(vcpu);
6754 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6755 __kvm_migrate_timers(vcpu);
6756 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6757 kvm_gen_update_masterclock(vcpu->kvm);
6758 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6759 kvm_gen_kvmclock_update(vcpu);
6760 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6761 r = kvm_guest_time_update(vcpu);
6762 if (unlikely(r))
6763 goto out;
6765 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6766 kvm_mmu_sync_roots(vcpu);
6767 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6768 kvm_vcpu_flush_tlb(vcpu);
6769 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6770 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6771 r = 0;
6772 goto out;
6774 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6775 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6776 r = 0;
6777 goto out;
6779 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6780 /* Page is swapped out. Do synthetic halt */
6781 vcpu->arch.apf.halted = true;
6782 r = 1;
6783 goto out;
6785 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6786 record_steal_time(vcpu);
6787 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6788 process_smi(vcpu);
6789 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6790 process_nmi(vcpu);
6791 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6792 kvm_pmu_handle_event(vcpu);
6793 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6794 kvm_pmu_deliver_pmi(vcpu);
6795 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6796 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6797 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6798 vcpu->arch.ioapic_handled_vectors)) {
6799 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6800 vcpu->run->eoi.vector =
6801 vcpu->arch.pending_ioapic_eoi;
6802 r = 0;
6803 goto out;
6806 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6807 vcpu_scan_ioapic(vcpu);
6808 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6809 kvm_vcpu_reload_apic_access_page(vcpu);
6810 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6811 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6812 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6813 r = 0;
6814 goto out;
6816 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6817 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6818 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6819 r = 0;
6820 goto out;
6822 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6823 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6824 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6825 r = 0;
6826 goto out;
6830 * KVM_REQ_HV_STIMER has to be processed after
6831 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6832 * depend on the guest clock being up-to-date
6834 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6835 kvm_hv_process_stimers(vcpu);
6838 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6839 ++vcpu->stat.req_event;
6840 kvm_apic_accept_events(vcpu);
6841 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6842 r = 1;
6843 goto out;
6846 if (inject_pending_event(vcpu, req_int_win) != 0)
6847 req_immediate_exit = true;
6848 else {
6849 /* Enable NMI/IRQ window open exits if needed.
6851 * SMIs have two cases: 1) they can be nested, and
6852 * then there is nothing to do here because RSM will
6853 * cause a vmexit anyway; 2) or the SMI can be pending
6854 * because inject_pending_event has completed the
6855 * injection of an IRQ or NMI from the previous vmexit,
6856 * and then we request an immediate exit to inject the SMI.
6858 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6859 req_immediate_exit = true;
6860 if (vcpu->arch.nmi_pending)
6861 kvm_x86_ops->enable_nmi_window(vcpu);
6862 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6863 kvm_x86_ops->enable_irq_window(vcpu);
6866 if (kvm_lapic_enabled(vcpu)) {
6867 update_cr8_intercept(vcpu);
6868 kvm_lapic_sync_to_vapic(vcpu);
6872 r = kvm_mmu_reload(vcpu);
6873 if (unlikely(r)) {
6874 goto cancel_injection;
6877 preempt_disable();
6879 kvm_x86_ops->prepare_guest_switch(vcpu);
6880 kvm_load_guest_fpu(vcpu);
6883 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6884 * IPI are then delayed after guest entry, which ensures that they
6885 * result in virtual interrupt delivery.
6887 local_irq_disable();
6888 vcpu->mode = IN_GUEST_MODE;
6890 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6893 * 1) We should set ->mode before checking ->requests. Please see
6894 * the comment in kvm_vcpu_exiting_guest_mode().
6896 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6897 * pairs with the memory barrier implicit in pi_test_and_set_on
6898 * (see vmx_deliver_posted_interrupt).
6900 * 3) This also orders the write to mode from any reads to the page
6901 * tables done while the VCPU is running. Please see the comment
6902 * in kvm_flush_remote_tlbs.
6904 smp_mb__after_srcu_read_unlock();
6907 * This handles the case where a posted interrupt was
6908 * notified with kvm_vcpu_kick.
6910 if (kvm_lapic_enabled(vcpu)) {
6911 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6912 kvm_x86_ops->sync_pir_to_irr(vcpu);
6915 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
6916 || need_resched() || signal_pending(current)) {
6917 vcpu->mode = OUTSIDE_GUEST_MODE;
6918 smp_wmb();
6919 local_irq_enable();
6920 preempt_enable();
6921 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6922 r = 1;
6923 goto cancel_injection;
6926 kvm_load_guest_xcr0(vcpu);
6928 if (req_immediate_exit) {
6929 kvm_make_request(KVM_REQ_EVENT, vcpu);
6930 smp_send_reschedule(vcpu->cpu);
6933 trace_kvm_entry(vcpu->vcpu_id);
6934 wait_lapic_expire(vcpu);
6935 guest_enter_irqoff();
6937 if (unlikely(vcpu->arch.switch_db_regs)) {
6938 set_debugreg(0, 7);
6939 set_debugreg(vcpu->arch.eff_db[0], 0);
6940 set_debugreg(vcpu->arch.eff_db[1], 1);
6941 set_debugreg(vcpu->arch.eff_db[2], 2);
6942 set_debugreg(vcpu->arch.eff_db[3], 3);
6943 set_debugreg(vcpu->arch.dr6, 6);
6944 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6947 kvm_x86_ops->run(vcpu);
6950 * Do this here before restoring debug registers on the host. And
6951 * since we do this before handling the vmexit, a DR access vmexit
6952 * can (a) read the correct value of the debug registers, (b) set
6953 * KVM_DEBUGREG_WONT_EXIT again.
6955 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6956 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6957 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6958 kvm_update_dr0123(vcpu);
6959 kvm_update_dr6(vcpu);
6960 kvm_update_dr7(vcpu);
6961 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6965 * If the guest has used debug registers, at least dr7
6966 * will be disabled while returning to the host.
6967 * If we don't have active breakpoints in the host, we don't
6968 * care about the messed up debug address registers. But if
6969 * we have some of them active, restore the old state.
6971 if (hw_breakpoint_active())
6972 hw_breakpoint_restore();
6974 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6976 vcpu->mode = OUTSIDE_GUEST_MODE;
6977 smp_wmb();
6979 kvm_put_guest_xcr0(vcpu);
6981 kvm_x86_ops->handle_external_intr(vcpu);
6983 ++vcpu->stat.exits;
6985 guest_exit_irqoff();
6987 local_irq_enable();
6988 preempt_enable();
6990 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6993 * Profile KVM exit RIPs:
6995 if (unlikely(prof_on == KVM_PROFILING)) {
6996 unsigned long rip = kvm_rip_read(vcpu);
6997 profile_hit(KVM_PROFILING, (void *)rip);
7000 if (unlikely(vcpu->arch.tsc_always_catchup))
7001 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7003 if (vcpu->arch.apic_attention)
7004 kvm_lapic_sync_from_vapic(vcpu);
7006 r = kvm_x86_ops->handle_exit(vcpu);
7007 return r;
7009 cancel_injection:
7010 kvm_x86_ops->cancel_injection(vcpu);
7011 if (unlikely(vcpu->arch.apic_attention))
7012 kvm_lapic_sync_from_vapic(vcpu);
7013 out:
7014 return r;
7017 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7019 if (!kvm_arch_vcpu_runnable(vcpu) &&
7020 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7021 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7022 kvm_vcpu_block(vcpu);
7023 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7025 if (kvm_x86_ops->post_block)
7026 kvm_x86_ops->post_block(vcpu);
7028 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7029 return 1;
7032 kvm_apic_accept_events(vcpu);
7033 switch(vcpu->arch.mp_state) {
7034 case KVM_MP_STATE_HALTED:
7035 vcpu->arch.pv.pv_unhalted = false;
7036 vcpu->arch.mp_state =
7037 KVM_MP_STATE_RUNNABLE;
7038 case KVM_MP_STATE_RUNNABLE:
7039 vcpu->arch.apf.halted = false;
7040 break;
7041 case KVM_MP_STATE_INIT_RECEIVED:
7042 break;
7043 default:
7044 return -EINTR;
7045 break;
7047 return 1;
7050 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7052 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7053 kvm_x86_ops->check_nested_events(vcpu, false);
7055 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7056 !vcpu->arch.apf.halted);
7059 static int vcpu_run(struct kvm_vcpu *vcpu)
7061 int r;
7062 struct kvm *kvm = vcpu->kvm;
7064 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7066 for (;;) {
7067 if (kvm_vcpu_running(vcpu)) {
7068 r = vcpu_enter_guest(vcpu);
7069 } else {
7070 r = vcpu_block(kvm, vcpu);
7073 if (r <= 0)
7074 break;
7076 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7077 if (kvm_cpu_has_pending_timer(vcpu))
7078 kvm_inject_pending_timer_irqs(vcpu);
7080 if (dm_request_for_irq_injection(vcpu) &&
7081 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7082 r = 0;
7083 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7084 ++vcpu->stat.request_irq_exits;
7085 break;
7088 kvm_check_async_pf_completion(vcpu);
7090 if (signal_pending(current)) {
7091 r = -EINTR;
7092 vcpu->run->exit_reason = KVM_EXIT_INTR;
7093 ++vcpu->stat.signal_exits;
7094 break;
7096 if (need_resched()) {
7097 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7098 cond_resched();
7099 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7103 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7105 return r;
7108 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7110 int r;
7111 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7112 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7113 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7114 if (r != EMULATE_DONE)
7115 return 0;
7116 return 1;
7119 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7121 BUG_ON(!vcpu->arch.pio.count);
7123 return complete_emulated_io(vcpu);
7127 * Implements the following, as a state machine:
7129 * read:
7130 * for each fragment
7131 * for each mmio piece in the fragment
7132 * write gpa, len
7133 * exit
7134 * copy data
7135 * execute insn
7137 * write:
7138 * for each fragment
7139 * for each mmio piece in the fragment
7140 * write gpa, len
7141 * copy data
7142 * exit
7144 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7146 struct kvm_run *run = vcpu->run;
7147 struct kvm_mmio_fragment *frag;
7148 unsigned len;
7150 BUG_ON(!vcpu->mmio_needed);
7152 /* Complete previous fragment */
7153 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7154 len = min(8u, frag->len);
7155 if (!vcpu->mmio_is_write)
7156 memcpy(frag->data, run->mmio.data, len);
7158 if (frag->len <= 8) {
7159 /* Switch to the next fragment. */
7160 frag++;
7161 vcpu->mmio_cur_fragment++;
7162 } else {
7163 /* Go forward to the next mmio piece. */
7164 frag->data += len;
7165 frag->gpa += len;
7166 frag->len -= len;
7169 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7170 vcpu->mmio_needed = 0;
7172 /* FIXME: return into emulator if single-stepping. */
7173 if (vcpu->mmio_is_write)
7174 return 1;
7175 vcpu->mmio_read_completed = 1;
7176 return complete_emulated_io(vcpu);
7179 run->exit_reason = KVM_EXIT_MMIO;
7180 run->mmio.phys_addr = frag->gpa;
7181 if (vcpu->mmio_is_write)
7182 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7183 run->mmio.len = min(8u, frag->len);
7184 run->mmio.is_write = vcpu->mmio_is_write;
7185 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7186 return 0;
7190 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7192 struct fpu *fpu = &current->thread.fpu;
7193 int r;
7194 sigset_t sigsaved;
7196 fpu__activate_curr(fpu);
7198 if (vcpu->sigset_active)
7199 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7201 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7202 kvm_vcpu_block(vcpu);
7203 kvm_apic_accept_events(vcpu);
7204 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7205 r = -EAGAIN;
7206 goto out;
7209 /* re-sync apic's tpr */
7210 if (!lapic_in_kernel(vcpu)) {
7211 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7212 r = -EINVAL;
7213 goto out;
7217 if (unlikely(vcpu->arch.complete_userspace_io)) {
7218 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7219 vcpu->arch.complete_userspace_io = NULL;
7220 r = cui(vcpu);
7221 if (r <= 0)
7222 goto out;
7223 } else
7224 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7226 if (kvm_run->immediate_exit)
7227 r = -EINTR;
7228 else
7229 r = vcpu_run(vcpu);
7231 out:
7232 post_kvm_run_save(vcpu);
7233 if (vcpu->sigset_active)
7234 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7236 return r;
7239 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7241 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7243 * We are here if userspace calls get_regs() in the middle of
7244 * instruction emulation. Registers state needs to be copied
7245 * back from emulation context to vcpu. Userspace shouldn't do
7246 * that usually, but some bad designed PV devices (vmware
7247 * backdoor interface) need this to work
7249 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7250 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7252 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7253 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7254 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7255 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7256 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7257 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7258 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7259 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7260 #ifdef CONFIG_X86_64
7261 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7262 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7263 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7264 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7265 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7266 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7267 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7268 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7269 #endif
7271 regs->rip = kvm_rip_read(vcpu);
7272 regs->rflags = kvm_get_rflags(vcpu);
7274 return 0;
7277 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7279 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7280 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7282 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7283 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7284 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7285 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7286 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7287 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7288 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7289 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7290 #ifdef CONFIG_X86_64
7291 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7292 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7293 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7294 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7295 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7296 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7297 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7298 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7299 #endif
7301 kvm_rip_write(vcpu, regs->rip);
7302 kvm_set_rflags(vcpu, regs->rflags);
7304 vcpu->arch.exception.pending = false;
7306 kvm_make_request(KVM_REQ_EVENT, vcpu);
7308 return 0;
7311 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7313 struct kvm_segment cs;
7315 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7316 *db = cs.db;
7317 *l = cs.l;
7319 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7321 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7322 struct kvm_sregs *sregs)
7324 struct desc_ptr dt;
7326 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7327 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7328 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7329 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7330 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7331 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7333 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7334 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7336 kvm_x86_ops->get_idt(vcpu, &dt);
7337 sregs->idt.limit = dt.size;
7338 sregs->idt.base = dt.address;
7339 kvm_x86_ops->get_gdt(vcpu, &dt);
7340 sregs->gdt.limit = dt.size;
7341 sregs->gdt.base = dt.address;
7343 sregs->cr0 = kvm_read_cr0(vcpu);
7344 sregs->cr2 = vcpu->arch.cr2;
7345 sregs->cr3 = kvm_read_cr3(vcpu);
7346 sregs->cr4 = kvm_read_cr4(vcpu);
7347 sregs->cr8 = kvm_get_cr8(vcpu);
7348 sregs->efer = vcpu->arch.efer;
7349 sregs->apic_base = kvm_get_apic_base(vcpu);
7351 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7353 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7354 set_bit(vcpu->arch.interrupt.nr,
7355 (unsigned long *)sregs->interrupt_bitmap);
7357 return 0;
7360 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7361 struct kvm_mp_state *mp_state)
7363 kvm_apic_accept_events(vcpu);
7364 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7365 vcpu->arch.pv.pv_unhalted)
7366 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7367 else
7368 mp_state->mp_state = vcpu->arch.mp_state;
7370 return 0;
7373 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7374 struct kvm_mp_state *mp_state)
7376 if (!lapic_in_kernel(vcpu) &&
7377 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7378 return -EINVAL;
7380 /* INITs are latched while in SMM */
7381 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7382 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7383 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7384 return -EINVAL;
7386 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7387 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7388 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7389 } else
7390 vcpu->arch.mp_state = mp_state->mp_state;
7391 kvm_make_request(KVM_REQ_EVENT, vcpu);
7392 return 0;
7395 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7396 int reason, bool has_error_code, u32 error_code)
7398 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7399 int ret;
7401 init_emulate_ctxt(vcpu);
7403 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7404 has_error_code, error_code);
7406 if (ret)
7407 return EMULATE_FAIL;
7409 kvm_rip_write(vcpu, ctxt->eip);
7410 kvm_set_rflags(vcpu, ctxt->eflags);
7411 kvm_make_request(KVM_REQ_EVENT, vcpu);
7412 return EMULATE_DONE;
7414 EXPORT_SYMBOL_GPL(kvm_task_switch);
7416 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7417 struct kvm_sregs *sregs)
7419 struct msr_data apic_base_msr;
7420 int mmu_reset_needed = 0;
7421 int pending_vec, max_bits, idx;
7422 struct desc_ptr dt;
7424 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7425 return -EINVAL;
7427 dt.size = sregs->idt.limit;
7428 dt.address = sregs->idt.base;
7429 kvm_x86_ops->set_idt(vcpu, &dt);
7430 dt.size = sregs->gdt.limit;
7431 dt.address = sregs->gdt.base;
7432 kvm_x86_ops->set_gdt(vcpu, &dt);
7434 vcpu->arch.cr2 = sregs->cr2;
7435 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7436 vcpu->arch.cr3 = sregs->cr3;
7437 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7439 kvm_set_cr8(vcpu, sregs->cr8);
7441 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7442 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7443 apic_base_msr.data = sregs->apic_base;
7444 apic_base_msr.host_initiated = true;
7445 kvm_set_apic_base(vcpu, &apic_base_msr);
7447 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7448 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7449 vcpu->arch.cr0 = sregs->cr0;
7451 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7452 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7453 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7454 kvm_update_cpuid(vcpu);
7456 idx = srcu_read_lock(&vcpu->kvm->srcu);
7457 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7458 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7459 mmu_reset_needed = 1;
7461 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7463 if (mmu_reset_needed)
7464 kvm_mmu_reset_context(vcpu);
7466 max_bits = KVM_NR_INTERRUPTS;
7467 pending_vec = find_first_bit(
7468 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7469 if (pending_vec < max_bits) {
7470 kvm_queue_interrupt(vcpu, pending_vec, false);
7471 pr_debug("Set back pending irq %d\n", pending_vec);
7474 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7475 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7476 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7477 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7478 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7479 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7481 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7482 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7484 update_cr8_intercept(vcpu);
7486 /* Older userspace won't unhalt the vcpu on reset. */
7487 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7488 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7489 !is_protmode(vcpu))
7490 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7492 kvm_make_request(KVM_REQ_EVENT, vcpu);
7494 return 0;
7497 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7498 struct kvm_guest_debug *dbg)
7500 unsigned long rflags;
7501 int i, r;
7503 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7504 r = -EBUSY;
7505 if (vcpu->arch.exception.pending)
7506 goto out;
7507 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7508 kvm_queue_exception(vcpu, DB_VECTOR);
7509 else
7510 kvm_queue_exception(vcpu, BP_VECTOR);
7514 * Read rflags as long as potentially injected trace flags are still
7515 * filtered out.
7517 rflags = kvm_get_rflags(vcpu);
7519 vcpu->guest_debug = dbg->control;
7520 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7521 vcpu->guest_debug = 0;
7523 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7524 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7525 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7526 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7527 } else {
7528 for (i = 0; i < KVM_NR_DB_REGS; i++)
7529 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7531 kvm_update_dr7(vcpu);
7533 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7534 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7535 get_segment_base(vcpu, VCPU_SREG_CS);
7538 * Trigger an rflags update that will inject or remove the trace
7539 * flags.
7541 kvm_set_rflags(vcpu, rflags);
7543 kvm_x86_ops->update_bp_intercept(vcpu);
7545 r = 0;
7547 out:
7549 return r;
7553 * Translate a guest virtual address to a guest physical address.
7555 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7556 struct kvm_translation *tr)
7558 unsigned long vaddr = tr->linear_address;
7559 gpa_t gpa;
7560 int idx;
7562 idx = srcu_read_lock(&vcpu->kvm->srcu);
7563 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7564 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7565 tr->physical_address = gpa;
7566 tr->valid = gpa != UNMAPPED_GVA;
7567 tr->writeable = 1;
7568 tr->usermode = 0;
7570 return 0;
7573 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7575 struct fxregs_state *fxsave =
7576 &vcpu->arch.guest_fpu.state.fxsave;
7578 memcpy(fpu->fpr, fxsave->st_space, 128);
7579 fpu->fcw = fxsave->cwd;
7580 fpu->fsw = fxsave->swd;
7581 fpu->ftwx = fxsave->twd;
7582 fpu->last_opcode = fxsave->fop;
7583 fpu->last_ip = fxsave->rip;
7584 fpu->last_dp = fxsave->rdp;
7585 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7587 return 0;
7590 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7592 struct fxregs_state *fxsave =
7593 &vcpu->arch.guest_fpu.state.fxsave;
7595 memcpy(fxsave->st_space, fpu->fpr, 128);
7596 fxsave->cwd = fpu->fcw;
7597 fxsave->swd = fpu->fsw;
7598 fxsave->twd = fpu->ftwx;
7599 fxsave->fop = fpu->last_opcode;
7600 fxsave->rip = fpu->last_ip;
7601 fxsave->rdp = fpu->last_dp;
7602 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7604 return 0;
7607 static void fx_init(struct kvm_vcpu *vcpu)
7609 fpstate_init(&vcpu->arch.guest_fpu.state);
7610 if (boot_cpu_has(X86_FEATURE_XSAVES))
7611 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7612 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7615 * Ensure guest xcr0 is valid for loading
7617 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7619 vcpu->arch.cr0 |= X86_CR0_ET;
7622 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7624 if (vcpu->guest_fpu_loaded)
7625 return;
7628 * Restore all possible states in the guest,
7629 * and assume host would use all available bits.
7630 * Guest xcr0 would be loaded later.
7632 vcpu->guest_fpu_loaded = 1;
7633 __kernel_fpu_begin();
7634 /* PKRU is separately restored in kvm_x86_ops->run. */
7635 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7636 ~XFEATURE_MASK_PKRU);
7637 trace_kvm_fpu(1);
7640 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7642 if (!vcpu->guest_fpu_loaded)
7643 return;
7645 vcpu->guest_fpu_loaded = 0;
7646 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7647 __kernel_fpu_end();
7648 ++vcpu->stat.fpu_reload;
7649 trace_kvm_fpu(0);
7652 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7654 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7656 kvmclock_reset(vcpu);
7658 kvm_x86_ops->vcpu_free(vcpu);
7659 free_cpumask_var(wbinvd_dirty_mask);
7662 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7663 unsigned int id)
7665 struct kvm_vcpu *vcpu;
7667 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7668 printk_once(KERN_WARNING
7669 "kvm: SMP vm created on host with unstable TSC; "
7670 "guest TSC will not be reliable\n");
7672 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7674 return vcpu;
7677 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7679 int r;
7681 kvm_vcpu_mtrr_init(vcpu);
7682 r = vcpu_load(vcpu);
7683 if (r)
7684 return r;
7685 kvm_vcpu_reset(vcpu, false);
7686 kvm_mmu_setup(vcpu);
7687 vcpu_put(vcpu);
7688 return r;
7691 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7693 struct msr_data msr;
7694 struct kvm *kvm = vcpu->kvm;
7696 kvm_hv_vcpu_postcreate(vcpu);
7698 if (vcpu_load(vcpu))
7699 return;
7700 msr.data = 0x0;
7701 msr.index = MSR_IA32_TSC;
7702 msr.host_initiated = true;
7703 kvm_write_tsc(vcpu, &msr);
7704 vcpu_put(vcpu);
7706 if (!kvmclock_periodic_sync)
7707 return;
7709 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7710 KVMCLOCK_SYNC_PERIOD);
7713 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7715 int r;
7716 vcpu->arch.apf.msr_val = 0;
7718 r = vcpu_load(vcpu);
7719 BUG_ON(r);
7720 kvm_mmu_unload(vcpu);
7721 vcpu_put(vcpu);
7723 kvm_x86_ops->vcpu_free(vcpu);
7726 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7728 vcpu->arch.hflags = 0;
7730 vcpu->arch.smi_pending = 0;
7731 atomic_set(&vcpu->arch.nmi_queued, 0);
7732 vcpu->arch.nmi_pending = 0;
7733 vcpu->arch.nmi_injected = false;
7734 kvm_clear_interrupt_queue(vcpu);
7735 kvm_clear_exception_queue(vcpu);
7737 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7738 kvm_update_dr0123(vcpu);
7739 vcpu->arch.dr6 = DR6_INIT;
7740 kvm_update_dr6(vcpu);
7741 vcpu->arch.dr7 = DR7_FIXED_1;
7742 kvm_update_dr7(vcpu);
7744 vcpu->arch.cr2 = 0;
7746 kvm_make_request(KVM_REQ_EVENT, vcpu);
7747 vcpu->arch.apf.msr_val = 0;
7748 vcpu->arch.st.msr_val = 0;
7750 kvmclock_reset(vcpu);
7752 kvm_clear_async_pf_completion_queue(vcpu);
7753 kvm_async_pf_hash_reset(vcpu);
7754 vcpu->arch.apf.halted = false;
7756 if (!init_event) {
7757 kvm_pmu_reset(vcpu);
7758 vcpu->arch.smbase = 0x30000;
7760 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7761 vcpu->arch.msr_misc_features_enables = 0;
7764 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7765 vcpu->arch.regs_avail = ~0;
7766 vcpu->arch.regs_dirty = ~0;
7768 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7771 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7773 struct kvm_segment cs;
7775 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7776 cs.selector = vector << 8;
7777 cs.base = vector << 12;
7778 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7779 kvm_rip_write(vcpu, 0);
7782 int kvm_arch_hardware_enable(void)
7784 struct kvm *kvm;
7785 struct kvm_vcpu *vcpu;
7786 int i;
7787 int ret;
7788 u64 local_tsc;
7789 u64 max_tsc = 0;
7790 bool stable, backwards_tsc = false;
7792 kvm_shared_msr_cpu_online();
7793 ret = kvm_x86_ops->hardware_enable();
7794 if (ret != 0)
7795 return ret;
7797 local_tsc = rdtsc();
7798 stable = !check_tsc_unstable();
7799 list_for_each_entry(kvm, &vm_list, vm_list) {
7800 kvm_for_each_vcpu(i, vcpu, kvm) {
7801 if (!stable && vcpu->cpu == smp_processor_id())
7802 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7803 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7804 backwards_tsc = true;
7805 if (vcpu->arch.last_host_tsc > max_tsc)
7806 max_tsc = vcpu->arch.last_host_tsc;
7812 * Sometimes, even reliable TSCs go backwards. This happens on
7813 * platforms that reset TSC during suspend or hibernate actions, but
7814 * maintain synchronization. We must compensate. Fortunately, we can
7815 * detect that condition here, which happens early in CPU bringup,
7816 * before any KVM threads can be running. Unfortunately, we can't
7817 * bring the TSCs fully up to date with real time, as we aren't yet far
7818 * enough into CPU bringup that we know how much real time has actually
7819 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7820 * variables that haven't been updated yet.
7822 * So we simply find the maximum observed TSC above, then record the
7823 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7824 * the adjustment will be applied. Note that we accumulate
7825 * adjustments, in case multiple suspend cycles happen before some VCPU
7826 * gets a chance to run again. In the event that no KVM threads get a
7827 * chance to run, we will miss the entire elapsed period, as we'll have
7828 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7829 * loose cycle time. This isn't too big a deal, since the loss will be
7830 * uniform across all VCPUs (not to mention the scenario is extremely
7831 * unlikely). It is possible that a second hibernate recovery happens
7832 * much faster than a first, causing the observed TSC here to be
7833 * smaller; this would require additional padding adjustment, which is
7834 * why we set last_host_tsc to the local tsc observed here.
7836 * N.B. - this code below runs only on platforms with reliable TSC,
7837 * as that is the only way backwards_tsc is set above. Also note
7838 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7839 * have the same delta_cyc adjustment applied if backwards_tsc
7840 * is detected. Note further, this adjustment is only done once,
7841 * as we reset last_host_tsc on all VCPUs to stop this from being
7842 * called multiple times (one for each physical CPU bringup).
7844 * Platforms with unreliable TSCs don't have to deal with this, they
7845 * will be compensated by the logic in vcpu_load, which sets the TSC to
7846 * catchup mode. This will catchup all VCPUs to real time, but cannot
7847 * guarantee that they stay in perfect synchronization.
7849 if (backwards_tsc) {
7850 u64 delta_cyc = max_tsc - local_tsc;
7851 list_for_each_entry(kvm, &vm_list, vm_list) {
7852 kvm->arch.backwards_tsc_observed = true;
7853 kvm_for_each_vcpu(i, vcpu, kvm) {
7854 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7855 vcpu->arch.last_host_tsc = local_tsc;
7856 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7860 * We have to disable TSC offset matching.. if you were
7861 * booting a VM while issuing an S4 host suspend....
7862 * you may have some problem. Solving this issue is
7863 * left as an exercise to the reader.
7865 kvm->arch.last_tsc_nsec = 0;
7866 kvm->arch.last_tsc_write = 0;
7870 return 0;
7873 void kvm_arch_hardware_disable(void)
7875 kvm_x86_ops->hardware_disable();
7876 drop_user_return_notifiers();
7879 int kvm_arch_hardware_setup(void)
7881 int r;
7883 r = kvm_x86_ops->hardware_setup();
7884 if (r != 0)
7885 return r;
7887 if (kvm_has_tsc_control) {
7889 * Make sure the user can only configure tsc_khz values that
7890 * fit into a signed integer.
7891 * A min value is not calculated needed because it will always
7892 * be 1 on all machines.
7894 u64 max = min(0x7fffffffULL,
7895 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7896 kvm_max_guest_tsc_khz = max;
7898 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7901 kvm_init_msr_list();
7902 return 0;
7905 void kvm_arch_hardware_unsetup(void)
7907 kvm_x86_ops->hardware_unsetup();
7910 void kvm_arch_check_processor_compat(void *rtn)
7912 kvm_x86_ops->check_processor_compatibility(rtn);
7915 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7917 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7919 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7921 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7923 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7926 struct static_key kvm_no_apic_vcpu __read_mostly;
7927 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7929 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7931 struct page *page;
7932 struct kvm *kvm;
7933 int r;
7935 BUG_ON(vcpu->kvm == NULL);
7936 kvm = vcpu->kvm;
7938 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7939 vcpu->arch.pv.pv_unhalted = false;
7940 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7941 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7942 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7943 else
7944 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7946 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7947 if (!page) {
7948 r = -ENOMEM;
7949 goto fail;
7951 vcpu->arch.pio_data = page_address(page);
7953 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7955 r = kvm_mmu_create(vcpu);
7956 if (r < 0)
7957 goto fail_free_pio_data;
7959 if (irqchip_in_kernel(kvm)) {
7960 r = kvm_create_lapic(vcpu);
7961 if (r < 0)
7962 goto fail_mmu_destroy;
7963 } else
7964 static_key_slow_inc(&kvm_no_apic_vcpu);
7966 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7967 GFP_KERNEL);
7968 if (!vcpu->arch.mce_banks) {
7969 r = -ENOMEM;
7970 goto fail_free_lapic;
7972 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7974 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7975 r = -ENOMEM;
7976 goto fail_free_mce_banks;
7979 fx_init(vcpu);
7981 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7982 vcpu->arch.pv_time_enabled = false;
7984 vcpu->arch.guest_supported_xcr0 = 0;
7985 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7987 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7989 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7991 kvm_async_pf_hash_reset(vcpu);
7992 kvm_pmu_init(vcpu);
7994 vcpu->arch.pending_external_vector = -1;
7996 kvm_hv_vcpu_init(vcpu);
7998 return 0;
8000 fail_free_mce_banks:
8001 kfree(vcpu->arch.mce_banks);
8002 fail_free_lapic:
8003 kvm_free_lapic(vcpu);
8004 fail_mmu_destroy:
8005 kvm_mmu_destroy(vcpu);
8006 fail_free_pio_data:
8007 free_page((unsigned long)vcpu->arch.pio_data);
8008 fail:
8009 return r;
8012 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8014 int idx;
8016 kvm_hv_vcpu_uninit(vcpu);
8017 kvm_pmu_destroy(vcpu);
8018 kfree(vcpu->arch.mce_banks);
8019 kvm_free_lapic(vcpu);
8020 idx = srcu_read_lock(&vcpu->kvm->srcu);
8021 kvm_mmu_destroy(vcpu);
8022 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8023 free_page((unsigned long)vcpu->arch.pio_data);
8024 if (!lapic_in_kernel(vcpu))
8025 static_key_slow_dec(&kvm_no_apic_vcpu);
8028 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8030 kvm_x86_ops->sched_in(vcpu, cpu);
8033 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8035 if (type)
8036 return -EINVAL;
8038 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8039 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8040 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8041 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8042 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8044 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8045 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8046 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8047 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8048 &kvm->arch.irq_sources_bitmap);
8050 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8051 mutex_init(&kvm->arch.apic_map_lock);
8052 mutex_init(&kvm->arch.hyperv.hv_lock);
8053 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8055 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8056 pvclock_update_vm_gtod_copy(kvm);
8058 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8059 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8061 kvm_page_track_init(kvm);
8062 kvm_mmu_init_vm(kvm);
8064 if (kvm_x86_ops->vm_init)
8065 return kvm_x86_ops->vm_init(kvm);
8067 return 0;
8070 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8072 int r;
8073 r = vcpu_load(vcpu);
8074 BUG_ON(r);
8075 kvm_mmu_unload(vcpu);
8076 vcpu_put(vcpu);
8079 static void kvm_free_vcpus(struct kvm *kvm)
8081 unsigned int i;
8082 struct kvm_vcpu *vcpu;
8085 * Unpin any mmu pages first.
8087 kvm_for_each_vcpu(i, vcpu, kvm) {
8088 kvm_clear_async_pf_completion_queue(vcpu);
8089 kvm_unload_vcpu_mmu(vcpu);
8091 kvm_for_each_vcpu(i, vcpu, kvm)
8092 kvm_arch_vcpu_free(vcpu);
8094 mutex_lock(&kvm->lock);
8095 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8096 kvm->vcpus[i] = NULL;
8098 atomic_set(&kvm->online_vcpus, 0);
8099 mutex_unlock(&kvm->lock);
8102 void kvm_arch_sync_events(struct kvm *kvm)
8104 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8105 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8106 kvm_free_pit(kvm);
8109 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8111 int i, r;
8112 unsigned long hva;
8113 struct kvm_memslots *slots = kvm_memslots(kvm);
8114 struct kvm_memory_slot *slot, old;
8116 /* Called with kvm->slots_lock held. */
8117 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8118 return -EINVAL;
8120 slot = id_to_memslot(slots, id);
8121 if (size) {
8122 if (slot->npages)
8123 return -EEXIST;
8126 * MAP_SHARED to prevent internal slot pages from being moved
8127 * by fork()/COW.
8129 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8130 MAP_SHARED | MAP_ANONYMOUS, 0);
8131 if (IS_ERR((void *)hva))
8132 return PTR_ERR((void *)hva);
8133 } else {
8134 if (!slot->npages)
8135 return 0;
8137 hva = 0;
8140 old = *slot;
8141 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8142 struct kvm_userspace_memory_region m;
8144 m.slot = id | (i << 16);
8145 m.flags = 0;
8146 m.guest_phys_addr = gpa;
8147 m.userspace_addr = hva;
8148 m.memory_size = size;
8149 r = __kvm_set_memory_region(kvm, &m);
8150 if (r < 0)
8151 return r;
8154 if (!size) {
8155 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8156 WARN_ON(r < 0);
8159 return 0;
8161 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8163 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8165 int r;
8167 mutex_lock(&kvm->slots_lock);
8168 r = __x86_set_memory_region(kvm, id, gpa, size);
8169 mutex_unlock(&kvm->slots_lock);
8171 return r;
8173 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8175 void kvm_arch_destroy_vm(struct kvm *kvm)
8177 if (current->mm == kvm->mm) {
8179 * Free memory regions allocated on behalf of userspace,
8180 * unless the the memory map has changed due to process exit
8181 * or fd copying.
8183 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8184 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8185 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8187 if (kvm_x86_ops->vm_destroy)
8188 kvm_x86_ops->vm_destroy(kvm);
8189 kvm_pic_destroy(kvm);
8190 kvm_ioapic_destroy(kvm);
8191 kvm_free_vcpus(kvm);
8192 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8193 kvm_mmu_uninit_vm(kvm);
8194 kvm_page_track_cleanup(kvm);
8197 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8198 struct kvm_memory_slot *dont)
8200 int i;
8202 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8203 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8204 kvfree(free->arch.rmap[i]);
8205 free->arch.rmap[i] = NULL;
8207 if (i == 0)
8208 continue;
8210 if (!dont || free->arch.lpage_info[i - 1] !=
8211 dont->arch.lpage_info[i - 1]) {
8212 kvfree(free->arch.lpage_info[i - 1]);
8213 free->arch.lpage_info[i - 1] = NULL;
8217 kvm_page_track_free_memslot(free, dont);
8220 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8221 unsigned long npages)
8223 int i;
8225 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8226 struct kvm_lpage_info *linfo;
8227 unsigned long ugfn;
8228 int lpages;
8229 int level = i + 1;
8231 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8232 slot->base_gfn, level) + 1;
8234 slot->arch.rmap[i] =
8235 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8236 if (!slot->arch.rmap[i])
8237 goto out_free;
8238 if (i == 0)
8239 continue;
8241 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8242 if (!linfo)
8243 goto out_free;
8245 slot->arch.lpage_info[i - 1] = linfo;
8247 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8248 linfo[0].disallow_lpage = 1;
8249 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8250 linfo[lpages - 1].disallow_lpage = 1;
8251 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8253 * If the gfn and userspace address are not aligned wrt each
8254 * other, or if explicitly asked to, disable large page
8255 * support for this slot
8257 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8258 !kvm_largepages_enabled()) {
8259 unsigned long j;
8261 for (j = 0; j < lpages; ++j)
8262 linfo[j].disallow_lpage = 1;
8266 if (kvm_page_track_create_memslot(slot, npages))
8267 goto out_free;
8269 return 0;
8271 out_free:
8272 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8273 kvfree(slot->arch.rmap[i]);
8274 slot->arch.rmap[i] = NULL;
8275 if (i == 0)
8276 continue;
8278 kvfree(slot->arch.lpage_info[i - 1]);
8279 slot->arch.lpage_info[i - 1] = NULL;
8281 return -ENOMEM;
8284 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8287 * memslots->generation has been incremented.
8288 * mmio generation may have reached its maximum value.
8290 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8293 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8294 struct kvm_memory_slot *memslot,
8295 const struct kvm_userspace_memory_region *mem,
8296 enum kvm_mr_change change)
8298 return 0;
8301 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8302 struct kvm_memory_slot *new)
8304 /* Still write protect RO slot */
8305 if (new->flags & KVM_MEM_READONLY) {
8306 kvm_mmu_slot_remove_write_access(kvm, new);
8307 return;
8311 * Call kvm_x86_ops dirty logging hooks when they are valid.
8313 * kvm_x86_ops->slot_disable_log_dirty is called when:
8315 * - KVM_MR_CREATE with dirty logging is disabled
8316 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8318 * The reason is, in case of PML, we need to set D-bit for any slots
8319 * with dirty logging disabled in order to eliminate unnecessary GPA
8320 * logging in PML buffer (and potential PML buffer full VMEXT). This
8321 * guarantees leaving PML enabled during guest's lifetime won't have
8322 * any additonal overhead from PML when guest is running with dirty
8323 * logging disabled for memory slots.
8325 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8326 * to dirty logging mode.
8328 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8330 * In case of write protect:
8332 * Write protect all pages for dirty logging.
8334 * All the sptes including the large sptes which point to this
8335 * slot are set to readonly. We can not create any new large
8336 * spte on this slot until the end of the logging.
8338 * See the comments in fast_page_fault().
8340 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8341 if (kvm_x86_ops->slot_enable_log_dirty)
8342 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8343 else
8344 kvm_mmu_slot_remove_write_access(kvm, new);
8345 } else {
8346 if (kvm_x86_ops->slot_disable_log_dirty)
8347 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8351 void kvm_arch_commit_memory_region(struct kvm *kvm,
8352 const struct kvm_userspace_memory_region *mem,
8353 const struct kvm_memory_slot *old,
8354 const struct kvm_memory_slot *new,
8355 enum kvm_mr_change change)
8357 int nr_mmu_pages = 0;
8359 if (!kvm->arch.n_requested_mmu_pages)
8360 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8362 if (nr_mmu_pages)
8363 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8366 * Dirty logging tracks sptes in 4k granularity, meaning that large
8367 * sptes have to be split. If live migration is successful, the guest
8368 * in the source machine will be destroyed and large sptes will be
8369 * created in the destination. However, if the guest continues to run
8370 * in the source machine (for example if live migration fails), small
8371 * sptes will remain around and cause bad performance.
8373 * Scan sptes if dirty logging has been stopped, dropping those
8374 * which can be collapsed into a single large-page spte. Later
8375 * page faults will create the large-page sptes.
8377 if ((change != KVM_MR_DELETE) &&
8378 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8379 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8380 kvm_mmu_zap_collapsible_sptes(kvm, new);
8383 * Set up write protection and/or dirty logging for the new slot.
8385 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8386 * been zapped so no dirty logging staff is needed for old slot. For
8387 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8388 * new and it's also covered when dealing with the new slot.
8390 * FIXME: const-ify all uses of struct kvm_memory_slot.
8392 if (change != KVM_MR_DELETE)
8393 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8396 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8398 kvm_mmu_invalidate_zap_all_pages(kvm);
8401 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8402 struct kvm_memory_slot *slot)
8404 kvm_page_track_flush_slot(kvm, slot);
8407 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8409 if (!list_empty_careful(&vcpu->async_pf.done))
8410 return true;
8412 if (kvm_apic_has_events(vcpu))
8413 return true;
8415 if (vcpu->arch.pv.pv_unhalted)
8416 return true;
8418 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8419 (vcpu->arch.nmi_pending &&
8420 kvm_x86_ops->nmi_allowed(vcpu)))
8421 return true;
8423 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8424 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8425 return true;
8427 if (kvm_arch_interrupt_allowed(vcpu) &&
8428 kvm_cpu_has_interrupt(vcpu))
8429 return true;
8431 if (kvm_hv_has_stimer_pending(vcpu))
8432 return true;
8434 return false;
8437 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8439 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8442 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8444 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8447 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8449 return kvm_x86_ops->interrupt_allowed(vcpu);
8452 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8454 if (is_64_bit_mode(vcpu))
8455 return kvm_rip_read(vcpu);
8456 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8457 kvm_rip_read(vcpu));
8459 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8461 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8463 return kvm_get_linear_rip(vcpu) == linear_rip;
8465 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8467 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8469 unsigned long rflags;
8471 rflags = kvm_x86_ops->get_rflags(vcpu);
8472 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8473 rflags &= ~X86_EFLAGS_TF;
8474 return rflags;
8476 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8478 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8480 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8481 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8482 rflags |= X86_EFLAGS_TF;
8483 kvm_x86_ops->set_rflags(vcpu, rflags);
8486 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8488 __kvm_set_rflags(vcpu, rflags);
8489 kvm_make_request(KVM_REQ_EVENT, vcpu);
8491 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8493 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8495 int r;
8497 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8498 work->wakeup_all)
8499 return;
8501 r = kvm_mmu_reload(vcpu);
8502 if (unlikely(r))
8503 return;
8505 if (!vcpu->arch.mmu.direct_map &&
8506 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8507 return;
8509 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8512 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8514 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8517 static inline u32 kvm_async_pf_next_probe(u32 key)
8519 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8522 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8524 u32 key = kvm_async_pf_hash_fn(gfn);
8526 while (vcpu->arch.apf.gfns[key] != ~0)
8527 key = kvm_async_pf_next_probe(key);
8529 vcpu->arch.apf.gfns[key] = gfn;
8532 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8534 int i;
8535 u32 key = kvm_async_pf_hash_fn(gfn);
8537 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8538 (vcpu->arch.apf.gfns[key] != gfn &&
8539 vcpu->arch.apf.gfns[key] != ~0); i++)
8540 key = kvm_async_pf_next_probe(key);
8542 return key;
8545 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8547 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8550 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8552 u32 i, j, k;
8554 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8555 while (true) {
8556 vcpu->arch.apf.gfns[i] = ~0;
8557 do {
8558 j = kvm_async_pf_next_probe(j);
8559 if (vcpu->arch.apf.gfns[j] == ~0)
8560 return;
8561 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8563 * k lies cyclically in ]i,j]
8564 * | i.k.j |
8565 * |....j i.k.| or |.k..j i...|
8567 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8568 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8569 i = j;
8573 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8576 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8577 sizeof(val));
8580 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8581 struct kvm_async_pf *work)
8583 struct x86_exception fault;
8585 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8586 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8588 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8589 (vcpu->arch.apf.send_user_only &&
8590 kvm_x86_ops->get_cpl(vcpu) == 0))
8591 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8592 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8593 fault.vector = PF_VECTOR;
8594 fault.error_code_valid = true;
8595 fault.error_code = 0;
8596 fault.nested_page_fault = false;
8597 fault.address = work->arch.token;
8598 fault.async_page_fault = true;
8599 kvm_inject_page_fault(vcpu, &fault);
8603 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8604 struct kvm_async_pf *work)
8606 struct x86_exception fault;
8608 if (work->wakeup_all)
8609 work->arch.token = ~0; /* broadcast wakeup */
8610 else
8611 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8612 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8614 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8615 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8616 fault.vector = PF_VECTOR;
8617 fault.error_code_valid = true;
8618 fault.error_code = 0;
8619 fault.nested_page_fault = false;
8620 fault.address = work->arch.token;
8621 fault.async_page_fault = true;
8622 kvm_inject_page_fault(vcpu, &fault);
8624 vcpu->arch.apf.halted = false;
8625 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8628 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8630 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8631 return true;
8632 else
8633 return kvm_can_do_async_pf(vcpu);
8636 void kvm_arch_start_assignment(struct kvm *kvm)
8638 atomic_inc(&kvm->arch.assigned_device_count);
8640 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8642 void kvm_arch_end_assignment(struct kvm *kvm)
8644 atomic_dec(&kvm->arch.assigned_device_count);
8646 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8648 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8650 return atomic_read(&kvm->arch.assigned_device_count);
8652 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8654 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8656 atomic_inc(&kvm->arch.noncoherent_dma_count);
8658 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8660 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8662 atomic_dec(&kvm->arch.noncoherent_dma_count);
8664 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8666 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8668 return atomic_read(&kvm->arch.noncoherent_dma_count);
8670 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8672 bool kvm_arch_has_irq_bypass(void)
8674 return kvm_x86_ops->update_pi_irte != NULL;
8677 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8678 struct irq_bypass_producer *prod)
8680 struct kvm_kernel_irqfd *irqfd =
8681 container_of(cons, struct kvm_kernel_irqfd, consumer);
8683 irqfd->producer = prod;
8685 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8686 prod->irq, irqfd->gsi, 1);
8689 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8690 struct irq_bypass_producer *prod)
8692 int ret;
8693 struct kvm_kernel_irqfd *irqfd =
8694 container_of(cons, struct kvm_kernel_irqfd, consumer);
8696 WARN_ON(irqfd->producer != prod);
8697 irqfd->producer = NULL;
8700 * When producer of consumer is unregistered, we change back to
8701 * remapped mode, so we can re-use the current implementation
8702 * when the irq is masked/disabled or the consumer side (KVM
8703 * int this case doesn't want to receive the interrupts.
8705 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8706 if (ret)
8707 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8708 " fails: %d\n", irqfd->consumer.token, ret);
8711 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8712 uint32_t guest_irq, bool set)
8714 if (!kvm_x86_ops->update_pi_irte)
8715 return -EINVAL;
8717 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8720 bool kvm_vector_hashing_enabled(void)
8722 return vector_hashing;
8724 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8726 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8727 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8728 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8729 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8730 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8731 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8732 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8733 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8734 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8735 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8736 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8737 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8738 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8739 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8740 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8741 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8742 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8743 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8744 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);