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IPV6: Fix for RT0 header ipv6 change.
[linux/fpc-iii.git] / drivers / net / qla3xxx.c
bloba8246eb2f8d93ba185e7e2a3a45ac140bb1c2f96
1 /*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/mm.h>
37
38 #include "qla3xxx.h"
39
40 #define DRV_NAME "qla3xxx"
41 #define DRV_STRING "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION "v2.03.00-k3"
43 #define PFX DRV_NAME " "
44
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION);
52
53 static const u32 default_msg
54 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57 static int debug = -1; /* defaults above */
58 module_param(debug, int, 0);
59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61 static int msi;
62 module_param(msi, int, 0);
63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
67 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
68 /* required last entry */
69 {0,}
70 };
71
72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
74 /*
75 * Caller must take hw_lock.
76 */
77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
78 u32 sem_mask, u32 sem_bits)
79 {
80 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
81 u32 value;
82 unsigned int seconds = 3;
83
84 do {
85 writel((sem_mask | sem_bits),
86 &port_regs->CommonRegs.semaphoreReg);
87 value = readl(&port_regs->CommonRegs.semaphoreReg);
88 if ((value & (sem_mask >> 16)) == sem_bits)
89 return 0;
90 ssleep(1);
91 } while(--seconds);
92 return -1;
93 }
94
95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
96 {
97 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
98 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
99 readl(&port_regs->CommonRegs.semaphoreReg);
100 }
101
102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
103 {
104 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105 u32 value;
106
107 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
108 value = readl(&port_regs->CommonRegs.semaphoreReg);
109 return ((value & (sem_mask >> 16)) == sem_bits);
110 }
111
112 /*
113 * Caller holds hw_lock.
114 */
115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
116 {
117 int i = 0;
118
119 while (1) {
120 if (!ql_sem_lock(qdev,
121 QL_DRVR_SEM_MASK,
122 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
123 * 2) << 1)) {
124 if (i < 10) {
125 ssleep(1);
126 i++;
127 } else {
128 printk(KERN_ERR PFX "%s: Timed out waiting for "
129 "driver lock...\n",
130 qdev->ndev->name);
131 return 0;
132 }
133 } else {
134 printk(KERN_DEBUG PFX
135 "%s: driver lock acquired.\n",
136 qdev->ndev->name);
137 return 1;
138 }
139 }
140 }
141
142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
143 {
144 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
145
146 writel(((ISP_CONTROL_NP_MASK << 16) | page),
147 &port_regs->CommonRegs.ispControlStatus);
148 readl(&port_regs->CommonRegs.ispControlStatus);
149 qdev->current_page = page;
150 }
151
152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
153 u32 __iomem * reg)
154 {
155 u32 value;
156 unsigned long hw_flags;
157
158 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
159 value = readl(reg);
160 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
161
162 return value;
163 }
164
165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
166 u32 __iomem * reg)
167 {
168 return readl(reg);
169 }
170
171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
172 {
173 u32 value;
174 unsigned long hw_flags;
175
176 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
177
178 if (qdev->current_page != 0)
179 ql_set_register_page(qdev,0);
180 value = readl(reg);
181
182 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
183 return value;
184 }
185
186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
187 {
188 if (qdev->current_page != 0)
189 ql_set_register_page(qdev,0);
190 return readl(reg);
191 }
192
193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
194 u32 __iomem *reg, u32 value)
195 {
196 unsigned long hw_flags;
197
198 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
199 writel(value, reg);
200 readl(reg);
201 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
202 return;
203 }
204
205 static void ql_write_common_reg(struct ql3_adapter *qdev,
206 u32 __iomem *reg, u32 value)
207 {
208 writel(value, reg);
209 readl(reg);
210 return;
211 }
212
213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
214 u32 __iomem *reg, u32 value)
215 {
216 writel(value, reg);
217 readl(reg);
218 udelay(1);
219 return;
220 }
221
222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
223 u32 __iomem *reg, u32 value)
224 {
225 if (qdev->current_page != 0)
226 ql_set_register_page(qdev,0);
227 writel(value, reg);
228 readl(reg);
229 return;
230 }
231
232 /*
233 * Caller holds hw_lock. Only called during init.
234 */
235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
236 u32 __iomem *reg, u32 value)
237 {
238 if (qdev->current_page != 1)
239 ql_set_register_page(qdev,1);
240 writel(value, reg);
241 readl(reg);
242 return;
243 }
244
245 /*
246 * Caller holds hw_lock. Only called during init.
247 */
248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
249 u32 __iomem *reg, u32 value)
250 {
251 if (qdev->current_page != 2)
252 ql_set_register_page(qdev,2);
253 writel(value, reg);
254 readl(reg);
255 return;
256 }
257
258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
259 {
260 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
261
262 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
263 (ISP_IMR_ENABLE_INT << 16));
264
265 }
266
267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
268 {
269 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
270
271 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
272 ((0xff << 16) | ISP_IMR_ENABLE_INT));
273
274 }
275
276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
277 struct ql_rcv_buf_cb *lrg_buf_cb)
278 {
279 dma_addr_t map;
280 int err;
281 lrg_buf_cb->next = NULL;
282
283 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
284 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
285 } else {
286 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
287 qdev->lrg_buf_free_tail = lrg_buf_cb;
288 }
289
290 if (!lrg_buf_cb->skb) {
291 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
292 qdev->lrg_buffer_len);
293 if (unlikely(!lrg_buf_cb->skb)) {
294 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
295 qdev->ndev->name);
296 qdev->lrg_buf_skb_check++;
297 } else {
298 /*
299 * We save some space to copy the ethhdr from first
300 * buffer
301 */
302 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
303 map = pci_map_single(qdev->pdev,
304 lrg_buf_cb->skb->data,
305 qdev->lrg_buffer_len -
306 QL_HEADER_SPACE,
307 PCI_DMA_FROMDEVICE);
308 err = pci_dma_mapping_error(map);
309 if(err) {
310 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
311 qdev->ndev->name, err);
312 dev_kfree_skb(lrg_buf_cb->skb);
313 lrg_buf_cb->skb = NULL;
314
315 qdev->lrg_buf_skb_check++;
316 return;
317 }
318
319 lrg_buf_cb->buf_phy_addr_low =
320 cpu_to_le32(LS_64BITS(map));
321 lrg_buf_cb->buf_phy_addr_high =
322 cpu_to_le32(MS_64BITS(map));
323 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
324 pci_unmap_len_set(lrg_buf_cb, maplen,
325 qdev->lrg_buffer_len -
326 QL_HEADER_SPACE);
327 }
328 }
329
330 qdev->lrg_buf_free_count++;
331 }
332
333 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
334 *qdev)
335 {
336 struct ql_rcv_buf_cb *lrg_buf_cb;
337
338 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
339 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
340 qdev->lrg_buf_free_tail = NULL;
341 qdev->lrg_buf_free_count--;
342 }
343
344 return lrg_buf_cb;
345 }
346
347 static u32 addrBits = EEPROM_NO_ADDR_BITS;
348 static u32 dataBits = EEPROM_NO_DATA_BITS;
349
350 static void fm93c56a_deselect(struct ql3_adapter *qdev);
351 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
352 unsigned short *value);
353
354 /*
355 * Caller holds hw_lock.
356 */
357 static void fm93c56a_select(struct ql3_adapter *qdev)
358 {
359 struct ql3xxx_port_registers __iomem *port_regs =
360 qdev->mem_map_registers;
361
362 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
363 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
364 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
365 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
366 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
367 }
368
369 /*
370 * Caller holds hw_lock.
371 */
372 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
373 {
374 int i;
375 u32 mask;
376 u32 dataBit;
377 u32 previousBit;
378 struct ql3xxx_port_registers __iomem *port_regs =
379 qdev->mem_map_registers;
380
381 /* Clock in a zero, then do the start bit */
382 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
383 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
384 AUBURN_EEPROM_DO_1);
385 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
386 ISP_NVRAM_MASK | qdev->
387 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
388 AUBURN_EEPROM_CLK_RISE);
389 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
390 ISP_NVRAM_MASK | qdev->
391 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
392 AUBURN_EEPROM_CLK_FALL);
393
394 mask = 1 << (FM93C56A_CMD_BITS - 1);
395 /* Force the previous data bit to be different */
396 previousBit = 0xffff;
397 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
398 dataBit =
399 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
400 if (previousBit != dataBit) {
401 /*
402 * If the bit changed, then change the DO state to
403 * match
404 */
405 ql_write_nvram_reg(qdev,
406 &port_regs->CommonRegs.
407 serialPortInterfaceReg,
408 ISP_NVRAM_MASK | qdev->
409 eeprom_cmd_data | dataBit);
410 previousBit = dataBit;
411 }
412 ql_write_nvram_reg(qdev,
413 &port_regs->CommonRegs.
414 serialPortInterfaceReg,
415 ISP_NVRAM_MASK | qdev->
416 eeprom_cmd_data | dataBit |
417 AUBURN_EEPROM_CLK_RISE);
418 ql_write_nvram_reg(qdev,
419 &port_regs->CommonRegs.
420 serialPortInterfaceReg,
421 ISP_NVRAM_MASK | qdev->
422 eeprom_cmd_data | dataBit |
423 AUBURN_EEPROM_CLK_FALL);
424 cmd = cmd << 1;
425 }
426
427 mask = 1 << (addrBits - 1);
428 /* Force the previous data bit to be different */
429 previousBit = 0xffff;
430 for (i = 0; i < addrBits; i++) {
431 dataBit =
432 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
433 AUBURN_EEPROM_DO_0;
434 if (previousBit != dataBit) {
435 /*
436 * If the bit changed, then change the DO state to
437 * match
438 */
439 ql_write_nvram_reg(qdev,
440 &port_regs->CommonRegs.
441 serialPortInterfaceReg,
442 ISP_NVRAM_MASK | qdev->
443 eeprom_cmd_data | dataBit);
444 previousBit = dataBit;
445 }
446 ql_write_nvram_reg(qdev,
447 &port_regs->CommonRegs.
448 serialPortInterfaceReg,
449 ISP_NVRAM_MASK | qdev->
450 eeprom_cmd_data | dataBit |
451 AUBURN_EEPROM_CLK_RISE);
452 ql_write_nvram_reg(qdev,
453 &port_regs->CommonRegs.
454 serialPortInterfaceReg,
455 ISP_NVRAM_MASK | qdev->
456 eeprom_cmd_data | dataBit |
457 AUBURN_EEPROM_CLK_FALL);
458 eepromAddr = eepromAddr << 1;
459 }
460 }
461
462 /*
463 * Caller holds hw_lock.
464 */
465 static void fm93c56a_deselect(struct ql3_adapter *qdev)
466 {
467 struct ql3xxx_port_registers __iomem *port_regs =
468 qdev->mem_map_registers;
469 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
470 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
471 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
472 }
473
474 /*
475 * Caller holds hw_lock.
476 */
477 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
478 {
479 int i;
480 u32 data = 0;
481 u32 dataBit;
482 struct ql3xxx_port_registers __iomem *port_regs =
483 qdev->mem_map_registers;
484
485 /* Read the data bits */
486 /* The first bit is a dummy. Clock right over it. */
487 for (i = 0; i < dataBits; i++) {
488 ql_write_nvram_reg(qdev,
489 &port_regs->CommonRegs.
490 serialPortInterfaceReg,
491 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
492 AUBURN_EEPROM_CLK_RISE);
493 ql_write_nvram_reg(qdev,
494 &port_regs->CommonRegs.
495 serialPortInterfaceReg,
496 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
497 AUBURN_EEPROM_CLK_FALL);
498 dataBit =
499 (ql_read_common_reg
500 (qdev,
501 &port_regs->CommonRegs.
502 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
503 data = (data << 1) | dataBit;
504 }
505 *value = (u16) data;
506 }
507
508 /*
509 * Caller holds hw_lock.
510 */
511 static void eeprom_readword(struct ql3_adapter *qdev,
512 u32 eepromAddr, unsigned short *value)
513 {
514 fm93c56a_select(qdev);
515 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
516 fm93c56a_datain(qdev, value);
517 fm93c56a_deselect(qdev);
518 }
519
520 static void ql_swap_mac_addr(u8 * macAddress)
521 {
522 #ifdef __BIG_ENDIAN
523 u8 temp;
524 temp = macAddress[0];
525 macAddress[0] = macAddress[1];
526 macAddress[1] = temp;
527 temp = macAddress[2];
528 macAddress[2] = macAddress[3];
529 macAddress[3] = temp;
530 temp = macAddress[4];
531 macAddress[4] = macAddress[5];
532 macAddress[5] = temp;
533 #endif
534 }
535
536 static int ql_get_nvram_params(struct ql3_adapter *qdev)
537 {
538 u16 *pEEPROMData;
539 u16 checksum = 0;
540 u32 index;
541 unsigned long hw_flags;
542
543 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
544
545 pEEPROMData = (u16 *) & qdev->nvram_data;
546 qdev->eeprom_cmd_data = 0;
547 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
548 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
549 2) << 10)) {
550 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
551 __func__);
552 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
553 return -1;
554 }
555
556 for (index = 0; index < EEPROM_SIZE; index++) {
557 eeprom_readword(qdev, index, pEEPROMData);
558 checksum += *pEEPROMData;
559 pEEPROMData++;
560 }
561 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
562
563 if (checksum != 0) {
564 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
565 qdev->ndev->name, checksum);
566 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
567 return -1;
568 }
569
570 /*
571 * We have a problem with endianness for the MAC addresses
572 * and the two 8-bit values version, and numPorts. We
573 * have to swap them on big endian systems.
574 */
575 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
576 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
577 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
578 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
579 pEEPROMData = (u16 *) & qdev->nvram_data.version;
580 *pEEPROMData = le16_to_cpu(*pEEPROMData);
581
582 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
583 return checksum;
584 }
585
586 static const u32 PHYAddr[2] = {
587 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
588 };
589
590 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
591 {
592 struct ql3xxx_port_registers __iomem *port_regs =
593 qdev->mem_map_registers;
594 u32 temp;
595 int count = 1000;
596
597 while (count) {
598 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
599 if (!(temp & MAC_MII_STATUS_BSY))
600 return 0;
601 udelay(10);
602 count--;
603 }
604 return -1;
605 }
606
607 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
608 {
609 struct ql3xxx_port_registers __iomem *port_regs =
610 qdev->mem_map_registers;
611 u32 scanControl;
612
613 if (qdev->numPorts > 1) {
614 /* Auto scan will cycle through multiple ports */
615 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
616 } else {
617 scanControl = MAC_MII_CONTROL_SC;
618 }
619
620 /*
621 * Scan register 1 of PHY/PETBI,
622 * Set up to scan both devices
623 * The autoscan starts from the first register, completes
624 * the last one before rolling over to the first
625 */
626 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
627 PHYAddr[0] | MII_SCAN_REGISTER);
628
629 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
630 (scanControl) |
631 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
632 }
633
634 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
635 {
636 u8 ret;
637 struct ql3xxx_port_registers __iomem *port_regs =
638 qdev->mem_map_registers;
639
640 /* See if scan mode is enabled before we turn it off */
641 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
642 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
643 /* Scan is enabled */
644 ret = 1;
645 } else {
646 /* Scan is disabled */
647 ret = 0;
648 }
649
650 /*
651 * When disabling scan mode you must first change the MII register
652 * address
653 */
654 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
655 PHYAddr[0] | MII_SCAN_REGISTER);
656
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
658 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
659 MAC_MII_CONTROL_RC) << 16));
660
661 return ret;
662 }
663
664 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
665 u16 regAddr, u16 value, u32 mac_index)
666 {
667 struct ql3xxx_port_registers __iomem *port_regs =
668 qdev->mem_map_registers;
669 u8 scanWasEnabled;
670
671 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
672
673 if (ql_wait_for_mii_ready(qdev)) {
674 if (netif_msg_link(qdev))
675 printk(KERN_WARNING PFX
676 "%s Timed out waiting for management port to "
677 "get free before issuing command.\n",
678 qdev->ndev->name);
679 return -1;
680 }
681
682 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683 PHYAddr[mac_index] | regAddr);
684
685 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
686
687 /* Wait for write to complete 9/10/04 SJP */
688 if (ql_wait_for_mii_ready(qdev)) {
689 if (netif_msg_link(qdev))
690 printk(KERN_WARNING PFX
691 "%s: Timed out waiting for management port to"
692 "get free before issuing command.\n",
693 qdev->ndev->name);
694 return -1;
695 }
696
697 if (scanWasEnabled)
698 ql_mii_enable_scan_mode(qdev);
699
700 return 0;
701 }
702
703 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
704 u16 * value, u32 mac_index)
705 {
706 struct ql3xxx_port_registers __iomem *port_regs =
707 qdev->mem_map_registers;
708 u8 scanWasEnabled;
709 u32 temp;
710
711 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
712
713 if (ql_wait_for_mii_ready(qdev)) {
714 if (netif_msg_link(qdev))
715 printk(KERN_WARNING PFX
716 "%s: Timed out waiting for management port to "
717 "get free before issuing command.\n",
718 qdev->ndev->name);
719 return -1;
720 }
721
722 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
723 PHYAddr[mac_index] | regAddr);
724
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
726 (MAC_MII_CONTROL_RC << 16));
727
728 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
729 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
730
731 /* Wait for the read to complete */
732 if (ql_wait_for_mii_ready(qdev)) {
733 if (netif_msg_link(qdev))
734 printk(KERN_WARNING PFX
735 "%s: Timed out waiting for management port to "
736 "get free after issuing command.\n",
737 qdev->ndev->name);
738 return -1;
739 }
740
741 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
742 *value = (u16) temp;
743
744 if (scanWasEnabled)
745 ql_mii_enable_scan_mode(qdev);
746
747 return 0;
748 }
749
750 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
751 {
752 struct ql3xxx_port_registers __iomem *port_regs =
753 qdev->mem_map_registers;
754
755 ql_mii_disable_scan_mode(qdev);
756
757 if (ql_wait_for_mii_ready(qdev)) {
758 if (netif_msg_link(qdev))
759 printk(KERN_WARNING PFX
760 "%s: Timed out waiting for management port to "
761 "get free before issuing command.\n",
762 qdev->ndev->name);
763 return -1;
764 }
765
766 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
767 qdev->PHYAddr | regAddr);
768
769 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
770
771 /* Wait for write to complete. */
772 if (ql_wait_for_mii_ready(qdev)) {
773 if (netif_msg_link(qdev))
774 printk(KERN_WARNING PFX
775 "%s: Timed out waiting for management port to "
776 "get free before issuing command.\n",
777 qdev->ndev->name);
778 return -1;
779 }
780
781 ql_mii_enable_scan_mode(qdev);
782
783 return 0;
784 }
785
786 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
787 {
788 u32 temp;
789 struct ql3xxx_port_registers __iomem *port_regs =
790 qdev->mem_map_registers;
791
792 ql_mii_disable_scan_mode(qdev);
793
794 if (ql_wait_for_mii_ready(qdev)) {
795 if (netif_msg_link(qdev))
796 printk(KERN_WARNING PFX
797 "%s: Timed out waiting for management port to "
798 "get free before issuing command.\n",
799 qdev->ndev->name);
800 return -1;
801 }
802
803 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
804 qdev->PHYAddr | regAddr);
805
806 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
807 (MAC_MII_CONTROL_RC << 16));
808
809 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
810 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
811
812 /* Wait for the read to complete */
813 if (ql_wait_for_mii_ready(qdev)) {
814 if (netif_msg_link(qdev))
815 printk(KERN_WARNING PFX
816 "%s: Timed out waiting for management port to "
817 "get free before issuing command.\n",
818 qdev->ndev->name);
819 return -1;
820 }
821
822 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
823 *value = (u16) temp;
824
825 ql_mii_enable_scan_mode(qdev);
826
827 return 0;
828 }
829
830 static void ql_petbi_reset(struct ql3_adapter *qdev)
831 {
832 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
833 }
834
835 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
836 {
837 u16 reg;
838
839 /* Enable Auto-negotiation sense */
840 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
841 reg |= PETBI_TBI_AUTO_SENSE;
842 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
843
844 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
845 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
846
847 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
848 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
849 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
850
851 }
852
853 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
854 {
855 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
856 mac_index);
857 }
858
859 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
860 {
861 u16 reg;
862
863 /* Enable Auto-negotiation sense */
864 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
865 reg |= PETBI_TBI_AUTO_SENSE;
866 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
867
868 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
869 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
870
871 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
872 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
873 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
874 mac_index);
875 }
876
877 static void ql_petbi_init(struct ql3_adapter *qdev)
878 {
879 ql_petbi_reset(qdev);
880 ql_petbi_start_neg(qdev);
881 }
882
883 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
884 {
885 ql_petbi_reset_ex(qdev, mac_index);
886 ql_petbi_start_neg_ex(qdev, mac_index);
887 }
888
889 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
890 {
891 u16 reg;
892
893 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
894 return 0;
895
896 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
897 }
898
899 static int ql_phy_get_speed(struct ql3_adapter *qdev)
900 {
901 u16 reg;
902
903 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
904 return 0;
905
906 reg = (((reg & 0x18) >> 3) & 3);
907
908 if (reg == 2)
909 return SPEED_1000;
910 else if (reg == 1)
911 return SPEED_100;
912 else if (reg == 0)
913 return SPEED_10;
914 else
915 return -1;
916 }
917
918 static int ql_is_full_dup(struct ql3_adapter *qdev)
919 {
920 u16 reg;
921
922 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
923 return 0;
924
925 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
926 }
927
928 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
929 {
930 u16 reg;
931
932 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
933 return 0;
934
935 return (reg & PHY_NEG_PAUSE) != 0;
936 }
937
938 /*
939 * Caller holds hw_lock.
940 */
941 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
942 {
943 struct ql3xxx_port_registers __iomem *port_regs =
944 qdev->mem_map_registers;
945 u32 value;
946
947 if (enable)
948 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
949 else
950 value = (MAC_CONFIG_REG_PE << 16);
951
952 if (qdev->mac_index)
953 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
954 else
955 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
956 }
957
958 /*
959 * Caller holds hw_lock.
960 */
961 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
962 {
963 struct ql3xxx_port_registers __iomem *port_regs =
964 qdev->mem_map_registers;
965 u32 value;
966
967 if (enable)
968 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
969 else
970 value = (MAC_CONFIG_REG_SR << 16);
971
972 if (qdev->mac_index)
973 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
974 else
975 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
976 }
977
978 /*
979 * Caller holds hw_lock.
980 */
981 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
982 {
983 struct ql3xxx_port_registers __iomem *port_regs =
984 qdev->mem_map_registers;
985 u32 value;
986
987 if (enable)
988 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
989 else
990 value = (MAC_CONFIG_REG_GM << 16);
991
992 if (qdev->mac_index)
993 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
994 else
995 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
996 }
997
998 /*
999 * Caller holds hw_lock.
1000 */
1001 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1002 {
1003 struct ql3xxx_port_registers __iomem *port_regs =
1004 qdev->mem_map_registers;
1005 u32 value;
1006
1007 if (enable)
1008 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1009 else
1010 value = (MAC_CONFIG_REG_FD << 16);
1011
1012 if (qdev->mac_index)
1013 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1014 else
1015 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1016 }
1017
1018 /*
1019 * Caller holds hw_lock.
1020 */
1021 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1022 {
1023 struct ql3xxx_port_registers __iomem *port_regs =
1024 qdev->mem_map_registers;
1025 u32 value;
1026
1027 if (enable)
1028 value =
1029 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1030 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1031 else
1032 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1033
1034 if (qdev->mac_index)
1035 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1036 else
1037 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1038 }
1039
1040 /*
1041 * Caller holds hw_lock.
1042 */
1043 static int ql_is_fiber(struct ql3_adapter *qdev)
1044 {
1045 struct ql3xxx_port_registers __iomem *port_regs =
1046 qdev->mem_map_registers;
1047 u32 bitToCheck = 0;
1048 u32 temp;
1049
1050 switch (qdev->mac_index) {
1051 case 0:
1052 bitToCheck = PORT_STATUS_SM0;
1053 break;
1054 case 1:
1055 bitToCheck = PORT_STATUS_SM1;
1056 break;
1057 }
1058
1059 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1060 return (temp & bitToCheck) != 0;
1061 }
1062
1063 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1064 {
1065 u16 reg;
1066 ql_mii_read_reg(qdev, 0x00, &reg);
1067 return (reg & 0x1000) != 0;
1068 }
1069
1070 /*
1071 * Caller holds hw_lock.
1072 */
1073 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1074 {
1075 struct ql3xxx_port_registers __iomem *port_regs =
1076 qdev->mem_map_registers;
1077 u32 bitToCheck = 0;
1078 u32 temp;
1079
1080 switch (qdev->mac_index) {
1081 case 0:
1082 bitToCheck = PORT_STATUS_AC0;
1083 break;
1084 case 1:
1085 bitToCheck = PORT_STATUS_AC1;
1086 break;
1087 }
1088
1089 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1090 if (temp & bitToCheck) {
1091 if (netif_msg_link(qdev))
1092 printk(KERN_INFO PFX
1093 "%s: Auto-Negotiate complete.\n",
1094 qdev->ndev->name);
1095 return 1;
1096 } else {
1097 if (netif_msg_link(qdev))
1098 printk(KERN_WARNING PFX
1099 "%s: Auto-Negotiate incomplete.\n",
1100 qdev->ndev->name);
1101 return 0;
1102 }
1103 }
1104
1105 /*
1106 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1107 */
1108 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1109 {
1110 if (ql_is_fiber(qdev))
1111 return ql_is_petbi_neg_pause(qdev);
1112 else
1113 return ql_is_phy_neg_pause(qdev);
1114 }
1115
1116 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1117 {
1118 struct ql3xxx_port_registers __iomem *port_regs =
1119 qdev->mem_map_registers;
1120 u32 bitToCheck = 0;
1121 u32 temp;
1122
1123 switch (qdev->mac_index) {
1124 case 0:
1125 bitToCheck = PORT_STATUS_AE0;
1126 break;
1127 case 1:
1128 bitToCheck = PORT_STATUS_AE1;
1129 break;
1130 }
1131 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1132 return (temp & bitToCheck) != 0;
1133 }
1134
1135 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1136 {
1137 if (ql_is_fiber(qdev))
1138 return SPEED_1000;
1139 else
1140 return ql_phy_get_speed(qdev);
1141 }
1142
1143 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1144 {
1145 if (ql_is_fiber(qdev))
1146 return 1;
1147 else
1148 return ql_is_full_dup(qdev);
1149 }
1150
1151 /*
1152 * Caller holds hw_lock.
1153 */
1154 static int ql_link_down_detect(struct ql3_adapter *qdev)
1155 {
1156 struct ql3xxx_port_registers __iomem *port_regs =
1157 qdev->mem_map_registers;
1158 u32 bitToCheck = 0;
1159 u32 temp;
1160
1161 switch (qdev->mac_index) {
1162 case 0:
1163 bitToCheck = ISP_CONTROL_LINK_DN_0;
1164 break;
1165 case 1:
1166 bitToCheck = ISP_CONTROL_LINK_DN_1;
1167 break;
1168 }
1169
1170 temp =
1171 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1172 return (temp & bitToCheck) != 0;
1173 }
1174
1175 /*
1176 * Caller holds hw_lock.
1177 */
1178 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1179 {
1180 struct ql3xxx_port_registers __iomem *port_regs =
1181 qdev->mem_map_registers;
1182
1183 switch (qdev->mac_index) {
1184 case 0:
1185 ql_write_common_reg(qdev,
1186 &port_regs->CommonRegs.ispControlStatus,
1187 (ISP_CONTROL_LINK_DN_0) |
1188 (ISP_CONTROL_LINK_DN_0 << 16));
1189 break;
1190
1191 case 1:
1192 ql_write_common_reg(qdev,
1193 &port_regs->CommonRegs.ispControlStatus,
1194 (ISP_CONTROL_LINK_DN_1) |
1195 (ISP_CONTROL_LINK_DN_1 << 16));
1196 break;
1197
1198 default:
1199 return 1;
1200 }
1201
1202 return 0;
1203 }
1204
1205 /*
1206 * Caller holds hw_lock.
1207 */
1208 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1209 u32 mac_index)
1210 {
1211 struct ql3xxx_port_registers __iomem *port_regs =
1212 qdev->mem_map_registers;
1213 u32 bitToCheck = 0;
1214 u32 temp;
1215
1216 switch (mac_index) {
1217 case 0:
1218 bitToCheck = PORT_STATUS_F1_ENABLED;
1219 break;
1220 case 1:
1221 bitToCheck = PORT_STATUS_F3_ENABLED;
1222 break;
1223 default:
1224 break;
1225 }
1226
1227 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228 if (temp & bitToCheck) {
1229 if (netif_msg_link(qdev))
1230 printk(KERN_DEBUG PFX
1231 "%s: is not link master.\n", qdev->ndev->name);
1232 return 0;
1233 } else {
1234 if (netif_msg_link(qdev))
1235 printk(KERN_DEBUG PFX
1236 "%s: is link master.\n", qdev->ndev->name);
1237 return 1;
1238 }
1239 }
1240
1241 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1242 {
1243 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1244 }
1245
1246 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248 u16 reg;
1249
1250 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1251 PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1252
1253 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1254 ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1255 mac_index);
1256 }
1257
1258 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1259 {
1260 ql_phy_reset_ex(qdev, mac_index);
1261 ql_phy_start_neg_ex(qdev, mac_index);
1262 }
1263
1264 /*
1265 * Caller holds hw_lock.
1266 */
1267 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1268 {
1269 struct ql3xxx_port_registers __iomem *port_regs =
1270 qdev->mem_map_registers;
1271 u32 bitToCheck = 0;
1272 u32 temp, linkState;
1273
1274 switch (qdev->mac_index) {
1275 case 0:
1276 bitToCheck = PORT_STATUS_UP0;
1277 break;
1278 case 1:
1279 bitToCheck = PORT_STATUS_UP1;
1280 break;
1281 }
1282 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1283 if (temp & bitToCheck) {
1284 linkState = LS_UP;
1285 } else {
1286 linkState = LS_DOWN;
1287 if (netif_msg_link(qdev))
1288 printk(KERN_WARNING PFX
1289 "%s: Link is down.\n", qdev->ndev->name);
1290 }
1291 return linkState;
1292 }
1293
1294 static int ql_port_start(struct ql3_adapter *qdev)
1295 {
1296 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1297 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1298 2) << 7))
1299 return -1;
1300
1301 if (ql_is_fiber(qdev)) {
1302 ql_petbi_init(qdev);
1303 } else {
1304 /* Copper port */
1305 ql_phy_init_ex(qdev, qdev->mac_index);
1306 }
1307
1308 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1309 return 0;
1310 }
1311
1312 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1313 {
1314
1315 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1316 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1317 2) << 7))
1318 return -1;
1319
1320 if (!ql_auto_neg_error(qdev)) {
1321 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1322 /* configure the MAC */
1323 if (netif_msg_link(qdev))
1324 printk(KERN_DEBUG PFX
1325 "%s: Configuring link.\n",
1326 qdev->ndev->
1327 name);
1328 ql_mac_cfg_soft_reset(qdev, 1);
1329 ql_mac_cfg_gig(qdev,
1330 (ql_get_link_speed
1331 (qdev) ==
1332 SPEED_1000));
1333 ql_mac_cfg_full_dup(qdev,
1334 ql_is_link_full_dup
1335 (qdev));
1336 ql_mac_cfg_pause(qdev,
1337 ql_is_neg_pause
1338 (qdev));
1339 ql_mac_cfg_soft_reset(qdev, 0);
1340
1341 /* enable the MAC */
1342 if (netif_msg_link(qdev))
1343 printk(KERN_DEBUG PFX
1344 "%s: Enabling mac.\n",
1345 qdev->ndev->
1346 name);
1347 ql_mac_enable(qdev, 1);
1348 }
1349
1350 if (netif_msg_link(qdev))
1351 printk(KERN_DEBUG PFX
1352 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1353 qdev->ndev->name);
1354 qdev->port_link_state = LS_UP;
1355 netif_start_queue(qdev->ndev);
1356 netif_carrier_on(qdev->ndev);
1357 if (netif_msg_link(qdev))
1358 printk(KERN_INFO PFX
1359 "%s: Link is up at %d Mbps, %s duplex.\n",
1360 qdev->ndev->name,
1361 ql_get_link_speed(qdev),
1362 ql_is_link_full_dup(qdev)
1363 ? "full" : "half");
1364
1365 } else { /* Remote error detected */
1366
1367 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1368 if (netif_msg_link(qdev))
1369 printk(KERN_DEBUG PFX
1370 "%s: Remote error detected. "
1371 "Calling ql_port_start().\n",
1372 qdev->ndev->
1373 name);
1374 /*
1375 * ql_port_start() is shared code and needs
1376 * to lock the PHY on it's own.
1377 */
1378 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1379 if(ql_port_start(qdev)) {/* Restart port */
1380 return -1;
1381 } else
1382 return 0;
1383 }
1384 }
1385 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1386 return 0;
1387 }
1388
1389 static void ql_link_state_machine(struct ql3_adapter *qdev)
1390 {
1391 u32 curr_link_state;
1392 unsigned long hw_flags;
1393
1394 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1395
1396 curr_link_state = ql_get_link_state(qdev);
1397
1398 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1399 if (netif_msg_link(qdev))
1400 printk(KERN_INFO PFX
1401 "%s: Reset in progress, skip processing link "
1402 "state.\n", qdev->ndev->name);
1403
1404 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1405 return;
1406 }
1407
1408 switch (qdev->port_link_state) {
1409 default:
1410 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1411 ql_port_start(qdev);
1412 }
1413 qdev->port_link_state = LS_DOWN;
1414 /* Fall Through */
1415
1416 case LS_DOWN:
1417 if (netif_msg_link(qdev))
1418 printk(KERN_DEBUG PFX
1419 "%s: port_link_state = LS_DOWN.\n",
1420 qdev->ndev->name);
1421 if (curr_link_state == LS_UP) {
1422 if (netif_msg_link(qdev))
1423 printk(KERN_DEBUG PFX
1424 "%s: curr_link_state = LS_UP.\n",
1425 qdev->ndev->name);
1426 if (ql_is_auto_neg_complete(qdev))
1427 ql_finish_auto_neg(qdev);
1428
1429 if (qdev->port_link_state == LS_UP)
1430 ql_link_down_detect_clear(qdev);
1431
1432 }
1433 break;
1434
1435 case LS_UP:
1436 /*
1437 * See if the link is currently down or went down and came
1438 * back up
1439 */
1440 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1441 if (netif_msg_link(qdev))
1442 printk(KERN_INFO PFX "%s: Link is down.\n",
1443 qdev->ndev->name);
1444 qdev->port_link_state = LS_DOWN;
1445 }
1446 break;
1447 }
1448 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1449 }
1450
1451 /*
1452 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1453 */
1454 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1455 {
1456 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1457 set_bit(QL_LINK_MASTER,&qdev->flags);
1458 else
1459 clear_bit(QL_LINK_MASTER,&qdev->flags);
1460 }
1461
1462 /*
1463 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1464 */
1465 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1466 {
1467 ql_mii_enable_scan_mode(qdev);
1468
1469 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1470 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1471 ql_petbi_init_ex(qdev, qdev->mac_index);
1472 } else {
1473 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1474 ql_phy_init_ex(qdev, qdev->mac_index);
1475 }
1476 }
1477
1478 /*
1479 * MII_Setup needs to be called before taking the PHY out of reset so that the
1480 * management interface clock speed can be set properly. It would be better if
1481 * we had a way to disable MDC until after the PHY is out of reset, but we
1482 * don't have that capability.
1483 */
1484 static int ql_mii_setup(struct ql3_adapter *qdev)
1485 {
1486 u32 reg;
1487 struct ql3xxx_port_registers __iomem *port_regs =
1488 qdev->mem_map_registers;
1489
1490 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1491 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1492 2) << 7))
1493 return -1;
1494
1495 if (qdev->device_id == QL3032_DEVICE_ID)
1496 ql_write_page0_reg(qdev,
1497 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1498
1499 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1500 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1501
1502 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1503 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1504
1505 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1506 return 0;
1507 }
1508
1509 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1510 {
1511 u32 supported;
1512
1513 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1514 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1515 | SUPPORTED_Autoneg;
1516 } else {
1517 supported = SUPPORTED_10baseT_Half
1518 | SUPPORTED_10baseT_Full
1519 | SUPPORTED_100baseT_Half
1520 | SUPPORTED_100baseT_Full
1521 | SUPPORTED_1000baseT_Half
1522 | SUPPORTED_1000baseT_Full
1523 | SUPPORTED_Autoneg | SUPPORTED_TP;
1524 }
1525
1526 return supported;
1527 }
1528
1529 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1530 {
1531 int status;
1532 unsigned long hw_flags;
1533 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1534 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1535 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1536 2) << 7)) {
1537 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1538 return 0;
1539 }
1540 status = ql_is_auto_cfg(qdev);
1541 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1542 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543 return status;
1544 }
1545
1546 static u32 ql_get_speed(struct ql3_adapter *qdev)
1547 {
1548 u32 status;
1549 unsigned long hw_flags;
1550 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1551 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1552 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1553 2) << 7)) {
1554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1555 return 0;
1556 }
1557 status = ql_get_link_speed(qdev);
1558 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1559 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560 return status;
1561 }
1562
1563 static int ql_get_full_dup(struct ql3_adapter *qdev)
1564 {
1565 int status;
1566 unsigned long hw_flags;
1567 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1568 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1569 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1570 2) << 7)) {
1571 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1572 return 0;
1573 }
1574 status = ql_is_link_full_dup(qdev);
1575 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1576 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1577 return status;
1578 }
1579
1580
1581 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1582 {
1583 struct ql3_adapter *qdev = netdev_priv(ndev);
1584
1585 ecmd->transceiver = XCVR_INTERNAL;
1586 ecmd->supported = ql_supported_modes(qdev);
1587
1588 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1589 ecmd->port = PORT_FIBRE;
1590 } else {
1591 ecmd->port = PORT_TP;
1592 ecmd->phy_address = qdev->PHYAddr;
1593 }
1594 ecmd->advertising = ql_supported_modes(qdev);
1595 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1596 ecmd->speed = ql_get_speed(qdev);
1597 ecmd->duplex = ql_get_full_dup(qdev);
1598 return 0;
1599 }
1600
1601 static void ql_get_drvinfo(struct net_device *ndev,
1602 struct ethtool_drvinfo *drvinfo)
1603 {
1604 struct ql3_adapter *qdev = netdev_priv(ndev);
1605 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1606 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1607 strncpy(drvinfo->fw_version, "N/A", 32);
1608 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1609 drvinfo->n_stats = 0;
1610 drvinfo->testinfo_len = 0;
1611 drvinfo->regdump_len = 0;
1612 drvinfo->eedump_len = 0;
1613 }
1614
1615 static u32 ql_get_msglevel(struct net_device *ndev)
1616 {
1617 struct ql3_adapter *qdev = netdev_priv(ndev);
1618 return qdev->msg_enable;
1619 }
1620
1621 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1622 {
1623 struct ql3_adapter *qdev = netdev_priv(ndev);
1624 qdev->msg_enable = value;
1625 }
1626
1627 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1628 .get_settings = ql_get_settings,
1629 .get_drvinfo = ql_get_drvinfo,
1630 .get_perm_addr = ethtool_op_get_perm_addr,
1631 .get_link = ethtool_op_get_link,
1632 .get_msglevel = ql_get_msglevel,
1633 .set_msglevel = ql_set_msglevel,
1634 };
1635
1636 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1637 {
1638 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1639 dma_addr_t map;
1640 int err;
1641
1642 while (lrg_buf_cb) {
1643 if (!lrg_buf_cb->skb) {
1644 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1645 qdev->lrg_buffer_len);
1646 if (unlikely(!lrg_buf_cb->skb)) {
1647 printk(KERN_DEBUG PFX
1648 "%s: Failed netdev_alloc_skb().\n",
1649 qdev->ndev->name);
1650 break;
1651 } else {
1652 /*
1653 * We save some space to copy the ethhdr from
1654 * first buffer
1655 */
1656 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1657 map = pci_map_single(qdev->pdev,
1658 lrg_buf_cb->skb->data,
1659 qdev->lrg_buffer_len -
1660 QL_HEADER_SPACE,
1661 PCI_DMA_FROMDEVICE);
1662
1663 err = pci_dma_mapping_error(map);
1664 if(err) {
1665 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1666 qdev->ndev->name, err);
1667 dev_kfree_skb(lrg_buf_cb->skb);
1668 lrg_buf_cb->skb = NULL;
1669 break;
1670 }
1671
1672
1673 lrg_buf_cb->buf_phy_addr_low =
1674 cpu_to_le32(LS_64BITS(map));
1675 lrg_buf_cb->buf_phy_addr_high =
1676 cpu_to_le32(MS_64BITS(map));
1677 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1678 pci_unmap_len_set(lrg_buf_cb, maplen,
1679 qdev->lrg_buffer_len -
1680 QL_HEADER_SPACE);
1681 --qdev->lrg_buf_skb_check;
1682 if (!qdev->lrg_buf_skb_check)
1683 return 1;
1684 }
1685 }
1686 lrg_buf_cb = lrg_buf_cb->next;
1687 }
1688 return 0;
1689 }
1690
1691 /*
1692 * Caller holds hw_lock.
1693 */
1694 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1695 {
1696 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1697 if (qdev->small_buf_release_cnt >= 16) {
1698 while (qdev->small_buf_release_cnt >= 16) {
1699 qdev->small_buf_q_producer_index++;
1700
1701 if (qdev->small_buf_q_producer_index ==
1702 NUM_SBUFQ_ENTRIES)
1703 qdev->small_buf_q_producer_index = 0;
1704 qdev->small_buf_release_cnt -= 8;
1705 }
1706 wmb();
1707 writel(qdev->small_buf_q_producer_index,
1708 &port_regs->CommonRegs.rxSmallQProducerIndex);
1709 }
1710 }
1711
1712 /*
1713 * Caller holds hw_lock.
1714 */
1715 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1716 {
1717 struct bufq_addr_element *lrg_buf_q_ele;
1718 int i;
1719 struct ql_rcv_buf_cb *lrg_buf_cb;
1720 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1721
1722 if ((qdev->lrg_buf_free_count >= 8)
1723 && (qdev->lrg_buf_release_cnt >= 16)) {
1724
1725 if (qdev->lrg_buf_skb_check)
1726 if (!ql_populate_free_queue(qdev))
1727 return;
1728
1729 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1730
1731 while ((qdev->lrg_buf_release_cnt >= 16)
1732 && (qdev->lrg_buf_free_count >= 8)) {
1733
1734 for (i = 0; i < 8; i++) {
1735 lrg_buf_cb =
1736 ql_get_from_lrg_buf_free_list(qdev);
1737 lrg_buf_q_ele->addr_high =
1738 lrg_buf_cb->buf_phy_addr_high;
1739 lrg_buf_q_ele->addr_low =
1740 lrg_buf_cb->buf_phy_addr_low;
1741 lrg_buf_q_ele++;
1742
1743 qdev->lrg_buf_release_cnt--;
1744 }
1745
1746 qdev->lrg_buf_q_producer_index++;
1747
1748 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1749 qdev->lrg_buf_q_producer_index = 0;
1750
1751 if (qdev->lrg_buf_q_producer_index ==
1752 (qdev->num_lbufq_entries - 1)) {
1753 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1754 }
1755 }
1756 wmb();
1757 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1758 writel(qdev->lrg_buf_q_producer_index,
1759 &port_regs->CommonRegs.rxLargeQProducerIndex);
1760 }
1761 }
1762
1763 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1764 struct ob_mac_iocb_rsp *mac_rsp)
1765 {
1766 struct ql_tx_buf_cb *tx_cb;
1767 int i;
1768 int retval = 0;
1769
1770 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1771 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
1772 }
1773
1774 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1775
1776 /* Check the transmit response flags for any errors */
1777 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1778 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
1779
1780 qdev->stats.tx_errors++;
1781 retval = -EIO;
1782 goto frame_not_sent;
1783 }
1784
1785 if(tx_cb->seg_count == 0) {
1786 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
1787
1788 qdev->stats.tx_errors++;
1789 retval = -EIO;
1790 goto invalid_seg_count;
1791 }
1792
1793 pci_unmap_single(qdev->pdev,
1794 pci_unmap_addr(&tx_cb->map[0], mapaddr),
1795 pci_unmap_len(&tx_cb->map[0], maplen),
1796 PCI_DMA_TODEVICE);
1797 tx_cb->seg_count--;
1798 if (tx_cb->seg_count) {
1799 for (i = 1; i < tx_cb->seg_count; i++) {
1800 pci_unmap_page(qdev->pdev,
1801 pci_unmap_addr(&tx_cb->map[i],
1802 mapaddr),
1803 pci_unmap_len(&tx_cb->map[i], maplen),
1804 PCI_DMA_TODEVICE);
1805 }
1806 }
1807 qdev->stats.tx_packets++;
1808 qdev->stats.tx_bytes += tx_cb->skb->len;
1809
1810 frame_not_sent:
1811 dev_kfree_skb_irq(tx_cb->skb);
1812 tx_cb->skb = NULL;
1813
1814 invalid_seg_count:
1815 atomic_inc(&qdev->tx_count);
1816 }
1817
1818 void ql_get_sbuf(struct ql3_adapter *qdev)
1819 {
1820 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1821 qdev->small_buf_index = 0;
1822 qdev->small_buf_release_cnt++;
1823 }
1824
1825 struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1826 {
1827 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1828 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1829 qdev->lrg_buf_release_cnt++;
1830 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1831 qdev->lrg_buf_index = 0;
1832 return(lrg_buf_cb);
1833 }
1834
1835 /*
1836 * The difference between 3022 and 3032 for inbound completions:
1837 * 3022 uses two buffers per completion. The first buffer contains
1838 * (some) header info, the second the remainder of the headers plus
1839 * the data. For this chip we reserve some space at the top of the
1840 * receive buffer so that the header info in buffer one can be
1841 * prepended to the buffer two. Buffer two is the sent up while
1842 * buffer one is returned to the hardware to be reused.
1843 * 3032 receives all of it's data and headers in one buffer for a
1844 * simpler process. 3032 also supports checksum verification as
1845 * can be seen in ql_process_macip_rx_intr().
1846 */
1847 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1848 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1849 {
1850 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1851 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1852 struct sk_buff *skb;
1853 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1854
1855 /*
1856 * Get the inbound address list (small buffer).
1857 */
1858 ql_get_sbuf(qdev);
1859
1860 if (qdev->device_id == QL3022_DEVICE_ID)
1861 lrg_buf_cb1 = ql_get_lbuf(qdev);
1862
1863 /* start of second buffer */
1864 lrg_buf_cb2 = ql_get_lbuf(qdev);
1865 skb = lrg_buf_cb2->skb;
1866
1867 qdev->stats.rx_packets++;
1868 qdev->stats.rx_bytes += length;
1869
1870 skb_put(skb, length);
1871 pci_unmap_single(qdev->pdev,
1872 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1873 pci_unmap_len(lrg_buf_cb2, maplen),
1874 PCI_DMA_FROMDEVICE);
1875 prefetch(skb->data);
1876 skb->dev = qdev->ndev;
1877 skb->ip_summed = CHECKSUM_NONE;
1878 skb->protocol = eth_type_trans(skb, qdev->ndev);
1879
1880 netif_receive_skb(skb);
1881 qdev->ndev->last_rx = jiffies;
1882 lrg_buf_cb2->skb = NULL;
1883
1884 if (qdev->device_id == QL3022_DEVICE_ID)
1885 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1886 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1887 }
1888
1889 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1890 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1891 {
1892 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1893 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1894 struct sk_buff *skb1 = NULL, *skb2;
1895 struct net_device *ndev = qdev->ndev;
1896 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1897 u16 size = 0;
1898
1899 /*
1900 * Get the inbound address list (small buffer).
1901 */
1902
1903 ql_get_sbuf(qdev);
1904
1905 if (qdev->device_id == QL3022_DEVICE_ID) {
1906 /* start of first buffer on 3022 */
1907 lrg_buf_cb1 = ql_get_lbuf(qdev);
1908 skb1 = lrg_buf_cb1->skb;
1909 size = ETH_HLEN;
1910 if (*((u16 *) skb1->data) != 0xFFFF)
1911 size += VLAN_ETH_HLEN - ETH_HLEN;
1912 }
1913
1914 /* start of second buffer */
1915 lrg_buf_cb2 = ql_get_lbuf(qdev);
1916 skb2 = lrg_buf_cb2->skb;
1917
1918 skb_put(skb2, length); /* Just the second buffer length here. */
1919 pci_unmap_single(qdev->pdev,
1920 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1921 pci_unmap_len(lrg_buf_cb2, maplen),
1922 PCI_DMA_FROMDEVICE);
1923 prefetch(skb2->data);
1924
1925 skb2->ip_summed = CHECKSUM_NONE;
1926 if (qdev->device_id == QL3022_DEVICE_ID) {
1927 /*
1928 * Copy the ethhdr from first buffer to second. This
1929 * is necessary for 3022 IP completions.
1930 */
1931 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1932 } else {
1933 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1934 if (checksum &
1935 (IB_IP_IOCB_RSP_3032_ICE |
1936 IB_IP_IOCB_RSP_3032_CE)) {
1937 printk(KERN_ERR
1938 "%s: Bad checksum for this %s packet, checksum = %x.\n",
1939 __func__,
1940 ((checksum &
1941 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1942 "UDP"),checksum);
1943 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
1944 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
1945 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
1946 skb2->ip_summed = CHECKSUM_UNNECESSARY;
1947 }
1948 }
1949 skb2->dev = qdev->ndev;
1950 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1951
1952 netif_receive_skb(skb2);
1953 qdev->stats.rx_packets++;
1954 qdev->stats.rx_bytes += length;
1955 ndev->last_rx = jiffies;
1956 lrg_buf_cb2->skb = NULL;
1957
1958 if (qdev->device_id == QL3022_DEVICE_ID)
1959 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1960 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1961 }
1962
1963 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1964 int *tx_cleaned, int *rx_cleaned, int work_to_do)
1965 {
1966 struct net_rsp_iocb *net_rsp;
1967 struct net_device *ndev = qdev->ndev;
1968 int work_done = 0;
1969
1970 /* While there are entries in the completion queue. */
1971 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
1972 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
1973
1974 net_rsp = qdev->rsp_current;
1975 switch (net_rsp->opcode) {
1976
1977 case OPCODE_OB_MAC_IOCB_FN0:
1978 case OPCODE_OB_MAC_IOCB_FN2:
1979 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1980 net_rsp);
1981 (*tx_cleaned)++;
1982 break;
1983
1984 case OPCODE_IB_MAC_IOCB:
1985 case OPCODE_IB_3032_MAC_IOCB:
1986 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1987 net_rsp);
1988 (*rx_cleaned)++;
1989 break;
1990
1991 case OPCODE_IB_IP_IOCB:
1992 case OPCODE_IB_3032_IP_IOCB:
1993 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1994 net_rsp);
1995 (*rx_cleaned)++;
1996 break;
1997 default:
1998 {
1999 u32 *tmp = (u32 *) net_rsp;
2000 printk(KERN_ERR PFX
2001 "%s: Hit default case, not "
2002 "handled!\n"
2003 " dropping the packet, opcode = "
2004 "%x.\n",
2005 ndev->name, net_rsp->opcode);
2006 printk(KERN_ERR PFX
2007 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2008 (unsigned long int)tmp[0],
2009 (unsigned long int)tmp[1],
2010 (unsigned long int)tmp[2],
2011 (unsigned long int)tmp[3]);
2012 }
2013 }
2014
2015 qdev->rsp_consumer_index++;
2016
2017 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2018 qdev->rsp_consumer_index = 0;
2019 qdev->rsp_current = qdev->rsp_q_virt_addr;
2020 } else {
2021 qdev->rsp_current++;
2022 }
2023
2024 work_done = *tx_cleaned + *rx_cleaned;
2025 }
2026
2027 return work_done;
2028 }
2029
2030 static int ql_poll(struct net_device *ndev, int *budget)
2031 {
2032 struct ql3_adapter *qdev = netdev_priv(ndev);
2033 int work_to_do = min(*budget, ndev->quota);
2034 int rx_cleaned = 0, tx_cleaned = 0;
2035 unsigned long hw_flags;
2036 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2037
2038 if (!netif_carrier_ok(ndev))
2039 goto quit_polling;
2040
2041 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2042 *budget -= rx_cleaned;
2043 ndev->quota -= rx_cleaned;
2044
2045 if( tx_cleaned + rx_cleaned != work_to_do ||
2046 !netif_running(ndev)) {
2047 quit_polling:
2048 netif_rx_complete(ndev);
2049
2050 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2051 ql_update_small_bufq_prod_index(qdev);
2052 ql_update_lrg_bufq_prod_index(qdev);
2053 writel(qdev->rsp_consumer_index,
2054 &port_regs->CommonRegs.rspQConsumerIndex);
2055 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2056
2057 ql_enable_interrupts(qdev);
2058 return 0;
2059 }
2060 return 1;
2061 }
2062
2063 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2064 {
2065
2066 struct net_device *ndev = dev_id;
2067 struct ql3_adapter *qdev = netdev_priv(ndev);
2068 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2069 u32 value;
2070 int handled = 1;
2071 u32 var;
2072
2073 port_regs = qdev->mem_map_registers;
2074
2075 value =
2076 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2077
2078 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2079 spin_lock(&qdev->adapter_lock);
2080 netif_stop_queue(qdev->ndev);
2081 netif_carrier_off(qdev->ndev);
2082 ql_disable_interrupts(qdev);
2083 qdev->port_link_state = LS_DOWN;
2084 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2085
2086 if (value & ISP_CONTROL_FE) {
2087 /*
2088 * Chip Fatal Error.
2089 */
2090 var =
2091 ql_read_page0_reg_l(qdev,
2092 &port_regs->PortFatalErrStatus);
2093 printk(KERN_WARNING PFX
2094 "%s: Resetting chip. PortFatalErrStatus "
2095 "register = 0x%x\n", ndev->name, var);
2096 set_bit(QL_RESET_START,&qdev->flags) ;
2097 } else {
2098 /*
2099 * Soft Reset Requested.
2100 */
2101 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2102 printk(KERN_ERR PFX
2103 "%s: Another function issued a reset to the "
2104 "chip. ISR value = %x.\n", ndev->name, value);
2105 }
2106 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2107 spin_unlock(&qdev->adapter_lock);
2108 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2109 ql_disable_interrupts(qdev);
2110 if (likely(netif_rx_schedule_prep(ndev))) {
2111 __netif_rx_schedule(ndev);
2112 }
2113 } else {
2114 return IRQ_NONE;
2115 }
2116
2117 return IRQ_RETVAL(handled);
2118 }
2119
2120 /*
2121 * Get the total number of segments needed for the
2122 * given number of fragments. This is necessary because
2123 * outbound address lists (OAL) will be used when more than
2124 * two frags are given. Each address list has 5 addr/len
2125 * pairs. The 5th pair in each AOL is used to point to
2126 * the next AOL if more frags are coming.
2127 * That is why the frags:segment count ratio is not linear.
2128 */
2129 static int ql_get_seg_count(struct ql3_adapter *qdev,
2130 unsigned short frags)
2131 {
2132 if (qdev->device_id == QL3022_DEVICE_ID)
2133 return 1;
2134
2135 switch(frags) {
2136 case 0: return 1; /* just the skb->data seg */
2137 case 1: return 2; /* skb->data + 1 frag */
2138 case 2: return 3; /* skb->data + 2 frags */
2139 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2140 case 4: return 6;
2141 case 5: return 7;
2142 case 6: return 8;
2143 case 7: return 10;
2144 case 8: return 11;
2145 case 9: return 12;
2146 case 10: return 13;
2147 case 11: return 15;
2148 case 12: return 16;
2149 case 13: return 17;
2150 case 14: return 18;
2151 case 15: return 20;
2152 case 16: return 21;
2153 case 17: return 22;
2154 case 18: return 23;
2155 }
2156 return -1;
2157 }
2158
2159 static void ql_hw_csum_setup(struct sk_buff *skb,
2160 struct ob_mac_iocb_req *mac_iocb_ptr)
2161 {
2162 struct ethhdr *eth;
2163 struct iphdr *ip = NULL;
2164 u8 offset = ETH_HLEN;
2165
2166 eth = (struct ethhdr *)(skb->data);
2167
2168 if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2169 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2170 } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2171 ((struct vlan_ethhdr *)skb->data)->
2172 h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2173 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2174 offset = VLAN_ETH_HLEN;
2175 }
2176
2177 if (ip) {
2178 if (ip->protocol == IPPROTO_TCP) {
2179 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2180 OB_3032MAC_IOCB_REQ_IC;
2181 mac_iocb_ptr->ip_hdr_off = offset;
2182 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2183 } else if (ip->protocol == IPPROTO_UDP) {
2184 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2185 OB_3032MAC_IOCB_REQ_IC;
2186 mac_iocb_ptr->ip_hdr_off = offset;
2187 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2188 }
2189 }
2190 }
2191
2192 /*
2193 * Map the buffers for this transmit. This will return
2194 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2195 */
2196 static int ql_send_map(struct ql3_adapter *qdev,
2197 struct ob_mac_iocb_req *mac_iocb_ptr,
2198 struct ql_tx_buf_cb *tx_cb,
2199 struct sk_buff *skb)
2200 {
2201 struct oal *oal;
2202 struct oal_entry *oal_entry;
2203 int len = skb_headlen(skb);
2204 dma_addr_t map;
2205 int err;
2206 int completed_segs, i;
2207 int seg_cnt, seg = 0;
2208 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2209
2210 seg_cnt = tx_cb->seg_count;
2211 /*
2212 * Map the skb buffer first.
2213 */
2214 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2215
2216 err = pci_dma_mapping_error(map);
2217 if(err) {
2218 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2219 qdev->ndev->name, err);
2220
2221 return NETDEV_TX_BUSY;
2222 }
2223
2224 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2225 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2226 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2227 oal_entry->len = cpu_to_le32(len);
2228 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2229 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2230 seg++;
2231
2232 if (seg_cnt == 1) {
2233 /* Terminate the last segment. */
2234 oal_entry->len =
2235 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2236 } else {
2237 oal = tx_cb->oal;
2238 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2239 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2240 oal_entry++;
2241 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2242 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2243 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2244 (seg == 17 && seg_cnt > 18)) {
2245 /* Continuation entry points to outbound address list. */
2246 map = pci_map_single(qdev->pdev, oal,
2247 sizeof(struct oal),
2248 PCI_DMA_TODEVICE);
2249
2250 err = pci_dma_mapping_error(map);
2251 if(err) {
2252
2253 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2254 qdev->ndev->name, err);
2255 goto map_error;
2256 }
2257
2258 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2259 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2260 oal_entry->len =
2261 cpu_to_le32(sizeof(struct oal) |
2262 OAL_CONT_ENTRY);
2263 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2264 map);
2265 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2266 sizeof(struct oal));
2267 oal_entry = (struct oal_entry *)oal;
2268 oal++;
2269 seg++;
2270 }
2271
2272 map =
2273 pci_map_page(qdev->pdev, frag->page,
2274 frag->page_offset, frag->size,
2275 PCI_DMA_TODEVICE);
2276
2277 err = pci_dma_mapping_error(map);
2278 if(err) {
2279 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2280 qdev->ndev->name, err);
2281 goto map_error;
2282 }
2283
2284 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2285 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2286 oal_entry->len = cpu_to_le32(frag->size);
2287 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2288 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2289 frag->size);
2290 }
2291 /* Terminate the last segment. */
2292 oal_entry->len =
2293 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2294 }
2295
2296 return NETDEV_TX_OK;
2297
2298 map_error:
2299 /* A PCI mapping failed and now we will need to back out
2300 * We need to traverse through the oal's and associated pages which
2301 * have been mapped and now we must unmap them to clean up properly
2302 */
2303
2304 seg = 1;
2305 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2306 oal = tx_cb->oal;
2307 for (i=0; i<completed_segs; i++,seg++) {
2308 oal_entry++;
2309
2310 if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2311 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2312 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2313 (seg == 17 && seg_cnt > 18)) {
2314 pci_unmap_single(qdev->pdev,
2315 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2316 pci_unmap_len(&tx_cb->map[seg], maplen),
2317 PCI_DMA_TODEVICE);
2318 oal++;
2319 seg++;
2320 }
2321
2322 pci_unmap_page(qdev->pdev,
2323 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2324 pci_unmap_len(&tx_cb->map[seg], maplen),
2325 PCI_DMA_TODEVICE);
2326 }
2327
2328 pci_unmap_single(qdev->pdev,
2329 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2330 pci_unmap_addr(&tx_cb->map[0], maplen),
2331 PCI_DMA_TODEVICE);
2332
2333 return NETDEV_TX_BUSY;
2334
2335 }
2336
2337 /*
2338 * The difference between 3022 and 3032 sends:
2339 * 3022 only supports a simple single segment transmission.
2340 * 3032 supports checksumming and scatter/gather lists (fragments).
2341 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2342 * in the IOCB plus a chain of outbound address lists (OAL) that
2343 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2344 * will used to point to an OAL when more ALP entries are required.
2345 * The IOCB is always the top of the chain followed by one or more
2346 * OALs (when necessary).
2347 */
2348 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2349 {
2350 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2351 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2352 struct ql_tx_buf_cb *tx_cb;
2353 u32 tot_len = skb->len;
2354 struct ob_mac_iocb_req *mac_iocb_ptr;
2355
2356 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2357 return NETDEV_TX_BUSY;
2358 }
2359
2360 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2361 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2362 (skb_shinfo(skb)->nr_frags))) == -1) {
2363 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2364 return NETDEV_TX_OK;
2365 }
2366
2367 mac_iocb_ptr = tx_cb->queue_entry;
2368 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2369 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2370 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2371 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2372 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2373 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2374 tx_cb->skb = skb;
2375 if (qdev->device_id == QL3032_DEVICE_ID &&
2376 skb->ip_summed == CHECKSUM_PARTIAL)
2377 ql_hw_csum_setup(skb, mac_iocb_ptr);
2378
2379 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2380 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2381 return NETDEV_TX_BUSY;
2382 }
2383
2384 wmb();
2385 qdev->req_producer_index++;
2386 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2387 qdev->req_producer_index = 0;
2388 wmb();
2389 ql_write_common_reg_l(qdev,
2390 &port_regs->CommonRegs.reqQProducerIndex,
2391 qdev->req_producer_index);
2392
2393 ndev->trans_start = jiffies;
2394 if (netif_msg_tx_queued(qdev))
2395 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2396 ndev->name, qdev->req_producer_index, skb->len);
2397
2398 atomic_dec(&qdev->tx_count);
2399 return NETDEV_TX_OK;
2400 }
2401
2402 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2403 {
2404 qdev->req_q_size =
2405 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2406
2407 qdev->req_q_virt_addr =
2408 pci_alloc_consistent(qdev->pdev,
2409 (size_t) qdev->req_q_size,
2410 &qdev->req_q_phy_addr);
2411
2412 if ((qdev->req_q_virt_addr == NULL) ||
2413 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2414 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2415 qdev->ndev->name);
2416 return -ENOMEM;
2417 }
2418
2419 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2420
2421 qdev->rsp_q_virt_addr =
2422 pci_alloc_consistent(qdev->pdev,
2423 (size_t) qdev->rsp_q_size,
2424 &qdev->rsp_q_phy_addr);
2425
2426 if ((qdev->rsp_q_virt_addr == NULL) ||
2427 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2428 printk(KERN_ERR PFX
2429 "%s: rspQ allocation failed\n",
2430 qdev->ndev->name);
2431 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2432 qdev->req_q_virt_addr,
2433 qdev->req_q_phy_addr);
2434 return -ENOMEM;
2435 }
2436
2437 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2438
2439 return 0;
2440 }
2441
2442 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2443 {
2444 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2445 printk(KERN_INFO PFX
2446 "%s: Already done.\n", qdev->ndev->name);
2447 return;
2448 }
2449
2450 pci_free_consistent(qdev->pdev,
2451 qdev->req_q_size,
2452 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2453
2454 qdev->req_q_virt_addr = NULL;
2455
2456 pci_free_consistent(qdev->pdev,
2457 qdev->rsp_q_size,
2458 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2459
2460 qdev->rsp_q_virt_addr = NULL;
2461
2462 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2463 }
2464
2465 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2466 {
2467 /* Create Large Buffer Queue */
2468 qdev->lrg_buf_q_size =
2469 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2470 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2471 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2472 else
2473 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2474
2475 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2476 if (qdev->lrg_buf == NULL) {
2477 printk(KERN_ERR PFX
2478 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2479 return -ENOMEM;
2480 }
2481
2482 qdev->lrg_buf_q_alloc_virt_addr =
2483 pci_alloc_consistent(qdev->pdev,
2484 qdev->lrg_buf_q_alloc_size,
2485 &qdev->lrg_buf_q_alloc_phy_addr);
2486
2487 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2488 printk(KERN_ERR PFX
2489 "%s: lBufQ failed\n", qdev->ndev->name);
2490 return -ENOMEM;
2491 }
2492 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2493 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2494
2495 /* Create Small Buffer Queue */
2496 qdev->small_buf_q_size =
2497 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2498 if (qdev->small_buf_q_size < PAGE_SIZE)
2499 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2500 else
2501 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2502
2503 qdev->small_buf_q_alloc_virt_addr =
2504 pci_alloc_consistent(qdev->pdev,
2505 qdev->small_buf_q_alloc_size,
2506 &qdev->small_buf_q_alloc_phy_addr);
2507
2508 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2509 printk(KERN_ERR PFX
2510 "%s: Small Buffer Queue allocation failed.\n",
2511 qdev->ndev->name);
2512 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2513 qdev->lrg_buf_q_alloc_virt_addr,
2514 qdev->lrg_buf_q_alloc_phy_addr);
2515 return -ENOMEM;
2516 }
2517
2518 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2519 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2520 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2521 return 0;
2522 }
2523
2524 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2525 {
2526 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2527 printk(KERN_INFO PFX
2528 "%s: Already done.\n", qdev->ndev->name);
2529 return;
2530 }
2531 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2532 pci_free_consistent(qdev->pdev,
2533 qdev->lrg_buf_q_alloc_size,
2534 qdev->lrg_buf_q_alloc_virt_addr,
2535 qdev->lrg_buf_q_alloc_phy_addr);
2536
2537 qdev->lrg_buf_q_virt_addr = NULL;
2538
2539 pci_free_consistent(qdev->pdev,
2540 qdev->small_buf_q_alloc_size,
2541 qdev->small_buf_q_alloc_virt_addr,
2542 qdev->small_buf_q_alloc_phy_addr);
2543
2544 qdev->small_buf_q_virt_addr = NULL;
2545
2546 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2547 }
2548
2549 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2550 {
2551 int i;
2552 struct bufq_addr_element *small_buf_q_entry;
2553
2554 /* Currently we allocate on one of memory and use it for smallbuffers */
2555 qdev->small_buf_total_size =
2556 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2557 QL_SMALL_BUFFER_SIZE);
2558
2559 qdev->small_buf_virt_addr =
2560 pci_alloc_consistent(qdev->pdev,
2561 qdev->small_buf_total_size,
2562 &qdev->small_buf_phy_addr);
2563
2564 if (qdev->small_buf_virt_addr == NULL) {
2565 printk(KERN_ERR PFX
2566 "%s: Failed to get small buffer memory.\n",
2567 qdev->ndev->name);
2568 return -ENOMEM;
2569 }
2570
2571 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2572 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2573
2574 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2575
2576 /* Initialize the small buffer queue. */
2577 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2578 small_buf_q_entry->addr_high =
2579 cpu_to_le32(qdev->small_buf_phy_addr_high);
2580 small_buf_q_entry->addr_low =
2581 cpu_to_le32(qdev->small_buf_phy_addr_low +
2582 (i * QL_SMALL_BUFFER_SIZE));
2583 small_buf_q_entry++;
2584 }
2585 qdev->small_buf_index = 0;
2586 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2587 return 0;
2588 }
2589
2590 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2591 {
2592 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2593 printk(KERN_INFO PFX
2594 "%s: Already done.\n", qdev->ndev->name);
2595 return;
2596 }
2597 if (qdev->small_buf_virt_addr != NULL) {
2598 pci_free_consistent(qdev->pdev,
2599 qdev->small_buf_total_size,
2600 qdev->small_buf_virt_addr,
2601 qdev->small_buf_phy_addr);
2602
2603 qdev->small_buf_virt_addr = NULL;
2604 }
2605 }
2606
2607 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2608 {
2609 int i = 0;
2610 struct ql_rcv_buf_cb *lrg_buf_cb;
2611
2612 for (i = 0; i < qdev->num_large_buffers; i++) {
2613 lrg_buf_cb = &qdev->lrg_buf[i];
2614 if (lrg_buf_cb->skb) {
2615 dev_kfree_skb(lrg_buf_cb->skb);
2616 pci_unmap_single(qdev->pdev,
2617 pci_unmap_addr(lrg_buf_cb, mapaddr),
2618 pci_unmap_len(lrg_buf_cb, maplen),
2619 PCI_DMA_FROMDEVICE);
2620 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2621 } else {
2622 break;
2623 }
2624 }
2625 }
2626
2627 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2628 {
2629 int i;
2630 struct ql_rcv_buf_cb *lrg_buf_cb;
2631 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2632
2633 for (i = 0; i < qdev->num_large_buffers; i++) {
2634 lrg_buf_cb = &qdev->lrg_buf[i];
2635 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2636 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2637 buf_addr_ele++;
2638 }
2639 qdev->lrg_buf_index = 0;
2640 qdev->lrg_buf_skb_check = 0;
2641 }
2642
2643 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2644 {
2645 int i;
2646 struct ql_rcv_buf_cb *lrg_buf_cb;
2647 struct sk_buff *skb;
2648 dma_addr_t map;
2649 int err;
2650
2651 for (i = 0; i < qdev->num_large_buffers; i++) {
2652 skb = netdev_alloc_skb(qdev->ndev,
2653 qdev->lrg_buffer_len);
2654 if (unlikely(!skb)) {
2655 /* Better luck next round */
2656 printk(KERN_ERR PFX
2657 "%s: large buff alloc failed, "
2658 "for %d bytes at index %d.\n",
2659 qdev->ndev->name,
2660 qdev->lrg_buffer_len * 2, i);
2661 ql_free_large_buffers(qdev);
2662 return -ENOMEM;
2663 } else {
2664
2665 lrg_buf_cb = &qdev->lrg_buf[i];
2666 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2667 lrg_buf_cb->index = i;
2668 lrg_buf_cb->skb = skb;
2669 /*
2670 * We save some space to copy the ethhdr from first
2671 * buffer
2672 */
2673 skb_reserve(skb, QL_HEADER_SPACE);
2674 map = pci_map_single(qdev->pdev,
2675 skb->data,
2676 qdev->lrg_buffer_len -
2677 QL_HEADER_SPACE,
2678 PCI_DMA_FROMDEVICE);
2679
2680 err = pci_dma_mapping_error(map);
2681 if(err) {
2682 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2683 qdev->ndev->name, err);
2684 ql_free_large_buffers(qdev);
2685 return -ENOMEM;
2686 }
2687
2688 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2689 pci_unmap_len_set(lrg_buf_cb, maplen,
2690 qdev->lrg_buffer_len -
2691 QL_HEADER_SPACE);
2692 lrg_buf_cb->buf_phy_addr_low =
2693 cpu_to_le32(LS_64BITS(map));
2694 lrg_buf_cb->buf_phy_addr_high =
2695 cpu_to_le32(MS_64BITS(map));
2696 }
2697 }
2698 return 0;
2699 }
2700
2701 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2702 {
2703 struct ql_tx_buf_cb *tx_cb;
2704 int i;
2705
2706 tx_cb = &qdev->tx_buf[0];
2707 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2708 if (tx_cb->oal) {
2709 kfree(tx_cb->oal);
2710 tx_cb->oal = NULL;
2711 }
2712 tx_cb++;
2713 }
2714 }
2715
2716 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2717 {
2718 struct ql_tx_buf_cb *tx_cb;
2719 int i;
2720 struct ob_mac_iocb_req *req_q_curr =
2721 qdev->req_q_virt_addr;
2722
2723 /* Create free list of transmit buffers */
2724 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2725
2726 tx_cb = &qdev->tx_buf[i];
2727 tx_cb->skb = NULL;
2728 tx_cb->queue_entry = req_q_curr;
2729 req_q_curr++;
2730 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2731 if (tx_cb->oal == NULL)
2732 return -1;
2733 }
2734 return 0;
2735 }
2736
2737 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2738 {
2739 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2740 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2741 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2742 }
2743 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2744 /*
2745 * Bigger buffers, so less of them.
2746 */
2747 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2748 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2749 } else {
2750 printk(KERN_ERR PFX
2751 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2752 qdev->ndev->name);
2753 return -ENOMEM;
2754 }
2755 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2756 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2757 qdev->max_frame_size =
2758 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2759
2760 /*
2761 * First allocate a page of shared memory and use it for shadow
2762 * locations of Network Request Queue Consumer Address Register and
2763 * Network Completion Queue Producer Index Register
2764 */
2765 qdev->shadow_reg_virt_addr =
2766 pci_alloc_consistent(qdev->pdev,
2767 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2768
2769 if (qdev->shadow_reg_virt_addr != NULL) {
2770 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2771 qdev->req_consumer_index_phy_addr_high =
2772 MS_64BITS(qdev->shadow_reg_phy_addr);
2773 qdev->req_consumer_index_phy_addr_low =
2774 LS_64BITS(qdev->shadow_reg_phy_addr);
2775
2776 qdev->prsp_producer_index =
2777 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2778 qdev->rsp_producer_index_phy_addr_high =
2779 qdev->req_consumer_index_phy_addr_high;
2780 qdev->rsp_producer_index_phy_addr_low =
2781 qdev->req_consumer_index_phy_addr_low + 8;
2782 } else {
2783 printk(KERN_ERR PFX
2784 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2785 return -ENOMEM;
2786 }
2787
2788 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2789 printk(KERN_ERR PFX
2790 "%s: ql_alloc_net_req_rsp_queues failed.\n",
2791 qdev->ndev->name);
2792 goto err_req_rsp;
2793 }
2794
2795 if (ql_alloc_buffer_queues(qdev) != 0) {
2796 printk(KERN_ERR PFX
2797 "%s: ql_alloc_buffer_queues failed.\n",
2798 qdev->ndev->name);
2799 goto err_buffer_queues;
2800 }
2801
2802 if (ql_alloc_small_buffers(qdev) != 0) {
2803 printk(KERN_ERR PFX
2804 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2805 goto err_small_buffers;
2806 }
2807
2808 if (ql_alloc_large_buffers(qdev) != 0) {
2809 printk(KERN_ERR PFX
2810 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2811 goto err_small_buffers;
2812 }
2813
2814 /* Initialize the large buffer queue. */
2815 ql_init_large_buffers(qdev);
2816 if (ql_create_send_free_list(qdev))
2817 goto err_free_list;
2818
2819 qdev->rsp_current = qdev->rsp_q_virt_addr;
2820
2821 return 0;
2822 err_free_list:
2823 ql_free_send_free_list(qdev);
2824 err_small_buffers:
2825 ql_free_buffer_queues(qdev);
2826 err_buffer_queues:
2827 ql_free_net_req_rsp_queues(qdev);
2828 err_req_rsp:
2829 pci_free_consistent(qdev->pdev,
2830 PAGE_SIZE,
2831 qdev->shadow_reg_virt_addr,
2832 qdev->shadow_reg_phy_addr);
2833
2834 return -ENOMEM;
2835 }
2836
2837 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2838 {
2839 ql_free_send_free_list(qdev);
2840 ql_free_large_buffers(qdev);
2841 ql_free_small_buffers(qdev);
2842 ql_free_buffer_queues(qdev);
2843 ql_free_net_req_rsp_queues(qdev);
2844 if (qdev->shadow_reg_virt_addr != NULL) {
2845 pci_free_consistent(qdev->pdev,
2846 PAGE_SIZE,
2847 qdev->shadow_reg_virt_addr,
2848 qdev->shadow_reg_phy_addr);
2849 qdev->shadow_reg_virt_addr = NULL;
2850 }
2851 }
2852
2853 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2854 {
2855 struct ql3xxx_local_ram_registers __iomem *local_ram =
2856 (void __iomem *)qdev->mem_map_registers;
2857
2858 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2859 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2860 2) << 4))
2861 return -1;
2862
2863 ql_write_page2_reg(qdev,
2864 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2865
2866 ql_write_page2_reg(qdev,
2867 &local_ram->maxBufletCount,
2868 qdev->nvram_data.bufletCount);
2869
2870 ql_write_page2_reg(qdev,
2871 &local_ram->freeBufletThresholdLow,
2872 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2873 (qdev->nvram_data.tcpWindowThreshold0));
2874
2875 ql_write_page2_reg(qdev,
2876 &local_ram->freeBufletThresholdHigh,
2877 qdev->nvram_data.tcpWindowThreshold50);
2878
2879 ql_write_page2_reg(qdev,
2880 &local_ram->ipHashTableBase,
2881 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2882 qdev->nvram_data.ipHashTableBaseLo);
2883 ql_write_page2_reg(qdev,
2884 &local_ram->ipHashTableCount,
2885 qdev->nvram_data.ipHashTableSize);
2886 ql_write_page2_reg(qdev,
2887 &local_ram->tcpHashTableBase,
2888 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2889 qdev->nvram_data.tcpHashTableBaseLo);
2890 ql_write_page2_reg(qdev,
2891 &local_ram->tcpHashTableCount,
2892 qdev->nvram_data.tcpHashTableSize);
2893 ql_write_page2_reg(qdev,
2894 &local_ram->ncbBase,
2895 (qdev->nvram_data.ncbTableBaseHi << 16) |
2896 qdev->nvram_data.ncbTableBaseLo);
2897 ql_write_page2_reg(qdev,
2898 &local_ram->maxNcbCount,
2899 qdev->nvram_data.ncbTableSize);
2900 ql_write_page2_reg(qdev,
2901 &local_ram->drbBase,
2902 (qdev->nvram_data.drbTableBaseHi << 16) |
2903 qdev->nvram_data.drbTableBaseLo);
2904 ql_write_page2_reg(qdev,
2905 &local_ram->maxDrbCount,
2906 qdev->nvram_data.drbTableSize);
2907 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2908 return 0;
2909 }
2910
2911 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2912 {
2913 u32 value;
2914 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2915 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2916 (void __iomem *)port_regs;
2917 u32 delay = 10;
2918 int status = 0;
2919
2920 if(ql_mii_setup(qdev))
2921 return -1;
2922
2923 /* Bring out PHY out of reset */
2924 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2925 (ISP_SERIAL_PORT_IF_WE |
2926 (ISP_SERIAL_PORT_IF_WE << 16)));
2927
2928 qdev->port_link_state = LS_DOWN;
2929 netif_carrier_off(qdev->ndev);
2930
2931 /* V2 chip fix for ARS-39168. */
2932 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2933 (ISP_SERIAL_PORT_IF_SDE |
2934 (ISP_SERIAL_PORT_IF_SDE << 16)));
2935
2936 /* Request Queue Registers */
2937 *((u32 *) (qdev->preq_consumer_index)) = 0;
2938 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2939 qdev->req_producer_index = 0;
2940
2941 ql_write_page1_reg(qdev,
2942 &hmem_regs->reqConsumerIndexAddrHigh,
2943 qdev->req_consumer_index_phy_addr_high);
2944 ql_write_page1_reg(qdev,
2945 &hmem_regs->reqConsumerIndexAddrLow,
2946 qdev->req_consumer_index_phy_addr_low);
2947
2948 ql_write_page1_reg(qdev,
2949 &hmem_regs->reqBaseAddrHigh,
2950 MS_64BITS(qdev->req_q_phy_addr));
2951 ql_write_page1_reg(qdev,
2952 &hmem_regs->reqBaseAddrLow,
2953 LS_64BITS(qdev->req_q_phy_addr));
2954 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2955
2956 /* Response Queue Registers */
2957 *((u16 *) (qdev->prsp_producer_index)) = 0;
2958 qdev->rsp_consumer_index = 0;
2959 qdev->rsp_current = qdev->rsp_q_virt_addr;
2960
2961 ql_write_page1_reg(qdev,
2962 &hmem_regs->rspProducerIndexAddrHigh,
2963 qdev->rsp_producer_index_phy_addr_high);
2964
2965 ql_write_page1_reg(qdev,
2966 &hmem_regs->rspProducerIndexAddrLow,
2967 qdev->rsp_producer_index_phy_addr_low);
2968
2969 ql_write_page1_reg(qdev,
2970 &hmem_regs->rspBaseAddrHigh,
2971 MS_64BITS(qdev->rsp_q_phy_addr));
2972
2973 ql_write_page1_reg(qdev,
2974 &hmem_regs->rspBaseAddrLow,
2975 LS_64BITS(qdev->rsp_q_phy_addr));
2976
2977 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2978
2979 /* Large Buffer Queue */
2980 ql_write_page1_reg(qdev,
2981 &hmem_regs->rxLargeQBaseAddrHigh,
2982 MS_64BITS(qdev->lrg_buf_q_phy_addr));
2983
2984 ql_write_page1_reg(qdev,
2985 &hmem_regs->rxLargeQBaseAddrLow,
2986 LS_64BITS(qdev->lrg_buf_q_phy_addr));
2987
2988 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
2989
2990 ql_write_page1_reg(qdev,
2991 &hmem_regs->rxLargeBufferLength,
2992 qdev->lrg_buffer_len);
2993
2994 /* Small Buffer Queue */
2995 ql_write_page1_reg(qdev,
2996 &hmem_regs->rxSmallQBaseAddrHigh,
2997 MS_64BITS(qdev->small_buf_q_phy_addr));
2998
2999 ql_write_page1_reg(qdev,
3000 &hmem_regs->rxSmallQBaseAddrLow,
3001 LS_64BITS(qdev->small_buf_q_phy_addr));
3002
3003 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3004 ql_write_page1_reg(qdev,
3005 &hmem_regs->rxSmallBufferLength,
3006 QL_SMALL_BUFFER_SIZE);
3007
3008 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3009 qdev->small_buf_release_cnt = 8;
3010 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3011 qdev->lrg_buf_release_cnt = 8;
3012 qdev->lrg_buf_next_free =
3013 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3014 qdev->small_buf_index = 0;
3015 qdev->lrg_buf_index = 0;
3016 qdev->lrg_buf_free_count = 0;
3017 qdev->lrg_buf_free_head = NULL;
3018 qdev->lrg_buf_free_tail = NULL;
3019
3020 ql_write_common_reg(qdev,
3021 &port_regs->CommonRegs.
3022 rxSmallQProducerIndex,
3023 qdev->small_buf_q_producer_index);
3024 ql_write_common_reg(qdev,
3025 &port_regs->CommonRegs.
3026 rxLargeQProducerIndex,
3027 qdev->lrg_buf_q_producer_index);
3028
3029 /*
3030 * Find out if the chip has already been initialized. If it has, then
3031 * we skip some of the initialization.
3032 */
3033 clear_bit(QL_LINK_MASTER, &qdev->flags);
3034 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3035 if ((value & PORT_STATUS_IC) == 0) {
3036
3037 /* Chip has not been configured yet, so let it rip. */
3038 if(ql_init_misc_registers(qdev)) {
3039 status = -1;
3040 goto out;
3041 }
3042
3043 value = qdev->nvram_data.tcpMaxWindowSize;
3044 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3045
3046 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3047
3048 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3049 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3050 * 2) << 13)) {
3051 status = -1;
3052 goto out;
3053 }
3054 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3055 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3056 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3057 16) | (INTERNAL_CHIP_SD |
3058 INTERNAL_CHIP_WE)));
3059 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3060 }
3061
3062 if (qdev->mac_index)
3063 ql_write_page0_reg(qdev,
3064 &port_regs->mac1MaxFrameLengthReg,
3065 qdev->max_frame_size);
3066 else
3067 ql_write_page0_reg(qdev,
3068 &port_regs->mac0MaxFrameLengthReg,
3069 qdev->max_frame_size);
3070
3071 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3072 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3073 2) << 7)) {
3074 status = -1;
3075 goto out;
3076 }
3077
3078 ql_init_scan_mode(qdev);
3079 ql_get_phy_owner(qdev);
3080
3081 /* Load the MAC Configuration */
3082
3083 /* Program lower 32 bits of the MAC address */
3084 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3085 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3086 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3087 ((qdev->ndev->dev_addr[2] << 24)
3088 | (qdev->ndev->dev_addr[3] << 16)
3089 | (qdev->ndev->dev_addr[4] << 8)
3090 | qdev->ndev->dev_addr[5]));
3091
3092 /* Program top 16 bits of the MAC address */
3093 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3094 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3095 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3096 ((qdev->ndev->dev_addr[0] << 8)
3097 | qdev->ndev->dev_addr[1]));
3098
3099 /* Enable Primary MAC */
3100 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3101 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3102 MAC_ADDR_INDIRECT_PTR_REG_PE));
3103
3104 /* Clear Primary and Secondary IP addresses */
3105 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3106 ((IP_ADDR_INDEX_REG_MASK << 16) |
3107 (qdev->mac_index << 2)));
3108 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3109
3110 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3111 ((IP_ADDR_INDEX_REG_MASK << 16) |
3112 ((qdev->mac_index << 2) + 1)));
3113 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3114
3115 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3116
3117 /* Indicate Configuration Complete */
3118 ql_write_page0_reg(qdev,
3119 &port_regs->portControl,
3120 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3121
3122 do {
3123 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3124 if (value & PORT_STATUS_IC)
3125 break;
3126 msleep(500);
3127 } while (--delay);
3128
3129 if (delay == 0) {
3130 printk(KERN_ERR PFX
3131 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3132 status = -1;
3133 goto out;
3134 }
3135
3136 /* Enable Ethernet Function */
3137 if (qdev->device_id == QL3032_DEVICE_ID) {
3138 value =
3139 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3140 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3141 QL3032_PORT_CONTROL_ET);
3142 ql_write_page0_reg(qdev, &port_regs->functionControl,
3143 ((value << 16) | value));
3144 } else {
3145 value =
3146 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3147 PORT_CONTROL_HH);
3148 ql_write_page0_reg(qdev, &port_regs->portControl,
3149 ((value << 16) | value));
3150 }
3151
3152
3153 out:
3154 return status;
3155 }
3156
3157 /*
3158 * Caller holds hw_lock.
3159 */
3160 static int ql_adapter_reset(struct ql3_adapter *qdev)
3161 {
3162 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3163 int status = 0;
3164 u16 value;
3165 int max_wait_time;
3166
3167 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3168 clear_bit(QL_RESET_DONE, &qdev->flags);
3169
3170 /*
3171 * Issue soft reset to chip.
3172 */
3173 printk(KERN_DEBUG PFX
3174 "%s: Issue soft reset to chip.\n",
3175 qdev->ndev->name);
3176 ql_write_common_reg(qdev,
3177 &port_regs->CommonRegs.ispControlStatus,
3178 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3179
3180 /* Wait 3 seconds for reset to complete. */
3181 printk(KERN_DEBUG PFX
3182 "%s: Wait 10 milliseconds for reset to complete.\n",
3183 qdev->ndev->name);
3184
3185 /* Wait until the firmware tells us the Soft Reset is done */
3186 max_wait_time = 5;
3187 do {
3188 value =
3189 ql_read_common_reg(qdev,
3190 &port_regs->CommonRegs.ispControlStatus);
3191 if ((value & ISP_CONTROL_SR) == 0)
3192 break;
3193
3194 ssleep(1);
3195 } while ((--max_wait_time));
3196
3197 /*
3198 * Also, make sure that the Network Reset Interrupt bit has been
3199 * cleared after the soft reset has taken place.
3200 */
3201 value =
3202 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3203 if (value & ISP_CONTROL_RI) {
3204 printk(KERN_DEBUG PFX
3205 "ql_adapter_reset: clearing RI after reset.\n");
3206 ql_write_common_reg(qdev,
3207 &port_regs->CommonRegs.
3208 ispControlStatus,
3209 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3210 }
3211
3212 if (max_wait_time == 0) {
3213 /* Issue Force Soft Reset */
3214 ql_write_common_reg(qdev,
3215 &port_regs->CommonRegs.
3216 ispControlStatus,
3217 ((ISP_CONTROL_FSR << 16) |
3218 ISP_CONTROL_FSR));
3219 /*
3220 * Wait until the firmware tells us the Force Soft Reset is
3221 * done
3222 */
3223 max_wait_time = 5;
3224 do {
3225 value =
3226 ql_read_common_reg(qdev,
3227 &port_regs->CommonRegs.
3228 ispControlStatus);
3229 if ((value & ISP_CONTROL_FSR) == 0) {
3230 break;
3231 }
3232 ssleep(1);
3233 } while ((--max_wait_time));
3234 }
3235 if (max_wait_time == 0)
3236 status = 1;
3237
3238 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3239 set_bit(QL_RESET_DONE, &qdev->flags);
3240 return status;
3241 }
3242
3243 static void ql_set_mac_info(struct ql3_adapter *qdev)
3244 {
3245 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3246 u32 value, port_status;
3247 u8 func_number;
3248
3249 /* Get the function number */
3250 value =
3251 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3252 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3253 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3254 switch (value & ISP_CONTROL_FN_MASK) {
3255 case ISP_CONTROL_FN0_NET:
3256 qdev->mac_index = 0;
3257 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3258 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3259 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3260 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3261 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3262 if (port_status & PORT_STATUS_SM0)
3263 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3264 else
3265 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3266 break;
3267
3268 case ISP_CONTROL_FN1_NET:
3269 qdev->mac_index = 1;
3270 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3271 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3272 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3273 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3274 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3275 if (port_status & PORT_STATUS_SM1)
3276 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3277 else
3278 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3279 break;
3280
3281 case ISP_CONTROL_FN0_SCSI:
3282 case ISP_CONTROL_FN1_SCSI:
3283 default:
3284 printk(KERN_DEBUG PFX
3285 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3286 qdev->ndev->name,value);
3287 break;
3288 }
3289 qdev->numPorts = qdev->nvram_data.numPorts;
3290 }
3291
3292 static void ql_display_dev_info(struct net_device *ndev)
3293 {
3294 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3295 struct pci_dev *pdev = qdev->pdev;
3296
3297 printk(KERN_INFO PFX
3298 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3299 DRV_NAME, qdev->index, qdev->chip_rev_id,
3300 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3301 qdev->pci_slot);
3302 printk(KERN_INFO PFX
3303 "%s Interface.\n",
3304 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3305
3306 /*
3307 * Print PCI bus width/type.
3308 */
3309 printk(KERN_INFO PFX
3310 "Bus interface is %s %s.\n",
3311 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3312 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3313
3314 printk(KERN_INFO PFX
3315 "mem IO base address adjusted = 0x%p\n",
3316 qdev->mem_map_registers);
3317 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3318
3319 if (netif_msg_probe(qdev))
3320 printk(KERN_INFO PFX
3321 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3322 ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3323 ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3324 ndev->dev_addr[5]);
3325 }
3326
3327 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3328 {
3329 struct net_device *ndev = qdev->ndev;
3330 int retval = 0;
3331
3332 netif_stop_queue(ndev);
3333 netif_carrier_off(ndev);
3334
3335 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3336 clear_bit(QL_LINK_MASTER,&qdev->flags);
3337
3338 ql_disable_interrupts(qdev);
3339
3340 free_irq(qdev->pdev->irq, ndev);
3341
3342 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3343 printk(KERN_INFO PFX
3344 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3345 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3346 pci_disable_msi(qdev->pdev);
3347 }
3348
3349 del_timer_sync(&qdev->adapter_timer);
3350
3351 netif_poll_disable(ndev);
3352
3353 if (do_reset) {
3354 int soft_reset;
3355 unsigned long hw_flags;
3356
3357 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3358 if (ql_wait_for_drvr_lock(qdev)) {
3359 if ((soft_reset = ql_adapter_reset(qdev))) {
3360 printk(KERN_ERR PFX
3361 "%s: ql_adapter_reset(%d) FAILED!\n",
3362 ndev->name, qdev->index);
3363 }
3364 printk(KERN_ERR PFX
3365 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3366 } else {
3367 printk(KERN_ERR PFX
3368 "%s: Could not acquire driver lock to do "
3369 "reset!\n", ndev->name);
3370 retval = -1;
3371 }
3372 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3373 }
3374 ql_free_mem_resources(qdev);
3375 return retval;
3376 }
3377
3378 static int ql_adapter_up(struct ql3_adapter *qdev)
3379 {
3380 struct net_device *ndev = qdev->ndev;
3381 int err;
3382 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3383 unsigned long hw_flags;
3384
3385 if (ql_alloc_mem_resources(qdev)) {
3386 printk(KERN_ERR PFX
3387 "%s Unable to allocate buffers.\n", ndev->name);
3388 return -ENOMEM;
3389 }
3390
3391 if (qdev->msi) {
3392 if (pci_enable_msi(qdev->pdev)) {
3393 printk(KERN_ERR PFX
3394 "%s: User requested MSI, but MSI failed to "
3395 "initialize. Continuing without MSI.\n",
3396 qdev->ndev->name);
3397 qdev->msi = 0;
3398 } else {
3399 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3400 set_bit(QL_MSI_ENABLED,&qdev->flags);
3401 irq_flags &= ~IRQF_SHARED;
3402 }
3403 }
3404
3405 if ((err = request_irq(qdev->pdev->irq,
3406 ql3xxx_isr,
3407 irq_flags, ndev->name, ndev))) {
3408 printk(KERN_ERR PFX
3409 "%s: Failed to reserve interrupt %d already in use.\n",
3410 ndev->name, qdev->pdev->irq);
3411 goto err_irq;
3412 }
3413
3414 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3415
3416 if ((err = ql_wait_for_drvr_lock(qdev))) {
3417 if ((err = ql_adapter_initialize(qdev))) {
3418 printk(KERN_ERR PFX
3419 "%s: Unable to initialize adapter.\n",
3420 ndev->name);
3421 goto err_init;
3422 }
3423 printk(KERN_ERR PFX
3424 "%s: Releaseing driver lock.\n",ndev->name);
3425 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3426 } else {
3427 printk(KERN_ERR PFX
3428 "%s: Could not aquire driver lock.\n",
3429 ndev->name);
3430 goto err_lock;
3431 }
3432
3433 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3434
3435 set_bit(QL_ADAPTER_UP,&qdev->flags);
3436
3437 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3438
3439 netif_poll_enable(ndev);
3440 ql_enable_interrupts(qdev);
3441 return 0;
3442
3443 err_init:
3444 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3445 err_lock:
3446 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3447 free_irq(qdev->pdev->irq, ndev);
3448 err_irq:
3449 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3450 printk(KERN_INFO PFX
3451 "%s: calling pci_disable_msi().\n",
3452 qdev->ndev->name);
3453 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3454 pci_disable_msi(qdev->pdev);
3455 }
3456 return err;
3457 }
3458
3459 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3460 {
3461 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3462 printk(KERN_ERR PFX
3463 "%s: Driver up/down cycle failed, "
3464 "closing device\n",qdev->ndev->name);
3465 dev_close(qdev->ndev);
3466 return -1;
3467 }
3468 return 0;
3469 }
3470
3471 static int ql3xxx_close(struct net_device *ndev)
3472 {
3473 struct ql3_adapter *qdev = netdev_priv(ndev);
3474
3475 /*
3476 * Wait for device to recover from a reset.
3477 * (Rarely happens, but possible.)
3478 */
3479 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3480 msleep(50);
3481
3482 ql_adapter_down(qdev,QL_DO_RESET);
3483 return 0;
3484 }
3485
3486 static int ql3xxx_open(struct net_device *ndev)
3487 {
3488 struct ql3_adapter *qdev = netdev_priv(ndev);
3489 return (ql_adapter_up(qdev));
3490 }
3491
3492 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3493 {
3494 struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3495 return &qdev->stats;
3496 }
3497
3498 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3499 {
3500 /*
3501 * We are manually parsing the list in the net_device structure.
3502 */
3503 return;
3504 }
3505
3506 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3507 {
3508 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3509 struct ql3xxx_port_registers __iomem *port_regs =
3510 qdev->mem_map_registers;
3511 struct sockaddr *addr = p;
3512 unsigned long hw_flags;
3513
3514 if (netif_running(ndev))
3515 return -EBUSY;
3516
3517 if (!is_valid_ether_addr(addr->sa_data))
3518 return -EADDRNOTAVAIL;
3519
3520 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3521
3522 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3523 /* Program lower 32 bits of the MAC address */
3524 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3525 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3526 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3527 ((ndev->dev_addr[2] << 24) | (ndev->
3528 dev_addr[3] << 16) |
3529 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3530
3531 /* Program top 16 bits of the MAC address */
3532 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3533 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3534 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3535 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3536 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3537
3538 return 0;
3539 }
3540
3541 static void ql3xxx_tx_timeout(struct net_device *ndev)
3542 {
3543 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3544
3545 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3546 /*
3547 * Stop the queues, we've got a problem.
3548 */
3549 netif_stop_queue(ndev);
3550
3551 /*
3552 * Wake up the worker to process this event.
3553 */
3554 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3555 }
3556
3557 static void ql_reset_work(struct work_struct *work)
3558 {
3559 struct ql3_adapter *qdev =
3560 container_of(work, struct ql3_adapter, reset_work.work);
3561 struct net_device *ndev = qdev->ndev;
3562 u32 value;
3563 struct ql_tx_buf_cb *tx_cb;
3564 int max_wait_time, i;
3565 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3566 unsigned long hw_flags;
3567
3568 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3569 clear_bit(QL_LINK_MASTER,&qdev->flags);
3570
3571 /*
3572 * Loop through the active list and return the skb.
3573 */
3574 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3575 int j;
3576 tx_cb = &qdev->tx_buf[i];
3577 if (tx_cb->skb) {
3578 printk(KERN_DEBUG PFX
3579 "%s: Freeing lost SKB.\n",
3580 qdev->ndev->name);
3581 pci_unmap_single(qdev->pdev,
3582 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3583 pci_unmap_len(&tx_cb->map[0], maplen),
3584 PCI_DMA_TODEVICE);
3585 for(j=1;j<tx_cb->seg_count;j++) {
3586 pci_unmap_page(qdev->pdev,
3587 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3588 pci_unmap_len(&tx_cb->map[j],maplen),
3589 PCI_DMA_TODEVICE);
3590 }
3591 dev_kfree_skb(tx_cb->skb);
3592 tx_cb->skb = NULL;
3593 }
3594 }
3595
3596 printk(KERN_ERR PFX
3597 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3598 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3599 ql_write_common_reg(qdev,
3600 &port_regs->CommonRegs.
3601 ispControlStatus,
3602 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3603 /*
3604 * Wait the for Soft Reset to Complete.
3605 */
3606 max_wait_time = 10;
3607 do {
3608 value = ql_read_common_reg(qdev,
3609 &port_regs->CommonRegs.
3610
3611 ispControlStatus);
3612 if ((value & ISP_CONTROL_SR) == 0) {
3613 printk(KERN_DEBUG PFX
3614 "%s: reset completed.\n",
3615 qdev->ndev->name);
3616 break;
3617 }
3618
3619 if (value & ISP_CONTROL_RI) {
3620 printk(KERN_DEBUG PFX
3621 "%s: clearing NRI after reset.\n",
3622 qdev->ndev->name);
3623 ql_write_common_reg(qdev,
3624 &port_regs->
3625 CommonRegs.
3626 ispControlStatus,
3627 ((ISP_CONTROL_RI <<
3628 16) | ISP_CONTROL_RI));
3629 }
3630
3631 ssleep(1);
3632 } while (--max_wait_time);
3633 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3634
3635 if (value & ISP_CONTROL_SR) {
3636
3637 /*
3638 * Set the reset flags and clear the board again.
3639 * Nothing else to do...
3640 */
3641 printk(KERN_ERR PFX
3642 "%s: Timed out waiting for reset to "
3643 "complete.\n", ndev->name);
3644 printk(KERN_ERR PFX
3645 "%s: Do a reset.\n", ndev->name);
3646 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3647 clear_bit(QL_RESET_START,&qdev->flags);
3648 ql_cycle_adapter(qdev,QL_DO_RESET);
3649 return;
3650 }
3651
3652 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3653 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3654 clear_bit(QL_RESET_START,&qdev->flags);
3655 ql_cycle_adapter(qdev,QL_NO_RESET);
3656 }
3657 }
3658
3659 static void ql_tx_timeout_work(struct work_struct *work)
3660 {
3661 struct ql3_adapter *qdev =
3662 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3663
3664 ql_cycle_adapter(qdev, QL_DO_RESET);
3665 }
3666
3667 static void ql_get_board_info(struct ql3_adapter *qdev)
3668 {
3669 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3670 u32 value;
3671
3672 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3673
3674 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3675 if (value & PORT_STATUS_64)
3676 qdev->pci_width = 64;
3677 else
3678 qdev->pci_width = 32;
3679 if (value & PORT_STATUS_X)
3680 qdev->pci_x = 1;
3681 else
3682 qdev->pci_x = 0;
3683 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3684 }
3685
3686 static void ql3xxx_timer(unsigned long ptr)
3687 {
3688 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3689
3690 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3691 printk(KERN_DEBUG PFX
3692 "%s: Reset in progress.\n",
3693 qdev->ndev->name);
3694 goto end;
3695 }
3696
3697 ql_link_state_machine(qdev);
3698
3699 /* Restart timer on 2 second interval. */
3700 end:
3701 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3702 }
3703
3704 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3705 const struct pci_device_id *pci_entry)
3706 {
3707 struct net_device *ndev = NULL;
3708 struct ql3_adapter *qdev = NULL;
3709 static int cards_found = 0;
3710 int pci_using_dac, err;
3711
3712 err = pci_enable_device(pdev);
3713 if (err) {
3714 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3715 pci_name(pdev));
3716 goto err_out;
3717 }
3718
3719 err = pci_request_regions(pdev, DRV_NAME);
3720 if (err) {
3721 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3722 pci_name(pdev));
3723 goto err_out_disable_pdev;
3724 }
3725
3726 pci_set_master(pdev);
3727
3728 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3729 pci_using_dac = 1;
3730 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3731 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3732 pci_using_dac = 0;
3733 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3734 }
3735
3736 if (err) {
3737 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3738 pci_name(pdev));
3739 goto err_out_free_regions;
3740 }
3741
3742 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3743 if (!ndev) {
3744 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3745 pci_name(pdev));
3746 err = -ENOMEM;
3747 goto err_out_free_regions;
3748 }
3749
3750 SET_MODULE_OWNER(ndev);
3751 SET_NETDEV_DEV(ndev, &pdev->dev);
3752
3753 pci_set_drvdata(pdev, ndev);
3754
3755 qdev = netdev_priv(ndev);
3756 qdev->index = cards_found;
3757 qdev->ndev = ndev;
3758 qdev->pdev = pdev;
3759 qdev->device_id = pci_entry->device;
3760 qdev->port_link_state = LS_DOWN;
3761 if (msi)
3762 qdev->msi = 1;
3763
3764 qdev->msg_enable = netif_msg_init(debug, default_msg);
3765
3766 if (pci_using_dac)
3767 ndev->features |= NETIF_F_HIGHDMA;
3768 if (qdev->device_id == QL3032_DEVICE_ID)
3769 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3770
3771 qdev->mem_map_registers =
3772 ioremap_nocache(pci_resource_start(pdev, 1),
3773 pci_resource_len(qdev->pdev, 1));
3774 if (!qdev->mem_map_registers) {
3775 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3776 pci_name(pdev));
3777 err = -EIO;
3778 goto err_out_free_ndev;
3779 }
3780
3781 spin_lock_init(&qdev->adapter_lock);
3782 spin_lock_init(&qdev->hw_lock);
3783
3784 /* Set driver entry points */
3785 ndev->open = ql3xxx_open;
3786 ndev->hard_start_xmit = ql3xxx_send;
3787 ndev->stop = ql3xxx_close;
3788 ndev->get_stats = ql3xxx_get_stats;
3789 ndev->set_multicast_list = ql3xxx_set_multicast_list;
3790 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3791 ndev->set_mac_address = ql3xxx_set_mac_address;
3792 ndev->tx_timeout = ql3xxx_tx_timeout;
3793 ndev->watchdog_timeo = 5 * HZ;
3794
3795 ndev->poll = &ql_poll;
3796 ndev->weight = 64;
3797
3798 ndev->irq = pdev->irq;
3799
3800 /* make sure the EEPROM is good */
3801 if (ql_get_nvram_params(qdev)) {
3802 printk(KERN_ALERT PFX
3803 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3804 qdev->index);
3805 err = -EIO;
3806 goto err_out_iounmap;
3807 }
3808
3809 ql_set_mac_info(qdev);
3810
3811 /* Validate and set parameters */
3812 if (qdev->mac_index) {
3813 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3814 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3815 ETH_ALEN);
3816 } else {
3817 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3818 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3819 ETH_ALEN);
3820 }
3821 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3822
3823 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3824
3825 /* Turn off support for multicasting */
3826 ndev->flags &= ~IFF_MULTICAST;
3827
3828 /* Record PCI bus information. */
3829 ql_get_board_info(qdev);
3830
3831 /*
3832 * Set the Maximum Memory Read Byte Count value. We do this to handle
3833 * jumbo frames.
3834 */
3835 if (qdev->pci_x) {
3836 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3837 }
3838
3839 err = register_netdev(ndev);
3840 if (err) {
3841 printk(KERN_ERR PFX "%s: cannot register net device\n",
3842 pci_name(pdev));
3843 goto err_out_iounmap;
3844 }
3845
3846 /* we're going to reset, so assume we have no link for now */
3847
3848 netif_carrier_off(ndev);
3849 netif_stop_queue(ndev);
3850
3851 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3852 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3853 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3854
3855 init_timer(&qdev->adapter_timer);
3856 qdev->adapter_timer.function = ql3xxx_timer;
3857 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3858 qdev->adapter_timer.data = (unsigned long)qdev;
3859
3860 if(!cards_found) {
3861 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3862 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3863 DRV_NAME, DRV_VERSION);
3864 }
3865 ql_display_dev_info(ndev);
3866
3867 cards_found++;
3868 return 0;
3869
3870 err_out_iounmap:
3871 iounmap(qdev->mem_map_registers);
3872 err_out_free_ndev:
3873 free_netdev(ndev);
3874 err_out_free_regions:
3875 pci_release_regions(pdev);
3876 err_out_disable_pdev:
3877 pci_disable_device(pdev);
3878 pci_set_drvdata(pdev, NULL);
3879 err_out:
3880 return err;
3881 }
3882
3883 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3884 {
3885 struct net_device *ndev = pci_get_drvdata(pdev);
3886 struct ql3_adapter *qdev = netdev_priv(ndev);
3887
3888 unregister_netdev(ndev);
3889 qdev = netdev_priv(ndev);
3890
3891 ql_disable_interrupts(qdev);
3892
3893 if (qdev->workqueue) {
3894 cancel_delayed_work(&qdev->reset_work);
3895 cancel_delayed_work(&qdev->tx_timeout_work);
3896 destroy_workqueue(qdev->workqueue);
3897 qdev->workqueue = NULL;
3898 }
3899
3900 iounmap(qdev->mem_map_registers);
3901 pci_release_regions(pdev);
3902 pci_set_drvdata(pdev, NULL);
3903 free_netdev(ndev);
3904 }
3905
3906 static struct pci_driver ql3xxx_driver = {
3907
3908 .name = DRV_NAME,
3909 .id_table = ql3xxx_pci_tbl,
3910 .probe = ql3xxx_probe,
3911 .remove = __devexit_p(ql3xxx_remove),
3912 };
3913
3914 static int __init ql3xxx_init_module(void)
3915 {
3916 return pci_register_driver(&ql3xxx_driver);
3917 }
3918
3919 static void __exit ql3xxx_exit(void)
3920 {
3921 pci_unregister_driver(&ql3xxx_driver);
3922 }
3923
3924 module_init(ql3xxx_init_module);
3925 module_exit(ql3xxx_exit);
Linux with added FPC-III support