drivers/base/regmap/regcache.c

   1 /*
   2  * Register cache access API
   3  *
   4  * Copyright 2011 Wolfson Microelectronics plc
   5  *
   6  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bsearch.h>
  14 #include <linux/device.h>
  15 #include <linux/export.h>
  16 #include <linux/slab.h>
  17 #include <linux/sort.h>
  18 #include <trace/events/regmap.h>
  19
  20 #include "internal.h"
  21
  22 static const struct regcache_ops *cache_types[] = {
  23         &regcache_rbtree_ops,
  24         &regcache_lzo_ops,
  25         &regcache_flat_ops,
  26 };
  27
  28 static int regcache_hw_init(struct regmap *map)
  29 {
  30         int i, j;
  31         int ret;
  32         int count;
  33         unsigned int val;
  34         void *tmp_buf;
  35
  36         if (!map->num_reg_defaults_raw)
  37                 return -EINVAL;
  38
  39         /* calculate the size of reg_defaults */
  40         for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
  41                 if (!regmap_volatile(map, i * map->reg_stride))
  42                         count++;
  43
  44         /* all registers are volatile, so just bypass */
  45         if (!count) {
  46                 map->cache_bypass = true;
  47                 return 0;
  48         }
  49
  50         map->num_reg_defaults = count;
  51         map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
  52                                           GFP_KERNEL);
  53         if (!map->reg_defaults)
  54                 return -ENOMEM;
  55
  56         if (!map->reg_defaults_raw) {
  57                 u32 cache_bypass = map->cache_bypass;
  58                 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
  59
  60                 /* Bypass the cache access till data read from HW*/
  61                 map->cache_bypass = 1;
  62                 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
  63                 if (!tmp_buf) {
  64                         ret = -ENOMEM;
  65                         goto err_free;
  66                 }
  67                 ret = regmap_raw_read(map, 0, tmp_buf,
  68                                       map->num_reg_defaults_raw);
  69                 map->cache_bypass = cache_bypass;
  70                 if (ret < 0)
  71                         goto err_cache_free;
  72
  73                 map->reg_defaults_raw = tmp_buf;
  74                 map->cache_free = 1;
  75         }
  76
  77         /* fill the reg_defaults */
  78         for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
  79                 if (regmap_volatile(map, i * map->reg_stride))
  80                         continue;
  81                 val = regcache_get_val(map, map->reg_defaults_raw, i);
  82                 map->reg_defaults[j].reg = i * map->reg_stride;
  83                 map->reg_defaults[j].def = val;
  84                 j++;
  85         }
  86
  87         return 0;
  88
  89 err_cache_free:
  90         kfree(tmp_buf);
  91 err_free:
  92         kfree(map->reg_defaults);
  93
  94         return ret;
  95 }
  96
  97 int regcache_init(struct regmap *map, const struct regmap_config *config)
  98 {
  99         int ret;
 100         int i;
 101         void *tmp_buf;
 102
 103         for (i = 0; i < config->num_reg_defaults; i++)
 104                 if (config->reg_defaults[i].reg % map->reg_stride)
 105                         return -EINVAL;
 106
 107         if (map->cache_type == REGCACHE_NONE) {
 108                 map->cache_bypass = true;
 109                 return 0;
 110         }
 111
 112         for (i = 0; i < ARRAY_SIZE(cache_types); i++)
 113                 if (cache_types[i]->type == map->cache_type)
 114                         break;
 115
 116         if (i == ARRAY_SIZE(cache_types)) {
 117                 dev_err(map->dev, "Could not match compress type: %d\n",
 118                         map->cache_type);
 119                 return -EINVAL;
 120         }
 121
 122         map->num_reg_defaults = config->num_reg_defaults;
 123         map->num_reg_defaults_raw = config->num_reg_defaults_raw;
 124         map->reg_defaults_raw = config->reg_defaults_raw;
 125         map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
 126         map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
 127
 128         map->cache = NULL;
 129         map->cache_ops = cache_types[i];
 130
 131         if (!map->cache_ops->read ||
 132             !map->cache_ops->write ||
 133             !map->cache_ops->name)
 134                 return -EINVAL;
 135
 136         /* We still need to ensure that the reg_defaults
 137          * won't vanish from under us.  We'll need to make
 138          * a copy of it.
 139          */
 140         if (config->reg_defaults) {
 141                 if (!map->num_reg_defaults)
 142                         return -EINVAL;
 143                 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
 144                                   sizeof(struct reg_default), GFP_KERNEL);
 145                 if (!tmp_buf)
 146                         return -ENOMEM;
 147                 map->reg_defaults = tmp_buf;
 148         } else if (map->num_reg_defaults_raw) {
 149                 /* Some devices such as PMICs don't have cache defaults,
 150                  * we cope with this by reading back the HW registers and
 151                  * crafting the cache defaults by hand.
 152                  */
 153                 ret = regcache_hw_init(map);
 154                 if (ret < 0)
 155                         return ret;
 156                 if (map->cache_bypass)
 157                         return 0;
 158         }
 159
 160         if (!map->max_register)
 161                 map->max_register = map->num_reg_defaults_raw;
 162
 163         if (map->cache_ops->init) {
 164                 dev_dbg(map->dev, "Initializing %s cache\n",
 165                         map->cache_ops->name);
 166                 ret = map->cache_ops->init(map);
 167                 if (ret)
 168                         goto err_free;
 169         }
 170         return 0;
 171
 172 err_free:
 173         kfree(map->reg_defaults);
 174         if (map->cache_free)
 175                 kfree(map->reg_defaults_raw);
 176
 177         return ret;
 178 }
 179
 180 void regcache_exit(struct regmap *map)
 181 {
 182         if (map->cache_type == REGCACHE_NONE)
 183                 return;
 184
 185         BUG_ON(!map->cache_ops);
 186
 187         kfree(map->reg_defaults);
 188         if (map->cache_free)
 189                 kfree(map->reg_defaults_raw);
 190
 191         if (map->cache_ops->exit) {
 192                 dev_dbg(map->dev, "Destroying %s cache\n",
 193                         map->cache_ops->name);
 194                 map->cache_ops->exit(map);
 195         }
 196 }
 197
 198 /**
 199  * regcache_read: Fetch the value of a given register from the cache.
 200  *
 201  * @map: map to configure.
 202  * @reg: The register index.
 203  * @value: The value to be returned.
 204  *
 205  * Return a negative value on failure, 0 on success.
 206  */
 207 int regcache_read(struct regmap *map,
 208                   unsigned int reg, unsigned int *value)
 209 {
 210         int ret;
 211
 212         if (map->cache_type == REGCACHE_NONE)
 213                 return -ENOSYS;
 214
 215         BUG_ON(!map->cache_ops);
 216
 217         if (!regmap_volatile(map, reg)) {
 218                 ret = map->cache_ops->read(map, reg, value);
 219
 220                 if (ret == 0)
 221                         trace_regmap_reg_read_cache(map, reg, *value);
 222
 223                 return ret;
 224         }
 225
 226         return -EINVAL;
 227 }
 228
 229 /**
 230  * regcache_write: Set the value of a given register in the cache.
 231  *
 232  * @map: map to configure.
 233  * @reg: The register index.
 234  * @value: The new register value.
 235  *
 236  * Return a negative value on failure, 0 on success.
 237  */
 238 int regcache_write(struct regmap *map,
 239                    unsigned int reg, unsigned int value)
 240 {
 241         if (map->cache_type == REGCACHE_NONE)
 242                 return 0;
 243
 244         BUG_ON(!map->cache_ops);
 245
 246         if (!regmap_volatile(map, reg))
 247                 return map->cache_ops->write(map, reg, value);
 248
 249         return 0;
 250 }
 251
 252 static int regcache_default_sync(struct regmap *map, unsigned int min,
 253                                  unsigned int max)
 254 {
 255         unsigned int reg;
 256
 257         for (reg = min; reg <= max; reg += map->reg_stride) {
 258                 unsigned int val;
 259                 int ret;
 260
 261                 if (regmap_volatile(map, reg) ||
 262                     !regmap_writeable(map, reg))
 263                         continue;
 264
 265                 ret = regcache_read(map, reg, &val);
 266                 if (ret)
 267                         return ret;
 268
 269                 /* Is this the hardware default?  If so skip. */
 270                 ret = regcache_lookup_reg(map, reg);
 271                 if (ret >= 0 && val == map->reg_defaults[ret].def)
 272                         continue;
 273
 274                 map->cache_bypass = 1;
 275                 ret = _regmap_write(map, reg, val);
 276                 map->cache_bypass = 0;
 277                 if (ret) {
 278                         dev_err(map->dev, "Unable to sync register %#x. %d\n",
 279                                 reg, ret);
 280                         return ret;
 281                 }
 282                 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
 283         }
 284
 285         return 0;
 286 }
 287
 288 /**
 289  * regcache_sync: Sync the register cache with the hardware.
 290  *
 291  * @map: map to configure.
 292  *
 293  * Any registers that should not be synced should be marked as
 294  * volatile.  In general drivers can choose not to use the provided
 295  * syncing functionality if they so require.
 296  *
 297  * Return a negative value on failure, 0 on success.
 298  */
 299 int regcache_sync(struct regmap *map)
 300 {
 301         int ret = 0;
 302         unsigned int i;
 303         const char *name;
 304         unsigned int bypass;
 305
 306         BUG_ON(!map->cache_ops);
 307
 308         map->lock(map->lock_arg);
 309         /* Remember the initial bypass state */
 310         bypass = map->cache_bypass;
 311         dev_dbg(map->dev, "Syncing %s cache\n",
 312                 map->cache_ops->name);
 313         name = map->cache_ops->name;
 314         trace_regcache_sync(map, name, "start");
 315
 316         if (!map->cache_dirty)
 317                 goto out;
 318
 319         map->async = true;
 320
 321         /* Apply any patch first */
 322         map->cache_bypass = 1;
 323         for (i = 0; i < map->patch_regs; i++) {
 324                 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
 325                 if (ret != 0) {
 326                         dev_err(map->dev, "Failed to write %x = %x: %d\n",
 327                                 map->patch[i].reg, map->patch[i].def, ret);
 328                         goto out;
 329                 }
 330         }
 331         map->cache_bypass = 0;
 332
 333         if (map->cache_ops->sync)
 334                 ret = map->cache_ops->sync(map, 0, map->max_register);
 335         else
 336                 ret = regcache_default_sync(map, 0, map->max_register);
 337
 338         if (ret == 0)
 339                 map->cache_dirty = false;
 340
 341 out:
 342         /* Restore the bypass state */
 343         map->async = false;
 344         map->cache_bypass = bypass;
 345         map->unlock(map->lock_arg);
 346
 347         regmap_async_complete(map);
 348
 349         trace_regcache_sync(map, name, "stop");
 350
 351         return ret;
 352 }
 353 EXPORT_SYMBOL_GPL(regcache_sync);
 354
 355 /**
 356  * regcache_sync_region: Sync part  of the register cache with the hardware.
 357  *
 358  * @map: map to sync.
 359  * @min: first register to sync
 360  * @max: last register to sync
 361  *
 362  * Write all non-default register values in the specified region to
 363  * the hardware.
 364  *
 365  * Return a negative value on failure, 0 on success.
 366  */
 367 int regcache_sync_region(struct regmap *map, unsigned int min,
 368                          unsigned int max)
 369 {
 370         int ret = 0;
 371         const char *name;
 372         unsigned int bypass;
 373
 374         BUG_ON(!map->cache_ops);
 375
 376         map->lock(map->lock_arg);
 377
 378         /* Remember the initial bypass state */
 379         bypass = map->cache_bypass;
 380
 381         name = map->cache_ops->name;
 382         dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
 383
 384         trace_regcache_sync(map, name, "start region");
 385
 386         if (!map->cache_dirty)
 387                 goto out;
 388
 389         map->async = true;
 390
 391         if (map->cache_ops->sync)
 392                 ret = map->cache_ops->sync(map, min, max);
 393         else
 394                 ret = regcache_default_sync(map, min, max);
 395
 396 out:
 397         /* Restore the bypass state */
 398         map->cache_bypass = bypass;
 399         map->async = false;
 400         map->unlock(map->lock_arg);
 401
 402         regmap_async_complete(map);
 403
 404         trace_regcache_sync(map, name, "stop region");
 405
 406         return ret;
 407 }
 408 EXPORT_SYMBOL_GPL(regcache_sync_region);
 409
 410 /**
 411  * regcache_drop_region: Discard part of the register cache
 412  *
 413  * @map: map to operate on
 414  * @min: first register to discard
 415  * @max: last register to discard
 416  *
 417  * Discard part of the register cache.
 418  *
 419  * Return a negative value on failure, 0 on success.
 420  */
 421 int regcache_drop_region(struct regmap *map, unsigned int min,
 422                          unsigned int max)
 423 {
 424         int ret = 0;
 425
 426         if (!map->cache_ops || !map->cache_ops->drop)
 427                 return -EINVAL;
 428
 429         map->lock(map->lock_arg);
 430
 431         trace_regcache_drop_region(map, min, max);
 432
 433         ret = map->cache_ops->drop(map, min, max);
 434
 435         map->unlock(map->lock_arg);
 436
 437         return ret;
 438 }
 439 EXPORT_SYMBOL_GPL(regcache_drop_region);
 440
 441 /**
 442  * regcache_cache_only: Put a register map into cache only mode
 443  *
 444  * @map: map to configure
 445  * @cache_only: flag if changes should be written to the hardware
 446  *
 447  * When a register map is marked as cache only writes to the register
 448  * map API will only update the register cache, they will not cause
 449  * any hardware changes.  This is useful for allowing portions of
 450  * drivers to act as though the device were functioning as normal when
 451  * it is disabled for power saving reasons.
 452  */
 453 void regcache_cache_only(struct regmap *map, bool enable)
 454 {
 455         map->lock(map->lock_arg);
 456         WARN_ON(map->cache_bypass && enable);
 457         map->cache_only = enable;
 458         trace_regmap_cache_only(map, enable);
 459         map->unlock(map->lock_arg);
 460 }
 461 EXPORT_SYMBOL_GPL(regcache_cache_only);
 462
 463 /**
 464  * regcache_mark_dirty: Mark the register cache as dirty
 465  *
 466  * @map: map to mark
 467  *
 468  * Mark the register cache as dirty, for example due to the device
 469  * having been powered down for suspend.  If the cache is not marked
 470  * as dirty then the cache sync will be suppressed.
 471  */
 472 void regcache_mark_dirty(struct regmap *map)
 473 {
 474         map->lock(map->lock_arg);
 475         map->cache_dirty = true;
 476         map->unlock(map->lock_arg);
 477 }
 478 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
 479
 480 /**
 481  * regcache_cache_bypass: Put a register map into cache bypass mode
 482  *
 483  * @map: map to configure
 484  * @cache_bypass: flag if changes should not be written to the hardware
 485  *
 486  * When a register map is marked with the cache bypass option, writes
 487  * to the register map API will only update the hardware and not the
 488  * the cache directly.  This is useful when syncing the cache back to
 489  * the hardware.
 490  */
 491 void regcache_cache_bypass(struct regmap *map, bool enable)
 492 {
 493         map->lock(map->lock_arg);
 494         WARN_ON(map->cache_only && enable);
 495         map->cache_bypass = enable;
 496         trace_regmap_cache_bypass(map, enable);
 497         map->unlock(map->lock_arg);
 498 }
 499 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
 500
 501 bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
 502                       unsigned int val)
 503 {
 504         if (regcache_get_val(map, base, idx) == val)
 505                 return true;
 506
 507         /* Use device native format if possible */
 508         if (map->format.format_val) {
 509                 map->format.format_val(base + (map->cache_word_size * idx),
 510                                        val, 0);
 511                 return false;
 512         }
 513
 514         switch (map->cache_word_size) {
 515         case 1: {
 516                 u8 *cache = base;
 517                 cache[idx] = val;
 518                 break;
 519         }
 520         case 2: {
 521                 u16 *cache = base;
 522                 cache[idx] = val;
 523                 break;
 524         }
 525         case 4: {
 526                 u32 *cache = base;
 527                 cache[idx] = val;
 528                 break;
 529         }
 530         default:
 531                 BUG();
 532         }
 533         return false;
 534 }
 535
 536 unsigned int regcache_get_val(struct regmap *map, const void *base,
 537                               unsigned int idx)
 538 {
 539         if (!base)
 540                 return -EINVAL;
 541
 542         /* Use device native format if possible */
 543         if (map->format.parse_val)
 544                 return map->format.parse_val(regcache_get_val_addr(map, base,
 545                                                                    idx));
 546
 547         switch (map->cache_word_size) {
 548         case 1: {
 549                 const u8 *cache = base;
 550                 return cache[idx];
 551         }
 552         case 2: {
 553                 const u16 *cache = base;
 554                 return cache[idx];
 555         }
 556         case 4: {
 557                 const u32 *cache = base;
 558                 return cache[idx];
 559         }
 560         default:
 561                 BUG();
 562         }
 563         /* unreachable */
 564         return -1;
 565 }
 566
 567 static int regcache_default_cmp(const void *a, const void *b)
 568 {
 569         const struct reg_default *_a = a;
 570         const struct reg_default *_b = b;
 571
 572         return _a->reg - _b->reg;
 573 }
 574
 575 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
 576 {
 577         struct reg_default key;
 578         struct reg_default *r;
 579
 580         key.reg = reg;
 581         key.def = 0;
 582
 583         r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
 584                     sizeof(struct reg_default), regcache_default_cmp);
 585
 586         if (r)
 587                 return r - map->reg_defaults;
 588         else
 589                 return -ENOENT;
 590 }
 591
 592 static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
 593 {
 594         if (!cache_present)
 595                 return true;
 596
 597         return test_bit(idx, cache_present);
 598 }
 599
 600 static int regcache_sync_block_single(struct regmap *map, void *block,
 601                                       unsigned long *cache_present,
 602                                       unsigned int block_base,
 603                                       unsigned int start, unsigned int end)
 604 {
 605         unsigned int i, regtmp, val;
 606         int ret;
 607
 608         for (i = start; i < end; i++) {
 609                 regtmp = block_base + (i * map->reg_stride);
 610
 611                 if (!regcache_reg_present(cache_present, i) ||
 612                     !regmap_writeable(map, regtmp))
 613                         continue;
 614
 615                 val = regcache_get_val(map, block, i);
 616
 617                 /* Is this the hardware default?  If so skip. */
 618                 ret = regcache_lookup_reg(map, regtmp);
 619                 if (ret >= 0 && val == map->reg_defaults[ret].def)
 620                         continue;
 621
 622                 map->cache_bypass = 1;
 623
 624                 ret = _regmap_write(map, regtmp, val);
 625
 626                 map->cache_bypass = 0;
 627                 if (ret != 0) {
 628                         dev_err(map->dev, "Unable to sync register %#x. %d\n",
 629                                 regtmp, ret);
 630                         return ret;
 631                 }
 632                 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
 633                         regtmp, val);
 634         }
 635
 636         return 0;
 637 }
 638
 639 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
 640                                          unsigned int base, unsigned int cur)
 641 {
 642         size_t val_bytes = map->format.val_bytes;
 643         int ret, count;
 644
 645         if (*data == NULL)
 646                 return 0;
 647
 648         count = (cur - base) / map->reg_stride;
 649
 650         dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
 651                 count * val_bytes, count, base, cur - map->reg_stride);
 652
 653         map->cache_bypass = 1;
 654
 655         ret = _regmap_raw_write(map, base, *data, count * val_bytes);
 656         if (ret)
 657                 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
 658                         base, cur - map->reg_stride, ret);
 659
 660         map->cache_bypass = 0;
 661
 662         *data = NULL;
 663
 664         return ret;
 665 }
 666
 667 static int regcache_sync_block_raw(struct regmap *map, void *block,
 668                             unsigned long *cache_present,
 669                             unsigned int block_base, unsigned int start,
 670                             unsigned int end)
 671 {
 672         unsigned int i, val;
 673         unsigned int regtmp = 0;
 674         unsigned int base = 0;
 675         const void *data = NULL;
 676         int ret;
 677
 678         for (i = start; i < end; i++) {
 679                 regtmp = block_base + (i * map->reg_stride);
 680
 681                 if (!regcache_reg_present(cache_present, i) ||
 682                     !regmap_writeable(map, regtmp)) {
 683                         ret = regcache_sync_block_raw_flush(map, &data,
 684                                                             base, regtmp);
 685                         if (ret != 0)
 686                                 return ret;
 687                         continue;
 688                 }
 689
 690                 val = regcache_get_val(map, block, i);
 691
 692                 /* Is this the hardware default?  If so skip. */
 693                 ret = regcache_lookup_reg(map, regtmp);
 694                 if (ret >= 0 && val == map->reg_defaults[ret].def) {
 695                         ret = regcache_sync_block_raw_flush(map, &data,
 696                                                             base, regtmp);
 697                         if (ret != 0)
 698                                 return ret;
 699                         continue;
 700                 }
 701
 702                 if (!data) {
 703                         data = regcache_get_val_addr(map, block, i);
 704                         base = regtmp;
 705                 }
 706         }
 707
 708         return regcache_sync_block_raw_flush(map, &data, base, regtmp +
 709                         map->reg_stride);
 710 }
 711
 712 int regcache_sync_block(struct regmap *map, void *block,
 713                         unsigned long *cache_present,
 714                         unsigned int block_base, unsigned int start,
 715                         unsigned int end)
 716 {
 717         if (regmap_can_raw_write(map) && !map->use_single_rw)
 718                 return regcache_sync_block_raw(map, block, cache_present,
 719                                                block_base, start, end);
 720         else
 721                 return regcache_sync_block_single(map, block, cache_present,
 722                                                   block_base, start, end);
 723 }