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Bluetooth: hci_uart: Use generic functionality from Broadcom module
[linux/fpc-iii.git] / drivers / dma / ioat / dma_v3.c
blob194ec20c940841c9b0de473ac43417f4235c0482
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
24 *
25 * BSD LICENSE
26 *
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
31 *
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
37 * distribution.
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
53 */
54
55 /*
56 * Support routines for v3+ hardware
57 */
58 #include <linux/module.h>
59 #include <linux/pci.h>
60 #include <linux/gfp.h>
61 #include <linux/dmaengine.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/prefetch.h>
64 #include "../dmaengine.h"
65 #include "registers.h"
66 #include "hw.h"
67 #include "dma.h"
68 #include "dma_v2.h"
69
70 extern struct kmem_cache *ioat3_sed_cache;
71
72 /* ioat hardware assumes at least two sources for raid operations */
73 #define src_cnt_to_sw(x) ((x) + 2)
74 #define src_cnt_to_hw(x) ((x) - 2)
75 #define ndest_to_sw(x) ((x) + 1)
76 #define ndest_to_hw(x) ((x) - 1)
77 #define src16_cnt_to_sw(x) ((x) + 9)
78 #define src16_cnt_to_hw(x) ((x) - 9)
79
80 /* provide a lookup table for setting the source address in the base or
81 * extended descriptor of an xor or pq descriptor
82 */
83 static const u8 xor_idx_to_desc = 0xe0;
84 static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 };
85 static const u8 pq_idx_to_desc = 0xf8;
86 static const u8 pq16_idx_to_desc[] = { 0, 0, 1, 1, 1, 1, 1, 1, 1,
87 2, 2, 2, 2, 2, 2, 2 };
88 static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 };
89 static const u8 pq16_idx_to_field[] = { 1, 4, 1, 2, 3, 4, 5, 6, 7,
90 0, 1, 2, 3, 4, 5, 6 };
91
92 static void ioat3_eh(struct ioat2_dma_chan *ioat);
93
94 static void xor_set_src(struct ioat_raw_descriptor *descs[2],
95 dma_addr_t addr, u32 offset, int idx)
96 {
97 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
98
99 raw->field[xor_idx_to_field[idx]] = addr + offset;
100 }
101
102 static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx)
103 {
104 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
105
106 return raw->field[pq_idx_to_field[idx]];
107 }
108
109 static dma_addr_t pq16_get_src(struct ioat_raw_descriptor *desc[3], int idx)
110 {
111 struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]];
112
113 return raw->field[pq16_idx_to_field[idx]];
114 }
115
116 static void pq_set_src(struct ioat_raw_descriptor *descs[2],
117 dma_addr_t addr, u32 offset, u8 coef, int idx)
118 {
119 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0];
120 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
121
122 raw->field[pq_idx_to_field[idx]] = addr + offset;
123 pq->coef[idx] = coef;
124 }
125
126 static bool is_jf_ioat(struct pci_dev *pdev)
127 {
128 switch (pdev->device) {
129 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
130 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
131 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
132 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
133 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
134 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
135 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
136 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
137 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
138 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
139 return true;
140 default:
141 return false;
142 }
143 }
144
145 static bool is_snb_ioat(struct pci_dev *pdev)
146 {
147 switch (pdev->device) {
148 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
149 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
150 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
151 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
152 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
153 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
154 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
155 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
156 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
157 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
158 return true;
159 default:
160 return false;
161 }
162 }
163
164 static bool is_ivb_ioat(struct pci_dev *pdev)
165 {
166 switch (pdev->device) {
167 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
168 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
169 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
170 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
171 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
172 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
173 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
174 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
175 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
176 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
177 return true;
178 default:
179 return false;
180 }
181
182 }
183
184 static bool is_hsw_ioat(struct pci_dev *pdev)
185 {
186 switch (pdev->device) {
187 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
188 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
189 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
190 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
191 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
192 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
193 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
194 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
195 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
196 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
197 return true;
198 default:
199 return false;
200 }
201
202 }
203
204 static bool is_xeon_cb32(struct pci_dev *pdev)
205 {
206 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
207 is_hsw_ioat(pdev);
208 }
209
210 static bool is_bwd_ioat(struct pci_dev *pdev)
211 {
212 switch (pdev->device) {
213 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
214 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
215 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
216 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
217 /* even though not Atom, BDX-DE has same DMA silicon */
218 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
219 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
220 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
221 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
222 return true;
223 default:
224 return false;
225 }
226 }
227
228 static bool is_bwd_noraid(struct pci_dev *pdev)
229 {
230 switch (pdev->device) {
231 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
232 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
233 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
234 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
235 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
236 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
237 return true;
238 default:
239 return false;
240 }
241
242 }
243
244 static void pq16_set_src(struct ioat_raw_descriptor *desc[3],
245 dma_addr_t addr, u32 offset, u8 coef, unsigned idx)
246 {
247 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *)desc[0];
248 struct ioat_pq16a_descriptor *pq16 =
249 (struct ioat_pq16a_descriptor *)desc[1];
250 struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]];
251
252 raw->field[pq16_idx_to_field[idx]] = addr + offset;
253
254 if (idx < 8)
255 pq->coef[idx] = coef;
256 else
257 pq16->coef[idx - 8] = coef;
258 }
259
260 static struct ioat_sed_ent *
261 ioat3_alloc_sed(struct ioatdma_device *device, unsigned int hw_pool)
262 {
263 struct ioat_sed_ent *sed;
264 gfp_t flags = __GFP_ZERO | GFP_ATOMIC;
265
266 sed = kmem_cache_alloc(ioat3_sed_cache, flags);
267 if (!sed)
268 return NULL;
269
270 sed->hw_pool = hw_pool;
271 sed->hw = dma_pool_alloc(device->sed_hw_pool[hw_pool],
272 flags, &sed->dma);
273 if (!sed->hw) {
274 kmem_cache_free(ioat3_sed_cache, sed);
275 return NULL;
276 }
277
278 return sed;
279 }
280
281 static void ioat3_free_sed(struct ioatdma_device *device, struct ioat_sed_ent *sed)
282 {
283 if (!sed)
284 return;
285
286 dma_pool_free(device->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma);
287 kmem_cache_free(ioat3_sed_cache, sed);
288 }
289
290 static bool desc_has_ext(struct ioat_ring_ent *desc)
291 {
292 struct ioat_dma_descriptor *hw = desc->hw;
293
294 if (hw->ctl_f.op == IOAT_OP_XOR ||
295 hw->ctl_f.op == IOAT_OP_XOR_VAL) {
296 struct ioat_xor_descriptor *xor = desc->xor;
297
298 if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
299 return true;
300 } else if (hw->ctl_f.op == IOAT_OP_PQ ||
301 hw->ctl_f.op == IOAT_OP_PQ_VAL) {
302 struct ioat_pq_descriptor *pq = desc->pq;
303
304 if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
305 return true;
306 }
307
308 return false;
309 }
310
311 static u64 ioat3_get_current_completion(struct ioat_chan_common *chan)
312 {
313 u64 phys_complete;
314 u64 completion;
315
316 completion = *chan->completion;
317 phys_complete = ioat_chansts_to_addr(completion);
318
319 dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
320 (unsigned long long) phys_complete);
321
322 return phys_complete;
323 }
324
325 static bool ioat3_cleanup_preamble(struct ioat_chan_common *chan,
326 u64 *phys_complete)
327 {
328 *phys_complete = ioat3_get_current_completion(chan);
329 if (*phys_complete == chan->last_completion)
330 return false;
331
332 clear_bit(IOAT_COMPLETION_ACK, &chan->state);
333 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
334
335 return true;
336 }
337
338 static void
339 desc_get_errstat(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc)
340 {
341 struct ioat_dma_descriptor *hw = desc->hw;
342
343 switch (hw->ctl_f.op) {
344 case IOAT_OP_PQ_VAL:
345 case IOAT_OP_PQ_VAL_16S:
346 {
347 struct ioat_pq_descriptor *pq = desc->pq;
348
349 /* check if there's error written */
350 if (!pq->dwbes_f.wbes)
351 return;
352
353 /* need to set a chanerr var for checking to clear later */
354
355 if (pq->dwbes_f.p_val_err)
356 *desc->result |= SUM_CHECK_P_RESULT;
357
358 if (pq->dwbes_f.q_val_err)
359 *desc->result |= SUM_CHECK_Q_RESULT;
360
361 return;
362 }
363 default:
364 return;
365 }
366 }
367
368 /**
369 * __cleanup - reclaim used descriptors
370 * @ioat: channel (ring) to clean
371 *
372 * The difference from the dma_v2.c __cleanup() is that this routine
373 * handles extended descriptors and dma-unmapping raid operations.
374 */
375 static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
376 {
377 struct ioat_chan_common *chan = &ioat->base;
378 struct ioatdma_device *device = chan->device;
379 struct ioat_ring_ent *desc;
380 bool seen_current = false;
381 int idx = ioat->tail, i;
382 u16 active;
383
384 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
385 __func__, ioat->head, ioat->tail, ioat->issued);
386
387 /*
388 * At restart of the channel, the completion address and the
389 * channel status will be 0 due to starting a new chain. Since
390 * it's new chain and the first descriptor "fails", there is
391 * nothing to clean up. We do not want to reap the entire submitted
392 * chain due to this 0 address value and then BUG.
393 */
394 if (!phys_complete)
395 return;
396
397 active = ioat2_ring_active(ioat);
398 for (i = 0; i < active && !seen_current; i++) {
399 struct dma_async_tx_descriptor *tx;
400
401 smp_read_barrier_depends();
402 prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
403 desc = ioat2_get_ring_ent(ioat, idx + i);
404 dump_desc_dbg(ioat, desc);
405
406 /* set err stat if we are using dwbes */
407 if (device->cap & IOAT_CAP_DWBES)
408 desc_get_errstat(ioat, desc);
409
410 tx = &desc->txd;
411 if (tx->cookie) {
412 dma_cookie_complete(tx);
413 dma_descriptor_unmap(tx);
414 if (tx->callback) {
415 tx->callback(tx->callback_param);
416 tx->callback = NULL;
417 }
418 }
419
420 if (tx->phys == phys_complete)
421 seen_current = true;
422
423 /* skip extended descriptors */
424 if (desc_has_ext(desc)) {
425 BUG_ON(i + 1 >= active);
426 i++;
427 }
428
429 /* cleanup super extended descriptors */
430 if (desc->sed) {
431 ioat3_free_sed(device, desc->sed);
432 desc->sed = NULL;
433 }
434 }
435 smp_mb(); /* finish all descriptor reads before incrementing tail */
436 ioat->tail = idx + i;
437 BUG_ON(active && !seen_current); /* no active descs have written a completion? */
438 chan->last_completion = phys_complete;
439
440 if (active - i == 0) {
441 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
442 __func__);
443 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
444 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
445 }
446 /* 5 microsecond delay per pending descriptor */
447 writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK),
448 chan->device->reg_base + IOAT_INTRDELAY_OFFSET);
449 }
450
451 static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
452 {
453 struct ioat_chan_common *chan = &ioat->base;
454 u64 phys_complete;
455
456 spin_lock_bh(&chan->cleanup_lock);
457
458 if (ioat3_cleanup_preamble(chan, &phys_complete))
459 __cleanup(ioat, phys_complete);
460
461 if (is_ioat_halted(*chan->completion)) {
462 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
463
464 if (chanerr & IOAT_CHANERR_HANDLE_MASK) {
465 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
466 ioat3_eh(ioat);
467 }
468 }
469
470 spin_unlock_bh(&chan->cleanup_lock);
471 }
472
473 static void ioat3_cleanup_event(unsigned long data)
474 {
475 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
476 struct ioat_chan_common *chan = &ioat->base;
477
478 ioat3_cleanup(ioat);
479 if (!test_bit(IOAT_RUN, &chan->state))
480 return;
481 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
482 }
483
484 static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
485 {
486 struct ioat_chan_common *chan = &ioat->base;
487 u64 phys_complete;
488
489 ioat2_quiesce(chan, 0);
490 if (ioat3_cleanup_preamble(chan, &phys_complete))
491 __cleanup(ioat, phys_complete);
492
493 __ioat2_restart_chan(ioat);
494 }
495
496 static void ioat3_eh(struct ioat2_dma_chan *ioat)
497 {
498 struct ioat_chan_common *chan = &ioat->base;
499 struct pci_dev *pdev = to_pdev(chan);
500 struct ioat_dma_descriptor *hw;
501 struct dma_async_tx_descriptor *tx;
502 u64 phys_complete;
503 struct ioat_ring_ent *desc;
504 u32 err_handled = 0;
505 u32 chanerr_int;
506 u32 chanerr;
507
508 /* cleanup so tail points to descriptor that caused the error */
509 if (ioat3_cleanup_preamble(chan, &phys_complete))
510 __cleanup(ioat, phys_complete);
511
512 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
513 pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int);
514
515 dev_dbg(to_dev(chan), "%s: error = %x:%x\n",
516 __func__, chanerr, chanerr_int);
517
518 desc = ioat2_get_ring_ent(ioat, ioat->tail);
519 hw = desc->hw;
520 dump_desc_dbg(ioat, desc);
521
522 switch (hw->ctl_f.op) {
523 case IOAT_OP_XOR_VAL:
524 if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
525 *desc->result |= SUM_CHECK_P_RESULT;
526 err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
527 }
528 break;
529 case IOAT_OP_PQ_VAL:
530 case IOAT_OP_PQ_VAL_16S:
531 if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
532 *desc->result |= SUM_CHECK_P_RESULT;
533 err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
534 }
535 if (chanerr & IOAT_CHANERR_XOR_Q_ERR) {
536 *desc->result |= SUM_CHECK_Q_RESULT;
537 err_handled |= IOAT_CHANERR_XOR_Q_ERR;
538 }
539 break;
540 }
541
542 /* fault on unhandled error or spurious halt */
543 if (chanerr ^ err_handled || chanerr == 0) {
544 dev_err(to_dev(chan), "%s: fatal error (%x:%x)\n",
545 __func__, chanerr, err_handled);
546 BUG();
547 } else { /* cleanup the faulty descriptor */
548 tx = &desc->txd;
549 if (tx->cookie) {
550 dma_cookie_complete(tx);
551 dma_descriptor_unmap(tx);
552 if (tx->callback) {
553 tx->callback(tx->callback_param);
554 tx->callback = NULL;
555 }
556 }
557 }
558
559 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
560 pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int);
561
562 /* mark faulting descriptor as complete */
563 *chan->completion = desc->txd.phys;
564
565 spin_lock_bh(&ioat->prep_lock);
566 ioat3_restart_channel(ioat);
567 spin_unlock_bh(&ioat->prep_lock);
568 }
569
570 static void check_active(struct ioat2_dma_chan *ioat)
571 {
572 struct ioat_chan_common *chan = &ioat->base;
573
574 if (ioat2_ring_active(ioat)) {
575 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
576 return;
577 }
578
579 if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state))
580 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
581 else if (ioat->alloc_order > ioat_get_alloc_order()) {
582 /* if the ring is idle, empty, and oversized try to step
583 * down the size
584 */
585 reshape_ring(ioat, ioat->alloc_order - 1);
586
587 /* keep shrinking until we get back to our minimum
588 * default size
589 */
590 if (ioat->alloc_order > ioat_get_alloc_order())
591 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
592 }
593
594 }
595
596 static void ioat3_timer_event(unsigned long data)
597 {
598 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
599 struct ioat_chan_common *chan = &ioat->base;
600 dma_addr_t phys_complete;
601 u64 status;
602
603 status = ioat_chansts(chan);
604
605 /* when halted due to errors check for channel
606 * programming errors before advancing the completion state
607 */
608 if (is_ioat_halted(status)) {
609 u32 chanerr;
610
611 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
612 dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
613 __func__, chanerr);
614 if (test_bit(IOAT_RUN, &chan->state))
615 BUG_ON(is_ioat_bug(chanerr));
616 else /* we never got off the ground */
617 return;
618 }
619
620 /* if we haven't made progress and we have already
621 * acknowledged a pending completion once, then be more
622 * forceful with a restart
623 */
624 spin_lock_bh(&chan->cleanup_lock);
625 if (ioat_cleanup_preamble(chan, &phys_complete))
626 __cleanup(ioat, phys_complete);
627 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
628 spin_lock_bh(&ioat->prep_lock);
629 ioat3_restart_channel(ioat);
630 spin_unlock_bh(&ioat->prep_lock);
631 spin_unlock_bh(&chan->cleanup_lock);
632 return;
633 } else {
634 set_bit(IOAT_COMPLETION_ACK, &chan->state);
635 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
636 }
637
638
639 if (ioat2_ring_active(ioat))
640 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
641 else {
642 spin_lock_bh(&ioat->prep_lock);
643 check_active(ioat);
644 spin_unlock_bh(&ioat->prep_lock);
645 }
646 spin_unlock_bh(&chan->cleanup_lock);
647 }
648
649 static enum dma_status
650 ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie,
651 struct dma_tx_state *txstate)
652 {
653 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
654 enum dma_status ret;
655
656 ret = dma_cookie_status(c, cookie, txstate);
657 if (ret == DMA_COMPLETE)
658 return ret;
659
660 ioat3_cleanup(ioat);
661
662 return dma_cookie_status(c, cookie, txstate);
663 }
664
665 static struct dma_async_tx_descriptor *
666 __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
667 dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
668 size_t len, unsigned long flags)
669 {
670 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
671 struct ioat_ring_ent *compl_desc;
672 struct ioat_ring_ent *desc;
673 struct ioat_ring_ent *ext;
674 size_t total_len = len;
675 struct ioat_xor_descriptor *xor;
676 struct ioat_xor_ext_descriptor *xor_ex = NULL;
677 struct ioat_dma_descriptor *hw;
678 int num_descs, with_ext, idx, i;
679 u32 offset = 0;
680 u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
681
682 BUG_ON(src_cnt < 2);
683
684 num_descs = ioat2_xferlen_to_descs(ioat, len);
685 /* we need 2x the number of descriptors to cover greater than 5
686 * sources
687 */
688 if (src_cnt > 5) {
689 with_ext = 1;
690 num_descs *= 2;
691 } else
692 with_ext = 0;
693
694 /* completion writes from the raid engine may pass completion
695 * writes from the legacy engine, so we need one extra null
696 * (legacy) descriptor to ensure all completion writes arrive in
697 * order.
698 */
699 if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0)
700 idx = ioat->head;
701 else
702 return NULL;
703 i = 0;
704 do {
705 struct ioat_raw_descriptor *descs[2];
706 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
707 int s;
708
709 desc = ioat2_get_ring_ent(ioat, idx + i);
710 xor = desc->xor;
711
712 /* save a branch by unconditionally retrieving the
713 * extended descriptor xor_set_src() knows to not write
714 * to it in the single descriptor case
715 */
716 ext = ioat2_get_ring_ent(ioat, idx + i + 1);
717 xor_ex = ext->xor_ex;
718
719 descs[0] = (struct ioat_raw_descriptor *) xor;
720 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
721 for (s = 0; s < src_cnt; s++)
722 xor_set_src(descs, src[s], offset, s);
723 xor->size = xfer_size;
724 xor->dst_addr = dest + offset;
725 xor->ctl = 0;
726 xor->ctl_f.op = op;
727 xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
728
729 len -= xfer_size;
730 offset += xfer_size;
731 dump_desc_dbg(ioat, desc);
732 } while ((i += 1 + with_ext) < num_descs);
733
734 /* last xor descriptor carries the unmap parameters and fence bit */
735 desc->txd.flags = flags;
736 desc->len = total_len;
737 if (result)
738 desc->result = result;
739 xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
740
741 /* completion descriptor carries interrupt bit */
742 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
743 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
744 hw = compl_desc->hw;
745 hw->ctl = 0;
746 hw->ctl_f.null = 1;
747 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
748 hw->ctl_f.compl_write = 1;
749 hw->size = NULL_DESC_BUFFER_SIZE;
750 dump_desc_dbg(ioat, compl_desc);
751
752 /* we leave the channel locked to ensure in order submission */
753 return &compl_desc->txd;
754 }
755
756 static struct dma_async_tx_descriptor *
757 ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
758 unsigned int src_cnt, size_t len, unsigned long flags)
759 {
760 return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
761 }
762
763 static struct dma_async_tx_descriptor *
764 ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
765 unsigned int src_cnt, size_t len,
766 enum sum_check_flags *result, unsigned long flags)
767 {
768 /* the cleanup routine only sets bits on validate failure, it
769 * does not clear bits on validate success... so clear it here
770 */
771 *result = 0;
772
773 return __ioat3_prep_xor_lock(chan, result, src[0], &src[1],
774 src_cnt - 1, len, flags);
775 }
776
777 static void
778 dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext)
779 {
780 struct device *dev = to_dev(&ioat->base);
781 struct ioat_pq_descriptor *pq = desc->pq;
782 struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL;
783 struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex };
784 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
785 int i;
786
787 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
788 " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'"
789 " src_cnt: %d)\n",
790 desc_id(desc), (unsigned long long) desc->txd.phys,
791 (unsigned long long) (pq_ex ? pq_ex->next : pq->next),
792 desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en,
793 pq->ctl_f.compl_write,
794 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
795 pq->ctl_f.src_cnt);
796 for (i = 0; i < src_cnt; i++)
797 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
798 (unsigned long long) pq_get_src(descs, i), pq->coef[i]);
799 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
800 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
801 dev_dbg(dev, "\tNEXT: %#llx\n", pq->next);
802 }
803
804 static void dump_pq16_desc_dbg(struct ioat2_dma_chan *ioat,
805 struct ioat_ring_ent *desc)
806 {
807 struct device *dev = to_dev(&ioat->base);
808 struct ioat_pq_descriptor *pq = desc->pq;
809 struct ioat_raw_descriptor *descs[] = { (void *)pq,
810 (void *)pq,
811 (void *)pq };
812 int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt);
813 int i;
814
815 if (desc->sed) {
816 descs[1] = (void *)desc->sed->hw;
817 descs[2] = (void *)desc->sed->hw + 64;
818 }
819
820 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
821 " sz: %#x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'"
822 " src_cnt: %d)\n",
823 desc_id(desc), (unsigned long long) desc->txd.phys,
824 (unsigned long long) pq->next,
825 desc->txd.flags, pq->size, pq->ctl,
826 pq->ctl_f.op, pq->ctl_f.int_en,
827 pq->ctl_f.compl_write,
828 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
829 pq->ctl_f.src_cnt);
830 for (i = 0; i < src_cnt; i++) {
831 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
832 (unsigned long long) pq16_get_src(descs, i),
833 pq->coef[i]);
834 }
835 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
836 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
837 }
838
839 static struct dma_async_tx_descriptor *
840 __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result,
841 const dma_addr_t *dst, const dma_addr_t *src,
842 unsigned int src_cnt, const unsigned char *scf,
843 size_t len, unsigned long flags)
844 {
845 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
846 struct ioat_chan_common *chan = &ioat->base;
847 struct ioatdma_device *device = chan->device;
848 struct ioat_ring_ent *compl_desc;
849 struct ioat_ring_ent *desc;
850 struct ioat_ring_ent *ext;
851 size_t total_len = len;
852 struct ioat_pq_descriptor *pq;
853 struct ioat_pq_ext_descriptor *pq_ex = NULL;
854 struct ioat_dma_descriptor *hw;
855 u32 offset = 0;
856 u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ;
857 int i, s, idx, with_ext, num_descs;
858 int cb32 = (device->version < IOAT_VER_3_3) ? 1 : 0;
859
860 dev_dbg(to_dev(chan), "%s\n", __func__);
861 /* the engine requires at least two sources (we provide
862 * at least 1 implied source in the DMA_PREP_CONTINUE case)
863 */
864 BUG_ON(src_cnt + dmaf_continue(flags) < 2);
865
866 num_descs = ioat2_xferlen_to_descs(ioat, len);
867 /* we need 2x the number of descriptors to cover greater than 3
868 * sources (we need 1 extra source in the q-only continuation
869 * case and 3 extra sources in the p+q continuation case.
870 */
871 if (src_cnt + dmaf_p_disabled_continue(flags) > 3 ||
872 (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) {
873 with_ext = 1;
874 num_descs *= 2;
875 } else
876 with_ext = 0;
877
878 /* completion writes from the raid engine may pass completion
879 * writes from the legacy engine, so we need one extra null
880 * (legacy) descriptor to ensure all completion writes arrive in
881 * order.
882 */
883 if (likely(num_descs) &&
884 ioat2_check_space_lock(ioat, num_descs + cb32) == 0)
885 idx = ioat->head;
886 else
887 return NULL;
888 i = 0;
889 do {
890 struct ioat_raw_descriptor *descs[2];
891 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
892
893 desc = ioat2_get_ring_ent(ioat, idx + i);
894 pq = desc->pq;
895
896 /* save a branch by unconditionally retrieving the
897 * extended descriptor pq_set_src() knows to not write
898 * to it in the single descriptor case
899 */
900 ext = ioat2_get_ring_ent(ioat, idx + i + with_ext);
901 pq_ex = ext->pq_ex;
902
903 descs[0] = (struct ioat_raw_descriptor *) pq;
904 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
905
906 for (s = 0; s < src_cnt; s++)
907 pq_set_src(descs, src[s], offset, scf[s], s);
908
909 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
910 if (dmaf_p_disabled_continue(flags))
911 pq_set_src(descs, dst[1], offset, 1, s++);
912 else if (dmaf_continue(flags)) {
913 pq_set_src(descs, dst[0], offset, 0, s++);
914 pq_set_src(descs, dst[1], offset, 1, s++);
915 pq_set_src(descs, dst[1], offset, 0, s++);
916 }
917 pq->size = xfer_size;
918 pq->p_addr = dst[0] + offset;
919 pq->q_addr = dst[1] + offset;
920 pq->ctl = 0;
921 pq->ctl_f.op = op;
922 /* we turn on descriptor write back error status */
923 if (device->cap & IOAT_CAP_DWBES)
924 pq->ctl_f.wb_en = result ? 1 : 0;
925 pq->ctl_f.src_cnt = src_cnt_to_hw(s);
926 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
927 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
928
929 len -= xfer_size;
930 offset += xfer_size;
931 } while ((i += 1 + with_ext) < num_descs);
932
933 /* last pq descriptor carries the unmap parameters and fence bit */
934 desc->txd.flags = flags;
935 desc->len = total_len;
936 if (result)
937 desc->result = result;
938 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
939 dump_pq_desc_dbg(ioat, desc, ext);
940
941 if (!cb32) {
942 pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
943 pq->ctl_f.compl_write = 1;
944 compl_desc = desc;
945 } else {
946 /* completion descriptor carries interrupt bit */
947 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
948 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
949 hw = compl_desc->hw;
950 hw->ctl = 0;
951 hw->ctl_f.null = 1;
952 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
953 hw->ctl_f.compl_write = 1;
954 hw->size = NULL_DESC_BUFFER_SIZE;
955 dump_desc_dbg(ioat, compl_desc);
956 }
957
958
959 /* we leave the channel locked to ensure in order submission */
960 return &compl_desc->txd;
961 }
962
963 static struct dma_async_tx_descriptor *
964 __ioat3_prep_pq16_lock(struct dma_chan *c, enum sum_check_flags *result,
965 const dma_addr_t *dst, const dma_addr_t *src,
966 unsigned int src_cnt, const unsigned char *scf,
967 size_t len, unsigned long flags)
968 {
969 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
970 struct ioat_chan_common *chan = &ioat->base;
971 struct ioatdma_device *device = chan->device;
972 struct ioat_ring_ent *desc;
973 size_t total_len = len;
974 struct ioat_pq_descriptor *pq;
975 u32 offset = 0;
976 u8 op;
977 int i, s, idx, num_descs;
978
979 /* this function is only called with 9-16 sources */
980 op = result ? IOAT_OP_PQ_VAL_16S : IOAT_OP_PQ_16S;
981
982 dev_dbg(to_dev(chan), "%s\n", __func__);
983
984 num_descs = ioat2_xferlen_to_descs(ioat, len);
985
986 /*
987 * 16 source pq is only available on cb3.3 and has no completion
988 * write hw bug.
989 */
990 if (num_descs && ioat2_check_space_lock(ioat, num_descs) == 0)
991 idx = ioat->head;
992 else
993 return NULL;
994
995 i = 0;
996
997 do {
998 struct ioat_raw_descriptor *descs[4];
999 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
1000
1001 desc = ioat2_get_ring_ent(ioat, idx + i);
1002 pq = desc->pq;
1003
1004 descs[0] = (struct ioat_raw_descriptor *) pq;
1005
1006 desc->sed = ioat3_alloc_sed(device, (src_cnt-2) >> 3);
1007 if (!desc->sed) {
1008 dev_err(to_dev(chan),
1009 "%s: no free sed entries\n", __func__);
1010 return NULL;
1011 }
1012
1013 pq->sed_addr = desc->sed->dma;
1014 desc->sed->parent = desc;
1015
1016 descs[1] = (struct ioat_raw_descriptor *)desc->sed->hw;
1017 descs[2] = (void *)descs[1] + 64;
1018
1019 for (s = 0; s < src_cnt; s++)
1020 pq16_set_src(descs, src[s], offset, scf[s], s);
1021
1022 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
1023 if (dmaf_p_disabled_continue(flags))
1024 pq16_set_src(descs, dst[1], offset, 1, s++);
1025 else if (dmaf_continue(flags)) {
1026 pq16_set_src(descs, dst[0], offset, 0, s++);
1027 pq16_set_src(descs, dst[1], offset, 1, s++);
1028 pq16_set_src(descs, dst[1], offset, 0, s++);
1029 }
1030
1031 pq->size = xfer_size;
1032 pq->p_addr = dst[0] + offset;
1033 pq->q_addr = dst[1] + offset;
1034 pq->ctl = 0;
1035 pq->ctl_f.op = op;
1036 pq->ctl_f.src_cnt = src16_cnt_to_hw(s);
1037 /* we turn on descriptor write back error status */
1038 if (device->cap & IOAT_CAP_DWBES)
1039 pq->ctl_f.wb_en = result ? 1 : 0;
1040 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
1041 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
1042
1043 len -= xfer_size;
1044 offset += xfer_size;
1045 } while (++i < num_descs);
1046
1047 /* last pq descriptor carries the unmap parameters and fence bit */
1048 desc->txd.flags = flags;
1049 desc->len = total_len;
1050 if (result)
1051 desc->result = result;
1052 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
1053
1054 /* with cb3.3 we should be able to do completion w/o a null desc */
1055 pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
1056 pq->ctl_f.compl_write = 1;
1057
1058 dump_pq16_desc_dbg(ioat, desc);
1059
1060 /* we leave the channel locked to ensure in order submission */
1061 return &desc->txd;
1062 }
1063
1064 static int src_cnt_flags(unsigned int src_cnt, unsigned long flags)
1065 {
1066 if (dmaf_p_disabled_continue(flags))
1067 return src_cnt + 1;
1068 else if (dmaf_continue(flags))
1069 return src_cnt + 3;
1070 else
1071 return src_cnt;
1072 }
1073
1074 static struct dma_async_tx_descriptor *
1075 ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
1076 unsigned int src_cnt, const unsigned char *scf, size_t len,
1077 unsigned long flags)
1078 {
1079 /* specify valid address for disabled result */
1080 if (flags & DMA_PREP_PQ_DISABLE_P)
1081 dst[0] = dst[1];
1082 if (flags & DMA_PREP_PQ_DISABLE_Q)
1083 dst[1] = dst[0];
1084
1085 /* handle the single source multiply case from the raid6
1086 * recovery path
1087 */
1088 if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) {
1089 dma_addr_t single_source[2];
1090 unsigned char single_source_coef[2];
1091
1092 BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q);
1093 single_source[0] = src[0];
1094 single_source[1] = src[0];
1095 single_source_coef[0] = scf[0];
1096 single_source_coef[1] = 0;
1097
1098 return src_cnt_flags(src_cnt, flags) > 8 ?
1099 __ioat3_prep_pq16_lock(chan, NULL, dst, single_source,
1100 2, single_source_coef, len,
1101 flags) :
1102 __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2,
1103 single_source_coef, len, flags);
1104
1105 } else {
1106 return src_cnt_flags(src_cnt, flags) > 8 ?
1107 __ioat3_prep_pq16_lock(chan, NULL, dst, src, src_cnt,
1108 scf, len, flags) :
1109 __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt,
1110 scf, len, flags);
1111 }
1112 }
1113
1114 static struct dma_async_tx_descriptor *
1115 ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
1116 unsigned int src_cnt, const unsigned char *scf, size_t len,
1117 enum sum_check_flags *pqres, unsigned long flags)
1118 {
1119 /* specify valid address for disabled result */
1120 if (flags & DMA_PREP_PQ_DISABLE_P)
1121 pq[0] = pq[1];
1122 if (flags & DMA_PREP_PQ_DISABLE_Q)
1123 pq[1] = pq[0];
1124
1125 /* the cleanup routine only sets bits on validate failure, it
1126 * does not clear bits on validate success... so clear it here
1127 */
1128 *pqres = 0;
1129
1130 return src_cnt_flags(src_cnt, flags) > 8 ?
1131 __ioat3_prep_pq16_lock(chan, pqres, pq, src, src_cnt, scf, len,
1132 flags) :
1133 __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len,
1134 flags);
1135 }
1136
1137 static struct dma_async_tx_descriptor *
1138 ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
1139 unsigned int src_cnt, size_t len, unsigned long flags)
1140 {
1141 unsigned char scf[src_cnt];
1142 dma_addr_t pq[2];
1143
1144 memset(scf, 0, src_cnt);
1145 pq[0] = dst;
1146 flags |= DMA_PREP_PQ_DISABLE_Q;
1147 pq[1] = dst; /* specify valid address for disabled result */
1148
1149 return src_cnt_flags(src_cnt, flags) > 8 ?
1150 __ioat3_prep_pq16_lock(chan, NULL, pq, src, src_cnt, scf, len,
1151 flags) :
1152 __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len,
1153 flags);
1154 }
1155
1156 static struct dma_async_tx_descriptor *
1157 ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
1158 unsigned int src_cnt, size_t len,
1159 enum sum_check_flags *result, unsigned long flags)
1160 {
1161 unsigned char scf[src_cnt];
1162 dma_addr_t pq[2];
1163
1164 /* the cleanup routine only sets bits on validate failure, it
1165 * does not clear bits on validate success... so clear it here
1166 */
1167 *result = 0;
1168
1169 memset(scf, 0, src_cnt);
1170 pq[0] = src[0];
1171 flags |= DMA_PREP_PQ_DISABLE_Q;
1172 pq[1] = pq[0]; /* specify valid address for disabled result */
1173
1174 return src_cnt_flags(src_cnt, flags) > 8 ?
1175 __ioat3_prep_pq16_lock(chan, result, pq, &src[1], src_cnt - 1,
1176 scf, len, flags) :
1177 __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1,
1178 scf, len, flags);
1179 }
1180
1181 static struct dma_async_tx_descriptor *
1182 ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags)
1183 {
1184 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
1185 struct ioat_ring_ent *desc;
1186 struct ioat_dma_descriptor *hw;
1187
1188 if (ioat2_check_space_lock(ioat, 1) == 0)
1189 desc = ioat2_get_ring_ent(ioat, ioat->head);
1190 else
1191 return NULL;
1192
1193 hw = desc->hw;
1194 hw->ctl = 0;
1195 hw->ctl_f.null = 1;
1196 hw->ctl_f.int_en = 1;
1197 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
1198 hw->ctl_f.compl_write = 1;
1199 hw->size = NULL_DESC_BUFFER_SIZE;
1200 hw->src_addr = 0;
1201 hw->dst_addr = 0;
1202
1203 desc->txd.flags = flags;
1204 desc->len = 1;
1205
1206 dump_desc_dbg(ioat, desc);
1207
1208 /* we leave the channel locked to ensure in order submission */
1209 return &desc->txd;
1210 }
1211
1212 static void ioat3_dma_test_callback(void *dma_async_param)
1213 {
1214 struct completion *cmp = dma_async_param;
1215
1216 complete(cmp);
1217 }
1218
1219 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
1220 static int ioat_xor_val_self_test(struct ioatdma_device *device)
1221 {
1222 int i, src_idx;
1223 struct page *dest;
1224 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
1225 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
1226 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
1227 dma_addr_t dest_dma;
1228 struct dma_async_tx_descriptor *tx;
1229 struct dma_chan *dma_chan;
1230 dma_cookie_t cookie;
1231 u8 cmp_byte = 0;
1232 u32 cmp_word;
1233 u32 xor_val_result;
1234 int err = 0;
1235 struct completion cmp;
1236 unsigned long tmo;
1237 struct device *dev = &device->pdev->dev;
1238 struct dma_device *dma = &device->common;
1239 u8 op = 0;
1240
1241 dev_dbg(dev, "%s\n", __func__);
1242
1243 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
1244 return 0;
1245
1246 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
1247 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1248 if (!xor_srcs[src_idx]) {
1249 while (src_idx--)
1250 __free_page(xor_srcs[src_idx]);
1251 return -ENOMEM;
1252 }
1253 }
1254
1255 dest = alloc_page(GFP_KERNEL);
1256 if (!dest) {
1257 while (src_idx--)
1258 __free_page(xor_srcs[src_idx]);
1259 return -ENOMEM;
1260 }
1261
1262 /* Fill in src buffers */
1263 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
1264 u8 *ptr = page_address(xor_srcs[src_idx]);
1265 for (i = 0; i < PAGE_SIZE; i++)
1266 ptr[i] = (1 << src_idx);
1267 }
1268
1269 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
1270 cmp_byte ^= (u8) (1 << src_idx);
1271
1272 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1273 (cmp_byte << 8) | cmp_byte;
1274
1275 memset(page_address(dest), 0, PAGE_SIZE);
1276
1277 dma_chan = container_of(dma->channels.next, struct dma_chan,
1278 device_node);
1279 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
1280 err = -ENODEV;
1281 goto out;
1282 }
1283
1284 /* test xor */
1285 op = IOAT_OP_XOR;
1286
1287 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1288 if (dma_mapping_error(dev, dest_dma))
1289 goto dma_unmap;
1290
1291 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1292 dma_srcs[i] = DMA_ERROR_CODE;
1293 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
1294 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
1295 DMA_TO_DEVICE);
1296 if (dma_mapping_error(dev, dma_srcs[i]))
1297 goto dma_unmap;
1298 }
1299 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1300 IOAT_NUM_SRC_TEST, PAGE_SIZE,
1301 DMA_PREP_INTERRUPT);
1302
1303 if (!tx) {
1304 dev_err(dev, "Self-test xor prep failed\n");
1305 err = -ENODEV;
1306 goto dma_unmap;
1307 }
1308
1309 async_tx_ack(tx);
1310 init_completion(&cmp);
1311 tx->callback = ioat3_dma_test_callback;
1312 tx->callback_param = &cmp;
1313 cookie = tx->tx_submit(tx);
1314 if (cookie < 0) {
1315 dev_err(dev, "Self-test xor setup failed\n");
1316 err = -ENODEV;
1317 goto dma_unmap;
1318 }
1319 dma->device_issue_pending(dma_chan);
1320
1321 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1322
1323 if (tmo == 0 ||
1324 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1325 dev_err(dev, "Self-test xor timed out\n");
1326 err = -ENODEV;
1327 goto dma_unmap;
1328 }
1329
1330 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1331 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1332
1333 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1334 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1335 u32 *ptr = page_address(dest);
1336 if (ptr[i] != cmp_word) {
1337 dev_err(dev, "Self-test xor failed compare\n");
1338 err = -ENODEV;
1339 goto free_resources;
1340 }
1341 }
1342 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1343
1344 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1345
1346 /* skip validate if the capability is not present */
1347 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
1348 goto free_resources;
1349
1350 op = IOAT_OP_XOR_VAL;
1351
1352 /* validate the sources with the destintation page */
1353 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1354 xor_val_srcs[i] = xor_srcs[i];
1355 xor_val_srcs[i] = dest;
1356
1357 xor_val_result = 1;
1358
1359 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1360 dma_srcs[i] = DMA_ERROR_CODE;
1361 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
1362 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
1363 DMA_TO_DEVICE);
1364 if (dma_mapping_error(dev, dma_srcs[i]))
1365 goto dma_unmap;
1366 }
1367 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
1368 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
1369 &xor_val_result, DMA_PREP_INTERRUPT);
1370 if (!tx) {
1371 dev_err(dev, "Self-test zero prep failed\n");
1372 err = -ENODEV;
1373 goto dma_unmap;
1374 }
1375
1376 async_tx_ack(tx);
1377 init_completion(&cmp);
1378 tx->callback = ioat3_dma_test_callback;
1379 tx->callback_param = &cmp;
1380 cookie = tx->tx_submit(tx);
1381 if (cookie < 0) {
1382 dev_err(dev, "Self-test zero setup failed\n");
1383 err = -ENODEV;
1384 goto dma_unmap;
1385 }
1386 dma->device_issue_pending(dma_chan);
1387
1388 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1389
1390 if (tmo == 0 ||
1391 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1392 dev_err(dev, "Self-test validate timed out\n");
1393 err = -ENODEV;
1394 goto dma_unmap;
1395 }
1396
1397 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1398 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1399
1400 if (xor_val_result != 0) {
1401 dev_err(dev, "Self-test validate failed compare\n");
1402 err = -ENODEV;
1403 goto free_resources;
1404 }
1405
1406 memset(page_address(dest), 0, PAGE_SIZE);
1407
1408 /* test for non-zero parity sum */
1409 op = IOAT_OP_XOR_VAL;
1410
1411 xor_val_result = 0;
1412 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1413 dma_srcs[i] = DMA_ERROR_CODE;
1414 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
1415 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
1416 DMA_TO_DEVICE);
1417 if (dma_mapping_error(dev, dma_srcs[i]))
1418 goto dma_unmap;
1419 }
1420 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
1421 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
1422 &xor_val_result, DMA_PREP_INTERRUPT);
1423 if (!tx) {
1424 dev_err(dev, "Self-test 2nd zero prep failed\n");
1425 err = -ENODEV;
1426 goto dma_unmap;
1427 }
1428
1429 async_tx_ack(tx);
1430 init_completion(&cmp);
1431 tx->callback = ioat3_dma_test_callback;
1432 tx->callback_param = &cmp;
1433 cookie = tx->tx_submit(tx);
1434 if (cookie < 0) {
1435 dev_err(dev, "Self-test 2nd zero setup failed\n");
1436 err = -ENODEV;
1437 goto dma_unmap;
1438 }
1439 dma->device_issue_pending(dma_chan);
1440
1441 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1442
1443 if (tmo == 0 ||
1444 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1445 dev_err(dev, "Self-test 2nd validate timed out\n");
1446 err = -ENODEV;
1447 goto dma_unmap;
1448 }
1449
1450 if (xor_val_result != SUM_CHECK_P_RESULT) {
1451 dev_err(dev, "Self-test validate failed compare\n");
1452 err = -ENODEV;
1453 goto dma_unmap;
1454 }
1455
1456 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1457 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1458
1459 goto free_resources;
1460 dma_unmap:
1461 if (op == IOAT_OP_XOR) {
1462 if (dest_dma != DMA_ERROR_CODE)
1463 dma_unmap_page(dev, dest_dma, PAGE_SIZE,
1464 DMA_FROM_DEVICE);
1465 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1466 if (dma_srcs[i] != DMA_ERROR_CODE)
1467 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1468 DMA_TO_DEVICE);
1469 } else if (op == IOAT_OP_XOR_VAL) {
1470 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1471 if (dma_srcs[i] != DMA_ERROR_CODE)
1472 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1473 DMA_TO_DEVICE);
1474 }
1475 free_resources:
1476 dma->device_free_chan_resources(dma_chan);
1477 out:
1478 src_idx = IOAT_NUM_SRC_TEST;
1479 while (src_idx--)
1480 __free_page(xor_srcs[src_idx]);
1481 __free_page(dest);
1482 return err;
1483 }
1484
1485 static int ioat3_dma_self_test(struct ioatdma_device *device)
1486 {
1487 int rc = ioat_dma_self_test(device);
1488
1489 if (rc)
1490 return rc;
1491
1492 rc = ioat_xor_val_self_test(device);
1493 if (rc)
1494 return rc;
1495
1496 return 0;
1497 }
1498
1499 static int ioat3_irq_reinit(struct ioatdma_device *device)
1500 {
1501 struct pci_dev *pdev = device->pdev;
1502 int irq = pdev->irq, i;
1503
1504 if (!is_bwd_ioat(pdev))
1505 return 0;
1506
1507 switch (device->irq_mode) {
1508 case IOAT_MSIX:
1509 for (i = 0; i < device->common.chancnt; i++) {
1510 struct msix_entry *msix = &device->msix_entries[i];
1511 struct ioat_chan_common *chan;
1512
1513 chan = ioat_chan_by_index(device, i);
1514 devm_free_irq(&pdev->dev, msix->vector, chan);
1515 }
1516
1517 pci_disable_msix(pdev);
1518 break;
1519 case IOAT_MSI:
1520 pci_disable_msi(pdev);
1521 /* fall through */
1522 case IOAT_INTX:
1523 devm_free_irq(&pdev->dev, irq, device);
1524 break;
1525 default:
1526 return 0;
1527 }
1528 device->irq_mode = IOAT_NOIRQ;
1529
1530 return ioat_dma_setup_interrupts(device);
1531 }
1532
1533 static int ioat3_reset_hw(struct ioat_chan_common *chan)
1534 {
1535 /* throw away whatever the channel was doing and get it
1536 * initialized, with ioat3 specific workarounds
1537 */
1538 struct ioatdma_device *device = chan->device;
1539 struct pci_dev *pdev = device->pdev;
1540 u32 chanerr;
1541 u16 dev_id;
1542 int err;
1543
1544 ioat2_quiesce(chan, msecs_to_jiffies(100));
1545
1546 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
1547 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
1548
1549 if (device->version < IOAT_VER_3_3) {
1550 /* clear any pending errors */
1551 err = pci_read_config_dword(pdev,
1552 IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
1553 if (err) {
1554 dev_err(&pdev->dev,
1555 "channel error register unreachable\n");
1556 return err;
1557 }
1558 pci_write_config_dword(pdev,
1559 IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
1560
1561 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
1562 * (workaround for spurious config parity error after restart)
1563 */
1564 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
1565 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
1566 pci_write_config_dword(pdev,
1567 IOAT_PCI_DMAUNCERRSTS_OFFSET,
1568 0x10);
1569 }
1570 }
1571
1572 err = ioat2_reset_sync(chan, msecs_to_jiffies(200));
1573 if (!err)
1574 err = ioat3_irq_reinit(device);
1575
1576 if (err)
1577 dev_err(&pdev->dev, "Failed to reset: %d\n", err);
1578
1579 return err;
1580 }
1581
1582 static void ioat3_intr_quirk(struct ioatdma_device *device)
1583 {
1584 struct dma_device *dma;
1585 struct dma_chan *c;
1586 struct ioat_chan_common *chan;
1587 u32 errmask;
1588
1589 dma = &device->common;
1590
1591 /*
1592 * if we have descriptor write back error status, we mask the
1593 * error interrupts
1594 */
1595 if (device->cap & IOAT_CAP_DWBES) {
1596 list_for_each_entry(c, &dma->channels, device_node) {
1597 chan = to_chan_common(c);
1598 errmask = readl(chan->reg_base +
1599 IOAT_CHANERR_MASK_OFFSET);
1600 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1601 IOAT_CHANERR_XOR_Q_ERR;
1602 writel(errmask, chan->reg_base +
1603 IOAT_CHANERR_MASK_OFFSET);
1604 }
1605 }
1606 }
1607
1608 int ioat3_dma_probe(struct ioatdma_device *device, int dca)
1609 {
1610 struct pci_dev *pdev = device->pdev;
1611 int dca_en = system_has_dca_enabled(pdev);
1612 struct dma_device *dma;
1613 struct dma_chan *c;
1614 struct ioat_chan_common *chan;
1615 bool is_raid_device = false;
1616 int err;
1617
1618 device->enumerate_channels = ioat2_enumerate_channels;
1619 device->reset_hw = ioat3_reset_hw;
1620 device->self_test = ioat3_dma_self_test;
1621 device->intr_quirk = ioat3_intr_quirk;
1622 dma = &device->common;
1623 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
1624 dma->device_issue_pending = ioat2_issue_pending;
1625 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
1626 dma->device_free_chan_resources = ioat2_free_chan_resources;
1627
1628 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1629 dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;
1630
1631 device->cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
1632
1633 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1634 device->cap &= ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1635
1636 /* dca is incompatible with raid operations */
1637 if (dca_en && (device->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1638 device->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1639
1640 if (device->cap & IOAT_CAP_XOR) {
1641 is_raid_device = true;
1642 dma->max_xor = 8;
1643
1644 dma_cap_set(DMA_XOR, dma->cap_mask);
1645 dma->device_prep_dma_xor = ioat3_prep_xor;
1646
1647 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1648 dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
1649 }
1650
1651 if (device->cap & IOAT_CAP_PQ) {
1652 is_raid_device = true;
1653
1654 dma->device_prep_dma_pq = ioat3_prep_pq;
1655 dma->device_prep_dma_pq_val = ioat3_prep_pq_val;
1656 dma_cap_set(DMA_PQ, dma->cap_mask);
1657 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1658
1659 if (device->cap & IOAT_CAP_RAID16SS) {
1660 dma_set_maxpq(dma, 16, 0);
1661 } else {
1662 dma_set_maxpq(dma, 8, 0);
1663 }
1664
1665 if (!(device->cap & IOAT_CAP_XOR)) {
1666 dma->device_prep_dma_xor = ioat3_prep_pqxor;
1667 dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val;
1668 dma_cap_set(DMA_XOR, dma->cap_mask);
1669 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1670
1671 if (device->cap & IOAT_CAP_RAID16SS) {
1672 dma->max_xor = 16;
1673 } else {
1674 dma->max_xor = 8;
1675 }
1676 }
1677 }
1678
1679 dma->device_tx_status = ioat3_tx_status;
1680 device->cleanup_fn = ioat3_cleanup_event;
1681 device->timer_fn = ioat3_timer_event;
1682
1683 /* starting with CB3.3 super extended descriptors are supported */
1684 if (device->cap & IOAT_CAP_RAID16SS) {
1685 char pool_name[14];
1686 int i;
1687
1688 for (i = 0; i < MAX_SED_POOLS; i++) {
1689 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1690
1691 /* allocate SED DMA pool */
1692 device->sed_hw_pool[i] = dmam_pool_create(pool_name,
1693 &pdev->dev,
1694 SED_SIZE * (i + 1), 64, 0);
1695 if (!device->sed_hw_pool[i])
1696 return -ENOMEM;
1697
1698 }
1699 }
1700
1701 err = ioat_probe(device);
1702 if (err)
1703 return err;
1704
1705 list_for_each_entry(c, &dma->channels, device_node) {
1706 chan = to_chan_common(c);
1707 writel(IOAT_DMA_DCA_ANY_CPU,
1708 chan->reg_base + IOAT_DCACTRL_OFFSET);
1709 }
1710
1711 err = ioat_register(device);
1712 if (err)
1713 return err;
1714
1715 ioat_kobject_add(device, &ioat2_ktype);
1716
1717 if (dca)
1718 device->dca = ioat3_dca_init(pdev, device->reg_base);
1719
1720 return 0;
1721 }
Linux with added FPC-III support