drivers/dma/ioat/hw.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef _IOAT_HW_H_
  22 #define _IOAT_HW_H_
  23
  24 /* PCI Configuration Space Values */
  25 #define IOAT_MMIO_BAR           0
  26
  27 /* CB device ID's */
  28 #define IOAT_PCI_DID_5000       0x1A38
  29 #define IOAT_PCI_DID_CNB        0x360B
  30 #define IOAT_PCI_DID_SCNB       0x65FF
  31 #define IOAT_PCI_DID_SNB        0x402F
  32
  33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
  34 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
  35 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
  36 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
  37 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
  38 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
  39 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
  40 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
  41 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
  42 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
  43
  44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0   0x2f20
  45 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1   0x2f21
  46 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2   0x2f22
  47 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3   0x2f23
  48 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4   0x2f24
  49 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5   0x2f25
  50 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6   0x2f26
  51 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7   0x2f27
  52 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8   0x2f2e
  53 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9   0x2f2f
  54
  55 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0   0x0C50
  56 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1   0x0C51
  57 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2   0x0C52
  58 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3   0x0C53
  59
  60 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
  61 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
  62 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
  63 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
  64
  65 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  66 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  67 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  68 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
  69 #define IOAT_VER_3_3            0x33    /* Version 3.3 */
  70
  71
  72 int system_has_dca_enabled(struct pci_dev *pdev);
  73
  74 struct ioat_dma_descriptor {
  75         uint32_t        size;
  76         union {
  77                 uint32_t ctl;
  78                 struct {
  79                         unsigned int int_en:1;
  80                         unsigned int src_snoop_dis:1;
  81                         unsigned int dest_snoop_dis:1;
  82                         unsigned int compl_write:1;
  83                         unsigned int fence:1;
  84                         unsigned int null:1;
  85                         unsigned int src_brk:1;
  86                         unsigned int dest_brk:1;
  87                         unsigned int bundle:1;
  88                         unsigned int dest_dca:1;
  89                         unsigned int hint:1;
  90                         unsigned int rsvd2:13;
  91                         #define IOAT_OP_COPY 0x00
  92                         unsigned int op:8;
  93                 } ctl_f;
  94         };
  95         uint64_t        src_addr;
  96         uint64_t        dst_addr;
  97         uint64_t        next;
  98         uint64_t        rsv1;
  99         uint64_t        rsv2;
 100         /* store some driver data in an unused portion of the descriptor */
 101         union {
 102                 uint64_t        user1;
 103                 uint64_t        tx_cnt;
 104         };
 105         uint64_t        user2;
 106 };
 107
 108 struct ioat_xor_descriptor {
 109         uint32_t        size;
 110         union {
 111                 uint32_t ctl;
 112                 struct {
 113                         unsigned int int_en:1;
 114                         unsigned int src_snoop_dis:1;
 115                         unsigned int dest_snoop_dis:1;
 116                         unsigned int compl_write:1;
 117                         unsigned int fence:1;
 118                         unsigned int src_cnt:3;
 119                         unsigned int bundle:1;
 120                         unsigned int dest_dca:1;
 121                         unsigned int hint:1;
 122                         unsigned int rsvd:13;
 123                         #define IOAT_OP_XOR 0x87
 124                         #define IOAT_OP_XOR_VAL 0x88
 125                         unsigned int op:8;
 126                 } ctl_f;
 127         };
 128         uint64_t        src_addr;
 129         uint64_t        dst_addr;
 130         uint64_t        next;
 131         uint64_t        src_addr2;
 132         uint64_t        src_addr3;
 133         uint64_t        src_addr4;
 134         uint64_t        src_addr5;
 135 };
 136
 137 struct ioat_xor_ext_descriptor {
 138         uint64_t        src_addr6;
 139         uint64_t        src_addr7;
 140         uint64_t        src_addr8;
 141         uint64_t        next;
 142         uint64_t        rsvd[4];
 143 };
 144
 145 struct ioat_pq_descriptor {
 146         union {
 147                 uint32_t        size;
 148                 uint32_t        dwbes;
 149                 struct {
 150                         unsigned int rsvd:25;
 151                         unsigned int p_val_err:1;
 152                         unsigned int q_val_err:1;
 153                         unsigned int rsvd1:4;
 154                         unsigned int wbes:1;
 155                 } dwbes_f;
 156         };
 157         union {
 158                 uint32_t ctl;
 159                 struct {
 160                         unsigned int int_en:1;
 161                         unsigned int src_snoop_dis:1;
 162                         unsigned int dest_snoop_dis:1;
 163                         unsigned int compl_write:1;
 164                         unsigned int fence:1;
 165                         unsigned int src_cnt:3;
 166                         unsigned int bundle:1;
 167                         unsigned int dest_dca:1;
 168                         unsigned int hint:1;
 169                         unsigned int p_disable:1;
 170                         unsigned int q_disable:1;
 171                         unsigned int rsvd2:2;
 172                         unsigned int wb_en:1;
 173                         unsigned int prl_en:1;
 174                         unsigned int rsvd3:7;
 175                         #define IOAT_OP_PQ 0x89
 176                         #define IOAT_OP_PQ_VAL 0x8a
 177                         #define IOAT_OP_PQ_16S 0xa0
 178                         #define IOAT_OP_PQ_VAL_16S 0xa1
 179                         unsigned int op:8;
 180                 } ctl_f;
 181         };
 182         uint64_t        src_addr;
 183         uint64_t        p_addr;
 184         uint64_t        next;
 185         uint64_t        src_addr2;
 186         union {
 187                 uint64_t        src_addr3;
 188                 uint64_t        sed_addr;
 189         };
 190         uint8_t         coef[8];
 191         uint64_t        q_addr;
 192 };
 193
 194 struct ioat_pq_ext_descriptor {
 195         uint64_t        src_addr4;
 196         uint64_t        src_addr5;
 197         uint64_t        src_addr6;
 198         uint64_t        next;
 199         uint64_t        src_addr7;
 200         uint64_t        src_addr8;
 201         uint64_t        rsvd[2];
 202 };
 203
 204 struct ioat_pq_update_descriptor {
 205         uint32_t        size;
 206         union {
 207                 uint32_t ctl;
 208                 struct {
 209                         unsigned int int_en:1;
 210                         unsigned int src_snoop_dis:1;
 211                         unsigned int dest_snoop_dis:1;
 212                         unsigned int compl_write:1;
 213                         unsigned int fence:1;
 214                         unsigned int src_cnt:3;
 215                         unsigned int bundle:1;
 216                         unsigned int dest_dca:1;
 217                         unsigned int hint:1;
 218                         unsigned int p_disable:1;
 219                         unsigned int q_disable:1;
 220                         unsigned int rsvd:3;
 221                         unsigned int coef:8;
 222                         #define IOAT_OP_PQ_UP 0x8b
 223                         unsigned int op:8;
 224                 } ctl_f;
 225         };
 226         uint64_t        src_addr;
 227         uint64_t        p_addr;
 228         uint64_t        next;
 229         uint64_t        src_addr2;
 230         uint64_t        p_src;
 231         uint64_t        q_src;
 232         uint64_t        q_addr;
 233 };
 234
 235 struct ioat_raw_descriptor {
 236         uint64_t        field[8];
 237 };
 238
 239 struct ioat_pq16a_descriptor {
 240         uint8_t coef[8];
 241         uint64_t src_addr3;
 242         uint64_t src_addr4;
 243         uint64_t src_addr5;
 244         uint64_t src_addr6;
 245         uint64_t src_addr7;
 246         uint64_t src_addr8;
 247         uint64_t src_addr9;
 248 };
 249
 250 struct ioat_pq16b_descriptor {
 251         uint64_t src_addr10;
 252         uint64_t src_addr11;
 253         uint64_t src_addr12;
 254         uint64_t src_addr13;
 255         uint64_t src_addr14;
 256         uint64_t src_addr15;
 257         uint64_t src_addr16;
 258         uint64_t rsvd;
 259 };
 260
 261 union ioat_sed_pq_descriptor {
 262         struct ioat_pq16a_descriptor a;
 263         struct ioat_pq16b_descriptor b;
 264 };
 265
 266 #define SED_SIZE        64
 267
 268 struct ioat_sed_raw_descriptor {
 269         uint64_t        a[8];
 270         uint64_t        b[8];
 271         uint64_t        c[8];
 272 };
 273
 274 #endif