drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

   1 /*
   2 * Copyright (C) 2012 Invensense, Inc.
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 #include <linux/i2c.h>
  14 #include <linux/kfifo.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/iio/iio.h>
  17 #include <linux/iio/buffer.h>
  18 #include <linux/iio/sysfs.h>
  19 #include <linux/iio/kfifo_buf.h>
  20 #include <linux/iio/trigger.h>
  21 #include <linux/iio/triggered_buffer.h>
  22 #include <linux/iio/trigger_consumer.h>
  23 #include <linux/platform_data/invensense_mpu6050.h>
  24
  25 /**
  26  *  struct inv_mpu6050_reg_map - Notable registers.
  27  *  @sample_rate_div:   Divider applied to gyro output rate.
  28  *  @lpf:               Configures internal low pass filter.
  29  *  @user_ctrl:         Enables/resets the FIFO.
  30  *  @fifo_en:           Determines which data will appear in FIFO.
  31  *  @gyro_config:       gyro config register.
  32  *  @accl_config:       accel config register
  33  *  @fifo_count_h:      Upper byte of FIFO count.
  34  *  @fifo_r_w:          FIFO register.
  35  *  @raw_gyro:          Address of first gyro register.
  36  *  @raw_accl:          Address of first accel register.
  37  *  @temperature:       temperature register
  38  *  @int_enable:        Interrupt enable register.
  39  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  40  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  41  */
  42 struct inv_mpu6050_reg_map {
  43         u8 sample_rate_div;
  44         u8 lpf;
  45         u8 user_ctrl;
  46         u8 fifo_en;
  47         u8 gyro_config;
  48         u8 accl_config;
  49         u8 fifo_count_h;
  50         u8 fifo_r_w;
  51         u8 raw_gyro;
  52         u8 raw_accl;
  53         u8 temperature;
  54         u8 int_enable;
  55         u8 pwr_mgmt_1;
  56         u8 pwr_mgmt_2;
  57         u8 int_pin_cfg;
  58 };
  59
  60 /*device enum */
  61 enum inv_devices {
  62         INV_MPU6050,
  63         INV_MPU6500,
  64         INV_NUM_PARTS
  65 };
  66
  67 /**
  68  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  69  *  @fsr:               Full scale range.
  70  *  @lpf:               Digital low pass filter frequency.
  71  *  @accl_fs:           accel full scale range.
  72  *  @enable:            master enable state.
  73  *  @accl_fifo_enable:  enable accel data output
  74  *  @gyro_fifo_enable:  enable gyro data output
  75  *  @fifo_rate:         FIFO update rate.
  76  */
  77 struct inv_mpu6050_chip_config {
  78         unsigned int fsr:2;
  79         unsigned int lpf:3;
  80         unsigned int accl_fs:2;
  81         unsigned int enable:1;
  82         unsigned int accl_fifo_enable:1;
  83         unsigned int gyro_fifo_enable:1;
  84         u16 fifo_rate;
  85 };
  86
  87 /**
  88  *  struct inv_mpu6050_hw - Other important hardware information.
  89  *  @num_reg:   Number of registers on device.
  90  *  @name:      name of the chip.
  91  *  @reg:   register map of the chip.
  92  *  @config:    configuration of the chip.
  93  */
  94 struct inv_mpu6050_hw {
  95         u8 num_reg;
  96         u8 *name;
  97         const struct inv_mpu6050_reg_map *reg;
  98         const struct inv_mpu6050_chip_config *config;
  99 };
 100
 101 /*
 102  *  struct inv_mpu6050_state - Driver state variables.
 103  *  @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
 104  *  @trig:              IIO trigger.
 105  *  @chip_config:       Cached attribute information.
 106  *  @reg:               Map of important registers.
 107  *  @hw:                Other hardware-specific information.
 108  *  @chip_type:         chip type.
 109  *  @time_stamp_lock:   spin lock to time stamp.
 110  *  @client:            i2c client handle.
 111  *  @plat_data:         platform data.
 112  *  @timestamps:        kfifo queue to store time stamp.
 113  */
 114 struct inv_mpu6050_state {
 115 #define TIMESTAMP_FIFO_SIZE 16
 116         struct iio_trigger  *trig;
 117         struct inv_mpu6050_chip_config chip_config;
 118         const struct inv_mpu6050_reg_map *reg;
 119         const struct inv_mpu6050_hw *hw;
 120         enum   inv_devices chip_type;
 121         spinlock_t time_stamp_lock;
 122         struct i2c_client *client;
 123         struct i2c_adapter *mux_adapter;
 124         unsigned int powerup_count;
 125         struct inv_mpu6050_platform_data plat_data;
 126         DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
 127 };
 128
 129 /*register and associated bit definition*/
 130 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 131 #define INV_MPU6050_REG_CONFIG              0x1A
 132 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 133 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 134
 135 #define INV_MPU6050_REG_FIFO_EN             0x23
 136 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 137 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 138
 139 #define INV_MPU6050_REG_INT_ENABLE          0x38
 140 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 141 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 142
 143 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 144 #define INV_MPU6050_REG_TEMPERATURE         0x41
 145 #define INV_MPU6050_REG_RAW_GYRO            0x43
 146
 147 #define INV_MPU6050_REG_USER_CTRL           0x6A
 148 #define INV_MPU6050_BIT_FIFO_RST            0x04
 149 #define INV_MPU6050_BIT_DMP_RST             0x08
 150 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 151 #define INV_MPU6050_BIT_FIFO_EN             0x40
 152 #define INV_MPU6050_BIT_DMP_EN              0x80
 153
 154 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 155 #define INV_MPU6050_BIT_H_RESET             0x80
 156 #define INV_MPU6050_BIT_SLEEP               0x40
 157 #define INV_MPU6050_BIT_CLK_MASK            0x7
 158
 159 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 160 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 161 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 162
 163 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 164 #define INV_MPU6050_REG_FIFO_R_W            0x74
 165
 166 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 167 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 168 #define INV_MPU6050_FIFO_THRESHOLD           500
 169 #define INV_MPU6050_POWER_UP_TIME            100
 170 #define INV_MPU6050_TEMP_UP_TIME             100
 171 #define INV_MPU6050_SENSOR_UP_TIME           30
 172 #define INV_MPU6050_REG_UP_TIME              5
 173
 174 #define INV_MPU6050_TEMP_OFFSET              12421
 175 #define INV_MPU6050_TEMP_SCALE               2941
 176 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 177 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 178 #define INV_MPU6050_THREE_AXIS               3
 179 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 180 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 181
 182 /* 6 + 6 round up and plus 8 */
 183 #define INV_MPU6050_OUTPUT_DATA_SIZE         24
 184
 185 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 186 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 187
 188 /* init parameters */
 189 #define INV_MPU6050_INIT_FIFO_RATE           50
 190 #define INV_MPU6050_TIME_STAMP_TOR           5
 191 #define INV_MPU6050_MAX_FIFO_RATE            1000
 192 #define INV_MPU6050_MIN_FIFO_RATE            4
 193 #define INV_MPU6050_ONE_K_HZ                 1000
 194
 195 /* scan element definition */
 196 enum inv_mpu6050_scan {
 197         INV_MPU6050_SCAN_ACCL_X,
 198         INV_MPU6050_SCAN_ACCL_Y,
 199         INV_MPU6050_SCAN_ACCL_Z,
 200         INV_MPU6050_SCAN_GYRO_X,
 201         INV_MPU6050_SCAN_GYRO_Y,
 202         INV_MPU6050_SCAN_GYRO_Z,
 203         INV_MPU6050_SCAN_TIMESTAMP,
 204 };
 205
 206 enum inv_mpu6050_filter_e {
 207         INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 208         INV_MPU6050_FILTER_188HZ,
 209         INV_MPU6050_FILTER_98HZ,
 210         INV_MPU6050_FILTER_42HZ,
 211         INV_MPU6050_FILTER_20HZ,
 212         INV_MPU6050_FILTER_10HZ,
 213         INV_MPU6050_FILTER_5HZ,
 214         INV_MPU6050_FILTER_2100HZ_NOLPF,
 215         NUM_MPU6050_FILTER
 216 };
 217
 218 /* IIO attribute address */
 219 enum INV_MPU6050_IIO_ATTR_ADDR {
 220         ATTR_GYRO_MATRIX,
 221         ATTR_ACCL_MATRIX,
 222 };
 223
 224 enum inv_mpu6050_accl_fs_e {
 225         INV_MPU6050_FS_02G = 0,
 226         INV_MPU6050_FS_04G,
 227         INV_MPU6050_FS_08G,
 228         INV_MPU6050_FS_16G,
 229         NUM_ACCL_FSR
 230 };
 231
 232 enum inv_mpu6050_fsr_e {
 233         INV_MPU6050_FSR_250DPS = 0,
 234         INV_MPU6050_FSR_500DPS,
 235         INV_MPU6050_FSR_1000DPS,
 236         INV_MPU6050_FSR_2000DPS,
 237         NUM_MPU6050_FSR
 238 };
 239
 240 enum inv_mpu6050_clock_sel_e {
 241         INV_CLK_INTERNAL = 0,
 242         INV_CLK_PLL,
 243         NUM_CLK
 244 };
 245
 246 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
 247 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 248 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
 249 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
 250 int inv_reset_fifo(struct iio_dev *indio_dev);
 251 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 252 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 253 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);