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Bluetooth: hci_uart: Use generic functionality from Broadcom module
[linux/fpc-iii.git] / drivers / iommu / intel_irq_remapping.c
blob14de1ab223c864c00a866ebbba6d68d3fc50cb6c
1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
7 #include <linux/pci.h>
8 #include <linux/irq.h>
9 #include <linux/intel-iommu.h>
10 #include <linux/acpi.h>
11 #include <asm/io_apic.h>
12 #include <asm/smp.h>
13 #include <asm/cpu.h>
14 #include <asm/irq_remapping.h>
15 #include <asm/pci-direct.h>
16 #include <asm/msidef.h>
17
18 #include "irq_remapping.h"
19
20 struct ioapic_scope {
21 struct intel_iommu *iommu;
22 unsigned int id;
23 unsigned int bus; /* PCI bus number */
24 unsigned int devfn; /* PCI devfn number */
25 };
26
27 struct hpet_scope {
28 struct intel_iommu *iommu;
29 u8 id;
30 unsigned int bus;
31 unsigned int devfn;
32 };
33
34 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
35 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
36
37 static int __read_mostly eim_mode;
38 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
39 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
40
41 /*
42 * Lock ordering:
43 * ->dmar_global_lock
44 * ->irq_2_ir_lock
45 * ->qi->q_lock
46 * ->iommu->register_lock
47 * Note:
48 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
49 * in single-threaded environment with interrupt disabled, so no need to tabke
50 * the dmar_global_lock.
51 */
52 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
53
54 static int __init parse_ioapics_under_ir(void);
55
56 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
57 {
58 struct irq_cfg *cfg = irq_cfg(irq);
59 return cfg ? &cfg->irq_2_iommu : NULL;
60 }
61
62 static int get_irte(int irq, struct irte *entry)
63 {
64 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
65 unsigned long flags;
66 int index;
67
68 if (!entry || !irq_iommu)
69 return -1;
70
71 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
72
73 if (unlikely(!irq_iommu->iommu)) {
74 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
75 return -1;
76 }
77
78 index = irq_iommu->irte_index + irq_iommu->sub_handle;
79 *entry = *(irq_iommu->iommu->ir_table->base + index);
80
81 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
82 return 0;
83 }
84
85 static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
86 {
87 struct ir_table *table = iommu->ir_table;
88 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
89 struct irq_cfg *cfg = irq_cfg(irq);
90 unsigned int mask = 0;
91 unsigned long flags;
92 int index;
93
94 if (!count || !irq_iommu)
95 return -1;
96
97 if (count > 1) {
98 count = __roundup_pow_of_two(count);
99 mask = ilog2(count);
100 }
101
102 if (mask > ecap_max_handle_mask(iommu->ecap)) {
103 printk(KERN_ERR
104 "Requested mask %x exceeds the max invalidation handle"
105 " mask value %Lx\n", mask,
106 ecap_max_handle_mask(iommu->ecap));
107 return -1;
108 }
109
110 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
111 index = bitmap_find_free_region(table->bitmap,
112 INTR_REMAP_TABLE_ENTRIES, mask);
113 if (index < 0) {
114 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
115 } else {
116 cfg->remapped = 1;
117 irq_iommu->iommu = iommu;
118 irq_iommu->irte_index = index;
119 irq_iommu->sub_handle = 0;
120 irq_iommu->irte_mask = mask;
121 }
122 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
123
124 return index;
125 }
126
127 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
128 {
129 struct qi_desc desc;
130
131 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
132 | QI_IEC_SELECTIVE;
133 desc.high = 0;
134
135 return qi_submit_sync(&desc, iommu);
136 }
137
138 static int map_irq_to_irte_handle(int irq, u16 *sub_handle)
139 {
140 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
141 unsigned long flags;
142 int index;
143
144 if (!irq_iommu)
145 return -1;
146
147 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
148 *sub_handle = irq_iommu->sub_handle;
149 index = irq_iommu->irte_index;
150 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
151 return index;
152 }
153
154 static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
155 {
156 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
157 struct irq_cfg *cfg = irq_cfg(irq);
158 unsigned long flags;
159
160 if (!irq_iommu)
161 return -1;
162
163 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
164
165 cfg->remapped = 1;
166 irq_iommu->iommu = iommu;
167 irq_iommu->irte_index = index;
168 irq_iommu->sub_handle = subhandle;
169 irq_iommu->irte_mask = 0;
170
171 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
172
173 return 0;
174 }
175
176 static int modify_irte(int irq, struct irte *irte_modified)
177 {
178 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
179 struct intel_iommu *iommu;
180 unsigned long flags;
181 struct irte *irte;
182 int rc, index;
183
184 if (!irq_iommu)
185 return -1;
186
187 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
188
189 iommu = irq_iommu->iommu;
190
191 index = irq_iommu->irte_index + irq_iommu->sub_handle;
192 irte = &iommu->ir_table->base[index];
193
194 set_64bit(&irte->low, irte_modified->low);
195 set_64bit(&irte->high, irte_modified->high);
196 __iommu_flush_cache(iommu, irte, sizeof(*irte));
197
198 rc = qi_flush_iec(iommu, index, 0);
199 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
200
201 return rc;
202 }
203
204 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
205 {
206 int i;
207
208 for (i = 0; i < MAX_HPET_TBS; i++)
209 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
210 return ir_hpet[i].iommu;
211 return NULL;
212 }
213
214 static struct intel_iommu *map_ioapic_to_ir(int apic)
215 {
216 int i;
217
218 for (i = 0; i < MAX_IO_APICS; i++)
219 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
220 return ir_ioapic[i].iommu;
221 return NULL;
222 }
223
224 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
225 {
226 struct dmar_drhd_unit *drhd;
227
228 drhd = dmar_find_matched_drhd_unit(dev);
229 if (!drhd)
230 return NULL;
231
232 return drhd->iommu;
233 }
234
235 static int clear_entries(struct irq_2_iommu *irq_iommu)
236 {
237 struct irte *start, *entry, *end;
238 struct intel_iommu *iommu;
239 int index;
240
241 if (irq_iommu->sub_handle)
242 return 0;
243
244 iommu = irq_iommu->iommu;
245 index = irq_iommu->irte_index + irq_iommu->sub_handle;
246
247 start = iommu->ir_table->base + index;
248 end = start + (1 << irq_iommu->irte_mask);
249
250 for (entry = start; entry < end; entry++) {
251 set_64bit(&entry->low, 0);
252 set_64bit(&entry->high, 0);
253 }
254 bitmap_release_region(iommu->ir_table->bitmap, index,
255 irq_iommu->irte_mask);
256
257 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
258 }
259
260 static int free_irte(int irq)
261 {
262 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
263 unsigned long flags;
264 int rc;
265
266 if (!irq_iommu)
267 return -1;
268
269 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
270
271 rc = clear_entries(irq_iommu);
272
273 irq_iommu->iommu = NULL;
274 irq_iommu->irte_index = 0;
275 irq_iommu->sub_handle = 0;
276 irq_iommu->irte_mask = 0;
277
278 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
279
280 return rc;
281 }
282
283 /*
284 * source validation type
285 */
286 #define SVT_NO_VERIFY 0x0 /* no verification is required */
287 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
288 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
289
290 /*
291 * source-id qualifier
292 */
293 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
294 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
295 * the third least significant bit
296 */
297 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
298 * the second and third least significant bits
299 */
300 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
301 * the least three significant bits
302 */
303
304 /*
305 * set SVT, SQ and SID fields of irte to verify
306 * source ids of interrupt requests
307 */
308 static void set_irte_sid(struct irte *irte, unsigned int svt,
309 unsigned int sq, unsigned int sid)
310 {
311 if (disable_sourceid_checking)
312 svt = SVT_NO_VERIFY;
313 irte->svt = svt;
314 irte->sq = sq;
315 irte->sid = sid;
316 }
317
318 static int set_ioapic_sid(struct irte *irte, int apic)
319 {
320 int i;
321 u16 sid = 0;
322
323 if (!irte)
324 return -1;
325
326 down_read(&dmar_global_lock);
327 for (i = 0; i < MAX_IO_APICS; i++) {
328 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
329 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
330 break;
331 }
332 }
333 up_read(&dmar_global_lock);
334
335 if (sid == 0) {
336 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
337 return -1;
338 }
339
340 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
341
342 return 0;
343 }
344
345 static int set_hpet_sid(struct irte *irte, u8 id)
346 {
347 int i;
348 u16 sid = 0;
349
350 if (!irte)
351 return -1;
352
353 down_read(&dmar_global_lock);
354 for (i = 0; i < MAX_HPET_TBS; i++) {
355 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
356 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
357 break;
358 }
359 }
360 up_read(&dmar_global_lock);
361
362 if (sid == 0) {
363 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
364 return -1;
365 }
366
367 /*
368 * Should really use SQ_ALL_16. Some platforms are broken.
369 * While we figure out the right quirks for these broken platforms, use
370 * SQ_13_IGNORE_3 for now.
371 */
372 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
373
374 return 0;
375 }
376
377 struct set_msi_sid_data {
378 struct pci_dev *pdev;
379 u16 alias;
380 };
381
382 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
383 {
384 struct set_msi_sid_data *data = opaque;
385
386 data->pdev = pdev;
387 data->alias = alias;
388
389 return 0;
390 }
391
392 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
393 {
394 struct set_msi_sid_data data;
395
396 if (!irte || !dev)
397 return -1;
398
399 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
400
401 /*
402 * DMA alias provides us with a PCI device and alias. The only case
403 * where the it will return an alias on a different bus than the
404 * device is the case of a PCIe-to-PCI bridge, where the alias is for
405 * the subordinate bus. In this case we can only verify the bus.
406 *
407 * If the alias device is on a different bus than our source device
408 * then we have a topology based alias, use it.
409 *
410 * Otherwise, the alias is for a device DMA quirk and we cannot
411 * assume that MSI uses the same requester ID. Therefore use the
412 * original device.
413 */
414 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
415 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
416 PCI_DEVID(PCI_BUS_NUM(data.alias),
417 dev->bus->number));
418 else if (data.pdev->bus->number != dev->bus->number)
419 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
420 else
421 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
422 PCI_DEVID(dev->bus->number, dev->devfn));
423
424 return 0;
425 }
426
427 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
428 {
429 u64 addr;
430 u32 sts;
431 unsigned long flags;
432
433 addr = virt_to_phys((void *)iommu->ir_table->base);
434
435 raw_spin_lock_irqsave(&iommu->register_lock, flags);
436
437 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
438 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
439
440 /* Set interrupt-remapping table pointer */
441 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
442
443 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
444 readl, (sts & DMA_GSTS_IRTPS), sts);
445 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
446
447 /*
448 * global invalidation of interrupt entry cache before enabling
449 * interrupt-remapping.
450 */
451 qi_global_iec(iommu);
452
453 raw_spin_lock_irqsave(&iommu->register_lock, flags);
454
455 /* Enable interrupt-remapping */
456 iommu->gcmd |= DMA_GCMD_IRE;
457 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
458 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
459
460 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
461 readl, (sts & DMA_GSTS_IRES), sts);
462
463 /*
464 * With CFI clear in the Global Command register, we should be
465 * protected from dangerous (i.e. compatibility) interrupts
466 * regardless of x2apic status. Check just to be sure.
467 */
468 if (sts & DMA_GSTS_CFIS)
469 WARN(1, KERN_WARNING
470 "Compatibility-format IRQs enabled despite intr remapping;\n"
471 "you are vulnerable to IRQ injection.\n");
472
473 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
474 }
475
476 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
477 {
478 struct ir_table *ir_table;
479 struct page *pages;
480 unsigned long *bitmap;
481
482 if (iommu->ir_table)
483 return 0;
484
485 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
486 if (!ir_table)
487 return -ENOMEM;
488
489 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
490 INTR_REMAP_PAGE_ORDER);
491
492 if (!pages) {
493 pr_err("IR%d: failed to allocate pages of order %d\n",
494 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
495 goto out_free_table;
496 }
497
498 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
499 sizeof(long), GFP_ATOMIC);
500 if (bitmap == NULL) {
501 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
502 goto out_free_pages;
503 }
504
505 ir_table->base = page_address(pages);
506 ir_table->bitmap = bitmap;
507 iommu->ir_table = ir_table;
508 return 0;
509
510 out_free_pages:
511 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
512 out_free_table:
513 kfree(ir_table);
514 return -ENOMEM;
515 }
516
517 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
518 {
519 if (iommu && iommu->ir_table) {
520 free_pages((unsigned long)iommu->ir_table->base,
521 INTR_REMAP_PAGE_ORDER);
522 kfree(iommu->ir_table->bitmap);
523 kfree(iommu->ir_table);
524 iommu->ir_table = NULL;
525 }
526 }
527
528 /*
529 * Disable Interrupt Remapping.
530 */
531 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
532 {
533 unsigned long flags;
534 u32 sts;
535
536 if (!ecap_ir_support(iommu->ecap))
537 return;
538
539 /*
540 * global invalidation of interrupt entry cache before disabling
541 * interrupt-remapping.
542 */
543 qi_global_iec(iommu);
544
545 raw_spin_lock_irqsave(&iommu->register_lock, flags);
546
547 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
548 if (!(sts & DMA_GSTS_IRES))
549 goto end;
550
551 iommu->gcmd &= ~DMA_GCMD_IRE;
552 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
553
554 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
555 readl, !(sts & DMA_GSTS_IRES), sts);
556
557 end:
558 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
559 }
560
561 static int __init dmar_x2apic_optout(void)
562 {
563 struct acpi_table_dmar *dmar;
564 dmar = (struct acpi_table_dmar *)dmar_tbl;
565 if (!dmar || no_x2apic_optout)
566 return 0;
567 return dmar->flags & DMAR_X2APIC_OPT_OUT;
568 }
569
570 static void __init intel_cleanup_irq_remapping(void)
571 {
572 struct dmar_drhd_unit *drhd;
573 struct intel_iommu *iommu;
574
575 for_each_iommu(iommu, drhd) {
576 if (ecap_ir_support(iommu->ecap)) {
577 iommu_disable_irq_remapping(iommu);
578 intel_teardown_irq_remapping(iommu);
579 }
580 }
581
582 if (x2apic_supported())
583 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
584 }
585
586 static int __init intel_prepare_irq_remapping(void)
587 {
588 struct dmar_drhd_unit *drhd;
589 struct intel_iommu *iommu;
590
591 if (irq_remap_broken) {
592 printk(KERN_WARNING
593 "This system BIOS has enabled interrupt remapping\n"
594 "on a chipset that contains an erratum making that\n"
595 "feature unstable. To maintain system stability\n"
596 "interrupt remapping is being disabled. Please\n"
597 "contact your BIOS vendor for an update\n");
598 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
599 return -ENODEV;
600 }
601
602 if (dmar_table_init() < 0)
603 return -ENODEV;
604
605 if (!dmar_ir_support())
606 return -ENODEV;
607
608 if (parse_ioapics_under_ir() != 1) {
609 printk(KERN_INFO "Not enabling interrupt remapping\n");
610 goto error;
611 }
612
613 /* First make sure all IOMMUs support IRQ remapping */
614 for_each_iommu(iommu, drhd)
615 if (!ecap_ir_support(iommu->ecap))
616 goto error;
617
618 /* Do the allocations early */
619 for_each_iommu(iommu, drhd)
620 if (intel_setup_irq_remapping(iommu))
621 goto error;
622
623 return 0;
624
625 error:
626 intel_cleanup_irq_remapping();
627 return -ENODEV;
628 }
629
630 static int __init intel_enable_irq_remapping(void)
631 {
632 struct dmar_drhd_unit *drhd;
633 struct intel_iommu *iommu;
634 int setup = 0;
635 int eim = 0;
636
637 if (x2apic_supported()) {
638 eim = !dmar_x2apic_optout();
639 if (!eim)
640 printk(KERN_WARNING
641 "Your BIOS is broken and requested that x2apic be disabled.\n"
642 "This will slightly decrease performance.\n"
643 "Use 'intremap=no_x2apic_optout' to override BIOS request.\n");
644 }
645
646 for_each_iommu(iommu, drhd) {
647 /*
648 * If the queued invalidation is already initialized,
649 * shouldn't disable it.
650 */
651 if (iommu->qi)
652 continue;
653
654 /*
655 * Clear previous faults.
656 */
657 dmar_fault(-1, iommu);
658
659 /*
660 * Disable intr remapping and queued invalidation, if already
661 * enabled prior to OS handover.
662 */
663 iommu_disable_irq_remapping(iommu);
664
665 dmar_disable_qi(iommu);
666 }
667
668 /*
669 * check for the Interrupt-remapping support
670 */
671 for_each_iommu(iommu, drhd)
672 if (eim && !ecap_eim_support(iommu->ecap)) {
673 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
674 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
675 eim = 0;
676 }
677 eim_mode = eim;
678 if (eim)
679 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
680
681 /*
682 * Enable queued invalidation for all the DRHD's.
683 */
684 for_each_iommu(iommu, drhd) {
685 int ret = dmar_enable_qi(iommu);
686
687 if (ret) {
688 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
689 " invalidation, ecap %Lx, ret %d\n",
690 drhd->reg_base_addr, iommu->ecap, ret);
691 goto error;
692 }
693 }
694
695 /*
696 * Setup Interrupt-remapping for all the DRHD's now.
697 */
698 for_each_iommu(iommu, drhd) {
699 iommu_set_irq_remapping(iommu, eim);
700 setup = 1;
701 }
702
703 if (!setup)
704 goto error;
705
706 irq_remapping_enabled = 1;
707
708 /*
709 * VT-d has a different layout for IO-APIC entries when
710 * interrupt remapping is enabled. So it needs a special routine
711 * to print IO-APIC entries for debugging purposes too.
712 */
713 x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries;
714
715 pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic");
716
717 return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
718
719 error:
720 intel_cleanup_irq_remapping();
721 return -1;
722 }
723
724 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
725 struct intel_iommu *iommu,
726 struct acpi_dmar_hardware_unit *drhd)
727 {
728 struct acpi_dmar_pci_path *path;
729 u8 bus;
730 int count, free = -1;
731
732 bus = scope->bus;
733 path = (struct acpi_dmar_pci_path *)(scope + 1);
734 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
735 / sizeof(struct acpi_dmar_pci_path);
736
737 while (--count > 0) {
738 /*
739 * Access PCI directly due to the PCI
740 * subsystem isn't initialized yet.
741 */
742 bus = read_pci_config_byte(bus, path->device, path->function,
743 PCI_SECONDARY_BUS);
744 path++;
745 }
746
747 for (count = 0; count < MAX_HPET_TBS; count++) {
748 if (ir_hpet[count].iommu == iommu &&
749 ir_hpet[count].id == scope->enumeration_id)
750 return 0;
751 else if (ir_hpet[count].iommu == NULL && free == -1)
752 free = count;
753 }
754 if (free == -1) {
755 pr_warn("Exceeded Max HPET blocks\n");
756 return -ENOSPC;
757 }
758
759 ir_hpet[free].iommu = iommu;
760 ir_hpet[free].id = scope->enumeration_id;
761 ir_hpet[free].bus = bus;
762 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
763 pr_info("HPET id %d under DRHD base 0x%Lx\n",
764 scope->enumeration_id, drhd->address);
765
766 return 0;
767 }
768
769 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
770 struct intel_iommu *iommu,
771 struct acpi_dmar_hardware_unit *drhd)
772 {
773 struct acpi_dmar_pci_path *path;
774 u8 bus;
775 int count, free = -1;
776
777 bus = scope->bus;
778 path = (struct acpi_dmar_pci_path *)(scope + 1);
779 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
780 / sizeof(struct acpi_dmar_pci_path);
781
782 while (--count > 0) {
783 /*
784 * Access PCI directly due to the PCI
785 * subsystem isn't initialized yet.
786 */
787 bus = read_pci_config_byte(bus, path->device, path->function,
788 PCI_SECONDARY_BUS);
789 path++;
790 }
791
792 for (count = 0; count < MAX_IO_APICS; count++) {
793 if (ir_ioapic[count].iommu == iommu &&
794 ir_ioapic[count].id == scope->enumeration_id)
795 return 0;
796 else if (ir_ioapic[count].iommu == NULL && free == -1)
797 free = count;
798 }
799 if (free == -1) {
800 pr_warn("Exceeded Max IO APICS\n");
801 return -ENOSPC;
802 }
803
804 ir_ioapic[free].bus = bus;
805 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
806 ir_ioapic[free].iommu = iommu;
807 ir_ioapic[free].id = scope->enumeration_id;
808 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
809 scope->enumeration_id, drhd->address, iommu->seq_id);
810
811 return 0;
812 }
813
814 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
815 struct intel_iommu *iommu)
816 {
817 int ret = 0;
818 struct acpi_dmar_hardware_unit *drhd;
819 struct acpi_dmar_device_scope *scope;
820 void *start, *end;
821
822 drhd = (struct acpi_dmar_hardware_unit *)header;
823 start = (void *)(drhd + 1);
824 end = ((void *)drhd) + header->length;
825
826 while (start < end && ret == 0) {
827 scope = start;
828 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
829 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
830 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
831 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
832 start += scope->length;
833 }
834
835 return ret;
836 }
837
838 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
839 {
840 int i;
841
842 for (i = 0; i < MAX_HPET_TBS; i++)
843 if (ir_hpet[i].iommu == iommu)
844 ir_hpet[i].iommu = NULL;
845
846 for (i = 0; i < MAX_IO_APICS; i++)
847 if (ir_ioapic[i].iommu == iommu)
848 ir_ioapic[i].iommu = NULL;
849 }
850
851 /*
852 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
853 * hardware unit.
854 */
855 static int __init parse_ioapics_under_ir(void)
856 {
857 struct dmar_drhd_unit *drhd;
858 struct intel_iommu *iommu;
859 int ir_supported = 0;
860 int ioapic_idx;
861
862 for_each_iommu(iommu, drhd)
863 if (ecap_ir_support(iommu->ecap)) {
864 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
865 return -1;
866
867 ir_supported = 1;
868 }
869
870 if (!ir_supported)
871 return 0;
872
873 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
874 int ioapic_id = mpc_ioapic_id(ioapic_idx);
875 if (!map_ioapic_to_ir(ioapic_id)) {
876 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
877 "interrupt remapping will be disabled\n",
878 ioapic_id);
879 return -1;
880 }
881 }
882
883 return 1;
884 }
885
886 static int __init ir_dev_scope_init(void)
887 {
888 int ret;
889
890 if (!irq_remapping_enabled)
891 return 0;
892
893 down_write(&dmar_global_lock);
894 ret = dmar_dev_scope_init();
895 up_write(&dmar_global_lock);
896
897 return ret;
898 }
899 rootfs_initcall(ir_dev_scope_init);
900
901 static void disable_irq_remapping(void)
902 {
903 struct dmar_drhd_unit *drhd;
904 struct intel_iommu *iommu = NULL;
905
906 /*
907 * Disable Interrupt-remapping for all the DRHD's now.
908 */
909 for_each_iommu(iommu, drhd) {
910 if (!ecap_ir_support(iommu->ecap))
911 continue;
912
913 iommu_disable_irq_remapping(iommu);
914 }
915 }
916
917 static int reenable_irq_remapping(int eim)
918 {
919 struct dmar_drhd_unit *drhd;
920 int setup = 0;
921 struct intel_iommu *iommu = NULL;
922
923 for_each_iommu(iommu, drhd)
924 if (iommu->qi)
925 dmar_reenable_qi(iommu);
926
927 /*
928 * Setup Interrupt-remapping for all the DRHD's now.
929 */
930 for_each_iommu(iommu, drhd) {
931 if (!ecap_ir_support(iommu->ecap))
932 continue;
933
934 /* Set up interrupt remapping for iommu.*/
935 iommu_set_irq_remapping(iommu, eim);
936 setup = 1;
937 }
938
939 if (!setup)
940 goto error;
941
942 return 0;
943
944 error:
945 /*
946 * handle error condition gracefully here!
947 */
948 return -1;
949 }
950
951 static void prepare_irte(struct irte *irte, int vector,
952 unsigned int dest)
953 {
954 memset(irte, 0, sizeof(*irte));
955
956 irte->present = 1;
957 irte->dst_mode = apic->irq_dest_mode;
958 /*
959 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
960 * actual level or edge trigger will be setup in the IO-APIC
961 * RTE. This will help simplify level triggered irq migration.
962 * For more details, see the comments (in io_apic.c) explainig IO-APIC
963 * irq migration in the presence of interrupt-remapping.
964 */
965 irte->trigger_mode = 0;
966 irte->dlvry_mode = apic->irq_delivery_mode;
967 irte->vector = vector;
968 irte->dest_id = IRTE_DEST(dest);
969 irte->redir_hint = 1;
970 }
971
972 static int intel_setup_ioapic_entry(int irq,
973 struct IO_APIC_route_entry *route_entry,
974 unsigned int destination, int vector,
975 struct io_apic_irq_attr *attr)
976 {
977 int ioapic_id = mpc_ioapic_id(attr->ioapic);
978 struct intel_iommu *iommu;
979 struct IR_IO_APIC_route_entry *entry;
980 struct irte irte;
981 int index;
982
983 down_read(&dmar_global_lock);
984 iommu = map_ioapic_to_ir(ioapic_id);
985 if (!iommu) {
986 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
987 index = -ENODEV;
988 } else {
989 index = alloc_irte(iommu, irq, 1);
990 if (index < 0) {
991 pr_warn("Failed to allocate IRTE for ioapic %d\n",
992 ioapic_id);
993 index = -ENOMEM;
994 }
995 }
996 up_read(&dmar_global_lock);
997 if (index < 0)
998 return index;
999
1000 prepare_irte(&irte, vector, destination);
1001
1002 /* Set source-id of interrupt request */
1003 set_ioapic_sid(&irte, ioapic_id);
1004
1005 modify_irte(irq, &irte);
1006
1007 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1008 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1009 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1010 "Avail:%X Vector:%02X Dest:%08X "
1011 "SID:%04X SQ:%X SVT:%X)\n",
1012 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
1013 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1014 irte.avail, irte.vector, irte.dest_id,
1015 irte.sid, irte.sq, irte.svt);
1016
1017 entry = (struct IR_IO_APIC_route_entry *)route_entry;
1018 memset(entry, 0, sizeof(*entry));
1019
1020 entry->index2 = (index >> 15) & 0x1;
1021 entry->zero = 0;
1022 entry->format = 1;
1023 entry->index = (index & 0x7fff);
1024 /*
1025 * IO-APIC RTE will be configured with virtual vector.
1026 * irq handler will do the explicit EOI to the io-apic.
1027 */
1028 entry->vector = attr->ioapic_pin;
1029 entry->mask = 0; /* enable IRQ */
1030 entry->trigger = attr->trigger;
1031 entry->polarity = attr->polarity;
1032
1033 /* Mask level triggered irqs.
1034 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1035 */
1036 if (attr->trigger)
1037 entry->mask = 1;
1038
1039 return 0;
1040 }
1041
1042 /*
1043 * Migrate the IO-APIC irq in the presence of intr-remapping.
1044 *
1045 * For both level and edge triggered, irq migration is a simple atomic
1046 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1047 *
1048 * For level triggered, we eliminate the io-apic RTE modification (with the
1049 * updated vector information), by using a virtual vector (io-apic pin number).
1050 * Real vector that is used for interrupting cpu will be coming from
1051 * the interrupt-remapping table entry.
1052 *
1053 * As the migration is a simple atomic update of IRTE, the same mechanism
1054 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1055 */
1056 static int
1057 intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
1058 bool force)
1059 {
1060 struct irq_cfg *cfg = irqd_cfg(data);
1061 unsigned int dest, irq = data->irq;
1062 struct irte irte;
1063 int err;
1064
1065 if (!config_enabled(CONFIG_SMP))
1066 return -EINVAL;
1067
1068 if (!cpumask_intersects(mask, cpu_online_mask))
1069 return -EINVAL;
1070
1071 if (get_irte(irq, &irte))
1072 return -EBUSY;
1073
1074 err = assign_irq_vector(irq, cfg, mask);
1075 if (err)
1076 return err;
1077
1078 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
1079 if (err) {
1080 if (assign_irq_vector(irq, cfg, data->affinity))
1081 pr_err("Failed to recover vector for irq %d\n", irq);
1082 return err;
1083 }
1084
1085 irte.vector = cfg->vector;
1086 irte.dest_id = IRTE_DEST(dest);
1087
1088 /*
1089 * Atomically updates the IRTE with the new destination, vector
1090 * and flushes the interrupt entry cache.
1091 */
1092 modify_irte(irq, &irte);
1093
1094 /*
1095 * After this point, all the interrupts will start arriving
1096 * at the new destination. So, time to cleanup the previous
1097 * vector allocation.
1098 */
1099 if (cfg->move_in_progress)
1100 send_cleanup_vector(cfg);
1101
1102 cpumask_copy(data->affinity, mask);
1103 return 0;
1104 }
1105
1106 static void intel_compose_msi_msg(struct pci_dev *pdev,
1107 unsigned int irq, unsigned int dest,
1108 struct msi_msg *msg, u8 hpet_id)
1109 {
1110 struct irq_cfg *cfg;
1111 struct irte irte;
1112 u16 sub_handle = 0;
1113 int ir_index;
1114
1115 cfg = irq_cfg(irq);
1116
1117 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
1118 BUG_ON(ir_index == -1);
1119
1120 prepare_irte(&irte, cfg->vector, dest);
1121
1122 /* Set source-id of interrupt request */
1123 if (pdev)
1124 set_msi_sid(&irte, pdev);
1125 else
1126 set_hpet_sid(&irte, hpet_id);
1127
1128 modify_irte(irq, &irte);
1129
1130 msg->address_hi = MSI_ADDR_BASE_HI;
1131 msg->data = sub_handle;
1132 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1133 MSI_ADDR_IR_SHV |
1134 MSI_ADDR_IR_INDEX1(ir_index) |
1135 MSI_ADDR_IR_INDEX2(ir_index);
1136 }
1137
1138 /*
1139 * Map the PCI dev to the corresponding remapping hardware unit
1140 * and allocate 'nvec' consecutive interrupt-remapping table entries
1141 * in it.
1142 */
1143 static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec)
1144 {
1145 struct intel_iommu *iommu;
1146 int index;
1147
1148 down_read(&dmar_global_lock);
1149 iommu = map_dev_to_ir(dev);
1150 if (!iommu) {
1151 printk(KERN_ERR
1152 "Unable to map PCI %s to iommu\n", pci_name(dev));
1153 index = -ENOENT;
1154 } else {
1155 index = alloc_irte(iommu, irq, nvec);
1156 if (index < 0) {
1157 printk(KERN_ERR
1158 "Unable to allocate %d IRTE for PCI %s\n",
1159 nvec, pci_name(dev));
1160 index = -ENOSPC;
1161 }
1162 }
1163 up_read(&dmar_global_lock);
1164
1165 return index;
1166 }
1167
1168 static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
1169 int index, int sub_handle)
1170 {
1171 struct intel_iommu *iommu;
1172 int ret = -ENOENT;
1173
1174 down_read(&dmar_global_lock);
1175 iommu = map_dev_to_ir(pdev);
1176 if (iommu) {
1177 /*
1178 * setup the mapping between the irq and the IRTE
1179 * base index, the sub_handle pointing to the
1180 * appropriate interrupt remap table entry.
1181 */
1182 set_irte_irq(irq, iommu, index, sub_handle);
1183 ret = 0;
1184 }
1185 up_read(&dmar_global_lock);
1186
1187 return ret;
1188 }
1189
1190 static int intel_alloc_hpet_msi(unsigned int irq, unsigned int id)
1191 {
1192 int ret = -1;
1193 struct intel_iommu *iommu;
1194 int index;
1195
1196 down_read(&dmar_global_lock);
1197 iommu = map_hpet_to_ir(id);
1198 if (iommu) {
1199 index = alloc_irte(iommu, irq, 1);
1200 if (index >= 0)
1201 ret = 0;
1202 }
1203 up_read(&dmar_global_lock);
1204
1205 return ret;
1206 }
1207
1208 struct irq_remap_ops intel_irq_remap_ops = {
1209 .prepare = intel_prepare_irq_remapping,
1210 .enable = intel_enable_irq_remapping,
1211 .disable = disable_irq_remapping,
1212 .reenable = reenable_irq_remapping,
1213 .enable_faulting = enable_drhd_fault_handling,
1214 .setup_ioapic_entry = intel_setup_ioapic_entry,
1215 .set_affinity = intel_ioapic_set_affinity,
1216 .free_irq = free_irte,
1217 .compose_msi_msg = intel_compose_msi_msg,
1218 .msi_alloc_irq = intel_msi_alloc_irq,
1219 .msi_setup_irq = intel_msi_setup_irq,
1220 .alloc_hpet_msi = intel_alloc_hpet_msi,
1221 };
1222
1223 /*
1224 * Support of Interrupt Remapping Unit Hotplug
1225 */
1226 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1227 {
1228 int ret;
1229 int eim = x2apic_enabled();
1230
1231 if (eim && !ecap_eim_support(iommu->ecap)) {
1232 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1233 iommu->reg_phys, iommu->ecap);
1234 return -ENODEV;
1235 }
1236
1237 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1238 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1239 iommu->reg_phys);
1240 return -ENODEV;
1241 }
1242
1243 /* TODO: check all IOAPICs are covered by IOMMU */
1244
1245 /* Setup Interrupt-remapping now. */
1246 ret = intel_setup_irq_remapping(iommu);
1247 if (ret) {
1248 pr_err("DRHD %Lx: failed to allocate resource\n",
1249 iommu->reg_phys);
1250 ir_remove_ioapic_hpet_scope(iommu);
1251 return ret;
1252 }
1253
1254 if (!iommu->qi) {
1255 /* Clear previous faults. */
1256 dmar_fault(-1, iommu);
1257 iommu_disable_irq_remapping(iommu);
1258 dmar_disable_qi(iommu);
1259 }
1260
1261 /* Enable queued invalidation */
1262 ret = dmar_enable_qi(iommu);
1263 if (!ret) {
1264 iommu_set_irq_remapping(iommu, eim);
1265 } else {
1266 pr_err("DRHD %Lx: failed to enable queued invalidation, ecap %Lx, ret %d\n",
1267 iommu->reg_phys, iommu->ecap, ret);
1268 intel_teardown_irq_remapping(iommu);
1269 ir_remove_ioapic_hpet_scope(iommu);
1270 }
1271
1272 return ret;
1273 }
1274
1275 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1276 {
1277 int ret = 0;
1278 struct intel_iommu *iommu = dmaru->iommu;
1279
1280 if (!irq_remapping_enabled)
1281 return 0;
1282 if (iommu == NULL)
1283 return -EINVAL;
1284 if (!ecap_ir_support(iommu->ecap))
1285 return 0;
1286
1287 if (insert) {
1288 if (!iommu->ir_table)
1289 ret = dmar_ir_add(dmaru, iommu);
1290 } else {
1291 if (iommu->ir_table) {
1292 if (!bitmap_empty(iommu->ir_table->bitmap,
1293 INTR_REMAP_TABLE_ENTRIES)) {
1294 ret = -EBUSY;
1295 } else {
1296 iommu_disable_irq_remapping(iommu);
1297 intel_teardown_irq_remapping(iommu);
1298 ir_remove_ioapic_hpet_scope(iommu);
1299 }
1300 }
1301 }
1302
1303 return ret;
1304 }
Linux with added FPC-III support