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Bluetooth: hci_uart: Use generic functionality from Broadcom module
[linux/fpc-iii.git] / drivers / soc / tegra / pmc.c
blobc956395cf46f961beaf6f56674d20f58b2c717b6
1 /*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/clk/tegra.h>
23 #include <linux/debugfs.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/export.h>
27 #include <linux/init.h>
28 #include <linux/io.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/platform_device.h>
32 #include <linux/reboot.h>
33 #include <linux/reset.h>
34 #include <linux/seq_file.h>
35 #include <linux/spinlock.h>
36
37 #include <soc/tegra/common.h>
38 #include <soc/tegra/fuse.h>
39 #include <soc/tegra/pmc.h>
40
41 #define PMC_CNTRL 0x0
42 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
43 #define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */
44 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
45 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
46 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
47 #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
48
49 #define DPD_SAMPLE 0x020
50 #define DPD_SAMPLE_ENABLE (1 << 0)
51 #define DPD_SAMPLE_DISABLE (0 << 0)
52
53 #define PWRGATE_TOGGLE 0x30
54 #define PWRGATE_TOGGLE_START (1 << 8)
55
56 #define REMOVE_CLAMPING 0x34
57
58 #define PWRGATE_STATUS 0x38
59
60 #define PMC_SCRATCH0 0x50
61 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
62 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
63 #define PMC_SCRATCH0_MODE_RCM (1 << 1)
64 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
65 PMC_SCRATCH0_MODE_BOOTLOADER | \
66 PMC_SCRATCH0_MODE_RCM)
67
68 #define PMC_CPUPWRGOOD_TIMER 0xc8
69 #define PMC_CPUPWROFF_TIMER 0xcc
70
71 #define PMC_SCRATCH41 0x140
72
73 #define PMC_SENSOR_CTRL 0x1b0
74 #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
75 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
76
77 #define IO_DPD_REQ 0x1b8
78 #define IO_DPD_REQ_CODE_IDLE (0 << 30)
79 #define IO_DPD_REQ_CODE_OFF (1 << 30)
80 #define IO_DPD_REQ_CODE_ON (2 << 30)
81 #define IO_DPD_REQ_CODE_MASK (3 << 30)
82
83 #define IO_DPD_STATUS 0x1bc
84 #define IO_DPD2_REQ 0x1c0
85 #define IO_DPD2_STATUS 0x1c4
86 #define SEL_DPD_TIM 0x1c8
87
88 #define PMC_SCRATCH54 0x258
89 #define PMC_SCRATCH54_DATA_SHIFT 8
90 #define PMC_SCRATCH54_ADDR_SHIFT 0
91
92 #define PMC_SCRATCH55 0x25c
93 #define PMC_SCRATCH55_RESET_TEGRA (1 << 31)
94 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
95 #define PMC_SCRATCH55_PINMUX_SHIFT 24
96 #define PMC_SCRATCH55_16BITOP (1 << 15)
97 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
98 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
99
100 #define GPU_RG_CNTRL 0x2d4
101
102 struct tegra_pmc_soc {
103 unsigned int num_powergates;
104 const char *const *powergates;
105 unsigned int num_cpu_powergates;
106 const u8 *cpu_powergates;
107
108 bool has_tsense_reset;
109 bool has_gpu_clamps;
110 };
111
112 /**
113 * struct tegra_pmc - NVIDIA Tegra PMC
114 * @base: pointer to I/O remapped register region
115 * @clk: pointer to pclk clock
116 * @rate: currently configured rate of pclk
117 * @suspend_mode: lowest suspend mode available
118 * @cpu_good_time: CPU power good time (in microseconds)
119 * @cpu_off_time: CPU power off time (in microsecends)
120 * @core_osc_time: core power good OSC time (in microseconds)
121 * @core_pmu_time: core power good PMU time (in microseconds)
122 * @core_off_time: core power off time (in microseconds)
123 * @corereq_high: core power request is active-high
124 * @sysclkreq_high: system clock request is active-high
125 * @combined_req: combined power request for CPU & core
126 * @cpu_pwr_good_en: CPU power good signal is enabled
127 * @lp0_vec_phys: physical base address of the LP0 warm boot code
128 * @lp0_vec_size: size of the LP0 warm boot code
129 * @powergates_lock: mutex for power gate register access
130 */
131 struct tegra_pmc {
132 struct device *dev;
133 void __iomem *base;
134 struct clk *clk;
135
136 const struct tegra_pmc_soc *soc;
137
138 unsigned long rate;
139
140 enum tegra_suspend_mode suspend_mode;
141 u32 cpu_good_time;
142 u32 cpu_off_time;
143 u32 core_osc_time;
144 u32 core_pmu_time;
145 u32 core_off_time;
146 bool corereq_high;
147 bool sysclkreq_high;
148 bool combined_req;
149 bool cpu_pwr_good_en;
150 u32 lp0_vec_phys;
151 u32 lp0_vec_size;
152
153 struct mutex powergates_lock;
154 };
155
156 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
157 .base = NULL,
158 .suspend_mode = TEGRA_SUSPEND_NONE,
159 };
160
161 static u32 tegra_pmc_readl(unsigned long offset)
162 {
163 return readl(pmc->base + offset);
164 }
165
166 static void tegra_pmc_writel(u32 value, unsigned long offset)
167 {
168 writel(value, pmc->base + offset);
169 }
170
171 /**
172 * tegra_powergate_set() - set the state of a partition
173 * @id: partition ID
174 * @new_state: new state of the partition
175 */
176 static int tegra_powergate_set(int id, bool new_state)
177 {
178 bool status;
179
180 mutex_lock(&pmc->powergates_lock);
181
182 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
183
184 if (status == new_state) {
185 mutex_unlock(&pmc->powergates_lock);
186 return 0;
187 }
188
189 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
190
191 mutex_unlock(&pmc->powergates_lock);
192
193 return 0;
194 }
195
196 /**
197 * tegra_powergate_power_on() - power on partition
198 * @id: partition ID
199 */
200 int tegra_powergate_power_on(int id)
201 {
202 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
203 return -EINVAL;
204
205 return tegra_powergate_set(id, true);
206 }
207
208 /**
209 * tegra_powergate_power_off() - power off partition
210 * @id: partition ID
211 */
212 int tegra_powergate_power_off(int id)
213 {
214 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
215 return -EINVAL;
216
217 return tegra_powergate_set(id, false);
218 }
219 EXPORT_SYMBOL(tegra_powergate_power_off);
220
221 /**
222 * tegra_powergate_is_powered() - check if partition is powered
223 * @id: partition ID
224 */
225 int tegra_powergate_is_powered(int id)
226 {
227 u32 status;
228
229 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
230 return -EINVAL;
231
232 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
233 return !!status;
234 }
235
236 /**
237 * tegra_powergate_remove_clamping() - remove power clamps for partition
238 * @id: partition ID
239 */
240 int tegra_powergate_remove_clamping(int id)
241 {
242 u32 mask;
243
244 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
245 return -EINVAL;
246
247 /*
248 * On Tegra124 and later, the clamps for the GPU are controlled by a
249 * separate register (with different semantics).
250 */
251 if (id == TEGRA_POWERGATE_3D) {
252 if (pmc->soc->has_gpu_clamps) {
253 tegra_pmc_writel(0, GPU_RG_CNTRL);
254 return 0;
255 }
256 }
257
258 /*
259 * Tegra 2 has a bug where PCIE and VDE clamping masks are
260 * swapped relatively to the partition ids
261 */
262 if (id == TEGRA_POWERGATE_VDEC)
263 mask = (1 << TEGRA_POWERGATE_PCIE);
264 else if (id == TEGRA_POWERGATE_PCIE)
265 mask = (1 << TEGRA_POWERGATE_VDEC);
266 else
267 mask = (1 << id);
268
269 tegra_pmc_writel(mask, REMOVE_CLAMPING);
270
271 return 0;
272 }
273 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
274
275 /**
276 * tegra_powergate_sequence_power_up() - power up partition
277 * @id: partition ID
278 * @clk: clock for partition
279 * @rst: reset for partition
280 *
281 * Must be called with clk disabled, and returns with clk enabled.
282 */
283 int tegra_powergate_sequence_power_up(int id, struct clk *clk,
284 struct reset_control *rst)
285 {
286 int ret;
287
288 reset_control_assert(rst);
289
290 ret = tegra_powergate_power_on(id);
291 if (ret)
292 goto err_power;
293
294 ret = clk_prepare_enable(clk);
295 if (ret)
296 goto err_clk;
297
298 usleep_range(10, 20);
299
300 ret = tegra_powergate_remove_clamping(id);
301 if (ret)
302 goto err_clamp;
303
304 usleep_range(10, 20);
305 reset_control_deassert(rst);
306
307 return 0;
308
309 err_clamp:
310 clk_disable_unprepare(clk);
311 err_clk:
312 tegra_powergate_power_off(id);
313 err_power:
314 return ret;
315 }
316 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
317
318 #ifdef CONFIG_SMP
319 /**
320 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
321 * @cpuid: CPU partition ID
322 *
323 * Returns the partition ID corresponding to the CPU partition ID or a
324 * negative error code on failure.
325 */
326 static int tegra_get_cpu_powergate_id(int cpuid)
327 {
328 if (pmc->soc && cpuid > 0 && cpuid < pmc->soc->num_cpu_powergates)
329 return pmc->soc->cpu_powergates[cpuid];
330
331 return -EINVAL;
332 }
333
334 /**
335 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
336 * @cpuid: CPU partition ID
337 */
338 bool tegra_pmc_cpu_is_powered(int cpuid)
339 {
340 int id;
341
342 id = tegra_get_cpu_powergate_id(cpuid);
343 if (id < 0)
344 return false;
345
346 return tegra_powergate_is_powered(id);
347 }
348
349 /**
350 * tegra_pmc_cpu_power_on() - power on CPU partition
351 * @cpuid: CPU partition ID
352 */
353 int tegra_pmc_cpu_power_on(int cpuid)
354 {
355 int id;
356
357 id = tegra_get_cpu_powergate_id(cpuid);
358 if (id < 0)
359 return id;
360
361 return tegra_powergate_set(id, true);
362 }
363
364 /**
365 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
366 * @cpuid: CPU partition ID
367 */
368 int tegra_pmc_cpu_remove_clamping(int cpuid)
369 {
370 int id;
371
372 id = tegra_get_cpu_powergate_id(cpuid);
373 if (id < 0)
374 return id;
375
376 return tegra_powergate_remove_clamping(id);
377 }
378 #endif /* CONFIG_SMP */
379
380 /**
381 * tegra_pmc_restart() - reboot the system
382 * @mode: which mode to reboot in
383 * @cmd: reboot command
384 */
385 void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
386 {
387 u32 value;
388
389 value = tegra_pmc_readl(PMC_SCRATCH0);
390 value &= ~PMC_SCRATCH0_MODE_MASK;
391
392 if (cmd) {
393 if (strcmp(cmd, "recovery") == 0)
394 value |= PMC_SCRATCH0_MODE_RECOVERY;
395
396 if (strcmp(cmd, "bootloader") == 0)
397 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
398
399 if (strcmp(cmd, "forced-recovery") == 0)
400 value |= PMC_SCRATCH0_MODE_RCM;
401 }
402
403 tegra_pmc_writel(value, PMC_SCRATCH0);
404
405 value = tegra_pmc_readl(0);
406 value |= 0x10;
407 tegra_pmc_writel(value, 0);
408 }
409
410 static int powergate_show(struct seq_file *s, void *data)
411 {
412 unsigned int i;
413
414 seq_printf(s, " powergate powered\n");
415 seq_printf(s, "------------------\n");
416
417 for (i = 0; i < pmc->soc->num_powergates; i++) {
418 if (!pmc->soc->powergates[i])
419 continue;
420
421 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
422 tegra_powergate_is_powered(i) ? "yes" : "no");
423 }
424
425 return 0;
426 }
427
428 static int powergate_open(struct inode *inode, struct file *file)
429 {
430 return single_open(file, powergate_show, inode->i_private);
431 }
432
433 static const struct file_operations powergate_fops = {
434 .open = powergate_open,
435 .read = seq_read,
436 .llseek = seq_lseek,
437 .release = single_release,
438 };
439
440 static int tegra_powergate_debugfs_init(void)
441 {
442 struct dentry *d;
443
444 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
445 &powergate_fops);
446 if (!d)
447 return -ENOMEM;
448
449 return 0;
450 }
451
452 static int tegra_io_rail_prepare(int id, unsigned long *request,
453 unsigned long *status, unsigned int *bit)
454 {
455 unsigned long rate, value;
456 struct clk *clk;
457
458 *bit = id % 32;
459
460 /*
461 * There are two sets of 30 bits to select IO rails, but bits 30 and
462 * 31 are control bits rather than IO rail selection bits.
463 */
464 if (id > 63 || *bit == 30 || *bit == 31)
465 return -EINVAL;
466
467 if (id < 32) {
468 *status = IO_DPD_STATUS;
469 *request = IO_DPD_REQ;
470 } else {
471 *status = IO_DPD2_STATUS;
472 *request = IO_DPD2_REQ;
473 }
474
475 clk = clk_get_sys(NULL, "pclk");
476 if (IS_ERR(clk))
477 return PTR_ERR(clk);
478
479 rate = clk_get_rate(clk);
480 clk_put(clk);
481
482 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
483
484 /* must be at least 200 ns, in APB (PCLK) clock cycles */
485 value = DIV_ROUND_UP(1000000000, rate);
486 value = DIV_ROUND_UP(200, value);
487 tegra_pmc_writel(value, SEL_DPD_TIM);
488
489 return 0;
490 }
491
492 static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
493 unsigned long val, unsigned long timeout)
494 {
495 unsigned long value;
496
497 timeout = jiffies + msecs_to_jiffies(timeout);
498
499 while (time_after(timeout, jiffies)) {
500 value = tegra_pmc_readl(offset);
501 if ((value & mask) == val)
502 return 0;
503
504 usleep_range(250, 1000);
505 }
506
507 return -ETIMEDOUT;
508 }
509
510 static void tegra_io_rail_unprepare(void)
511 {
512 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
513 }
514
515 int tegra_io_rail_power_on(int id)
516 {
517 unsigned long request, status, value;
518 unsigned int bit, mask;
519 int err;
520
521 err = tegra_io_rail_prepare(id, &request, &status, &bit);
522 if (err < 0)
523 return err;
524
525 mask = 1 << bit;
526
527 value = tegra_pmc_readl(request);
528 value |= mask;
529 value &= ~IO_DPD_REQ_CODE_MASK;
530 value |= IO_DPD_REQ_CODE_OFF;
531 tegra_pmc_writel(value, request);
532
533 err = tegra_io_rail_poll(status, mask, 0, 250);
534 if (err < 0)
535 return err;
536
537 tegra_io_rail_unprepare();
538
539 return 0;
540 }
541 EXPORT_SYMBOL(tegra_io_rail_power_on);
542
543 int tegra_io_rail_power_off(int id)
544 {
545 unsigned long request, status, value;
546 unsigned int bit, mask;
547 int err;
548
549 err = tegra_io_rail_prepare(id, &request, &status, &bit);
550 if (err < 0)
551 return err;
552
553 mask = 1 << bit;
554
555 value = tegra_pmc_readl(request);
556 value |= mask;
557 value &= ~IO_DPD_REQ_CODE_MASK;
558 value |= IO_DPD_REQ_CODE_ON;
559 tegra_pmc_writel(value, request);
560
561 err = tegra_io_rail_poll(status, mask, mask, 250);
562 if (err < 0)
563 return err;
564
565 tegra_io_rail_unprepare();
566
567 return 0;
568 }
569 EXPORT_SYMBOL(tegra_io_rail_power_off);
570
571 #ifdef CONFIG_PM_SLEEP
572 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
573 {
574 return pmc->suspend_mode;
575 }
576
577 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
578 {
579 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
580 return;
581
582 pmc->suspend_mode = mode;
583 }
584
585 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
586 {
587 unsigned long long rate = 0;
588 u32 value;
589
590 switch (mode) {
591 case TEGRA_SUSPEND_LP1:
592 rate = 32768;
593 break;
594
595 case TEGRA_SUSPEND_LP2:
596 rate = clk_get_rate(pmc->clk);
597 break;
598
599 default:
600 break;
601 }
602
603 if (WARN_ON_ONCE(rate == 0))
604 rate = 100000000;
605
606 if (rate != pmc->rate) {
607 u64 ticks;
608
609 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
610 do_div(ticks, USEC_PER_SEC);
611 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
612
613 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
614 do_div(ticks, USEC_PER_SEC);
615 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
616
617 wmb();
618
619 pmc->rate = rate;
620 }
621
622 value = tegra_pmc_readl(PMC_CNTRL);
623 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
624 value |= PMC_CNTRL_CPU_PWRREQ_OE;
625 tegra_pmc_writel(value, PMC_CNTRL);
626 }
627 #endif
628
629 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
630 {
631 u32 value, values[2];
632
633 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
634 } else {
635 switch (value) {
636 case 0:
637 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
638 break;
639
640 case 1:
641 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
642 break;
643
644 case 2:
645 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
646 break;
647
648 default:
649 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
650 break;
651 }
652 }
653
654 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
655
656 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
657 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
658
659 pmc->cpu_good_time = value;
660
661 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
662 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
663
664 pmc->cpu_off_time = value;
665
666 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
667 values, ARRAY_SIZE(values)))
668 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
669
670 pmc->core_osc_time = values[0];
671 pmc->core_pmu_time = values[1];
672
673 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
674 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
675
676 pmc->core_off_time = value;
677
678 pmc->corereq_high = of_property_read_bool(np,
679 "nvidia,core-power-req-active-high");
680
681 pmc->sysclkreq_high = of_property_read_bool(np,
682 "nvidia,sys-clock-req-active-high");
683
684 pmc->combined_req = of_property_read_bool(np,
685 "nvidia,combined-power-req");
686
687 pmc->cpu_pwr_good_en = of_property_read_bool(np,
688 "nvidia,cpu-pwr-good-en");
689
690 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
691 ARRAY_SIZE(values)))
692 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
693 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
694
695 pmc->lp0_vec_phys = values[0];
696 pmc->lp0_vec_size = values[1];
697
698 return 0;
699 }
700
701 static void tegra_pmc_init(struct tegra_pmc *pmc)
702 {
703 u32 value;
704
705 /* Always enable CPU power request */
706 value = tegra_pmc_readl(PMC_CNTRL);
707 value |= PMC_CNTRL_CPU_PWRREQ_OE;
708 tegra_pmc_writel(value, PMC_CNTRL);
709
710 value = tegra_pmc_readl(PMC_CNTRL);
711
712 if (pmc->sysclkreq_high)
713 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
714 else
715 value |= PMC_CNTRL_SYSCLK_POLARITY;
716
717 /* configure the output polarity while the request is tristated */
718 tegra_pmc_writel(value, PMC_CNTRL);
719
720 /* now enable the request */
721 value = tegra_pmc_readl(PMC_CNTRL);
722 value |= PMC_CNTRL_SYSCLK_OE;
723 tegra_pmc_writel(value, PMC_CNTRL);
724 }
725
726 void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
727 {
728 static const char disabled[] = "emergency thermal reset disabled";
729 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
730 struct device *dev = pmc->dev;
731 struct device_node *np;
732 u32 value, checksum;
733
734 if (!pmc->soc->has_tsense_reset)
735 goto out;
736
737 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
738 if (!np) {
739 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
740 goto out;
741 }
742
743 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
744 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
745 goto out;
746 }
747
748 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
749 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
750 goto out;
751 }
752
753 if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
754 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
755 goto out;
756 }
757
758 if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
759 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
760 goto out;
761 }
762
763 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
764 pinmux = 0;
765
766 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
767 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
768 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
769
770 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
771 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
772 tegra_pmc_writel(value, PMC_SCRATCH54);
773
774 value = PMC_SCRATCH55_RESET_TEGRA;
775 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
776 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
777 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
778
779 /*
780 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
781 * contain the checksum and are currently zero, so they are not added.
782 */
783 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
784 + ((value >> 24) & 0xff);
785 checksum &= 0xff;
786 checksum = 0x100 - checksum;
787
788 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
789
790 tegra_pmc_writel(value, PMC_SCRATCH55);
791
792 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
793 value |= PMC_SENSOR_CTRL_ENABLE_RST;
794 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
795
796 dev_info(pmc->dev, "emergency thermal reset enabled\n");
797
798 out:
799 of_node_put(np);
800 return;
801 }
802
803 static int tegra_pmc_probe(struct platform_device *pdev)
804 {
805 void __iomem *base = pmc->base;
806 struct resource *res;
807 int err;
808
809 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
810 if (err < 0)
811 return err;
812
813 /* take over the memory region from the early initialization */
814 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815 pmc->base = devm_ioremap_resource(&pdev->dev, res);
816 if (IS_ERR(pmc->base))
817 return PTR_ERR(pmc->base);
818
819 iounmap(base);
820
821 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
822 if (IS_ERR(pmc->clk)) {
823 err = PTR_ERR(pmc->clk);
824 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
825 return err;
826 }
827
828 pmc->dev = &pdev->dev;
829
830 tegra_pmc_init(pmc);
831
832 tegra_pmc_init_tsense_reset(pmc);
833
834 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
835 err = tegra_powergate_debugfs_init();
836 if (err < 0)
837 return err;
838 }
839
840 return 0;
841 }
842
843 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
844 static int tegra_pmc_suspend(struct device *dev)
845 {
846 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
847
848 return 0;
849 }
850
851 static int tegra_pmc_resume(struct device *dev)
852 {
853 tegra_pmc_writel(0x0, PMC_SCRATCH41);
854
855 return 0;
856 }
857
858 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
859
860 #endif
861
862 static const char * const tegra20_powergates[] = {
863 [TEGRA_POWERGATE_CPU] = "cpu",
864 [TEGRA_POWERGATE_3D] = "3d",
865 [TEGRA_POWERGATE_VENC] = "venc",
866 [TEGRA_POWERGATE_VDEC] = "vdec",
867 [TEGRA_POWERGATE_PCIE] = "pcie",
868 [TEGRA_POWERGATE_L2] = "l2",
869 [TEGRA_POWERGATE_MPE] = "mpe",
870 };
871
872 static const struct tegra_pmc_soc tegra20_pmc_soc = {
873 .num_powergates = ARRAY_SIZE(tegra20_powergates),
874 .powergates = tegra20_powergates,
875 .num_cpu_powergates = 0,
876 .cpu_powergates = NULL,
877 .has_tsense_reset = false,
878 .has_gpu_clamps = false,
879 };
880
881 static const char * const tegra30_powergates[] = {
882 [TEGRA_POWERGATE_CPU] = "cpu0",
883 [TEGRA_POWERGATE_3D] = "3d0",
884 [TEGRA_POWERGATE_VENC] = "venc",
885 [TEGRA_POWERGATE_VDEC] = "vdec",
886 [TEGRA_POWERGATE_PCIE] = "pcie",
887 [TEGRA_POWERGATE_L2] = "l2",
888 [TEGRA_POWERGATE_MPE] = "mpe",
889 [TEGRA_POWERGATE_HEG] = "heg",
890 [TEGRA_POWERGATE_SATA] = "sata",
891 [TEGRA_POWERGATE_CPU1] = "cpu1",
892 [TEGRA_POWERGATE_CPU2] = "cpu2",
893 [TEGRA_POWERGATE_CPU3] = "cpu3",
894 [TEGRA_POWERGATE_CELP] = "celp",
895 [TEGRA_POWERGATE_3D1] = "3d1",
896 };
897
898 static const u8 tegra30_cpu_powergates[] = {
899 TEGRA_POWERGATE_CPU,
900 TEGRA_POWERGATE_CPU1,
901 TEGRA_POWERGATE_CPU2,
902 TEGRA_POWERGATE_CPU3,
903 };
904
905 static const struct tegra_pmc_soc tegra30_pmc_soc = {
906 .num_powergates = ARRAY_SIZE(tegra30_powergates),
907 .powergates = tegra30_powergates,
908 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
909 .cpu_powergates = tegra30_cpu_powergates,
910 .has_tsense_reset = true,
911 .has_gpu_clamps = false,
912 };
913
914 static const char * const tegra114_powergates[] = {
915 [TEGRA_POWERGATE_CPU] = "crail",
916 [TEGRA_POWERGATE_3D] = "3d",
917 [TEGRA_POWERGATE_VENC] = "venc",
918 [TEGRA_POWERGATE_VDEC] = "vdec",
919 [TEGRA_POWERGATE_MPE] = "mpe",
920 [TEGRA_POWERGATE_HEG] = "heg",
921 [TEGRA_POWERGATE_CPU1] = "cpu1",
922 [TEGRA_POWERGATE_CPU2] = "cpu2",
923 [TEGRA_POWERGATE_CPU3] = "cpu3",
924 [TEGRA_POWERGATE_CELP] = "celp",
925 [TEGRA_POWERGATE_CPU0] = "cpu0",
926 [TEGRA_POWERGATE_C0NC] = "c0nc",
927 [TEGRA_POWERGATE_C1NC] = "c1nc",
928 [TEGRA_POWERGATE_DIS] = "dis",
929 [TEGRA_POWERGATE_DISB] = "disb",
930 [TEGRA_POWERGATE_XUSBA] = "xusba",
931 [TEGRA_POWERGATE_XUSBB] = "xusbb",
932 [TEGRA_POWERGATE_XUSBC] = "xusbc",
933 };
934
935 static const u8 tegra114_cpu_powergates[] = {
936 TEGRA_POWERGATE_CPU0,
937 TEGRA_POWERGATE_CPU1,
938 TEGRA_POWERGATE_CPU2,
939 TEGRA_POWERGATE_CPU3,
940 };
941
942 static const struct tegra_pmc_soc tegra114_pmc_soc = {
943 .num_powergates = ARRAY_SIZE(tegra114_powergates),
944 .powergates = tegra114_powergates,
945 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
946 .cpu_powergates = tegra114_cpu_powergates,
947 .has_tsense_reset = true,
948 .has_gpu_clamps = false,
949 };
950
951 static const char * const tegra124_powergates[] = {
952 [TEGRA_POWERGATE_CPU] = "crail",
953 [TEGRA_POWERGATE_3D] = "3d",
954 [TEGRA_POWERGATE_VENC] = "venc",
955 [TEGRA_POWERGATE_PCIE] = "pcie",
956 [TEGRA_POWERGATE_VDEC] = "vdec",
957 [TEGRA_POWERGATE_L2] = "l2",
958 [TEGRA_POWERGATE_MPE] = "mpe",
959 [TEGRA_POWERGATE_HEG] = "heg",
960 [TEGRA_POWERGATE_SATA] = "sata",
961 [TEGRA_POWERGATE_CPU1] = "cpu1",
962 [TEGRA_POWERGATE_CPU2] = "cpu2",
963 [TEGRA_POWERGATE_CPU3] = "cpu3",
964 [TEGRA_POWERGATE_CELP] = "celp",
965 [TEGRA_POWERGATE_CPU0] = "cpu0",
966 [TEGRA_POWERGATE_C0NC] = "c0nc",
967 [TEGRA_POWERGATE_C1NC] = "c1nc",
968 [TEGRA_POWERGATE_SOR] = "sor",
969 [TEGRA_POWERGATE_DIS] = "dis",
970 [TEGRA_POWERGATE_DISB] = "disb",
971 [TEGRA_POWERGATE_XUSBA] = "xusba",
972 [TEGRA_POWERGATE_XUSBB] = "xusbb",
973 [TEGRA_POWERGATE_XUSBC] = "xusbc",
974 [TEGRA_POWERGATE_VIC] = "vic",
975 [TEGRA_POWERGATE_IRAM] = "iram",
976 };
977
978 static const u8 tegra124_cpu_powergates[] = {
979 TEGRA_POWERGATE_CPU0,
980 TEGRA_POWERGATE_CPU1,
981 TEGRA_POWERGATE_CPU2,
982 TEGRA_POWERGATE_CPU3,
983 };
984
985 static const struct tegra_pmc_soc tegra124_pmc_soc = {
986 .num_powergates = ARRAY_SIZE(tegra124_powergates),
987 .powergates = tegra124_powergates,
988 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
989 .cpu_powergates = tegra124_cpu_powergates,
990 .has_tsense_reset = true,
991 .has_gpu_clamps = true,
992 };
993
994 static const struct of_device_id tegra_pmc_match[] = {
995 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
996 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
997 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
998 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
999 { }
1000 };
1001
1002 static struct platform_driver tegra_pmc_driver = {
1003 .driver = {
1004 .name = "tegra-pmc",
1005 .suppress_bind_attrs = true,
1006 .of_match_table = tegra_pmc_match,
1007 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1008 .pm = &tegra_pmc_pm_ops,
1009 #endif
1010 },
1011 .probe = tegra_pmc_probe,
1012 };
1013 module_platform_driver(tegra_pmc_driver);
1014
1015 /*
1016 * Early initialization to allow access to registers in the very early boot
1017 * process.
1018 */
1019 static int __init tegra_pmc_early_init(void)
1020 {
1021 const struct of_device_id *match;
1022 struct device_node *np;
1023 struct resource regs;
1024 bool invert;
1025 u32 value;
1026
1027 if (!soc_is_tegra())
1028 return 0;
1029
1030 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1031 if (!np) {
1032 pr_warn("PMC device node not found, disabling powergating\n");
1033
1034 regs.start = 0x7000e400;
1035 regs.end = 0x7000e7ff;
1036 regs.flags = IORESOURCE_MEM;
1037
1038 pr_warn("Using memory region %pR\n", &regs);
1039 } else {
1040 pmc->soc = match->data;
1041 }
1042
1043 if (of_address_to_resource(np, 0, &regs) < 0) {
1044 pr_err("failed to get PMC registers\n");
1045 return -ENXIO;
1046 }
1047
1048 pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
1049 if (!pmc->base) {
1050 pr_err("failed to map PMC registers\n");
1051 return -ENXIO;
1052 }
1053
1054 mutex_init(&pmc->powergates_lock);
1055
1056 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1057
1058 value = tegra_pmc_readl(PMC_CNTRL);
1059
1060 if (invert)
1061 value |= PMC_CNTRL_INTR_POLARITY;
1062 else
1063 value &= ~PMC_CNTRL_INTR_POLARITY;
1064
1065 tegra_pmc_writel(value, PMC_CNTRL);
1066
1067 return 0;
1068 }
1069 early_initcall(tegra_pmc_early_init);
Linux with added FPC-III support